A configurable reduction circuit for integer operations in post-quantum cryptographic algorithms
By designing configurable reduction circuits, different forms of reduction operations in post-quantum cryptography algorithms are uniformly supported, and multiplier resources are shared, solving the problem of low hardware resource utilization and realizing efficient reuse of hardware resources and reduced complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2026-03-18
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, different forms of reduction operations in post-quantum cryptography algorithms typically employ independent arithmetic circuits, resulting in low hardware resource utilization. In particular, in FPGA or ASIC implementations, the repeated use of wide-bit multipliers increases area and power consumption.
Design a configurable reduction circuit that receives integer inputs of different bit widths and utilizes configurable multipliers and post-processing components to achieve unified support for Barrett's principle modulo reduction and multiplication mapping interval reduction, sharing wide-bit multiplier resources and reducing hardware resource consumption.
While ensuring functional correctness, it reduces hardware resource consumption and implementation complexity, and improves the utilization rate of hardware resources, especially saving half of the DSP resources in FPGA or ASIC platforms.
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Figure CN121864307B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of hardware implementation technology of cryptographic algorithms, and more specifically, relates to a configurable reduction circuit for integer operations in post-quantum cryptographic algorithms. Background Technology
[0002] In the digital age, information security has become a crucial cornerstone for national security, economic stability, and the protection of personal privacy. Whether it's military communications, financial transactions, industrial control systems, or everyday e-commerce and social media applications, all rely heavily on the security provided by existing cryptographic systems. However, the security of traditional cryptographic protocols rests on the intractability of certain mathematical problems within the classical computing model, and the rapid development of quantum computing poses a serious challenge to this foundation. Once quantum computers become practical, widely used public-key cryptosystems (such as RSA and ECC) will face the risk of being cracked; this threat is known as the "quantum threat."
[0003] Post-quantum cryptography algorithms, such as Hamming Quasi-Cyclic (HQC) based on coding theory, involve numerous operations in their core computations, including random number generation, integer mapping, and modular reduction. In existing implementations, different forms of reduction operations typically employ independent arithmetic circuits, leading to low hardware resource utilization. This is particularly true in FPGA or ASIC implementations, where the repeated use of wide-bit multipliers significantly increases area and power consumption.
[0004] Therefore, there is an urgent need for a reduction circuit that can uniformly support multiple reduction operations at the hardware level, so as to reduce hardware resource overhead and improve the overall system efficiency. Summary of the Invention
[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a configurable reduction circuit for integer operations in post-quantum cryptography algorithms. Its purpose is to solve the technical problem that the existing different forms of reduction operations usually use independent arithmetic circuits, resulting in low hardware resource utilization.
[0006] To achieve the above objectives, according to one aspect of the present invention, a configurable reduction circuit for integer operations in post-quantum cryptography algorithms is provided, comprising: a first integer input terminal, a second integer input terminal, a third integer input terminal, a security level input terminal, a mode selection input terminal, and a reduced integer output terminal;
[0007] The configurable reduction circuit is used to receive an 8-bit integer index value input from the first integer input terminal, a 24-bit random integer input from the second integer input terminal, a 32-bit random integer input from the third integer input terminal, a 2-bit security level signal input from the security level input terminal, and a 1-bit mode selection signal input from the mode selection input terminal, and selects the corresponding 16-bit intermediate parameter n and 18-bit intermediate parameter n based on the 2-bit security level signal input from the security level input terminal. u Based on the 1-bit mode selection signal, one of the two reduced paths is selected using 16-bit intermediate parameters n and 18-bit intermediate parameters n. u The reduction process yields a 16-bit modulo-reduced result, which is then output via the reduced integer output terminal.
[0008] The 8-bit integer index value and its corresponding 32-bit random integer form the first reduction path, and the 24-bit random integer forms the second reduction path.
[0009] Furthermore, the configurable reduction circuit for integer operations in post-quantum cryptography algorithms includes:
[0010] The first configurable multiplier has a first a1 input terminal, a2 input terminal, a1 input terminal, and a2 input terminal, which are respectively used to input the high 16 bits and 18 bits of the intermediate parameter n of a 24-bit random integer and a 32-bit random integer. u And the difference between the 16-bit intermediate parameter n and the 8-bit integer index value; the first configurable multiplier is used to multiply the first a1 input and the first b1 input or the first a2 input and the first b2 input to obtain the first multiplication result, and output it;
[0011] The second configurable multiplier has four input terminals: second a1, second a2, second b1, and second b2. These are used to input the high 10 bits of the lower 42 bits of the first multiplication result, the lower 16 bits of the 32-bit random integer, the 16-bit intermediate parameter n, and the difference between the 16-bit intermediate parameter n and the 8-bit integer index value. The second configurable multiplier is used to multiply the second a1 input terminal and the second b1 input terminal or to multiply the second a2 input terminal and the second b2 input terminal to obtain the second multiplication result, and then outputs it.
[0012] A post-processing component is used to obtain a first processing result and a second processing result, and select one of them for output; wherein, the first processing result is one of the differences between a 24-bit random integer and the lower 26 bits of the second multiplication result, and the difference obtained by subtracting the first difference from the 16-bit intermediate parameter n; if the first difference is greater than or equal to the 16-bit intermediate parameter n, then the first processing result is the second difference, otherwise it is the first difference; the second processing result is the sum of the sum of the higher 16 bits of the lower 32 bits of the second multiplication result and the lower 32 bits of the first multiplication result, shifted 16 bits to the right, and the sum of the 8-bit integer index value.
[0013] Furthermore, the configurable reduction circuit for integer operations in post-quantum cryptography algorithms further includes: a decision unit connected to the second integer input terminal and the first a1 input terminal, used to determine whether the 24-bit random integer is less than... If the value is less than a certain value, it is transmitted to the first input terminal a1, where n is a 16-bit intermediate parameter. This is the floor symbol.
[0014] Furthermore, the post-processing component includes:
[0015] A first processing unit, configured to generate the first processing result, includes: a first subtractor, a second subtractor, a comparator, and a selector; the first subtractor is configured to subtract the lower 26 bits of a 24-bit random integer from the second multiplication result; the second subtractor is configured to subtract the difference from a 16-bit intermediate parameter n; the comparator is configured to determine the relationship between the second difference and the 16-bit intermediate parameter n; the selector is configured to output the second difference if the first difference is greater than or equal to the 16-bit intermediate parameter n, and otherwise output the first difference.
[0016] The second processing unit, used to generate the second processing result, includes: a first shifter, a second shifter, a first adder, and a second adder; the first shifter is used to right-shift the lower 32 bits of the second multiplication result by 16 bits; the first adder is used to add the higher 16 bits of the lower 32 bits of the second multiplication result to the lower 32 bits of the first multiplication result; the second shifter is used to right-shift the output of the first adder by 16 bits; and the second adder is used to add the output of the second shifter to an 8-bit integer index value.
[0017] Furthermore, the first configurable multiplier includes:
[0018] The first selector is used to connect the first input terminal a1 and the first input terminal a2, and select one of them for output;
[0019] The second selector is used to connect the first input terminal b1 and the first input terminal b2, and select one of them for output;
[0020] The first multiplier is used to multiply the output of the first selector and the output of the second selector and then output the result.
[0021] Furthermore, the first configurable multiplier includes:
[0022] The third selector is used to connect the second input terminal a1 and the second input terminal a2, and select one of them for output;
[0023] The fourth selector is used to connect the second input terminal b1 and the second input terminal b2, and select one of them for output;
[0024] The second multiplier is used to multiply the output of the third selector and the output of the fourth selector and then output the result.
[0025] Furthermore, the configurable reduction circuit for integer operations in the post-quantum cryptography algorithm also includes multiple registers for storing data at each input.
[0026] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects:
[0027] (1) The reduction circuit for integer operations in post-quantum cryptography algorithms provided by this invention can receive 24-bit, 32-bit, or 8-bit integer input data. The 24-bit integer input is a modular reduction based on Barrett's principle, while the 32-bit and 8-bit inputs are used together as the input for interval reduction based on multiplication mapping. Finally, a 16-bit integer result in a unified format is output to represent the support set index or related intermediate calculation results. In hardware design, the configurable reduction circuit can unify the reduction process for 8-bit integer index values, 24-bit random integers, and 32-bit random integers, construct a shared wide-bit multiplier, and combine bit segment selection and control logic to reuse the same multiplication calculation resources in different reduction modes. This effectively reduces hardware resource consumption and implementation complexity while ensuring functional correctness.
[0028] (2) The core arithmetic unit of the configurable reduction circuit of this invention is a configurable multiplier. This multiplier contains two sets of selectable input ports, which can be switched between different operands via selection signals, thereby supporting multiplication operations with different bit widths and data sources. The multiplier can perform wide-bit integer multiplication and simultaneously output different bit segments of the multiplication result, providing a unified data foundation for subsequent high-bit truncation, low-bit back substitution, or correction operations. Through this structural design, the same multiplication hardware resources can be reused in different reduction modes for quotient estimation, interval mapping, or intermediate result calculation.
[0029] (3) For interval reduction paths based on multiplication mapping, the configurable reduction circuit achieves interval mapping by performing wide-bit multiplication of the input random number with the interval length parameter, and truncating the bit segment and offsetting the addition of the multiplication result. The two types of reduction paths share the multiplier under the scheduling of the control logic, and differ only in data selection and bit segment usage, which can effectively save hardware resources. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of a configurable reduction circuit for integer operations in a post-quantum cryptography algorithm provided by an embodiment of the present invention.
[0031] Figure 2 This is a circuit diagram of a configurable multiplier provided in an embodiment of the present invention.
[0032] Figure 3 This is a circuit diagram of a configurable reduction circuit for integer operations in a post-quantum cryptography algorithm, provided by an embodiment of the present invention.
[0033] Figure 4 This is a schematic diagram of a parameter selection module provided in an embodiment of the present invention. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0035] like Figure 1 As shown, this invention provides a configurable reduction circuit for integer operations in post-quantum cryptography algorithms, comprising: a first integer input terminal, a second integer input terminal, a third integer input terminal, a security level input terminal, a mode selection input terminal, and a reduced integer output terminal. The configurable reduction circuit receives an 8-bit integer index value input from the first integer input terminal, a 24-bit random integer input from the second integer input terminal, a 32-bit random integer input from the third integer input terminal, a 2-bit security level signal input from the security level input terminal, and a 1-bit mode selection signal input from the mode selection input terminal. It then selects the corresponding 16-bit intermediate parameter n and 18-bit intermediate parameter n based on the 2-bit security level signal input from the security level input terminal. u ; Select one of the two reduced paths based on the 1-bit mode selection signal using 16-bit and 18-bit intermediate parameters n uThe reduction process yields a 16-bit modulo-reduction result, which is then output via the reduced integer output terminal. The 8-bit integer index and its corresponding 32-bit random integer form the first reduction path, and the 24-bit random integer forms the second reduction path.
[0036] The following description uses the HQC algorithm as an example. The configurable reduction circuit provided in this embodiment is applicable to the HQC algorithm. By configuring the mode selection signal and the security level signal, it enables the reuse of wide-bit multipliers and their result bits for Barrett-based modular reduction and interval reduction based on multiplication mapping, thereby reducing hardware resource consumption and improving implementation efficiency. In the random support set generation process of the HQC algorithm, two different types of reduction operations are involved. One type is Barrett-based modular reduction, which approximates the quotient by performing wide-bit integer multiplication of the input integer with the pre-calculated parameters. Based on this, it further performs multiplication back substitution and subtraction correction with the modulus to obtain the final modular reduction result. This process not only requires truncating the high-order bits of the multiplication result to complete the quotient estimation, but also requires using the low-order bits of the multiplication result to participate in remainder reconstruction and condition correction to ensure the correctness of the reduction result. Another type of reduction operation is used to map random integers to dynamically changing target intervals. It achieves interval mapping by performing a wide-bit integer multiplication of the input random number with the interval length and combining it with a truncation operation on the high bits of the multiplication result.
[0037] Although the two types of reduction operations differ in mathematical form and application scenarios, from a hardware implementation perspective, they both use wide-bit integer multiplication as their core arithmetic operation. The main difference between the two types of reduction lies in the configuration of the multiplication operands and the strategy for using different bit segments of the multiplication result, rather than the multiplication structure itself. Therefore, in hardware design, by unifying the reduction process, constructing a shared wide-bit multiplier, and combining bit segment selection and control logic, the same multiplication computation resource can be reused under different mode selection signals. This effectively reduces hardware resource consumption and implementation complexity while ensuring functional correctness.
[0038] This configurable reduction circuit is designed for the random support set generation process in the HQC algorithm, uniformly supporting reduction operations with various input bit widths and different forms. Its overall structure is as follows: Figure 1As shown, the circuit is configured via a security level signal and a mode selection signal, which indicate the current HQC parameter set and the reduction method used, respectively. Depending on the configuration, the circuit can receive 24-bit, 32-bit, or 8-bit integer input data. The 24-bit integer input is based on Barrett's principle for modulo reduction, while the 32-bit and 8-bit inputs are used together as input for interval reduction based on multiplication mapping. The final output is a uniformly formatted 16-bit integer result, used to represent the support set index or related intermediate calculation results. This structure avoids designing separate computation units for different reduction algorithms by reusing internal arithmetic paths.
[0039] As an optional implementation, such as Figure 2 As shown, the core arithmetic unit of the configurable reduction circuit used for integer operations in post-quantum cryptography algorithms is a configurable multiplier. This multiplier contains two sets of selectable input ports, which are switched between different operands via selection signals, thus supporting multiplication operations with different bit widths and data sources. The multiplier can perform wide-bit integer multiplication and simultaneously output different bit segments of the multiplication result, providing a unified data foundation for subsequent high-bit truncation, low-bit back substitution, or correction operations. Through this structural design, the same multiplication hardware resource can be multiplexed under different mode selection signals for quotient estimation, interval mapping, or intermediate result calculation.
[0040] Furthermore, the configurable reduction circuit for integer operations in post-quantum cryptography algorithms includes: a first configurable multiplier, a second configurable multiplier, and a post-processing component.
[0041] The first configurable multiplier has a first a1 input terminal, a2 input terminal, a1 input terminal, and a2 input terminal, which are respectively used to input the high 16 bits and 18 bits of the intermediate parameter n of a 24-bit random integer and a 32-bit random integer. u And the difference between the 16-bit intermediate parameter n and the 8-bit integer index value; the first configurable multiplier is used to multiply the first a1 input and the first b1 input or the first a2 input and the first b2 input to obtain the first multiplication result, and output it.
[0042] The second configurable multiplier has four input terminals: second a1, second a2, second b1, and second b2. These are used to input the high 10 bits of the lower 42 bits of the first multiplication result, the lower 16 bits of the 32-bit random integer, the 16-bit intermediate parameter n, and the difference between the 16-bit intermediate parameter n and the 8-bit integer index value, respectively. The second configurable multiplier is used to multiply the second a1 input terminal and the second b1 input terminal or to multiply the second a2 input terminal and the second b2 input terminal to obtain the second multiplication result, and then output it.
[0043] The post-processing component is used to obtain a first processing result and a second processing result, and select one of them for output. The first processing result is one of the differences between the 24-bit random integer and the lower 26 bits of the second multiplication result, and the difference between the first difference and the 16-bit intermediate parameter n. If the first difference is greater than or equal to the 16-bit intermediate parameter n, the first processing result is the second difference; otherwise, it is the first difference. The second processing result is the sum of the sum of the higher 16 bits of the lower 32 bits of the second multiplication result and the lower 32 bits of the first multiplication result, shifted 16 bits to the right, and the sum of the 8-bit integer index value.
[0044] As an optional implementation, such as Figure 3 As shown, the configurable reduction circuit for integer operations in post-quantum cryptography algorithms further includes: a decision unit connected to the second integer input and the first a1 input, used to determine whether a 24-bit random integer is less than... If the value is less than 1, it is transmitted to the first input terminal a1, where n is a 16-bit intermediate parameter. The symbol is used for rounding down. Further, the first configurable multiplier includes: a first selector, a second selector, and a first multiplier. The first selector is used to connect to the first input terminal a1 and the first input terminal a2, selecting one for output; the second selector is used to connect to the first input terminal b1 and the first input terminal b2, selecting one for output; the first multiplier is used to multiply the output of the first selector and the output of the second selector and output the result. Further, the second configurable multiplier includes: a third selector, a fourth selector, and a second multiplier. The third selector is used to connect to the second input terminal a1 and the second input terminal a2, selecting one for output; the fourth selector is used to connect to the second input terminal b1 and the second input terminal b2, selecting one for output; the second multiplier is used to multiply the output of the third selector and the output of the fourth selector and output the result.
[0045] Figure 3 Detailed data path implementation of the configurable reduction circuit is presented. For the Barrett-based modular reduction path, the circuit first performs necessary rejection checks and registers on the input 24-bit integer. Then, it uses a configurable multiplier to perform a wide-bit multiplication of the input integer with the pre-calculated parameter n, and obtains an approximate quotient by truncating the high-order bits. Subsequently, it performs a back-multiplication of this quotient with the 16-bit intermediate parameter n, and combines subtraction and conditional selection logic to complete the remainder correction, thus obtaining the final modular reduction result. For the interval reduction path based on multiplication mapping, the circuit performs a wide-bit multiplication of the input random number with the interval length parameter, and performs bit segment truncation and addition offset on the multiplication result to achieve interval mapping. Both types of reduction paths share the multiplier under the scheduling of the control logic, differing only in data selection and bit segment usage.
[0046] Furthermore, the post-processing component includes a first processing unit and a second processing unit. The first processing unit, used to generate a first processing result, includes a first subtractor, a second subtractor, a comparator, and a selector. The first subtractor is used to subtract the lower 26 bits of the second multiplication result from the 24-bit random integer. The second subtractor is used to subtract the difference from the 16-bit intermediate parameter n. The comparator is used to determine the relationship between the second difference and the 16-bit intermediate parameter n. The selector outputs the second difference if the first difference is greater than or equal to the 16-bit intermediate parameter n, and the first difference otherwise. The second processing unit, used to generate the second processing result, includes: a first shifter, a second shifter, a first adder, and a second adder; the first shifter is used to right-shift the lower 32 bits of the second multiplication result by 16 bits; the first adder is used to add the higher 16 bits of the lower 32 bits of the second multiplication result to the lower 32 bits of the first multiplication result; the second shifter is used to right-shift the output of the first adder by 16 bits; and the second adder is used to add the output of the second shifter to an 8-bit integer index value.
[0047] As an optional implementation, such as Figure 3 As shown, the configurable reduction circuit for integer operations in post-quantum cryptography algorithms also includes multiple registers for storing data at each input.
[0048] It should be noted that in the configurable reduction circuit described above, the intermediate parameters related to the safety level and their pre-calculated constants are configured through the parameter selection module, the structure of which is as follows: Figure 4 Furthermore, this parameter selection module selects the corresponding intermediate parameter n and the matching Barrett reduction pre-calculation parameter n from multiple sets of pre-stored constants based on the security level signal. u The values are then output to the data paths of the simplified circuit. The intermediate parameter n is represented by a 16-bit fixed-point matrix, corresponding to the parameter values of the HQC algorithm at different security levels. u The multiplication constant corresponding to the intermediate parameters is used in the wide-bit multiplication operation during the quotient estimation stage of Barrett modular reduction, and is represented by an 18-bit fixed-point symbol. Through this parameter selection module, the reduction circuit can support multiple HQC security level configurations without modifying the hardware structure. The reduction circuit only needs to switch control signals to update parameters under different security levels, avoiding the need to repeatedly implement arithmetic units for different parameter sets, further improving the versatility and scalability of the circuit structure.
[0049] The configurable reduction circuit provided by this invention addresses computational processes such as random support set generation in the HQC algorithm, uniformly supporting modular reduction operations based on Barrett's principle and interval reduction operations based on multiplication mapping. The reduction circuit uses wide-bit integer multiplication as its core arithmetic unit, achieving computational multiplexing under various mode selection signals by configuring multiplication operands and selecting and combining different bit segments of the multiplication result. Compared to configuring independent arithmetic units for different reduction algorithms, the configurable reduction circuit in this invention achieves efficient reuse of wide-bit multiplication resources while ensuring the correctness of HQC algorithm reduction operations, significantly reducing the overall hardware area and implementation complexity, especially saving half of the DSP resources. It is suitable for use as a general-purpose reduction circuit for the HQC algorithm in FPGA or ASIC platforms.
[0050] The technical features of the embodiments described above can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that the terms "in one embodiment," "for example," and "again" in this invention are intended to illustrate the invention and are not intended to limit the invention.
[0051] The embodiments described above are merely examples of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention.
Claims
1. A configurable reduction circuit for integer operations in post-quantum cryptography algorithms, characterized in that, It is equipped with: a first integer input terminal, a second integer input terminal, a third integer input terminal, a security level input terminal, a mode selection input terminal, and a reduced integer output terminal; The configurable reduction circuit is used to receive an 8-bit integer index value input from the first integer input terminal, a 24-bit random integer input from the second integer input terminal, a 32-bit random integer input from the third integer input terminal, a 2-bit security level signal input from the security level input terminal, and a 1-bit mode selection signal input from the mode selection input terminal, and selects the corresponding 16-bit intermediate parameter n and 18-bit intermediate parameter n based on the 2-bit security level signal input from the security level input terminal. u Based on the 1-bit mode selection signal, one of the two reduced paths is selected using 16-bit intermediate parameters n and 18-bit intermediate parameters n. u The reduction process yields a 16-bit modulo-reduced result, which is then output via the reduced integer output terminal. Based on the security level signal, select the corresponding intermediate parameter n and the matching Barrett reduction pre-calculation parameter n from multiple sets of pre-stored constants. u ;n u It is the multiplication constant corresponding to the intermediate parameter n; The 8-bit integer index value and its corresponding 32-bit random integer form the first reduction path, which is an interval reduction path based on multiplication mapping. The 24-bit random integer forms the second reduction path, which is a modular reduction path based on Barrett's principle.
2. The configurable reduction circuit for integer operations in post-quantum cryptography algorithms as described in claim 1, characterized in that, include: The first configurable multiplier has a first a1 input terminal, a2 input terminal, a1 input terminal, and a2 input terminal, which are respectively used to input the high 16 bits and 18 bits of the intermediate parameter n of a 24-bit random integer and a 32-bit random integer. u And the difference between the 16-bit intermediate parameter n and the 8-bit integer index value; the first configurable multiplier is used to multiply the first a1 input and the first b1 input or the first a2 input and the first b2 input to obtain the first multiplication result, and output it; The second configurable multiplier has four input terminals: second a1, second a2, second b1, and second b2. These are used to input the high 10 bits of the lower 42 bits of the first multiplication result, the lower 16 bits of the 32-bit random integer, the 16-bit intermediate parameter n, and the difference between the 16-bit intermediate parameter n and the 8-bit integer index value. The second configurable multiplier is used to multiply the second a1 input terminal and the second b1 input terminal or to multiply the second a2 input terminal and the second b2 input terminal to obtain the second multiplication result, and then outputs it. A post-processing component is used to obtain a first processing result and a second processing result, and select one of them for output; wherein, the first processing result is one of the differences between a 24-bit random integer and the lower 26 bits of the second multiplication result, and the difference obtained by subtracting the first difference from the 16-bit intermediate parameter n; if the first difference is greater than or equal to the 16-bit intermediate parameter n, then the first processing result is the second difference, otherwise it is the first difference; the second processing result is the sum of the sum of the higher 16 bits of the lower 32 bits of the second multiplication result and the lower 32 bits of the first multiplication result, shifted 16 bits to the right, and the sum of the 8-bit integer index value.
3. The configurable reduction circuit for integer operations in post-quantum cryptography algorithms as described in claim 2, characterized in that, Also includes: The decision unit, connected to the second integer input terminal and the first a1 input terminal, is used to determine whether the 24-bit random integer is less than... If the value is less than a certain value, it is transmitted to the first input terminal a1, where n is a 16-bit intermediate parameter. This is the floor symbol.
4. The configurable reduction circuit for integer operations in post-quantum cryptography algorithms as described in claim 2, characterized in that, The post-processing component includes: A first processing unit, configured to generate the first processing result, includes: a first subtractor, a second subtractor, a comparator, and a selector; the first subtractor is configured to subtract the lower 26 bits of a 24-bit random integer from the second multiplication result; the second subtractor is configured to subtract the difference from a 16-bit intermediate parameter n; the comparator is configured to determine the relationship between the second difference and the 16-bit intermediate parameter n; the selector is configured to output the second difference if the first difference is greater than or equal to the 16-bit intermediate parameter n, and otherwise output the first difference. The second processing unit, used to generate the second processing result, includes: a first shifter, a second shifter, a first adder, and a second adder; the first shifter is used to right-shift the lower 32 bits of the second multiplication result by 16 bits; the first adder is used to add the higher 16 bits of the lower 32 bits of the second multiplication result to the lower 32 bits of the first multiplication result; the second shifter is used to right-shift the output of the first adder by 16 bits; and the second adder is used to add the output of the second shifter to an 8-bit integer index value.
5. The configurable reduction circuit for integer operations in post-quantum cryptography algorithms as described in claim 2, characterized in that, The first configurable multiplier includes: The first selector is used to connect the first input terminal a1 and the first input terminal a2, and select one of them for output; The second selector is used to connect the first input terminal b1 and the first input terminal b2, and select one of them for output; The first multiplier is used to multiply the output of the first selector and the output of the second selector and then output the result.
6. The configurable reduction circuit for integer operations in post-quantum cryptography algorithms as described in claim 5, characterized in that, The first configurable multiplier includes: The third selector is used to connect the second input terminal a1 and the second input terminal a2, and select one of them for output; The fourth selector is used to connect the second input terminal b1 and the second input terminal b2, and select one of them for output; The second multiplier is used to multiply the output of the third selector and the output of the fourth selector and then output the result.
7. The configurable reduction circuit for integer operations in post-quantum cryptography algorithms as described in claim 1, characterized in that, It also includes multiple registers for storing data at each input.