Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises n device unit layers which are arranged in a stacked mode, each device unit layer comprises a substrate and a plurality of semiconductor layers located on the substrate, and the semiconductor layers extend in the direction perpendicular to the substrate; the semiconductor device further comprises a plurality of connecting parts, and each device unit layer except the nth device unit layer comprises at least one connecting part. The connecting part is located between the substrates of the adjacent device unit layers, one end of the connecting part is connected with the semiconductor layer of the ith device unit layer in the direction perpendicular to the substrate, and the other end of the connecting part is connected with the substrate of the (i + 1) th device unit layer; wherein n is an integer larger than or equal to 2, i is an integer larger than or equal to 1 and smaller than or equal to n-1, and the integration density, quality and the like of the semiconductor device can be improved.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily, while the types and number of devices contained in a single chip are increasing. This means that even minor differences in the manufacturing process can affect device performance. To minimize product costs, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands.

[0003] As the demand for memory continues to increase, the requirement for miniaturization of device size is becoming increasingly stringent. However, due to limitations in existing structures and processes, miniaturization of device size faces numerous challenges. Summary of the Invention

[0004] This disclosure provides a semiconductor device and its fabrication method, as well as an electronic device, which can solve the problems of large footprint, high production cost, low integration density, and poor integration quality of existing semiconductor devices.

[0005] On one hand, embodiments of this disclosure provide a semiconductor device, including n device unit layers stacked together, each device unit layer including a substrate and a plurality of semiconductor layers located on the substrate, the semiconductor layers extending in a direction perpendicular to the substrate; The semiconductor device further includes a plurality of connection components, and each device unit layer, except for the nth device unit layer, contains at least one of the connection components. The connecting component is located between the substrates of adjacent device unit layers. Along a direction perpendicular to the substrate, one end of the connecting component is connected to the semiconductor layer of the i-th device unit layer, and the other end of the connecting component is connected to the substrate of the (i+1)-th device unit layer. Where n is an integer greater than or equal to 2, and i is an integer greater than or equal to 1 and less than or equal to n-1.

[0006] In some exemplary embodiments, the connecting component, the semiconductor layer, and the substrate connected to the connecting component contain the same semiconductor material.

[0007] In some exemplary embodiments, the semiconductor device further includes a plurality of vias, at least one of the vias being located between the semiconductor layer and the substrate remote from the semiconductor layer, and the via exposing a portion of the semiconductor layer, the connection member being located within the via and connected to the semiconductor layer.

[0008] In some exemplary embodiments, in a direction perpendicular to the substrate, the orthographic projection of the connecting member on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate.

[0009] In some exemplary embodiments, the semiconductor layers of each device unit layer are arranged in an array in a direction parallel to the substrate, and the connecting component is connected to the semiconductor layer at the center of the device unit layer.

[0010] In some exemplary embodiments, the semiconductor device further includes an isolation layer through which the connection member extends in a direction perpendicular to the substrate.

[0011] In some exemplary embodiments, the semiconductor layer includes a first electrode, a channel layer, and a second electrode along a direction perpendicular to the substrate; The connecting component is connected to the first pole or the second pole; The sidewalls of the channel layer are surrounded by gate electrodes.

[0012] In some exemplary embodiments, the semiconductor device further includes: Multiple word lines, each word line extending along a second direction parallel to the substrate, the multiple word lines being spaced apart in a first direction parallel to the substrate, and multiple gate electrodes spaced apart along the second direction parallel to the substrate being connected to the same word line; Multiple bit lines, each extending along a first direction parallel to the substrate, the multiple bit lines being spaced apart along a second direction parallel to the substrate, and the second poles or first poles of multiple semiconductor layers spaced apart along the first direction parallel to the substrate being connected to the same bit line.

[0013] In some exemplary embodiments, each of the device unit layers includes a plurality of memory cells, and each memory cell includes a contact portion, the semiconductor layer, and a capacitor; The capacitor is connected to the semiconductor layer via the contact portion.

[0014] In some exemplary embodiments, the material of the contact portion includes heavily doped polymers and / or heavily doped polycrystalline silicon.

[0015] On the other hand, this disclosure provides a method for fabricating a semiconductor device, the semiconductor device comprising n stacked device unit layers, each device unit layer comprising a substrate and a plurality of semiconductor layers located on the substrate, the semiconductor layers extending in a direction perpendicular to the substrate; wherein n is an integer greater than or equal to 2; the fabrication method includes: Multiple semiconductor layers are formed on the substrate of the i-th device unit layer; At least one connection component is formed based on the plurality of semiconductor layers; The substrate upon which the (i+1)th device unit layer is formed based on the at least one connecting component; Along a direction perpendicular to the substrate, one end of the connecting member is connected to the semiconductor layer of the i-th device unit layer, and the other end of the connecting member is connected to the substrate of the (i+1)-th device unit layer; where i is an integer greater than or equal to 1 and less than or equal to n-1.

[0016] In some exemplary embodiments, forming at least one connection component based on the plurality of semiconductor layers includes: At least one via is formed, the at least one via extending in a direction perpendicular to the substrate, and the via exposing at least one portion of the semiconductor layer; The connecting component is formed within the via using a selective epitaxial process.

[0017] In some exemplary embodiments, the temperature range of the selective epitaxial process is between 300 degrees Celsius and 400 degrees Celsius.

[0018] In some exemplary embodiments, the substrate for forming the (i+1)th device unit layer based on the at least one connection member includes: An amorphous semiconductor material is deposited on the side of the substrate away from the i-th device unit layer of the connecting component; Irradiation with a laser device causes the amorphous semiconductor material to crystalline semiconductor material to form the substrate of the (i+1)th device unit layer.

[0019] On the other hand, embodiments of this disclosure provide an electronic device, including the semiconductor device described in any of the foregoing embodiments, or including a semiconductor device formed by the preparation method described in any of the foregoing embodiments.

[0020] The semiconductor device provided in this disclosure can achieve the stacking of multiple device unit layers by setting a connection component between the substrates of two adjacent device unit layers, thus solving the problems of large area occupation, high production cost, low integration density and poor integration quality of existing semiconductor devices.

[0021] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0022] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0023] Figure 1 This is a schematic diagram of the three-dimensional structure of a semiconductor device according to an embodiment of the present disclosure; Figure 1A This is a top view schematic diagram of a partial semiconductor device according to an embodiment of the present disclosure; Figure 2A and Figure 2B This is a schematic diagram of a semiconductor device after a conductive structure has been formed according to an embodiment of the present disclosure; Figure 3A and Figure 3B This is a schematic diagram of a semiconductor device after the formation of a first dielectric thin film according to an embodiment of the present disclosure; Figure 4A and Figure 4B This is a schematic diagram of a semiconductor device after trenching according to an embodiment of the present disclosure; Figure 5 This is a three-dimensional structural diagram of a semiconductor device after the formation of a second dielectric thin film according to an embodiment of the present disclosure; Figure 6 This is a three-dimensional structural diagram of a semiconductor device after the formation of the second dielectric layer according to an embodiment of the present disclosure; Figure 7 This is a three-dimensional structural diagram of a semiconductor device after a gate metal thin film has been formed, according to an embodiment of the present disclosure. Figure 8A , Figure 8B as well as Figure 8C This is a schematic diagram of a semiconductor device after the gate electrode has been formed according to an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the three-dimensional structure of a semiconductor device after a third dielectric thin film has been formed, according to an embodiment of the present disclosure. Figure 10 This is a cross-sectional view of a semiconductor device after a first through-hole has been formed, according to an embodiment of this disclosure. Figure 11 This is a cross-sectional schematic diagram of a semiconductor device after the contact portion has been formed according to an embodiment of the present disclosure; Figure 12 This is a schematic cross-sectional view of a semiconductor device after forming a capacitor according to an embodiment of the present disclosure; Figure 13 This is a cross-sectional view of a semiconductor device after a second via has been formed, according to an embodiment of the present disclosure. Figure 14 This is a cross-sectional schematic diagram of a semiconductor device after the interconnection component has been formed according to an embodiment of the present disclosure; Figure 15 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present disclosure after forming an amorphous semiconductor material; Figure 16 This is a schematic cross-sectional view of a semiconductor device after the second substrate has been formed, according to an embodiment of the present disclosure. Figure 17 This is a cross-sectional schematic diagram of a semiconductor device after the second device unit layer has been formed according to an embodiment of the present disclosure. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0025] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0026] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0027] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0028] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0029] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0030] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0031] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0032] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0033] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0034] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0035] Memory is a storage device used to store information in modern information technology. With the development of technology, the types of memory have become increasingly diverse, such as dynamic random access memory (DRAM), magnetic random access memory (MRAM), and static random access memory (SRAM).

[0036] With the ever-increasing demand for DRAM, DRAM manufacturers are actively pursuing the next stage of expansion. However, as memory cells approach their physical limits, DRAM R&D is facing even more severe challenges. DRAM architecture employing vertical channel transistors (VCTs) is one of the best candidate technologies for miniaturized DRAM products. Further miniaturization requires 3D stacked memory with VCTs. This 3D memory structure is difficult to achieve using traditional processes, mainly due to two issues: 1. How to grow a high-quality substrate on top of the memory cells; 2. Process compatibility issues with low thermal budgets.

[0037] This disclosure provides a semiconductor device comprising n stacked device unit layers, each device unit layer including a substrate and a plurality of semiconductor layers located on the substrate, the semiconductor layers extending in a direction perpendicular to the substrate; the semiconductor device further includes a plurality of connecting components, each device unit layer except the nth device unit layer including at least one connecting component; the connecting components are located between the substrates of adjacent device unit layers, in a direction perpendicular to the substrate, one end of the connecting component is connected to the semiconductor layer of the i-th device unit layer, and the other end of the connecting component is connected to the substrate of the (i+1)-th device unit layer; wherein, n is an integer greater than or equal to 2, and i is an integer greater than or equal to 1 and less than or equal to n-1.

[0038] The semiconductor device provided in this disclosure has the advantages of small footprint, low production cost and high integration density. By setting up connecting components, a substrate with a high-quality i+1th device unit layer can be obtained, which can improve the integration quality of the semiconductor device.

[0039] Figure 1 This is a schematic diagram of a three-dimensional structure of a semiconductor device according to an embodiment of this disclosure. Figure 1As shown, in this embodiment of the disclosure, three directions are defined: a first direction X, a second direction Y, and a third direction Z. The first direction X, the second direction Y, and the third direction Z can be mutually perpendicular. The semiconductor device 100 may include n device unit layers stacked together, where n is an integer greater than or equal to 2. Each device unit layer includes a substrate and multiple semiconductor layers located on the substrate. Figure 1 The example provided illustrates a semiconductor device 100 comprising three device unit layers. However, this disclosure does not limit the number of device unit layers included in the semiconductor device. The semiconductor device comprises three device unit layers, which may be referred to as the first device unit layer 101, the second device unit layer 102, and the third device unit layer 103, respectively. In some examples, the device unit layers may serve as logic circuits. In embodiments of this disclosure, the substrate included in the first device unit layer is also referred to as the first substrate, the substrate included in the second device unit layer is also referred to as the second substrate, and the substrate included in the third device unit layer is also referred to as the third substrate.

[0040] The first device unit layer 101 may include a first substrate 10 and at least two memory cells located on the first substrate 10. Each memory cell includes a transistor 20. The plane containing the first substrate 10 is parallel to the plane formed by the first direction X and the second direction Y. For example, the first device unit layer 101 may include two memory cells, or the first device unit layer 101 may include three memory cells, or the first device unit layer 101 may include five memory cells, etc. In this embodiment of the present disclosure, nine memory cells are included as an example of the first device unit layer. However, the present disclosure does not limit the number of memory cells included in the device unit layer. Multiple transistors 20 in the same device unit layer may be arranged in an array, for example, multiple transistors 20 may be arranged in a rectangular array, etc. The structures of the second device unit layer 102 and the third device unit layer 103 may be the same as the structure of the first device unit layer 101.

[0041] In some exemplary embodiments, such as Figure 1 As shown, the first device cell layer 101 may further include at least one word line WL and at least one bit line BL. For example, the first device cell layer 101 may include one word line WL and one bit line BL, or the first device cell layer 101 may include two word lines WL and two bit lines BL, etc. In this embodiment of the disclosure, a device cell layer including three word lines and three bit lines is taken as an example. However, this disclosure does not limit the number of word lines and bit lines included in the device cell layer.

[0042] Within the first device cell layer 101, bit lines BL are closer to the first substrate 10 than word lines WL. Multiple bit lines BL can extend uniformly along a first direction X, and are spaced apart along a second direction Y. For example, multiple bit lines BL can be arranged at equal intervals along the second direction Y. Multiple word lines WL can also extend uniformly along the second direction Y, and are spaced apart along the first direction X. For example, multiple word lines WL can be arranged at equal intervals along the first direction X.

[0043] In some exemplary embodiments, such as Figure 1 As shown, the first device cell layer 101 may include at least one row of memory cells, and each row of memory cells may include multiple transistors 20. The multiple transistors 20 located within the same row of memory cells may be arranged at intervals along a first direction X and may be connected to the same bit line BL. For example, as... Figure 1 As shown, the first device cell layer 101 includes three rows of memory cells, and each row of memory cells includes three transistors.

[0044] In some exemplary embodiments, such as Figure 1 As shown, the first device cell layer 101 may include at least one memory cell column, and the memory cell column may include multiple transistors 20. Multiple transistors 20 located within the same memory cell column may be arranged at intervals along the second direction Y and may be connected to the same word line WL. For example, as... Figure 1 As shown, the first device cell layer 101 includes three memory cell columns, each of which includes three transistors.

[0045] In some exemplary embodiments, such as Figure 1 As shown, transistor 20 may include a semiconductor layer 20a and a gate electrode 24. Semiconductor layer 20a may include a first electrode 21, a second electrode 22, and a channel layer 23. Semiconductor layer 20a may extend in a third direction Z. The first electrode 21 and the second electrode 22 may be located at opposite ends of the channel layer 23 in the third direction Z. For example, the first electrode 21 may be closer to the first substrate 10 than the second electrode 22.

[0046] The gate electrode 24 may surround the sidewall of the channel layer 23 and is insulated from the channel layer 23 via a gate insulating layer. Figure 1 The gate insulating layer is not shown. In the embodiments of this disclosure, the first electrode, the second electrode, the channel layer, and the gate electrode can form a vertical channel transistor, which is beneficial for forming a 3D stacked semiconductor structure. This can reduce the footprint of the semiconductor device, reduce production costs, increase integration density, and improve the short-channel effect of the transistor by changing the length of the channel layer (that is, the dimension along the third direction), thereby improving the performance of the semiconductor device.

[0047] In some exemplary embodiments, such as Figure 1 As shown, the semiconductor device 100 may further include at least one connection member 39, with each device unit layer except the nth device unit layer containing at least one connection member 39. The number of connection members contained in each device unit layer except the nth device unit layer may be the same or different. The second device unit layer 102 may include a second substrate 10b. For example, one connection member 39 may be located between the first substrate 10 and the second substrate 10b, or two connection members 39 may be located between the first substrate 10 and the second substrate 10b, etc. In the embodiments of this disclosure, the number of connection members between the substrates of two adjacent device unit layers is not limited. The connection member 39 includes a first end and a second end disposed opposite to each other. The first end may contact the semiconductor layer 20a, and the second end may contact the second substrate 10b. The materials of the semiconductor layer, the connection member, and the second substrate may all include the same semiconductor material, which can improve the quality of the second substrate, thereby improving the stacking quality of the semiconductor device.

[0048] In some exemplary embodiments, such as Figure 1 As shown, the third device unit layer 103 may include a third substrate 10c. For example, one connection member 39 may be located between the second substrate 10b and the third substrate 10c, or two connection members 39 may be located between the second substrate 10b and the third substrate 10c, etc. The connection member 39 includes a first end and a second end disposed opposite to each other. The first end may contact the semiconductor layer of a transistor in the second device unit layer 102, and the second end may contact the third substrate 10c.

[0049] In some exemplary embodiments, a plurality of transistors within the first device unit layer are arranged in an array, and the orthographic projection of the connection member 39 onto the plane of the first substrate 10 at least partially overlaps with the orthographic projection of the semiconductor layer of the transistor located at the middle position within the first device unit layer onto the plane of the first substrate 10. For example, the orthographic projection of the connection member 39 onto the plane of the first substrate 10 includes the orthographic projection of the semiconductor layer of the transistor located at the middle position within the first device unit layer onto the plane of the first substrate 10.

[0050] Figure 1A This is a partial top view of a semiconductor device according to an embodiment of the present disclosure. Figure 1AThe diagram only illustrates the first device unit layer and the connecting member 39 included in the first device unit layer. The first device unit layer includes nine transistors, and the nine semiconductor layers 20a of the nine transistors are arranged in a rectangular array. The orthographic projection of the connecting member 39 onto the plane of the first substrate 10 at least partially overlaps with the orthographic projection of the semiconductor layer 20a of the transistor located in the middle of the nine transistors onto the plane of the first substrate 10. For example, the orthographic projection of the connecting member 39 onto the plane of the first substrate 10 covers the orthographic projection of the semiconductor layer 20a of the transistor located in the middle of the first substrate 10, which is beneficial for forming a flatter second substrate and can improve the quality of the second substrate.

[0051] The following examples illustrate the structure of semiconductor devices through the fabrication process of semiconductor devices. The "patterning process" described in the embodiments of this disclosure includes at least one of the following processes for metallic, inorganic, or transparent conductive materials: coating with photoresist, mask exposure, development, etching, and photoresist stripping. For organic materials, it includes at least one of the following processes: coating with organic material, mask exposure, and development. The deposition process can be any one or more of sputtering, evaporation, and chemical vapor deposition; the coating process can be any one or more of spraying, spin coating, and inkjet printing; and the etching process can be any one or more of dry etching and wet etching. This disclosure does not limit the process.

[0052] The fabrication process of a semiconductor device may include forming multiple semiconductor layers on a substrate of the i-th device unit layer, forming at least one interconnecting component based on the multiple semiconductor layers, and forming a substrate of the (i+1)-th device unit layer based on the at least one interconnecting component. Here, i is an integer greater than or equal to 1 and less than or equal to n-1. In this embodiment, the fabrication process of the semiconductor device is illustrated using n=2 as an example.

[0053] Forming multiple semiconductor layers on the substrate of the first device unit layer may include the following steps: (01) A plurality of conductive structures 30 are formed on one side of the first substrate 10, and a plurality of first accommodating spaces 41 are formed, such as Figure 2A , Figure 2B As shown, Figure 2A This is a schematic diagram of the three-dimensional structure of a semiconductor device after the conductive structure has been formed. Figure 2B This is a top view schematic diagram of a semiconductor device after the conductive structure has been formed. For example, a semiconductor device is shown to have four conductive structures 30. The conductive structures 30 are configured to form a semiconductor layer containing bit lines and at least one transistor in subsequent processes. A first substrate can provide support for other components in the first device cell layer; for example, other components may include transistors, bit lines, word lines, and capacitors.

[0054] The orthographic projection of the conductive structure 30 onto the plane of the first substrate 10 can be a rectangle extending along the first direction X. Four conductive structures 30 can be arranged at intervals along the second direction Y. For example, two adjacent conductive structures 30 and the first substrate 10 can form a first receiving space 41, or the end of the conductive structure 30 along the first direction X can form a first receiving space 41 with the first substrate 10, or a conductive structure 30 located at the edge along the second direction Y can form a first receiving space 41 with the first substrate 10, etc.

[0055] In some exemplary embodiments, forming a plurality of conductive structures 30 may include: depositing a thin film on a first substrate 10 and employing a patterning process on the thin film to form a plurality of conductive structures 30 and a plurality of first accommodating spaces 41. For example, the patterning process may include at least one of dry etching and wet etching. For example, the deposition process may include atomic layer deposition (ALD) or chemical vapor deposition (CVD), etc.

[0056] In some exemplary embodiments, the material of the first substrate 10 may include monocrystalline silicon or the like.

[0057] In some exemplary embodiments, the material of the conductive structure 30 may include single-crystal silicon, which can give the transistor advantages such as high mobility, high reliability, and few defects.

[0058] In some exemplary embodiments, the first substrate 10 may be a composite layer structure. For example, the first substrate 10 may include a first sub-substrate and a second sub-substrate. For example, the first sub-substrate and the second sub-substrate may be stacked sequentially, or at least a portion of the first sub-substrate may be embedded within the second sub-substrate.

[0059] In some exemplary embodiments, the silicon substrate may be p-type doped to form a p-type well and a first substrate. The p-type well can prevent bit lines formed in subsequent processes from directly contacting the first substrate. The p-type well can also act as an isolation layer, preventing leakage and improving the performance of the semiconductor device.

[0060] (02) A first dielectric film 31 is formed on the first substrate 10 forming the aforementioned structure, and the first dielectric film 31 fills within a plurality of first accommodating spaces 41, such as Figure 3A , Figure 3B As shown, Figure 3A This is a schematic diagram of the three-dimensional structure of a semiconductor device after the formation of the first dielectric thin film. Figure 3BThis is a top view of the semiconductor device after the first dielectric thin film has been formed. The orthographic projection of the first dielectric thin film 31 onto the plane of the first substrate 10 does not overlap with the orthographic projection of the plurality of conductive structures 30 onto the plane of the first substrate 10. That is, the surface of the plurality of conductive structures 30 away from the first substrate 10 is not covered by the first dielectric thin film 31.

[0061] In some exemplary embodiments, the material of the first dielectric thin film 31 may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO) x ) or hafnium oxide (HfO) x At least one of the following:

[0062] In some exemplary embodiments, forming the first dielectric thin film 31 may include: depositing a dielectric thin film on a first substrate 10 on which the aforementioned structure is formed, and subsequently performing a planarization process on the first substrate 10 on which the aforementioned structure is formed. The planarization process can remove the dielectric thin film located on the side of the plurality of conductive structures 30 away from the first substrate 10. For example, the planarization process may include chemical mechanical polishing (CMP). For example, the deposition process may include atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0063] (03) A plurality of trenches 40 are formed on the first substrate 10 forming the aforementioned structure, such as Figure 4A , Figure 4B As shown, Figure 4A This is a schematic diagram of the three-dimensional structure of a semiconductor device after trenching. Figure 4B This is a top view of a semiconductor device after trenches have been formed. For example, five trenches 40 can be formed on the first substrate 10 where the aforementioned structure is formed.

[0064] Multiple trenches 40 extend along the second direction Y and are spaced apart along the first direction X. The orthographic projection of the trenches 40 onto the plane of the first substrate 10 can be a rectangle extending along the second direction Y. The first dielectric film and conductive structure located within the trenches 40 are etched away to form multiple semiconductor layers 20a. Each semiconductor layer includes a first electrode, a second electrode, and a channel layer. Exemplarily, along a third direction Z perpendicular to the substrate, the first electrode, channel layer, and second electrode are distributed sequentially. For example, along the third direction Z perpendicular to the substrate, the second electrode is located on the side of the channel layer away from the substrate, and the first electrode is located on the side of the channel layer closer to the substrate. In other embodiments, the side of the channel layer away from the substrate may be the first electrode, and the side of the channel layer closer to the substrate may be the second electrode. This application does not limit this. Multiple bit lines BL are formed based on the trenches 40, and the multiple semiconductor layers 20a formed by the same conductive structure are interconnected with the same bit line BL extending along the first direction. For example, the same conductive structure can form four semiconductor layers 20a.

[0065] In some exemplary embodiments, after forming a plurality of trenches 40 on the first substrate 10 forming the aforementioned structure, a metal material is subsequently deposited and annealed. Single-crystal silicon reacts with the metal material to form metal silicides, which are then etched to form a plurality of bit lines. The bit lines extend along a first direction and are spaced apart in a second direction. The metal material can be TiN, Ni, Cu, Co, etc., and this application does not impose any limitations on this.

[0066] In some exemplary embodiments, an etching process may be used to form a plurality of trenches 40. For example, the etching process may include at least one of dry etching and wet etching.

[0067] In some exemplary embodiments, the orthographic projection of the semiconductor layer 20a onto the plane of the first substrate 10 can be a square or a rectangle, etc. This disclosure does not limit the shape of the orthographic projection of the semiconductor layer onto the plane of the substrate.

[0068] (04) A second dielectric film 32 is formed on the first substrate 10 forming the aforementioned structure, and the second dielectric film 32 fills within the plurality of trenches 40, such as Figure 5 As shown, Figure 5 A schematic diagram of the three-dimensional structure of a semiconductor device after the formation of the second dielectric thin film.

[0069] In some exemplary embodiments, forming the second dielectric film 32 may include: forming a dielectric film on the first substrate 10 on which the aforementioned structure is formed using a process such as atomic layer deposition (ALD), and then planarizing the dielectric film using a process such as chemical mechanical polishing (CMP) to form the second dielectric film 32.

[0070] In some exemplary embodiments, the thickness H1 of the second dielectric film 32 can range from 3.0 nanometers to 8.0 nanometers.

[0071] In some exemplary embodiments, the surface of the second dielectric film 32 away from the first substrate 10 may be flush with the surface of the semiconductor layer 20a away from the first substrate 10, or the surface of the second dielectric film 32 away from the first substrate 10 may extend beyond the surface of the semiconductor layer 20a away from the first substrate 10 by 1.0 nm to 3.0 nm. For example, the surface of the second dielectric film 32 away from the first substrate 10 may extend beyond the surface of the semiconductor layer 20a away from the first substrate 10 by 2.0 nm. In the embodiments of this disclosure, setting the second dielectric film to extend beyond the surface of the semiconductor layer away from the first substrate is beneficial for controlling the height difference between the second dielectric layer and the semiconductor layer in subsequent processes, and can avoid electrical crosstalk between two adjacent transistors.

[0072] In some exemplary embodiments, the material of the second dielectric film 32 may be the same as or different from the material of the first dielectric film 31. The material of the second dielectric film 32 may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO) x ) or hafnium oxide (HfO) x At least one of the following:

[0073] (05) The first substrate 10 forming the aforementioned structure is patterned using a patterning process, such that the second dielectric film 32 forms the second dielectric layer 33 and the first dielectric film 31 forms the first dielectric layer 34, as shown below. Figure 6 As shown, Figure 6 This is a schematic diagram of the three-dimensional structure of a semiconductor device after the formation of the second dielectric layer. For example, the patterning process may include etching processes, etc. The first dielectric layer 34 and the second dielectric layer 33 can prevent electrical crosstalk between adjacent transistors, thereby improving the operating performance of the semiconductor device.

[0074] In some exemplary embodiments, patterning the first substrate 10 forming the aforementioned structure using a patterning process further includes forming a plurality of second accommodating spaces 42, wherein the first dielectric film located within the second accommodating spaces 42 is etched away. For example, the orthographic projection of the second accommodating space 42 onto the plane of the first substrate 10 can be a rectangle extending along the second direction Y.

[0075] In some exemplary embodiments, the orthographic projection of the semiconductor layer 20a onto the plane of the first substrate 10 lies within the orthographic projection of the second accommodating space 42 onto the plane of the first substrate 10, and the edge of the orthographic projection of the semiconductor layer 20a onto the plane of the first substrate 10 does not overlap with the edge of the orthographic projection of the second accommodating space 42 onto the plane of the first substrate 10. This facilitates the formation of a space between the semiconductor layer 20a and the second dielectric layer 33 for accommodating the gate electrode and gate insulating layer formed in subsequent processes, thereby forming an annular gate electrode surrounding the transistor channel layer. For example, only a portion of the semiconductor layer 20a is etched away, or only a portion of the second dielectric layer 33 is etched away, or both portions of the semiconductor layer 20a and the second dielectric layer 33 are etched away (see subsequent examples). Figure 8C (As shown).

[0076] In some exemplary embodiments, the surface of the first dielectric layer 34 away from the first substrate 10 has a first height h1 along the third direction Z between it and the first substrate 10; the surface of the second dielectric layer 33 away from the first substrate 10 has a second height h2 along the third direction Z between it and the first substrate 10; and the surface of the semiconductor layer 20a away from the first substrate 10 has a third height h3 along the third direction Z between it and the first substrate 10. h3 may be greater than h2, and h2 may be greater than h1. In some possible examples, h3 may be equal to h2.

[0077] (06) A gate metal thin film 35 is formed on the first substrate 10 on which the aforementioned structure is formed, such as Figure 7 As shown, Figure 7 This is a three-dimensional structural diagram of a semiconductor device after a gate metal thin film has been formed. The gate metal thin film 35 fills within a plurality of second receiving spaces 42, and the surface of the gate metal thin film 35 away from the first substrate 10 can be planar. For example, the gate metal thin film 35 may cover the surface of the semiconductor layer 20a away from the first substrate 10, and the gate metal thin film 35 may cover the surface of the second dielectric layer 33 away from the first substrate 10. The gate metal thin film 35 is configured to form at least one gate electrode via subsequent processes.

[0078] In some exemplary embodiments, forming the gate metal thin film 35 on the first substrate 10 forming the aforementioned structure may further include forming a gate insulating film prior to forming the gate metal thin film 35. For example, the orthographic projection of the gate insulating film onto the plane of the first substrate 10 may surround the orthographic projection of the semiconductor layer 20a onto the plane of the first substrate 10. The gate insulating film is configured to form at least one gate insulating layer via subsequent processes, which can be used to achieve insulation between the gate electrode and the channel layer.

[0079] In some exemplary embodiments, the material of the gate metal film 35 may include a metallic material. For example, the metallic material may include at least one of tungsten (W), molybdenum (Mo), cobalt (Co), titanium (Ti), copper (Cu), aluminum (Al), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), silver (Ag), or gold (Au), or an alloy of the above metals. The gate metal film 35 may be a single-layer or multi-layer structure. For example, the gate metal film 35 may be a multi-layer structure formed of titanium nitride (TiN) and tungsten (W). Alternatively, the gate metal film 35 may be a single-layer structure formed of tungsten (W).

[0080] In some exemplary embodiments, the material of the gate insulating film may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO) x ) or hafnium oxide (HfO) x At least one of the following: For example, the gate insulating film material may include a low-K dielectric material, i.e., a dielectric material with a dielectric constant K < 3.9, such as silicon dioxide (SiO2). Alternatively, the gate insulating film material may include a high dielectric constant material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. For example, a high dielectric constant material may include at least one of hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), and strontium titanate (SrTiO3). Using a high dielectric constant material for the gate insulating film can improve the insulation performance between the channel layer and the gate electrode of the transistor, thereby improving the electrical performance of the semiconductor device.

[0081] (07) The first substrate 10 forming the aforementioned structure is patterned using a patterning process, such that at least a plurality of gate electrodes 24 are formed in the gate metal thin film 35, and at least a plurality of gate insulating layers 25 are formed in the gate insulating thin film, exposing a portion of the semiconductor layer 20a and the surface of the second dielectric layer 33 away from the first substrate 10, such as... Figure 8A , Figure 8B as well as Figure 8C As shown, Figure 8A This is a schematic diagram of the three-dimensional structure of a semiconductor device after the gate electrode has been formed. Figure 8B This is a top view schematic diagram of a semiconductor device after the gate electrode has been formed. Figure 8C for Figure 8B A cross-sectional view at point AA, where... Figure 8A The gate insulation layer is not shown. Figure 8A In this configuration, the surface of the gate electrode 24 away from the first substrate 10 is flush with the surface of the second dielectric layer 33 away from the first substrate 10. Figure 8C In this configuration, the surface of the gate electrode 24 away from the first substrate 10 is closer to the first substrate 10 than the surface of the second dielectric layer 33 away from the first substrate 10. The gate insulating layer 25 may surround the sidewall of the semiconductor layer 20a, and the gate electrode 24 is disposed around the sidewall of the semiconductor layer 20a and insulated from the semiconductor layer 20a via the gate insulating layer 25.

[0082] In some exemplary embodiments, the plurality of gate electrodes 24 located between two adjacent second dielectric layers 33 can be an integral structure interconnected. The plurality of interconnected gate electrodes 24 can form a word line WL.

[0083] In some exemplary embodiments, such as Figure 8C As shown, there is a step difference H2 along the third direction Z between the surface of the second dielectric layer 33 away from the first substrate 10 and the surface of the gate electrode 24 away from the first substrate 10. H2 can be 10 nanometers or 15 nanometers, etc. However, this disclosure does not limit the value of the step difference H2. By designing this step difference, problems such as short circuits between transistors can be avoided, thereby improving the electrical performance of semiconductor devices.

[0084] In some exemplary embodiments, the surface of the gate electrode 24 away from the first substrate 10 may be flush with the surface of the gate insulating layer 25 away from the first substrate 10.

[0085] In some exemplary embodiments, the semiconductor layer 20a may include a channel layer 23, a first electrode 21, and a second electrode 22 connected to each other, with the first electrode 21 and the second electrode 22 located at opposite ends of the channel layer 23 extending in the direction of extension. The portion of the semiconductor layer 20a surrounded by the gate insulating layer 25 may constitute the channel layer 23. In embodiments of this disclosure, the transistor includes a first electrode 21, a second electrode 22, a channel layer 23, a gate electrode 24, and a gate insulating layer 25.

[0086] (08) A third dielectric thin film 36 is formed on the first substrate 10 that forms the aforementioned structure, such as Figure 9 As shown, Figure 9 This is a three-dimensional structural diagram of a semiconductor device after the formation of a third dielectric thin film. The orthographic projection of the third dielectric thin film 36 onto the plane of the first substrate 10 can cover the orthographic projection of the transistor onto the plane of the first substrate 10. For example, the third dielectric thin film 36 can be formed using atomic layer deposition. For example, the third dielectric thin film 36 can be planarized using chemical mechanical polishing (CMP).

[0087] In some exemplary embodiments, the material of the third dielectric film 36 may be the same as or different from the material of the first dielectric film 31. The material of the third dielectric film 36 may include silicon oxynitride (SiO2). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x ) or aluminum oxide (AlO) x ) or hafnium oxide (HfO) x At least one of the following:

[0088] In some exemplary embodiments, forming the third dielectric film 36 on the first substrate 10 on which the aforementioned structure is formed may further include annealing the first substrate 10 on which the third dielectric film 36 is formed. The annealing process can improve the density of the dielectric film, such as the third dielectric film, and enhance the insulation effect.

[0089] In some exemplary embodiments, the thickness of the third dielectric film 36 may range from 1.0 micrometer to 2.0 micrometer.

[0090] (09) The first substrate 10 forming the aforementioned structure is patterned using a patterning process to form a plurality of first vias K1, such as... Figure 10 As shown, Figure 10This is a cross-sectional view of a semiconductor device after the formation of a first via. For example, the patterning process may include at least one of dry etching and wet etching. The first via K1 and the second electrode 22 can be arranged in pairs. The orthographic projection of the first via K1 onto the plane of the first substrate 10 and the orthographic projection of the second electrode 22 onto the plane of the first substrate 10 can at least partially overlap. For example, the orthographic projection of the first via K1 onto the plane of the first substrate 10 and the orthographic projection of the second electrode 22 onto the plane of the first substrate 10 can overlap. The third dielectric film 36 located within the first via K1 is etched away, exposing a portion of the second electrode 22. The first via K1 is configured to accommodate subsequently formed contacts.

[0091] In some exemplary embodiments, the orthographic projection of the first via K1 onto the plane of the first substrate 10 can be a square, rectangle, circle, ellipse, or hexagon, etc.

[0092] In some exemplary embodiments, the depth of the first through-hole K1 can range from 50 angstroms to 500 angstroms.

[0093] (10) A plurality of contact portions 37 are formed on the first substrate 10 forming the aforementioned structure, such as Figure 11 As shown, Figure 11 This is a cross-sectional view of a semiconductor device after the contact portion has been formed. For example, contact portion 37 can be formed using an atomic layer deposition process. Contact portion 37 is located within a first via K1 and is connected to the second electrode 22. For example, the surface of contact portion 37 away from the first substrate 10 may be flush with the surface of the third dielectric film 36 away from the first substrate 10. Contact portion 37 is configured to connect a subsequently formed capacitor to the second electrode of a transistor.

[0094] In some exemplary embodiments, each memory cell includes a capacitor, a transistor, and a contact portion, and the capacitor located in the same memory cell can be connected to the transistor via the contact portion.

[0095] In some exemplary embodiments, the material of the contact portion 37 may include at least one of heavily doped polymers and heavily doped polycrystalline silicon. For example, the heavily doped polymer may include a highly phosphorus-doped polymer, such as phosphorus-doped carbon nitride (P-C3N4, abbreviated as PCN). In embodiments of this disclosure, by providing the contact portion, the contact resistance between the transistor and the capacitor can be reduced, thereby improving the electrical performance of the semiconductor device. For example, the material of the contact portion 37 may include substances such as metals; this application is not limited in this regard.

[0096] In some exemplary embodiments, high phosphorus doping refers to a phosphorus content greater than or equal to 10. 19For example, the phosphorus content is greater than or equal to 10 per cubic centimeter. 19 10 per cubic centimeter, and less than or equal to 10 24 Items per cubic centimeter.

[0097] (11) A plurality of capacitors 50 are formed on the first substrate 10 on which the aforementioned structure is formed, such as Figure 12 As shown, Figure 12 A cross-sectional view of a semiconductor device after a capacitor has been formed.

[0098] Capacitor 50 and transistor 20 are arranged in a one-to-one correspondence, and capacitor 50 is connected to the second electrode 22 of transistor 20. Capacitor 50 and transistor 20 can be connected via contact portion 37, which includes a first end and a second end arranged opposite to each other along a third direction Z. The first end is connected to capacitor 50, and the second end is connected to the second electrode 22 of transistor 20.

[0099] The capacitor 50 may include a first capacitor plate 51, a second capacitor plate 52, and a dielectric layer 53, with the dielectric layer 53 located between the first capacitor plate 51 and the second capacitor plate 52. The first capacitor plate 51 may be located between the dielectric layer 53 and the first substrate 10. The first capacitor plate 51 is connected to the second electrode 22 of the transistor 20.

[0100] In some exemplary embodiments, the multiple second capacitor plates 52 of the multiple capacitors 50 may be an integral structure interconnected with each other.

[0101] In some exemplary embodiments, the materials of the first capacitor plate 51 and the second capacitor plate 52 may be the same or different. For example, the materials of the first capacitor plate 51 and the second capacitor plate 52 may both be titanium nitride.

[0102] In some exemplary embodiments, the material of the dielectric layer 53 may include zirconium oxide (ZrO) and aluminum oxide (AlO), etc. For example, the dielectric layer 53 may be a stacked structure of ZrO / AlO / ZrO.

[0103] This completes the fabrication of the first device unit layer. In other exemplary embodiments, the device unit layer may not include a capacitor structure.

[0104] Subsequently, at least one connection component is formed based on the aforementioned semiconductor layer. Forming the connection component may include the following steps:

[0105] (21) A fourth dielectric thin film 38 is formed on the first substrate 10 on which the aforementioned structure is formed, and the first substrate 10 on which the fourth dielectric thin film 38 is formed is patterned using a patterning process to form at least one second via K2, such as Figure 13 As shown, Figure 13 This is a cross-sectional view of a semiconductor device after the formation of a second via. For example, the patterning process may include at least one of dry etching and wet etching. In embodiments of this disclosure, the fourth dielectric film may also be referred to as an isolation layer, and the second via may also be referred to as a via.

[0106] The orthographic projection of the second via K2 onto the plane of the first substrate 10 at least partially overlaps with the orthographic projection of the second electrode 22 of at least one transistor 20 onto the plane of the first substrate 10. For example, the orthographic projection of the second via K2 onto the plane of the first substrate 10 includes the orthographic projection of the second electrode 22 of one transistor 20 onto the plane of the first substrate 10. The capacitor 50 and contact 37 located within the second via K2 are etched away, exposing a portion of the second electrode 22 of the transistor 20. The second via K2 is configured to accommodate a connection component formed in a subsequent process. Increasing the area of ​​the second electrode of the transistor exposed by the second via facilitates the subsequent formation of the connection component using selective epitaxial processes, shortening the fabrication cycle and reducing fabrication costs. In a structure with nine transistors on the first substrate, the nine transistors are arranged in a three-row, three-column rectangular configuration, and the orthographic projection of the second via K2 onto the plane of the first substrate 10 includes the orthographic projection of the second electrode 22 located in the middle position onto the plane of the first substrate 10. For example, the center of the orthographic projection of the second via K2 onto the plane of the first substrate 10 coincides with the center of the orthographic projection of the second pole 22 at the middle position onto the plane of the first substrate 10.

[0107] In some exemplary embodiments, the orthographic projection of the second via K2 onto the plane of the first substrate 10 is located at the center of the first substrate 10. For example, the center of the orthographic projection of the second via K2 onto the plane of the first substrate 10 is located on the central axis of the first substrate 10 along a direction perpendicular to its plane. The position of the second via affects the position of the subsequently formed connecting components, which in turn affects the cycle time for forming the second substrate using laser liquid phase epitaxy. Placing the second via as close as possible to the center of the first substrate can shorten the cycle time for forming the second substrate using laser liquid phase epitaxy and improve the flatness of the second substrate. Furthermore, placing the second via as close as possible to the center of the first substrate can improve the stability of the connecting components in supporting the subsequently formed second memory cell.

[0108] In some exemplary embodiments, the shape of the orthographic projection of the second via K2 onto the plane of the first substrate 10 can be a square, a rectangle, a circle, or an ellipse, etc.

[0109] In some exemplary embodiments, the orthographic projection of the plane where the first substrate 10 of the second via K2 is located can completely cover the orthographic projection of the second electrode 22 on the plane where the first substrate 10 is located. In this way, the connecting component subsequently formed in the second via K2 can completely contact the second electrode 22, increasing the contact area between the connecting component and the second electrode, which is beneficial to the formation of the connecting component. In other embodiments, the orthographic projection of the plane where the first substrate 10 of the second via K2 can partially overlap with the orthographic projection of the second electrode 22 on the plane where the first substrate 10 is located. The second substrate can be formed by the semiconductor layer exposed in the second via K2 through liquid phase epitaxy. Even if the connecting component formed in the second via K2 has partial contact with the second electrode 22, this application does not limit this.

[0110] In some exemplary embodiments, the thickness of the fourth dielectric film 38 can range from 200 nanometers to 400 nanometers, which can avoid crosstalk between two adjacent memory cells.

[0111] (22) At least one connecting member 39 is formed on the first substrate 10 forming the aforementioned structure, the connecting member 39 being located within the second through hole K2, such as Figure 14 As shown, Figure 14 This is a cross-sectional view of the semiconductor device after the interconnect component has been formed. The surface of the interconnect component 39 away from the first substrate 10 can be flush with the surface of the second via K2 away from the first substrate 10.

[0112] In some exemplary embodiments, the connecting component 39 may be formed using a selective epitaxial process. The portion of the second electrode 22 exposed by the second via K2 may serve as a seed layer, and a single-crystal silicon may be grown within the second via K2 using a selective epitaxial process; this single-crystal silicon is the connecting component 39.

[0113] In some exemplary embodiments, the temperature range used for selective epitaxy can be from 300 degrees Celsius to 400 degrees Celsius. For example, the temperature used for selective epitaxy can be 350 degrees Celsius.

[0114] Subsequently, a second substrate is formed to create the second device unit layer. Forming the second substrate may include the following steps:

[0115] (31) An amorphous semiconductor material 60 is formed on the first substrate 10 on which the aforementioned structure is formed, such as... Figure 15 As shown, Figure 15This is a cross-sectional schematic diagram showing the formation of an amorphous semiconductor material for a semiconductor device. For example, the amorphous semiconductor material 60 can be formed using a chemical vapor deposition (CVD) process. The orthographic projection of the amorphous semiconductor material 60 onto the plane of the first substrate 10 may include the orthographic projection of the connecting member 39 onto the plane of the first substrate 10. For example, the amorphous semiconductor material 60 may include amorphous silicon. However, this disclosure does not limit the type of amorphous semiconductor material.

[0116] (32) The first substrate 10 forming the aforementioned structure is irradiated using a laser device 70, causing the amorphous semiconductor material 60 to form a crystalline semiconductor material to form the second substrate 10b of the second device unit layer. When the amorphous semiconductor material 60 includes amorphous silicon, laser irradiation can cause the amorphous silicon in the amorphous semiconductor material 60 to recrystallize into monocrystalline silicon, such as... Figure 16 As shown, Figure 16 This is a cross-sectional view of a semiconductor device after the second substrate has been formed.

[0117] In some exemplary embodiments, the power of the laser device 70 can range from 5.5 watts to 6.5 watts, for example, 6.0 watts. The wavelength of the laser emitted by the laser device 70 can range from 530 nanometers to 540 nanometers, for example, 532 nanometers. The pulse width of the laser emitted by the laser device 70 can range from 12 nanoseconds to 14 nanoseconds, for example, 13 nanoseconds. The frequency of the laser emitted by the laser device 70 can range from 45 kHz to 55 kHz, for example, 50 kHz. The transmission rate of the laser emitted by the laser device 70 can range from 20 mm / s to 30 mm / s, for example, 25 mm / s. The projected area of ​​the laser beam formed by the laser emitted by the laser device 70 can range from 87,200 square micrometers to 99,000 square micrometers, for example, a rectangle with a projected shape of 2190.6 micrometers × 42.2 micrometers. The orthographic projection shape of the laser beam formed by the laser emitted by the laser device 70 can be rectangular or circular, etc. In this embodiment of the present disclosure, the orthographic projection of the laser beam refers to the orthographic projection of the laser beam in a plane perpendicular to the central ray of the laser beam.

[0118] In this embodiment of the disclosure, a second substrate can be formed using a laser liquid phase epitaxy process. The material of the obtained second substrate includes crystalline semiconductor materials. Transistors can be fabricated on the second substrate, which can give the transistors advantages such as high mobility, good reliability, and few defects.

[0119] In some exemplary embodiments, after forming the interconnect components, P-type doped amorphous silicon is deposited and then irradiated with a laser to form a single-crystal silicon containing a P-type well, thus forming a second substrate. The P-type well prevents the bit lines formed in subsequent processes from directly contacting the second substrate. The P-type well acts as an isolation layer, preventing leakage and improving the performance of the semiconductor device. In some examples, after laser-induced formation of the single-crystal silicon layer, doping is performed to form the P-type well and the second substrate.

[0120] In some exemplary embodiments, such as Figure 17 As shown, after forming the second substrate 10b, steps (01) to (11) can be repeated to form the second device unit layer 102. In one example, steps (21) and (22) can be repeated to form the connection components of the second device unit layer. In one example, steps (31) and (32) can be repeated to form the third substrate of the third device unit layer. By repeating this process, a stack of multiple device unit layers is achieved. The semiconductor device provided by the embodiments of this disclosure has the advantages of small footprint, low production cost, and high integration density.

[0121] The fabrication method provided in this disclosure is also applicable to logic device circuits in structures where the device unit layer does not contain capacitors.

[0122] In some exemplary embodiments, the orthographic projections of bit lines located in different device unit layers onto the plane of the first substrate may not completely overlap. Along a third direction, the ends of bit lines in adjacent device unit layers may form a stepped structure to facilitate the connection between bit lines and bit line connection lines, thereby improving the rationality of semiconductor device structure design.

[0123] In some exemplary embodiments, the orthographic projections of word lines located in different device unit layers onto the plane of the first substrate may not completely overlap. Along a third direction, the ends of word lines in adjacent device unit layers may form a stepped structure to facilitate the connection between word lines and word line connection lines, thereby improving the rationality of semiconductor device structure design.

[0124] In some exemplary embodiments, the orthographic projections of capacitors located in different device unit layers on the plane of the first substrate may not completely overlap. Along a third direction, the ends of capacitors in adjacent device unit layers may form a stepped structure to facilitate the connection between capacitors and capacitor connection lines, thereby improving the rationality of semiconductor device structure design.

[0125] This disclosure provides a method for fabricating a semiconductor device, the semiconductor device comprising n stacked device unit layers, each device unit layer comprising a substrate and a plurality of semiconductor layers located on the substrate, the semiconductor layers extending in a direction perpendicular to the substrate; wherein n is an integer greater than or equal to 2; the fabrication method includes: Multiple semiconductor layers are formed on the substrate of the i-th device unit layer; At least one connection component is formed based on the plurality of semiconductor layers; The substrate upon which the (i+1)th device unit layer is formed based on the at least one connecting component; Along a direction perpendicular to the substrate, one end of the connecting member is connected to the semiconductor layer of the i-th device unit layer, and the other end of the connecting member is connected to the substrate of the (i+1)-th device unit layer; where i is an integer greater than or equal to 1 and less than or equal to n-1.

[0126] In some exemplary embodiments, forming at least one connection component based on the plurality of semiconductor layers includes: At least one via is formed, the at least one via extending in a direction perpendicular to the substrate, and the via exposing at least one portion of the semiconductor layer; The connecting component is formed within the via using a selective epitaxial process.

[0127] In some exemplary embodiments, the temperature range of the selective epitaxial process is between 300 degrees Celsius and 400 degrees Celsius.

[0128] In some exemplary embodiments, the substrate for forming the (i+1)th device unit layer based on the at least one connection member includes: An amorphous semiconductor material is deposited on the side of the substrate away from the i-th device unit layer of the connecting component; Irradiation with a laser device causes the amorphous semiconductor material to crystalline semiconductor material to form the substrate of the (i+1)th device unit layer.

[0129] This disclosure also provides an electronic device, which includes the semiconductor device provided in any of the above embodiments, or includes a semiconductor device fabricated using the preparation method provided in any of the above embodiments. This electronic device can be any electronic product with storage function, such as a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank.

[0130] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, It includes n device unit layers stacked together, each of the device unit layers including a substrate and a plurality of semiconductor layers located on the substrate, the semiconductor layers extending in a direction perpendicular to the substrate; The semiconductor device further includes a plurality of connection components, and each device unit layer, except for the nth device unit layer, contains at least one of the connection components. The connecting component is located between the substrates of adjacent device unit layers. Along a direction perpendicular to the substrate, one end of the connecting component is connected to the semiconductor layer of the i-th device unit layer, and the other end of the connecting component is connected to the substrate of the (i+1)-th device unit layer. Where n is an integer greater than or equal to 2, and i is an integer greater than or equal to 1 and less than or equal to n-1.

2. The semiconductor device as claimed in claim 1, characterized in that, The connecting component, the semiconductor layer, and the substrate connected to the connecting component all contain the same semiconductor material.

3. The semiconductor device as described in claim 1, characterized in that, The semiconductor device further includes a plurality of vias, at least one of the vias being located between the semiconductor layer and the substrate remote from the semiconductor layer, and the via exposing a portion of the semiconductor layer, the connection member being located within the via and connected to the semiconductor layer.

4. The semiconductor device as claimed in claim 1, characterized in that, In a direction perpendicular to the substrate, the orthographic projection of the connecting member on the substrate at least partially overlaps with the orthographic projection of the semiconductor layer on the substrate.

5. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor layers of each device unit layer are arranged in an array in a direction parallel to the substrate, and the connecting component is connected to the semiconductor layer at the center of the device unit layer.

6. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes an isolation layer, through which the connection member extends in a direction perpendicular to the substrate.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, Along a direction perpendicular to the substrate, the semiconductor layer includes a first electrode, a channel layer, and a second electrode; The connecting component is connected to the first pole or the second pole; The sidewalls of the channel layer are surrounded by gate electrodes.

8. The semiconductor device as claimed in claim 7, characterized in that, The semiconductor device further includes: Multiple word lines, each word line extending along a second direction parallel to the substrate, the multiple word lines being spaced apart in a first direction parallel to the substrate, and multiple gate electrodes spaced apart along the second direction parallel to the substrate being connected to the same word line; Multiple bit lines, each extending along a first direction parallel to the substrate, the multiple bit lines being spaced apart along a second direction parallel to the substrate, and the second poles or first poles of multiple semiconductor layers spaced apart along the first direction parallel to the substrate being connected to the same bit line.

9. The semiconductor device according to any one of claims 1 to 6, characterized in that, Each of the device unit layers includes a plurality of memory cells, and each memory cell includes a contact portion, the semiconductor layer, and a capacitor; The capacitor is connected to the semiconductor layer via the contact portion.

10. The semiconductor device as claimed in claim 9, characterized in that, The material of the contact portion includes heavily doped polymers and / or heavily doped polycrystalline silicon.

11. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes n stacked device unit layers, each device unit layer including a substrate and a plurality of semiconductor layers located on the substrate, the semiconductor layers extending in a direction perpendicular to the substrate; wherein, n is an integer greater than or equal to 2; the fabrication method includes: Multiple semiconductor layers are formed on the substrate of the i-th device unit layer; At least one connection component is formed based on the plurality of semiconductor layers; The substrate upon which the (i+1)th device unit layer is formed based on the at least one connecting component; Along a direction perpendicular to the substrate, one end of the connecting member is connected to the semiconductor layer of the i-th device unit layer, and the other end of the connecting member is connected to the substrate of the (i+1)-th device unit layer; where i is an integer greater than or equal to 1 and less than or equal to n-1.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The formation of at least one connection component based on the plurality of semiconductor layers includes: At least one via is formed, the at least one via extending in a direction perpendicular to the substrate, and the via exposing at least one portion of the semiconductor layer; The connecting component is formed within the via using a selective epitaxial process.

13. The method for fabricating a semiconductor device as described in claim 12, characterized in that, The temperature range of the selective epitaxial process is 300 degrees Celsius to 400 degrees Celsius.

14. The method for fabricating a semiconductor device according to any one of claims 11 to 13, characterized in that, The substrate for forming the (i+1)th device unit layer based on the at least one connecting component includes: An amorphous semiconductor material is deposited on the side of the substrate away from the i-th device unit layer of the connecting component; Irradiation with a laser device causes the amorphous semiconductor material to crystalline semiconductor material to form the substrate of the (i+1)th device unit layer.

15. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 10, or the semiconductor device formed by the preparation method as described in any one of claims 11 to 14.

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