Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes first conductive lines each extending in a first direction; second conductive lines over the first conductive lines and each extending in a second direction crossing the first direction; memory cells respectively located between the first conductive lines and the second conductive lines, each memory cell including a variable resistance pattern; a first gap filling pattern between a pair of first conductive lines adjacent in the second direction; a second gap filling pattern on the first gap filling pattern; and a third gap-filling pattern between the first gap-filling pattern and the second gap-filling pattern, the third gap-filling pattern having a first interface with the first gap-filling pattern and a second interface with the second gap-filling pattern. A first interface is positioned below a lower surface of the variable resistance pattern and a second interface is positioned above an upper surface of the variable resistance pattern.

Description

[0001] Cross-references to related applications This application claims priority to Korean Application No. 10-2024-0138722, filed on October 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to an electronic device and a method of manufacturing the electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0003] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices in which memory cells are formed as a single layer on a substrate has reached its limit, three-dimensional semiconductor devices in which memory cells are stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0004] According to embodiments of this disclosure, a semiconductor device may include: first conductors, each extending in a first direction; second conductors, located above the first conductors and each extending in a second direction intersecting the first direction; memory cells, respectively located between the first conductors and the second conductors, and each memory cell including a variable resistor pattern; a first gap fill pattern located between an adjacent pair of first conductors in the second direction; a second gap fill pattern located on the first gap fill pattern; and a third gap fill pattern located between the first and second gap fill patterns, the third gap fill pattern having a first interface with the first gap fill pattern and a second interface with the second gap fill pattern. The first interface is positioned below the lower surface of the variable resistor pattern, while the second interface with the second gap fill pattern is positioned above the upper surface of the variable resistor pattern.

[0005] According to embodiments of this disclosure, a semiconductor device may include: first conductors, each extending in a first direction; second conductors, located above the first conductors and each extending in a second direction intersecting the first direction; memory cells, respectively located between the first conductors and the second conductors, each memory cell including a variable resistor pattern; a first gap fill pattern, located between an adjacent pair of first conductors in the second direction, each first gap fill pattern including an oxide layer; and a third gap fill pattern, located on the first gap fill pattern. The third gap fill pattern has a lower surface positioned below the lower surface of the variable resistor pattern and an upper surface positioned above the upper surface of the variable resistor pattern.

[0006] According to embodiments of this disclosure, a method of manufacturing a semiconductor device may include: forming a variable resistance layer on a first conductive layer; forming variable resistance lines by etching the variable resistance layer; forming first conductive lines by etching the first conductive layer, each first conductive line extending in a first direction; forming a first gap fill pattern between an adjacent pair of first conductive lines such that the upper surface of the first gap fill pattern is positioned below the lower surface of each of the adjacent pair of variable resistance lines; and forming a second gap fill pattern on the first gap fill pattern such that the upper surface of the second gap fill pattern is positioned above the upper surface of each of the adjacent pair of variable resistance lines. Attached Figure Description

[0007] Figure 1A , Figure 1B and Figure 1C This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2A , Figure 2B and Figure 2C This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3A and Figure 3B This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10B This is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A and Figure 16B This is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0012] Embodiments of this disclosure provide a semiconductor device with a stable structure and improved properties, and a method for manufacturing the semiconductor device.

[0013] According to this technology, semiconductor devices with stable structures and improved reliability can be provided. Throughout the specification and claims, a list of terms beginning with phrases such as "at least one," "one or more," or "one or two" indicates a list of inclusion. For example, a list of "at least one of A or B" and a list of "one or both of A and B" each indicate A, or B, or AB (i.e., A and B). Furthermore, "on the second element" means that the first element may be "directly" on the second element, or that at least one intermediate element may be between the first element and the second element.

[0014] In the following description, embodiments based on the technical spirit of this disclosure are illustrated with reference to the accompanying drawings.

[0015] Figures 1A to 1C This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1A It can be a floor plan. Figure 1B It is along Figure 1A The cross-sectional view of line AA′, and Figure 1C It is along Figure 1A The cross-sectional view taken from line BB′.

[0016] refer to Figures 1A to 1C The semiconductor device may include a first wire 110, a second wire 120, and a memory cell 130. The semiconductor device may also include a first gap filling pattern 140, a second gap filling pattern 150, a third gap filling pattern 160, a fourth gap filling pattern 170, a fifth gap filling pattern 180, and a sixth gap filling pattern 190.

[0017] First conductors 110 may each extend in a first direction I. Second conductors 120 may intersect first conductors 110 and may be located above first conductors 110. Second conductors 120 may each extend in a second direction II intersecting the first direction I. For example, first conductors 110 may each be word lines, and second conductors 120 may be bit lines. As another example, first conductors 110 may each be bit lines, and second conductors 120 may each be word lines.

[0018] The storage cell 130 may be arranged along a first direction I and a second direction II. The storage cell 130 may be positioned between the first conductor 110 and the second conductor 120. The storage cell 130 may include a variable resistor pattern 133. The storage cell 130 may also include at least one of a first electrode pattern 131 or a second electrode pattern 135.

[0019] The first electrode pattern 131 may be part of or electrically connected to the first wire 110. The second electrode pattern 135 may be part of or electrically connected to the second wire 120. The first electrode pattern 131 or the second electrode pattern 135 may include a conductive material such as carbon or metal. For example, the first electrode pattern 131 and / or the second electrode pattern 135 may include carbon. As another example, the first electrode pattern 131 or the second electrode pattern 135 or both may include polycrystalline silicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), platinum (Pt), molybdenum (Mo), ruthenium (Ru), etc., and may include combinations thereof.

[0020] The variable resistor pattern 133 can be positioned between the first conductor 110 and the second conductor 120. The variable resistor pattern 133 can remain amorphous during programming operations and can remain crystalline after programming operations. In other words, the phase of the variable resistor pattern 133 can remain unchanged after programming operations. In this case, the variable resistor pattern 133 can be used simultaneously as a data storage device and a selection element. The variable resistor pattern 133 can include a resistive material and can have the property of reversibly changing between different resistance states according to the applied voltage or current. For example, the variable resistor pattern 133 can include a variable resistive material whose resistance changes without a phase transition, and can include a chalcogenide element. The variable resistor pattern 133 can include germanium (Ge), antimony (Sb), arsenic (As), silicon (Si), indium (In), tin (Sn), gallium (Ga), etc., or can include combinations thereof.

[0021] For reference, although not shown in this figure, the semiconductor device may also include a third electrode pattern and a switch pattern. For example, the semiconductor device may include a structure in which a first electrode pattern 131, a switch pattern, a third electrode pattern, a variable resistor pattern 133, and a second electrode pattern 135 are sequentially stacked. In this case, the first electrode pattern 131, the switch pattern, and the third electrode pattern can constitute a selection element. The selection element may be a diode, a PNP diode, a transistor, a vertical transistor, a bipolar junction transistor (BJT), a metal-insulator transition (MIT) element, a hybrid ion-electron conduction (MIEC) element, a bidirectional threshold switch (OTS) element, etc. For example, the switch pattern may include a chalcogenide material. Furthermore, the third electrode pattern, the variable resistor pattern 133, and the second electrode pattern 135 may constitute a memory element. The memory element and the selection element may share the third electrode pattern. The variable resistor pattern 133 may include a chalcogenide material.

[0022] The first gap-filling pattern 140 may be positioned between adjacent first conductors 110 in the second direction II. For example, the first gap-filling pattern 140 may be positioned between a pair of adjacent first conductors 110 in the second direction II. The first gap-filling pattern 140 may extend between adjacent first electrode patterns 131 along the second direction II. The first gap-filling pattern 140 may include an insulating material such as an oxide. For example, the first gap-filling pattern 140 may include at least one of tetraethyl orthosilicate (TEOS) material or spin-coated low-k (SOL) material.

[0023] The second gap-filling pattern 150 may be located above the first gap-filling pattern 140. The second gap-filling pattern 150 may be positioned between adjacent second electrode patterns 135 in the second direction II. For example, the second gap-filling pattern 150 may be positioned between a pair of adjacent second electrode patterns 135 in the second direction II. The second gap-filling pattern 150 may comprise the same material as the first gap-filling pattern 140. In other words, the second gap-filling pattern 150 may comprise a material common to the material of the first gap-filling pattern 140. For example, the second gap-filling pattern 150 may comprise an oxide and may comprise at least one of TEOS or SOL materials.

[0024] The third gap-filling pattern 160 can be positioned between the first gap-filling pattern 140 and the second gap-filling pattern 150. For example, the interface (or first interface) IF1 between the third gap-filling pattern 160 and the first gap-filling pattern 140 can be positioned below the lower surface 133L of the variable resistor pattern 133, and the interface (or second interface) IF2 between the third gap-filling pattern 160 and the second gap-filling pattern 150 can be positioned above the upper surface 133U of the variable resistor pattern 133. In other words, in the second direction II, the third gap-filling pattern 160 can cover all four corners 133C of the variable resistor pattern 133. Thus, even if the programming and erasing operations of the memory cell 130 are repeatedly performed, the separation of material included in the variable resistor pattern 133 to the outside of the memory cell 130 through the four corners 133C can be prevented or reduced.

[0025] The third gap-filling pattern 160 may include a material different from that of the first gap-filling pattern 140. For example, the third gap-filling pattern 160 may include a nitride. The third gap-filling pattern 160 may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN). In other words, in the second direction II, the four corners 133C of the variable resistor pattern 133 may be covered with a nitride. In this case, compared to the case where the four corners 133C of the variable resistor pattern 133 are covered with oxides, the degradation caused by performing repetitive operations of the memory cell 130 can be reduced. This is because the material properties of nitrides (e.g., modulus, hardness, etching selectivity, etc.) are superior to those of oxides. However, the third gap-filling pattern 160 is not limited to including a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN), and may include other types of silicon nitride layers according to embodiments of this disclosure.

[0026] The fourth gap-filling pattern 170 can be positioned on the first conductor 110. The fourth gap-filling pattern 170 can be positioned between adjacent first electrode patterns 131 in the first direction I. For example, the fourth gap-filling pattern 170 can be positioned between a pair of adjacent first electrode patterns 131 in the first direction I. The fourth gap-filling pattern 170 can comprise the same material as the first gap-filling pattern 140. For example, the fourth gap-filling pattern 170 can comprise an oxide and can comprise at least one of tetraethyl orthosilicate (TEOS) or spin-coated low-k (SOL) material.

[0027] The fifth gap fill pattern 180 may be located above the fourth gap fill pattern 170. The fifth gap fill pattern 180 may be positioned between adjacent second conductors 120 in the first direction I. For example, the fifth gap fill pattern 180 may be positioned between a pair of adjacent second conductors 120 in the first direction I. The fifth gap fill pattern 180 may extend between adjacent second electrode patterns 135 along the first direction I. The fifth gap fill pattern 180 may comprise the same material as the fourth gap fill pattern 170.

[0028] The sixth gap-filling pattern 190 can be positioned between the fourth gap-filling pattern 170 and the fifth gap-filling pattern 180. For example, the interface (or third interface) IF3 between the sixth gap-filling pattern 190 and the fourth gap-filling pattern 170 can be positioned below the lower surface 133L of the variable resistor pattern 133, and the interface (or fourth interface) IF4 between the sixth gap-filling pattern 190 and the fifth gap-filling pattern 180 can be positioned above the upper surface 133U of the variable resistor pattern 133. In other words, in the first direction I, the sixth gap-filling pattern 190 can cover all four corners 133C of the variable resistor pattern 133. This prevents or reduces the material included in the variable resistor pattern 133 from separating to the outside of the memory cell 130 through the four corners 133C due to repeated programming and erasing operations of the memory cell 130.

[0029] The sixth gap-filling pattern 190 may include a material different from that of the fourth gap-filling pattern 170. For example, the sixth gap-filling pattern 190 may include a nitride and may include at least one of silicon boron nitride (SiBN) or silicon carbon nitride (SiCN). In other words, in the first direction I, the four corners 133C of the variable resistor pattern 133 may be covered with a nitride. In this case, compared to the case where the four corners 133C of the variable resistor pattern 133 are covered with oxides, the degradation caused by performing repetitive operations of the memory cell 130 can be reduced. However, the sixth gap-filling pattern 190 is not limited to including a silicon boron nitride (SiBN) or silicon carbon nitride (SiCN) layer, and may include other types of silicon nitride layers according to embodiments of this disclosure.

[0030] According to the above structure, in the second direction II, the third gap filling pattern 160 can cover the four corners 133C of the variable resistor pattern 133 with nitride. Furthermore, in the first direction I, the sixth gap filling pattern 190 can cover the four corners 133C of the variable resistor pattern 133 with nitride. In this case, even if the programming and erasing operations of the memory cell 130 are repeatedly performed, the degradation of the memory cell 130 can be reduced, and the separation of material included in the variable resistor pattern 133 from the corners 133C of the variable resistor pattern 133 to the outside of the memory cell 130 can be prevented or reduced.

[0031] Figures 2A to 2C This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2A It can be a floor plan. Figure 2B It is along Figure 2A The cross-sectional view of line CC′, and Figure 2C It is along Figure 2A The cross-sectional view taken by line DD′. In the following text, content overlapping with the above is omitted.

[0032] refer to Figures 2A to 2C The semiconductor device may include a first conductive line 210, a second conductive line 220, a memory cell 230, a first gap filling pattern 240, a second gap filling pattern 250, a third gap filling pattern 260, a fourth gap filling pattern 270, a fifth gap filling pattern 280, and a sixth gap filling pattern 290. The semiconductor device may also include a first inner liner pattern LN1, a second inner liner pattern LN2, and a third inner liner pattern LN3.

[0033] The first conductor 210 may each extend in a first direction I. The second conductor 220 may intersect the first conductor 210 and may be located above the first conductor 210. The second conductor 220 may each extend in a second direction II that intersects the first direction I.

[0034] The storage cell 230 can be arranged along a first direction I and a second direction II intersecting the first direction I. The storage cell 230 can be positioned between the first wire 210 and the second wire 220. The storage cell 230 may include a first electrode pattern 231, a second electrode pattern 235, and a variable resistor pattern 233. Here, the variable resistor pattern 233 can be positioned between the first electrode pattern 231 and the second electrode pattern 235.

[0035] Each of the first liner patterns LN1 can cover a sidewall of a corresponding memory cell 230. Specifically, the first liner pattern LN1 can cover substantially the entire sidewall of the memory cell 230 adjacent to the first liner pattern LN1. For example, the first liner pattern LN1 can cover the corresponding sidewalls of the memory cell 230 adjacent in the second direction II. The first liner pattern LN1 can protect the memory cell 230 during the manufacturing process of the semiconductor device. Each of the first liner patterns LN1 can include a nitride and can each include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0036] The second liner pattern LN2 may be located on the first liner pattern LN1. Each second liner pattern LN2 may extend along the sidewall of a corresponding first conductor 210. For example, the second liner pattern LN2 may extend along the sidewall of the first conductor 210 adjacent to the second liner pattern LN2. The second liner pattern LN2 may protect the memory cell 230 during the manufacturing process of the semiconductor device. The second liner pattern LN2 may include a nitride and may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0037] The third liner pattern LN3 may cover one or more sidewalls of the memory cell 230. For example, the third liner pattern LN3 may cover adjacent sidewalls of the memory cell 230 in the first direction I. Specifically, the third liner pattern LN3 may cover the sidewalls of a pair of adjacent memory cells 230 in the first direction I. Furthermore, the third liner pattern LN3 may extend along the second direction II to cover the sidewalls of memory cells 230 arranged along the second direction II. The third liner pattern LN3 may protect the memory cell 230 during the manufacturing process of the semiconductor device. The third liner pattern LN3 may include a nitride and may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0038] For reference, according to embodiments of the present disclosure, the first liner pattern LN1, the second liner pattern LN2, and the third liner pattern LN3 are not limited to including silicon boron nitride (SiBN) or silicon carbon nitride (SiCN) layers, but may include other types of silicon nitride layers according to embodiments of the present disclosure.

[0039] The first gap-filling pattern 240 may be located on the second liner pattern LN2. For example, the first gap-filling pattern 240 may be positioned on the sidewall of the second liner pattern LN2. The first gap-filling pattern 240 may be positioned between adjacent first conductors 210 in the second direction II. The second gap-filling pattern 250 may be located above the first gap-filling pattern 240 and may be positioned between adjacent second electrode patterns 235 in the second direction II. At least one of the first gap-filling pattern 240 or the second gap-filling pattern 250 may include an oxide and may include at least one of tetraethyl orthosilicate (TEOS) material or spin-coated low-k (SOL) material.

[0040] The third gap-filling pattern 260 may be located on the second liner pattern LN2. For example, the third gap-filling pattern 260 may be located on the sidewall of the second liner pattern LN2. The third gap-filling pattern 260 may be positioned between the first gap-filling pattern 240 and the second gap-filling pattern 250. The interface between the third gap-filling pattern 260 and the first gap-filling pattern 240 may be positioned below the lower surface of the variable resistor pattern 233, and the interface between the third gap-filling pattern 260 and the second gap-filling pattern 250 may be positioned above the upper surface of the variable resistor pattern 233.

[0041] The third gap-filling pattern 260 may include a material different from that of the first gap-filling pattern 240. Furthermore, the third gap-filling pattern 260 may include the same material as at least one of the first liner pattern LN1 or the second liner pattern LN2. For example, the third gap-filling pattern 260 may include a nitride and may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0042] The fourth gap-filling pattern 270 can be positioned between adjacent first electrode patterns 231 in the first direction I. The fifth gap-filling pattern 280 can be located above the fourth gap-filling pattern 270 and can be positioned between adjacent second conductors 220 in the first direction I. At least one of the fourth gap-filling pattern 270 or the fifth gap-filling pattern 280 can comprise the same material as the first gap-filling pattern 240.

[0043] The sixth gap-filling pattern 290 can be located on the third inner liner pattern LN3. For example, the sixth gap-filling pattern 290 can be located on the sidewall of the third inner liner pattern LN3. The sixth gap-filling pattern 290 can be positioned between the fourth gap-filling pattern 270 and the fifth gap-filling pattern 280. For example, the interface between the sixth gap-filling pattern 290 and the fourth gap-filling pattern 270 can be positioned below the lower surface of the variable resistor pattern 233, and the interface between the sixth gap-filling pattern 290 and the fifth gap-filling pattern 280 can be positioned above the upper surface of the variable resistor pattern 233.

[0044] The sixth gap-filling pattern 290 may include a material different from that of the fourth gap-filling pattern 270. Furthermore, the sixth gap-filling pattern 290 may include the same material as the third liner pattern LN3. For example, the sixth gap-filling pattern 290 may include a nitride and may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0045] exist Figures 2A to 2C In the embodiments described, a first boundary surface exists between the first inner lining pattern LN1 and the second inner lining pattern LN2, and a second boundary surface exists between the second inner lining pattern LN2 and the third gap-filling pattern 260. However, the implementation of this disclosure is not limited to this. For example, the first inner lining pattern LN1, the second inner lining pattern LN2, and the third gap-filling pattern 260 can be formed in separate processes, but may include the same material, and therefore the first inner lining pattern LN1, the second inner lining pattern LN2, and the third gap-filling pattern 260 can be formed as a single integral without boundary surfaces formed therebetween. Similarly, the boundary surface between the third inner lining pattern LN3 and the sixth gap-filling pattern 290 may not exist.

[0046] Although the first liner pattern LN1 and the second liner pattern LN2 can linearly cover the corner 233C of the variable resistor pattern 233, a third gap-filling pattern 260 can be additionally formed, and thus the first liner pattern LN1, the second liner pattern LN2, and the third gap-filling pattern 260 can cover the corner 233C of the variable resistor pattern 233 with a nitride of sufficient thickness along the second direction II. Similarly, the third liner pattern LN3 and the sixth gap-filling pattern 290 can cover the corner 233C of the variable resistor pattern 233 with a nitride of sufficient thickness along the first direction I. In this case, even if the programming and erasing operations of the memory cell 230 are repeatedly performed, the degradation of the memory cell 230 can be prevented or reduced, and the separation of material included in the variable resistor pattern 233 to the outside of the memory cell 230 through the corner 233C can be prevented or reduced.

[0047] According to the above embodiments, the semiconductor device may include a first liner pattern LN1, a second liner pattern LN2, and a third gap fill pattern 260. Here, the first liner pattern LN1, the second liner pattern LN2, and the third gap fill pattern 260 may include nitrides. Similarly, the semiconductor device may include a third liner pattern LN3 and a sixth gap fill pattern 290. The third liner pattern LN3 and the sixth gap fill pattern 290 may include nitrides.

[0048] Figure 3A and Figure 3B This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, content overlapping with the above may be omitted in the following text.

[0049] refer to Figure 3A The semiconductor device may include a first wire 310, a second wire 320, a memory cell 330, a third gap filling pattern 360, a first liner pattern LN1, and a second liner pattern LN2.

[0050] The third gap fill pattern 360 can be located on the second liner pattern LN2. In other words, the third gap fill pattern 360, comprising nitride, can be located on the second liner pattern LN2. Here, the lower surface of the third gap fill pattern 360 can be positioned below the lower surface of the variable resistor pattern 333. Furthermore, the upper surface of the third gap fill pattern 360 can be positioned above the upper surface of the variable resistor pattern 333. By forming the third gap fill pattern 360 on the second liner pattern LN2 using a single material, the process can be simplified and the time and cost for manufacturing semiconductor devices can be reduced.

[0051] Furthermore, since the first liner pattern LN1, the second liner pattern LN2, and the third gap filling pattern 360 all include nitrides and cover all corners of the variable resistor pattern 333, the degradation of the memory cell 330 can be prevented or reduced, and the material of the variable resistor pattern 333 can be prevented or reduced from separating to the outside of the memory cell 330 through the corners.

[0052] refer to Figure 3B The semiconductor device may further include a first gap-filling pattern 340. Here, the first gap-filling pattern 340 may include an oxide. A third gap-filling pattern 360 may be located above the first gap-filling pattern 340. Here, the interface between the first gap-filling pattern 340 and the third gap-filling pattern 360 may be positioned below the lower surface of the variable resistor pattern 333. The upper surface of the third gap-filling pattern 360 may be positioned above the upper surface of the variable resistor pattern 333.

[0053] When the third gap-filling pattern 360 is formed on the second liner pattern LN2 using a single material, a void may form in the third gap-filling pattern 360 below the lower surface of the variable resistor pattern 333. Therefore, by forming the first gap-filling pattern 340 before forming the third gap-filling pattern 360, the formation of voids in the third gap-filling pattern 360 can be substantially prevented.

[0054] Figures 4A to 10B This is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A It is a floor plan, and Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B They are respectively along Figures 4A to 8A The cross-sectional view of the line EE′. Figure 9A and Figure 10A It is a floor plan, and Figure 9B and Figure 10B It is along Figure 9A and Figure 10A The cross-sectional view taken by line FF′. For the sake of brevity, the content overlapping with the above can be omitted in the following text.

[0055] refer to Figure 4A and Figure 4B A storage layer 420A, including a variable resistance layer 423A, can be formed on the first conductive layer 410A. First, a first electrode layer 421A can be formed on the first conductive layer 410A. Then, a variable resistance layer 423A can be formed on the first electrode layer 421A. Subsequently, a second electrode layer 425A can be formed on the variable resistance layer 423A. Here, the variable resistance layer 423A may include a chalcogenide material.

[0056] For reference, although not shown in this figure, the memory layer 420A can be formed by sequentially stacking the first electrode layer 421A, the switch layer, the third electrode layer, the variable resistor layer 423A, and the second electrode layer 425A.

[0057] Subsequently, a first hard mask pattern HM1 can be formed on the memory layer 420A. The first hard mask pattern HM1 can serve as a protective pattern to prevent or reduce damage to the memory layer 420A in subsequent processes.

[0058] refer to Figure 5A and Figure 5BA memory line 420L, including a variable resistance line 423L, can be formed. First, the second electrode layer 425A, the variable resistance layer 423A, and the first electrode layer 421A can be etched sequentially to form the second electrode line 425L, the variable resistance line 423L, and the first electrode line 421L, respectively extending along the first direction I.

[0059] Subsequently, the first conductive lines 410 can be formed. For example, the first conductive layer 410A can be etched using the first hard mask pattern HM1 to form the first conductive lines 410 extending in the first direction I. For reference, the conductive layer 410A can be etched simultaneously with the memory layer 420A.

[0060] refer to Figure 6A and Figure 6B A first gap-filling pattern 430 can be formed between the first conductors 410. For example, the first gap-filling pattern 430 can be formed between the first conductors 410 such that the upper surface of the first gap-filling pattern 430 is positioned below the lower surface 423LL of the variable resistance line 423L. Specifically, the first gap-filling pattern 430 can be formed between an adjacent pair of first conductors 410 such that the upper surface of the first gap-filling pattern 430 is positioned below the lower surface 423LL of each of the adjacent pair of variable resistance lines 423L. First, a preliminary first gap-filling pattern 430A can be coated between the first conductors 410. Specifically, the preliminary first gap-filling pattern 430A can be coated to fill the space between an adjacent pair of first conductors 410 such that the upper surface of the preliminary first gap-filling pattern 430A is positioned below the lower surface 423LL of each of the adjacent pair of variable resistance lines 423L. For example, the preliminary first gap-filling pattern 430A can be coated by spin coating. Subsequently, the preliminary first gap-filling pattern 430A can be cured to form the first gap-filling pattern 430. For example, the first gap-filling pattern 430 can be formed by curing the preliminary first gap-filling pattern 430A using an oven and UV cutting. Here, the first gap-filling pattern 430 may include an insulating material such as an oxide. For example, the first gap-filling pattern 430 may include at least one of tetraethyl orthosilicate (TEOS) material or spin-coated low-k (SOL) material. However, embodiments of this disclosure are not limited thereto, and the process of forming the preliminary first gap-filling pattern 430A may be omitted. For example, the first gap-filling pattern 430 may be formed using a deposition method.

[0061] For reference, although not shown in this drawing, residues may form on the sidewalls of the storage line 420L during the process of forming the preliminary first gap fill pattern 430A and the first gap fill pattern 430. In this case, the residues formed on the sidewalls of the storage line 420L can be removed before forming the second gap fill pattern 440 in a subsequent process, such that the upper surface of the first gap fill pattern 430 is positioned below the lower surface 423LL of each variable resistance line 423L.

[0062] refer to Figure 7A and Figure 7B A second gap-filling pattern 440 can be formed on the first gap-filling pattern 430. For example, the second gap-filling pattern 440 can be formed on the first gap-filling pattern 430 such that the upper surface of the second gap-filling pattern 440 is positioned over the upper surface 423LU of each variable resistance line 423L. First, a second gap-filling layer 440A can be deposited on the first gap-filling pattern 430. For example, the second gap-filling layer 440A can be deposited to fill the spaces between the variable resistance lines 423L. Subsequently, the second gap-filling layer 440A can be etched to form the second gap-filling pattern 440 such that the upper surface of the second gap-filling pattern 440 is positioned over the upper surface 423LU of each of the variable resistance lines 423L (e.g., an adjacent pair of variable resistance lines 423L).

[0063] Here, the second gap-filling pattern 440 may include a material different from that of the first gap-filling pattern 430. The second gap-filling pattern 440 may include an insulating material such as a nitride. For example, the second gap-filling pattern 440 may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0064] In this case, the second gap filling pattern 440 can cover all corners 423LC of the variable resistance line 423L. For example, the second gap filling pattern 440 can cover all four corners 423LC of the variable resistance line 423L in the second direction II with nitride.

[0065] refer to Figure 8A and Figure 8B A third gap-filling pattern 450 can be formed on the second gap-filling pattern 440. First, a preliminary third gap-filling pattern 450A can be applied to the second gap-filling pattern 440. Subsequently, the preliminary third gap-filling pattern 450A can be cured to form the third gap-filling pattern 450.

[0066] Here, the third gap-filling pattern 450 may include the same material as the first gap-filling pattern 430. For example, the third gap-filling pattern 450 may include an oxide and may include at least one of TEOS material or SOL material.

[0067] Subsequently, planarization can be performed to expose the second electrode lines 425L. For example, the first hard mask pattern HM1 can be removed. Furthermore, the third gap fill pattern 450 can be planarized to expose the upper surface of each second electrode line 425L.

[0068] refer to Figure 9A and Figure 9B The second conductive line 460 can be formed. First, a second conductive layer 460A can be formed on the storage line 420L. Subsequently, the second conductive layer 460A can be etched to form the second conductive line 460, each of the second conductive lines extending in a second direction II intersecting the first direction I.

[0069] For reference, a second hard mask pattern HM2 can be formed on the second conductive layer 460A. The second hard mask pattern HM2 can serve as a protective pattern to prevent or reduce damage to the memory line 420L in subsequent processes.

[0070] Subsequently, a memory cell 420 including a variable resistance pattern 423 can be formed. For example, the second electrode line 425L, the variable resistance line 423L, and the first electrode line 421L can be etched sequentially to form the second electrode pattern 425, the variable resistance pattern 423, and the first electrode pattern 421.

[0071] refer to Figure 10A and Figure 10B A fourth gap-filling pattern 470 can be formed such that the upper surface of the fourth gap-filling pattern 470 is positioned below the lower surface 423LL of each variable resistor pattern 423. First, a preliminary fourth gap-filling pattern 470A can be coated between the first electrode patterns 421. Subsequently, the preliminary fourth gap-filling pattern 470A can be cured to form the fourth gap-filling pattern 470. Here, the fourth gap-filling pattern 470 may comprise the same material as the first gap-filling pattern 430.

[0072] Subsequently, a fifth gap-fill pattern 480 can be formed on the fourth gap-fill pattern 470 such that the upper surface of the fifth gap-fill pattern 480 is positioned above the upper surface 423U of each variable resistor pattern 423. First, a fifth gap-fill layer 480A can be deposited. Subsequently, the fifth gap-fill layer 480A can be etched to form the fifth gap-fill pattern 480. Here, the fifth gap-fill pattern 480 can include a material different from that of the fourth gap-fill pattern 470. For example, the fifth gap-fill pattern 480 can include a nitride and can include at least one of silicon boron nitride (SiBN) or silicon carbon nitride (SiCN).

[0073] In this case, the fifth gap fill pattern 480 can cover all corners 423C of the variable resistor pattern 423. For example, the fifth gap fill pattern 480 can cover all four corners 423C of the variable resistor pattern 423 in the first direction I with nitride.

[0074] Subsequently, a sixth gap-filling pattern 490 can be formed on the fifth gap-filling pattern 480. First, a preliminary sixth gap-filling pattern 490A can be applied to the fifth gap-filling pattern 480. Subsequently, the preliminary sixth gap-filling pattern 490A can be cured to form the sixth gap-filling pattern 490. Here, the sixth gap-filling pattern 490 can include the same material as the fourth gap-filling pattern 470.

[0075] Subsequently, planarization can be performed to expose the second conductors 460. For example, the second hard mask pattern HM2 can be removed. Furthermore, the sixth gap fill pattern 490 can be planarized to expose the upper surface of each second conductor 460.

[0076] According to embodiments of this disclosure, the fifth gap-filling pattern 480 can cover all four corners 423C of the variable resistor pattern 423 with nitride in the first direction I, and the second gap-filling pattern 440 can cover all four corners of the variable resistor pattern 423 with nitride in the second direction II. In this case, even if the programming and erasing operations of the memory cell 420 are repeatedly performed, the separation of material included in the variable resistor pattern 423 to the outside of the memory cell 420 through the corners 423C can be prevented or reduced.

[0077] Furthermore, the second gap-filling pattern 440 and the fifth gap-filling pattern 480 may include nitrides. In this case, compared to the case where the corners of the variable resistor pattern 423 are covered with oxides, degradation due to repeated operation of the memory cell 420 can be reduced. This is because one or more material properties of nitrides (e.g., modulus, hardness, etching selectivity, etc.) are superior to those of oxides.

[0078] According to the manufacturing method described above, a second gap-filling pattern 440 and a fifth gap-filling pattern 480, comprising nitride, can be formed surrounding the sidewalls of the variable resistor pattern 423. Specifically, the second gap-filling pattern 440 can cover all four corners of the variable resistor pattern 423 with nitride in the second direction II, and the fifth gap-filling pattern 480 can cover all four corners 423C of the variable resistor pattern 423 with nitride in the first direction I. Therefore, degradation caused by repeated operation of the memory cell 420 can be reduced, and material separation of the variable resistor pattern 423 to the outside of the memory cell 420 through the corners can be prevented or reduced.

[0079] Figures 11A to 16B This is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 11A , Figure 12A , Figure 13A and Figure 14A It is a floor plan, and Figure 11B , Figure 12B , Figure 13B and Figure 14B They are respectively along Figure 11A , Figure 12A , Figure 13A and Figure 14A The cross-sectional view of line GG′. Figure 15A and Figure 16A It is a floor plan, and Figure 15B and Figure 16B It is along Figure 15A and Figure 16A The cross-sectional view taken by line HH′. For the sake of brevity, content overlapping with the above can be omitted in the following text.

[0080] refer to Figure 11A and Figure 11B A memory layer can be formed on the first conductive layer 510A. For example, the memory layer can be formed by sequentially stacking a first electrode layer, a variable resistance layer, and a second electrode layer on the first conductive layer 510A. Here, the variable resistance layer may include a chalcogenide material. Subsequently, a first hard mask pattern HM1 can be formed on the memory layer.

[0081] Subsequently, the memory layer can be etched to form memory lines 520L. For example, the second electrode layer, the variable resistance layer, and the first electrode layer can be etched sequentially to form second electrode lines 525L, variable resistance lines 523L, and first electrode lines 521L.

[0082] Subsequently, a first inner liner layer LN1A can be formed on the memory line 520L. For example, the first inner liner layer LN1A can be formed conformally along the memory line 520L and the first conductive layer 510A. Specifically, the first inner liner layer LN1A can be formed conformally along the upper surface of the first conductive layer 510A, the sidewalls of the memory line 520L, and the sidewalls and upper surface of the first hard mask pattern HM1. The first inner liner layer LN1A can prevent or reduce damage to the memory line 520L in subsequent processes.

[0083] The first inner liner layer LN1A may include an insulating material such as a nitride. For example, the first inner liner layer LN1A may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0084] refer to Figure 12A and Figure 12B The first inner liner layer LN1A can be etched to form a first inner liner pattern LN1. For example, the lower part of the first inner liner layer LN1A that contacts the first conductive layer 510A can be etched to form the first inner liner pattern LN1, thereby exposing the first conductive layer 510A.

[0085] Subsequently, the first conductive layer 510A can be etched to form a first conductive line 510 extending in the first direction I. In the process of etching the first conductive layer 510A to form the first conductive line 510, the first inner liner pattern LN1 can protect the memory line 520L.

[0086] Subsequently, a second liner layer LN2A can be formed on the first liner pattern LN1. For example, the second liner layer LN2A extending along the first conductor 510 can be formed on the first liner pattern LN1. Specifically, the second liner layer LN2A can be formed on the sidewall of the first conductor 510 and on the first liner pattern LN1. The second liner layer LN2A can prevent or reduce damage to the storage line 520L and the first conductor 510 in subsequent processes.

[0087] The second liner layer LN2A may comprise the same material as the first liner pattern LN1. For example, the second liner layer LN2A may comprise a nitride and may comprise at least one of a silicon boron nitride (SiBN) layer or a silicon carbon nitride (SiCN) layer.

[0088] refer to Figure 13A and Figure 13B A first gap-filling pattern 530 can be formed on the second inner liner layer LN2A. This can be achieved using a pattern similar to... Figure 6A and Figure 6BThe method for forming the first gap filling pattern 430 is used to form the first gap filling pattern 530. For example, the first gap filling pattern 530 can be formed such that the upper surface is positioned below the lower surface of the variable resistance line 523L.

[0089] refer to Figure 14A and Figure 14B A second gap-filling pattern 540 can be formed on the first gap-filling pattern 530. This can be achieved using a method similar to... Figure 7A and Figure 7B The method for forming the second gap filling pattern 440 is used to form the second gap filling pattern 540. For example, the second gap filling pattern 540 can be formed such that the upper surface is positioned above the upper surface of the variable resistance line 523L.

[0090] Furthermore, the second gap-filling pattern 540 may include the same material as the first liner pattern LN1 and the second liner layer LN2A. For example, the second gap-filling pattern 540 may include a nitride and may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0091] In this configuration, there may be no boundary surface between the first liner pattern LN1, the second liner layer LN2A, and the second gap-filling pattern 540. In other words, because the first liner pattern LN1, the second liner layer LN2A, and the second gap-filling pattern 540 can be formed in separate processes but may include the same materials, they can be formed as a single integrated unit without forming boundary surfaces between them.

[0092] The first liner pattern LN1 and the second liner layer LN2A can be used to linearly cover all corners of the variable resistance line 523L with nitride, but their thickness may be insufficient. To compensate for this, a second gap-filling pattern 540 comprising nitride can be additionally formed. That is, the first liner pattern LN1, the second liner layer LN2A, and the second gap-filling pattern 540 can cover the corners of the variable resistance line 523L in the second direction II with nitride of sufficient thickness.

[0093] Subsequently, a third gap-fill pattern 550 can be formed on the second gap-fill pattern 540. This can be achieved using a method similar to... Figure 8A and Figure 8B The method for forming the third gap filling pattern 450 forms the third gap filling pattern 550.

[0094] Subsequently, planarization can be performed to expose the second electrode lines 525L. For example, the first hard mask pattern HM1 can be removed, and the third gap fill pattern 550 can be planarized to expose the upper surface of each second electrode line 525L. In this process, the upper surface of the second liner layer LN2A can be etched to form the second liner pattern LN2.

[0095] refer to Figure 15A and Figure 15B The second conductive line 560 can be formed. First, a second conductive layer 560A can be formed on the storage line 520L. Subsequently, the second conductive layer 560A can be etched to form the second conductive line 560, each of the second conductive lines extending in a second direction II intersecting the first direction I.

[0096] Subsequently, a memory cell 520 including a variable resistance pattern can be formed. For example, the second electrode line 525L, the variable resistance line 523L, and the first electrode line 521L can be etched sequentially to form the second electrode pattern 525, the variable resistance pattern 523, and the first electrode pattern 521.

[0097] Subsequently, a third inner liner layer LN3A can be formed on the memory cell 520. For example, the third inner liner layer LN3A can be formed on the variable resistor pattern 523. The third inner liner layer LN3A can prevent or reduce damage to the memory cell 520 in subsequent processes.

[0098] The third inner liner layer LN3A may include an insulating material such as a nitride. For example, the third inner liner layer LN3A may include at least one of a silicon boron nitride layer (SiBN) or a silicon carbon nitride layer (SiCN).

[0099] refer to Figure 16A and Figure 16B A fourth gap-filling pattern 570 can be formed on the third inner liner layer LN3A. For example, the fourth gap-filling pattern 570 can be formed such that the upper surface of the fourth gap-filling pattern 570 is positioned below the lower surface of each of an adjacent pair of variable resistor patterns 523. Subsequently, a fifth gap-filling pattern 580 can be formed on the fourth gap-filling pattern 570. For example, the fifth gap-filling pattern 580 can be formed on the fourth gap-filling pattern 570 such that the upper surface of the fifth gap-filling pattern 580 is positioned above the upper surface of each of an adjacent pair of variable resistor patterns 523. Subsequently, a sixth gap-filling pattern 590 can be formed on the fifth gap-filling pattern 580. For reference, a similar pattern can be used. Figure 10A and Figure 10BThe method of forming the fourth gap filling pattern 470, the fifth gap filling pattern 480 and the sixth gap filling pattern 490 forms the fourth gap filling pattern 570, the fifth gap filling pattern 580 and the sixth gap filling pattern 590.

[0100] Subsequently, planarization can be performed to expose the second conductor 560. For example, the second hard mask pattern HM2 can be removed, and the sixth gap fill pattern 590 can be planarized to expose the upper surface of the second conductor 560. In this process, the upper portion of the third liner layer LN3A can be etched to form the third liner pattern LN3.

[0101] Here, the fifth gap-filling pattern 580 may comprise the same material as the third liner pattern LN3. In this case, the boundary surface between the third liner pattern LN3 and the fifth gap-filling pattern 580 may not exist. The third liner pattern LN3 may be used to linearly cover all corners of the variable resistor pattern 523 with nitride, but its thickness may be insufficient, and to compensate for this, a fifth gap-filling pattern 580 comprising nitride may be additionally formed.

[0102] That is, the first inner liner pattern LN1, the second inner liner pattern LN2, and the second gap filling pattern 540 can cover the corners of the variable resistance pattern 523 in the second direction II with nitride of sufficient thickness. The third inner liner layer LN3A and the fifth gap filling pattern 580 can cover the corners of the variable resistance pattern 523 in the first direction I with nitride of sufficient thickness.

[0103] In this case, even if the programming and erasing operations of the memory cell 520 are repeatedly performed, the degradation of the memory cell 520 can be prevented or reduced, and the material included in the variable resistor pattern 523 can be prevented or reduced from separating to the outside of the memory cell 520 through the corner.

[0104] For reference, Figures 11A to 16B In the embodiments described, the formation of the first gap filling pattern 530, the second gap filling pattern 540, the third gap filling pattern 550, the fourth gap filling pattern 570, the fifth gap filling pattern 580 and the sixth gap filling pattern 590 are described, but some of the configurations may be omitted according to the embodiments of this disclosure.

[0105] For example, the first gap filling pattern 530 and the third gap filling pattern 550 can be omitted, and the second gap filling pattern 540 can be formed on the second inner liner LN2A. Similarly, the fourth gap filling pattern 570 and the sixth gap filling pattern 590 can be omitted, and the fifth gap filling pattern 580 can be formed on the third inner liner LN3A.

[0106] In this case, because the processes of forming the first gap filling pattern 530 and the third gap filling pattern 550 are omitted, and the processes of forming the second gap filling pattern 540 are formed, and the processes of forming the fourth gap filling pattern 570 and the sixth gap filling pattern 590 are omitted, and the processes of forming the fifth gap filling pattern 580 are formed, the process time and process cost can be reduced.

[0107] As another example, the third gap fill pattern 550 can be omitted, and the second gap fill pattern 540 can be formed on the first gap fill pattern 530. Similarly, the sixth gap fill pattern 590 can be omitted, and the fifth gap fill pattern 580 can be formed on the third inner liner LN3A and the fourth gap fill pattern 570.

[0108] When the second gap-filling pattern 540 is formed of a single material on the second inner liner layer LN2A and the fifth gap-filling pattern 580 is formed of a single material on the third inner liner layer LN3A, voids may form inside the second gap-filling pattern 540 or the fifth gap-filling pattern 580, below the lower surface of the variable resistor pattern 523. Therefore, the first gap-filling pattern 530 can be formed before the second gap-filling pattern 540 is formed, and the fourth gap-filling pattern 570 can be formed before the fifth gap-filling pattern 580 is formed. Thus, voids can be substantially prevented from forming inside the second gap-filling pattern 540 or the fifth gap-filling pattern 580.

[0109] According to the manufacturing method described above, a first inner liner pattern LN1 and a second inner liner pattern LN2, as well as a second gap-filling pattern 540, can be formed covering the corners of the variable resistor pattern 523 in the second direction II. Furthermore, a third inner liner pattern LN3 and a fifth gap-filling pattern 580 covering the corners of the variable resistor pattern 523 in the first direction I can be formed. In this case, even if the programming and erasing operations of the memory cell 520 are repeatedly performed, degradation of the memory cell 520 can be prevented or reduced, and material included in the variable resistor pattern 523 can be prevented or reduced from separating to the outside of the memory cell 520 through the corners.

[0110] Although some specific embodiments of this disclosure have been described with reference to the accompanying drawings, the embodiments of this disclosure are not limited to those described above. Those skilled in the art to which this disclosure pertains can make various substitutions, modifications, and changes to the embodiments, and these also fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: First conductors, each first conductor extending in a first direction; The second conductor is located above the first conductor and extends in a second direction that intersects the first direction; Storage cells, each located between the first conductor and the second conductor, and each storage cell including a variable resistance pattern; A first gap-filling pattern is located between a pair of adjacent first conductors in the second direction; A second gap filling pattern is located on the first gap filling pattern; as well as A third gap-filling pattern is located between the first gap-filling pattern and the second gap-filling pattern. The third gap-filling pattern has a first interface with the first gap-filling pattern and a second interface with the second gap-filling pattern. The first interface is positioned below the lower surface of the variable resistor pattern, while the second interface is positioned above the upper surface of the variable resistor pattern.

2. The semiconductor device of claim 1, further comprising: First liner pattern, each first liner pattern covering the sidewall of a corresponding storage cell; as well as A second lining pattern is located on top of the first lining pattern, and each second lining pattern extends along the sidewall of a corresponding first conductor.

3. The semiconductor device of claim 2, wherein, At least one of the first lining pattern or the second lining pattern comprises the same material as the material of the third gap-filling pattern.

4. The semiconductor device as claimed in claim 1, wherein, The first gap-filling pattern comprises the same material as the second gap-filling pattern, and The third gap-filling pattern comprises a material different from that of the first gap-filling pattern.

5. The semiconductor device as claimed in claim 4, wherein, The first gap-filling pattern includes oxides, and The third gap filling pattern includes nitrides.

6. The semiconductor device of claim 5, wherein, The first gap-filling pattern comprises at least one of tetraethyl orthosilicate (TEOS) material or spin-coated low-k SOL material, and The third gap filling pattern includes at least one of silicon boron nitride (SiBN) or silicon carbon nitride (SiCN).

7. A semiconductor device, comprising: First conductors, each first conductor extending in a first direction; The second conductor is located above the first conductor and extends in a second direction that intersects the first direction; Storage cells, each located between the first conductor and the second conductor, and each storage cell including a variable resistance pattern; A first gap-filling pattern, located between a pair of adjacent first conductors in the second direction, and comprising oxide; and A third gap-filling pattern is located on the first gap-filling pattern. The third gap-filling pattern has a lower surface positioned below the lower surface of the variable resistor pattern and an upper surface positioned above the upper surface of the variable resistor pattern.

8. The semiconductor device of claim 7, further comprising: The second gap filling pattern is located on the third gap filling pattern.

9. The semiconductor device of claim 8, wherein, The first interface between the third gap filling pattern and the first gap filling pattern is located below the lower surface of the variable resistor pattern, and The second interface between the third gap filling pattern and the second gap filling pattern is located above the upper surface of the variable resistor pattern.

10. The semiconductor device of claim 8, wherein, The second gap-filling pattern comprises the same material as the first gap-filling pattern.

11. The semiconductor device of claim 7, wherein, The first gap-filling pattern comprises at least one of tetraethyl orthosilicate (TEOS) material or spin-coated low-k SOL material, and The third gap filling pattern includes at least one of silicon boron nitride (SiBN) or silicon carbon nitride (SiCN).

12. The semiconductor device of claim 7, further comprising: First liner pattern, each first liner pattern covering the sidewall of a corresponding storage cell; as well as A second lining pattern is located on top of the first lining pattern, and each second lining pattern extends along the sidewall of a corresponding first conductor.

13. The semiconductor device of claim 12, wherein, At least one of the first lining pattern or the second lining pattern comprises the same material as the material of the third gap-filling pattern.

14. A method for manufacturing a semiconductor device, the method comprising: A variable resistance layer is formed on the first conductive layer; Variable resistance lines are formed by etching the variable resistance layer; First conductive lines are formed by etching the first conductive layer, each first conductive line extending in a first direction; A first gap fill pattern is formed between an adjacent pair of first conductors, such that the upper surface of the first gap fill pattern is positioned below the lower surface of each of the adjacent pair of variable resistance lines. as well as A second gap-filling pattern is formed on the first gap-filling pattern such that the upper surface of the second gap-filling pattern is positioned above the upper surface of each of an adjacent pair of variable resistance lines.

15. The method of claim 14, wherein, The steps for forming the first gap-filling pattern include: A preliminary first gap-filling pattern is applied to fill the space between adjacent pairs of the first conductors, such that the upper surface of the preliminary first gap-filling pattern is positioned below the lower surface of each of the adjacent pair of variable resistance wires; and The first gap filling pattern is formed by solidifying the preliminary first gap filling pattern.

16. The method of claim 14, wherein, The steps for forming the second gap-filling pattern include: Deposit a second gap-filling layer on the first gap-filling pattern; and The second gap filling pattern is formed by etching the second gap filling layer such that the upper surface of the second gap filling pattern is positioned above the upper surface of each of an adjacent pair of variable resistance lines.

17. The method of claim 14, further comprising: Before forming the first conductor, a first inner liner is formed on the variable resistance line; The first liner pattern is formed by etching the first liner layer; The first conductive layer is etched to form the first wire; as well as A second liner layer is formed on the sidewall of the first conductor and on the first liner pattern.

18. The method of claim 17, wherein, At least one of the first liner or the second liner comprises the same material as the second gap-filling pattern.

19. The method of claim 14, further comprising: A second conductor is formed on the variable resistance line, and each second conductor extends in a second direction that intersects the first direction; A variable resistance pattern is formed by etching the variable resistance lines; as well as A third inner liner layer is formed on the variable resistance pattern.

20. The method of claim 19, further comprising: A fourth gap-filling pattern is formed such that the upper surface of the fourth gap-filling pattern is positioned below the lower surface of each of the adjacent pair of variable resistor patterns; A fifth gap-filling pattern is formed on the fourth gap-filling pattern, such that the upper surface of the fifth gap-filling pattern is positioned above the upper surface of each of the adjacent pair of variable resistor patterns; as well as A sixth gap filling pattern is formed on the fifth gap filling pattern.

21. The method of claim 14, further comprising: A third gap filling pattern is formed on the second gap filling pattern.

22. The method of claim 21, wherein, The first gap-filling pattern comprises the same material as the third gap-filling pattern, and The second gap-filling pattern comprises a material different from that of the first gap-filling pattern.

23. The method of claim 22, wherein, The first gap-filling pattern includes oxides, and The second gap filling pattern includes nitrides.

24. The method of claim 23, wherein, The first gap-filling pattern comprises at least one of tetraethyl orthosilicate (TEOS) material or spin-coated low-k SOL material, and The third gap filling pattern includes at least one of silicon boron nitride (SiBN) or silicon carbon nitride (SiCN).

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