Capacitor and forming method thereof

Abstract

The invention relates to a capacitor and a forming method thereof. According to the forming method, after a laminated structure comprising a plurality of sacrificial dielectric layers and a plurality of first conductive layers which are alternately stacked is formed on a substrate, a first polar plate connecting node which penetrates through the laminated structure and is connected with the first conductive layers is formed, then the sacrificial dielectric layers are removed through second through holes, gaps communicated with the second through holes are formed, and the first polar plate connecting node is connected with the first conductive layers. A capacitor dielectric layer is formed in the second through hole and the inner wall of the gap and filled with a second conducting layer, the second conducting layer formed corresponding to the second through hole serves as a second pole plate connecting node, the first conducting layer and the first pole plate connecting node form a first pole plate of the capacitor, and the second conducting layer forms a second pole plate of the capacitor; the polar plate area of the capacitor is related to the number of layers of the laminated structure, and the more the layers are, the larger the polar plate area is, so that the higher the capacitance density is, and high capacitance density and high integration level can be realized conveniently.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a capacitor and a method for forming the same. Background Technology

[0002] Capacitors are used in many semiconductor devices and circuits. For example, dynamic random access memory (DRAM) uses capacitors to store charge and maintains the charge in the capacitor at a level that can be read through periodic update operations. Some CMOS image sensors are equipped with lateral overflow capacitors that connect to the floating diffusion region to improve charge capacity. In supercomputing (HPC) circuits, ultra-high density capacitors are often used for decoupling.

[0003] Capacitance density represents the capacitance value of a capacitor per unit volume and can be used to measure the capacitor's ability to store charge. With technological advancements, many applications require capacitors with very high capacitance densities, such as ultra-high density capacitors. Currently, capacitor structures used to provide high or ultra-high capacitance densities include double- or multi-layer planar capacitors, deep trench capacitors, or integrated multilayer capacitors. Capacitance density can be increased by increasing the dielectric constant of the sacrificial dielectric layer and increasing the electrode surface area. However, for the above capacitor structures, further increasing the electrode surface area (i.e., increasing the integration density) within a limited space leads to a significant increase in manufacturing complexity and limited benefits, thus limiting the achievable capacitance density and integration density. Summary of the Invention

[0004] In order to obtain capacitors with high capacitance density and high integration, the present invention provides a method for forming a capacitor and a capacitor.

[0005] On one hand, the present invention provides a method for manufacturing a capacitor, the method comprising:

[0006] A stacked structure and a first isolation layer surrounding the side of the stacked structure are formed on a substrate. The stacked structure includes a plurality of sacrificial dielectric layers and a plurality of first conductive layers that are alternately stacked along the thickness direction of the substrate.

[0007] At least one first through-hole is formed through the stacked structure to expose each of the first conductive layers from the side, and the first through-hole is filled with conductive material to form a first electrode connection node connected to each of the first conductive layers;

[0008] A second isolation layer is formed covering the stacked structure, the first electrode connection node and the first isolation layer, and at least one second through hole is formed penetrating the second isolation layer and the stacked structure, the second through hole exposing each of the sacrificial dielectric layers and each of the first conductive layers from the side;

[0009] Etching the sacrificial dielectric layer to form a gap communicating with the second via, the gap exposing the surface of the first conductive layer that was originally adjacent to the sacrificial dielectric layer; and

[0010] A capacitor dielectric layer is formed on the inner wall of the second through hole and the gap, and a second conductive layer is filled in the second through hole and the gap. The second conductive layer formed corresponding to the second through hole is a second electrode connection node.

[0011] Optionally, forming a laminated structure on a substrate and a first insulating layer surrounding the sides of the laminated structure includes:

[0012] A first etch barrier layer, a multilayer film, and a second etch barrier layer are sequentially formed on the substrate. The multilayer film is formed by alternating stacking of multiple sacrificial dielectric layers and multiple first conductive layers.

[0013] An annular trench is formed penetrating the second etch barrier layer and the multilayer film, with its bottom surface exposed to the first etch barrier layer. The multilayer film and the second etch barrier layer defined by the annular trench form the stacked structure.

[0014] An isolation material is deposited within the annular trench and on the stacked structure, and a planarization process is performed using the second etch barrier layer as a stop layer. The remaining isolation material forms the first isolation layer.

[0015] Optionally, the bottom surfaces of the first through-hole and the second through-hole expose the first etch barrier layer; after forming the second electrode connection node, the fabrication method includes:

[0016] A third isolation layer is formed covering the second isolation layer and the second electrode connection node; and

[0017] A first electrode interconnect layer and a second electrode interconnect layer are formed on the surface of the third isolation layer. The first electrode interconnect layer is connected to the first electrode connection node through a first metal through-hole penetrating the third isolation layer and the second isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a second metal through-hole penetrating the third isolation layer.

[0018] Optionally, a first electrode bottom interconnect layer is formed on the substrate surface below the first etch barrier layer, the first electrode interconnect layer extending from the region forming the stacked structure to the region forming the first isolation layer; the bottom surface of the first through hole exposes the first electrode bottom interconnect layer, the first electrode connection node connects the first electrode bottom interconnect layer, and the bottom surface of the second through hole exposes the first etch barrier layer.

[0019] Optionally, after forming the second electrode connection node, the manufacturing method includes:

[0020] A third isolation layer is formed, the third isolation layer covering the stacked structure and the first isolation layer; and

[0021] A second electrode interconnect layer and a first electrode top interconnect layer are formed on the surface of the third isolation layer. The first electrode top interconnect layer is connected to the first electrode bottom interconnect layer through a third metal through-hole penetrating the third isolation layer and the first isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a fourth metal through-hole penetrating the third isolation layer.

[0022] Optionally, the first isolation layer comprises silicon oxide, and the second isolation layer comprises silicon nitride; after forming the second electrode connection node, the fabrication method includes:

[0023] The second isolation layer is etched to expose the first isolation layer;

[0024] Forming a nitride layer that covers the second isolation layer and exposes the first isolation layer; and

[0025] An oxide layer is covered on the first isolation layer and the nitrided layer, and the nitrided layer and the oxide layer constitute the third isolation layer.

[0026] Optionally, forming the first metal via and the second metal via includes:

[0027] Using the nitride layer and the first etching barrier layer as stop layers, the oxide layer and the first isolation layer are etched to form a via corresponding to the bottom interconnect layer of the first electrode plate and penetrating the oxide layer and the first isolation layer. A via corresponding to the connection node of the second electrode plate and penetrating the oxide layer is also formed.

[0028] Etching the silicon nitride layer and the first etch barrier layer exposed by the vias forms a first via exposing the bottom interconnect layer of the first electrode plate and a second via exposing the connection node of the second electrode plate, respectively; and

[0029] The first and second through holes are filled with conductive material to form the third and fourth metal through holes, respectively.

[0030] On one hand, the present invention provides a capacitor, the capacitor comprising:

[0031] Base;

[0032] A first isolation layer and a plurality of first conductive layers are formed on the substrate. The plurality of first conductive layers are respectively laid flat at different heights within the space surrounded by the first isolation layer, and there is a gap between adjacent first conductive layers that exposes the surface of the first conductive layer.

[0033] The first electrode plate connection node penetrates through the plurality of first conductive layers and is connected to each of the first conductive layers from the side.

[0034] The second isolation layer covers the plurality of first conductive layers and the first electrode plate connection node;

[0035] The second through hole penetrates the second isolation layer and the plurality of first conductive layers and connects the gap;

[0036] A capacitor dielectric layer is formed in the second through-hole and the inner wall of the gap; and

[0037] The second conductive layer covers the capacitor dielectric layer and fills the second through hole and the gap. The second conductive layer formed corresponding to the second through hole is the second electrode connection node.

[0038] Optionally, the capacitor further includes:

[0039] A first etch barrier layer is formed on the surface of the substrate, and a first isolation layer and the plurality of first conductive layers are formed on the first etch barrier layer; and

[0040] The second etch barrier layer is located above the first conductive layer, which is furthest from the substrate. The first electrode connection node, the second through hole, and the second electrode connection node all penetrate the second etch barrier layer.

[0041] Optionally, the bottom ends of the first electrode connection node and the second electrode connection node are connected to the first etching barrier layer; the capacitor further includes:

[0042] A third isolation layer covers the second isolation layer and the second electrode plate connection node; and

[0043] A first electrode interconnect layer and a second electrode interconnect layer are formed on the surface of the third isolation layer. The first electrode interconnect layer is connected to the first electrode connection node through a first metal through-hole penetrating the third isolation layer and the second isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a second metal through-hole penetrating the third isolation layer.

[0044] Optionally, a first electrode bottom interconnect layer is formed on the substrate surface, located below the first etch barrier layer. The first electrode bottom interconnect layer extends from below the first electrode connection node to below the first isolation layer. The bottom end of the first electrode connection node is connected to the first electrode bottom interconnect layer, and the bottom end of the second electrode connection node is connected to the first etch barrier layer.

[0045] Optionally, the capacitor further includes:

[0046] A third isolation layer covers the second isolation layer and the second electrode plate connection node; and

[0047] A first electrode top interconnect layer and a second electrode interconnect layer are formed on the surface of the third isolation layer. The first electrode top interconnect layer is connected to the first electrode bottom interconnect layer through a third metal through-hole penetrating the third isolation layer and the first isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a fourth metal through-hole penetrating the third isolation layer.

[0048] In the capacitor manufacturing method provided by this invention, after forming a stacked structure comprising alternatingly stacked sacrificial dielectric layers and multiple first conductive layers on a substrate, a first electrode connection node is formed that penetrates the stacked structure and connects each of the first conductive layers. Then, the sacrificial dielectric layer is removed using a second through-hole, forming a gap communicating with the second through-hole. This gap exposes the surface of the first conductive layer that was originally adjacent to the sacrificial dielectric layer. A capacitor dielectric layer is then formed in the second through-hole and the inner wall of the gap, and a second conductive layer is filled. The first conductive layer and the first electrode connection node constitute the first electrode of the capacitor, and the second conductive layer constitutes the second electrode of the capacitor. The electrode area of ​​the capacitor is related to the number of layers in the stacked structure; the more layers, the larger the electrode area, and thus the higher the capacitance density. Therefore, it is easy to achieve high capacitance density. Furthermore, by setting the stacked structure in the thickness direction of the substrate to obtain high capacitance density, the capacitor structure is compact, requiring a small substrate area to achieve high capacitance density, which also facilitates high integration.

[0049] In the capacitor provided by this invention, a first electrode connection node is connected to the plurality of first conductive layers to form the first electrode of the capacitor. A second through-hole penetrates the plurality of first conductive layers and connects the gaps between the plurality of first conductive layers. A capacitor dielectric layer is formed in the second through-hole and the inner wall of the gap. A second conductive layer covers the capacitor dielectric layer and forms the second electrode of the capacitor. The electrode area of ​​the capacitor is related to the number of first conductive layers; the more layers, the larger the electrode area, and thus the higher the capacitance density. Therefore, it is easy to achieve high capacitance density. Furthermore, by setting multiple first conductive layers in the thickness direction of the substrate to obtain high capacitance density, the capacitor structure is compact, and the substrate area required to achieve high capacitance density is small, which also facilitates high integration. Attached Figure Description

[0050] Figure 1 This is a schematic flowchart of a capacitor manufacturing method according to an embodiment of the present invention.

[0051] Figures 2A to 2L This is a cross-sectional schematic diagram of a method for manufacturing a capacitor according to an embodiment of the present invention.

[0052] Figure 3 This is a planar schematic diagram of the first through hole and the second through hole in one embodiment of the present invention.

[0053] Figures 4A to 4I This is a cross-sectional schematic diagram of a method for manufacturing a capacitor according to another embodiment of the present invention. Detailed Implementation

[0054] The capacitor and its forming method of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be understood that the drawings in this specification are in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. It should be noted that the order of the steps in the method presented herein is not necessarily the only order in which these steps are performed; some steps may be omitted and / or some other steps not described herein may be added to the method. It should be understood that spatial relative terms are intended to include different orientations in use or operation other than the orientation of the device as depicted in the figures. For example, if the structure in the figures is inverted or otherwise positioned (e.g., rotated), the exemplary term "on" may also include "below" and other orientational relationships.

[0055] Reference Figure 1This invention includes a method for manufacturing a capacitor. In this method, after forming a stacked structure comprising alternatingly stacked sacrificial dielectric layers and multiple first conductive layers on a substrate, a first electrode connection node is formed that penetrates the stacked structure and connects each of the first conductive layers. Then, the sacrificial dielectric layers are removed using a second through-hole, creating a gap between adjacent first conductive layers that communicates with the second through-hole. This gap exposes the surface of the first conductive layer that was originally adjacent to the sacrificial dielectric layer. A capacitor dielectric layer and a second conductive layer are then formed on the inner wall of the second through-hole and the gap. The first conductive layer and the first electrode connection node constitute the first electrode of the capacitor, and the second conductive layer constitutes the second electrode of the capacitor. The electrode area of ​​the capacitor is related to the number of layers in the stacked structure; the more layers, the larger the electrode area, and thus the higher the capacitance density. This facilitates achieving high capacitance density. Furthermore, by increasing the number of layers in the stacked structure in the thickness direction of the substrate to obtain high capacitance density, the capacitor structure becomes compact, requiring a small substrate area to achieve high capacitance density, which also facilitates high integration.

[0056] The method for manufacturing the capacitor is further described in detail below using Embodiment 1 and Embodiment 2, as well as the accompanying drawings. It should be understood that Embodiment 1 and Embodiment 2 are described separately only to more clearly illustrate the meaning of the present invention. They are merely exemplary specific implementations of the manufacturing and application embodiments and do not constitute a limitation on the scope of the manufacture and application of the present invention. Furthermore, the technical features mentioned in each embodiment are not all unique to that embodiment, and all features of each embodiment can also be considered as features of a general embodiment. In some implementations, the technical features of the following multiple embodiments can also be related to and inspired by each other to constitute new embodiments.

[0057] Example 1

[0058] Reference Figure 1 , Figures 2A to 2C The method for manufacturing the capacitor includes step S1: forming a stacked structure 10 and a first isolation layer 120 surrounding the side of the stacked structure 10 on a substrate 100. The stacked structure 10 includes a plurality of sacrificial dielectric layers 111 and a plurality of first conductive layers 112 alternately stacked along the thickness direction of the substrate 100.

[0059] The substrate 100 may include semiconductor substrates such as silicon substrates, germanium (Ge) substrates, germanium-silicon substrates, SOI (Silicon on Insulator) substrates, or GOI (Germanium on Insulator) substrates. Depending on the requirements, the semiconductor substrate may undergo various semiconductor processes (such as deposition, etching, ion implantation, etc.), and therefore the substrate 100 may also include semiconductor elements formed on the semiconductor substrate. These semiconductor elements may include active or passive circuit elements, such as at least one of MOS devices, sensor devices, and memory devices. As an example, the substrate 100 is a silicon substrate.

[0060] As an example, when performing step S1, firstly, as Figure 2A As shown, a first etch barrier layer 102, a multilayer film 110, and a second etch barrier layer 103 are sequentially formed on a substrate 100. The multilayer film 110 is formed by alternatingly stacking multiple sacrificial dielectric layers 111 and multiple first conductive layers 112. "Alternating stacking" means that after stacking a sacrificial dielectric layer 111 on the substrate 100, a first conductive layer 112 is stacked first and then another sacrificial dielectric layer 111 is stacked, and after stacking a first conductive layer 112, a sacrificial dielectric layer 111 is stacked first and then another first conductive layer 112 is stacked.

[0061] The first etch barrier layer 102 subsequently acts as an etch barrier when forming through-holes in the stacked structure 10. The first etch barrier layer 102 is, for example, silicon nitride. Before forming the first etch barrier layer 102, a pad oxide layer 101 (e.g., silicon oxide) may be formed on the surface of the substrate 100.

[0062] The sacrificial dielectric layer 111 is used to isolate adjacent first conductive layers 112 and control the spacing between adjacent first conductive layers 112. The sacrificial dielectric layer 111 is, for example, silicon oxide. The first conductive layer 112 is used to form the first electrode (or lower electrode) of the capacitor, and may include a conductive material suitable for use as a capacitor electrode and suitable for implementing the fabrication method of this embodiment, such as tungsten (W), tungsten silicide (SiW), titanium (Ti), titanium nitride (TiN), or doped polycrystalline silicon, etc. Here, as an example, the first conductive layer 112 is titanium nitride (TiN).

[0063] When forming the multilayer film 110 by alternately stacking multiple sacrificial dielectric layers 111 and multiple first conductive layers 112, the alternating stacking can begin with the sacrificial dielectric layer 111 or with the first conductive layer 112 on the first etch barrier layer 102. In this embodiment, the number of sacrificial dielectric layers 111 and first conductive layers 112 in the multilayer film 110 is, for example, equal. The multilayer film 110 can be regarded as a stack of multiple repeating units, where the repeating unit is a stack of sacrificial dielectric layers 111 and first conductive layers 112. However, it is not limited to this. In another embodiment, the number of sacrificial dielectric layers 111 and first conductive layers 112 in the multilayer film 110 may not be equal, wherein the bottom layer and the top layer of the multilayer film 110 are both sacrificial dielectric layers 111 or both are first conductive layers 112.

[0064] The second etch barrier layer 103 is stacked on the upper surface of the multilayer film 110. It can serve as a stop layer for etching or polishing processes during the subsequent formation of the first isolation layer 120, for example, it can act as an etch barrier when the sacrificial dielectric layer 111 is subsequently etched away. The second etch barrier layer 103 is, for example, made of silicon nitride.

[0065] like Figure 2B As shown, next, the area where the stacked structure is to be fabricated (i.e., the area where the capacitor is to be formed) can be defined by forming a photoresist layer and performing a photolithography process. Then, the second etch barrier layer 103 is etched to form a patterned hard mask layer. Afterwards, the multilayer film 110 is etched using an anisotropic dry etching process to form an annular trench 20 that penetrates the second etch barrier layer 103 and the multilayer film 110, with the bottom surface exposed by the first etch barrier layer 102. The multilayer film 110 and the second etch barrier layer 103 surrounded by the annular trench 20 form a stacked structure 10. Optionally, during the etching process, part of the first etch barrier layer 102 is also etched away, such that... Figure 2B As shown, the bottom surface of the annular trench 20 is lower than the lowest layer of the multilayer film 110 (e.g., the sacrificial dielectric layer 111).

[0066] like Figure 2CAs shown, next, an isolation material (such as silicon oxide) is deposited in the annular trench 20 and on the stacked structure 10 using processes such as PECVD (plasma-enhanced chemical vapor deposition), HDPCVD (high-density chemical vapor deposition), or SOD (spin-on insulating dielectric). A planarization process is then performed using the second etch stop layer 103 as a stop layer. The planarization process is, for example, CMP. After depositing the isolation material in the annular trench 20 and on the stacked structure 10, the isolation material above the annular trench 20 and above the second etch stop layer 103 is removed by CMP. The remaining isolation material is located in the annular trench 20 and its top surface is flush with the top surface of the second etch stop layer 103. The isolation material located in the annular trench 20 forms the first isolation layer 120. In another embodiment, the thickness of the stacked structure 10 is high, and therefore the depth of the annular trench 20 is large. After the isolation material is deposited, the thickness of the isolation material above the stacked structure 10 is much greater than the thickness of the isolation material above the annular trench 20. At this time, a mask layer can be used to protect the isolation material above the annular trench 10, and an etching process can be performed to remove part of the isolation material above the stacked structure 10. Then, CMP is performed so that the remaining isolation material is located in the annular trench 20 and its top surface is flush with the upper surface of the second etch barrier layer 103. The isolation material located in the annular trench 20 forms the first isolation layer 120.

[0067] Reference Figure 1 , Figures 2D to 2E The method for manufacturing the capacitor includes step S2: forming at least one through-hole T1 through a stacked structure 10 to expose each first conductive layer 112 from the side, and filling the first through-hole T1 with conductive material to form a first electrode connection node N1 connected to each first conductive layer 112.

[0068] As an example, when performing step S2, firstly, as Figure 2D As shown, the location of the first through-hole T1 can be defined by forming a patterned photoresist layer (not shown) on the substrate 100, and then the second etch barrier layer 103 and each sacrificial dielectric layer 111 and the first conductive layer 112 in the stacked structure 10 are etched sequentially. Optionally, during the etching process, part of the first etch barrier layer 103 is etched, so that the first through-hole T1 extends from the upper surface of the second etch barrier layer 103 into the first etch barrier layer 102, and the bottom surface of the first through-hole T1 exposes the first etch barrier layer 102; then, as... Figure 2E As shown, a conductive material is deposited on the substrate 100, which fills the first through hole T1 and covers the stacked structure 10 and the first isolation layer 120. Then, a planarization process is used to remove the conductive material above the first through hole T1 and above the stacked structure 10, so that the remaining conductive material fills the first through hole T1 and its upper surface is flush with the upper surface of the second etch barrier layer 103.

[0069] In this embodiment, the conductive material within the first through-hole T1 contacts and connects each of the first conductive layers 112, thus serving as the first electrode plate of the capacitor. The conductive material is, for example, the same as the material of the first conductive layer 112 (e.g., titanium nitride (TiN)). This conductive material within the first through-hole T1 forms the electrode signal terminal of the first electrode plate, referred to as the first electrode plate connection node N1. The first electrode plate connection node N1 can also provide structural support for the capacitor in the thickness direction (i.e., longitudinal direction) of the stacked structure 10; therefore, its number can be set as needed. To enhance support, for example, more than or equal to two first through-holes T1 are formed within the same stacked structure 10.

[0070] Reference Figure 1 , Figure 2F and Figure 2G The method for manufacturing the capacitor includes step S3: forming a second isolation layer 130 covering the stacked structure 10, the first electrode connection node N1 and the first isolation layer 120, and forming at least one second through hole T2 penetrating the second isolation layer 130 and the stacked structure 10, wherein the second through hole T2 exposes each sacrificial dielectric layer 111 and each first conductive layer 112 from the side.

[0071] As an example, when performing step S3, firstly, as Figure 2F As shown, a second isolation layer 130 is formed. This second isolation layer 130 can serve as a hard mask in the subsequent process of forming the second via, and also protects the first isolation layer 120 from above and acts as an etching barrier during the subsequent removal of the sacrificial dielectric layer 111. Here, the second isolation layer 130 is, for example, made of silicon nitride. Then, as... Figure 2G As shown, the location of the second via can be defined by forming a patterned photoresist layer (not shown) on the substrate 100, and then the second isolation layer 130, the second etch barrier layer 103, and each of the sacrificial dielectric layers 111 and the first conductive layer 112 in the stacked structure 10 are etched sequentially to form the second via T2. The bottom surface of the second via T2 exposes the first etch barrier layer 102. Optionally, during this etching, a portion of the first etch barrier layer 102 is etched away, thereby forming the second via T2 that extends from the upper surface of the second isolation layer 130 into the first etch barrier layer 102.

[0072] The second through-hole T2 is used for subsequent removal of the sacrificial dielectric layer 111 and for filling with conductive material used as the second electrode plate of the capacitor. The number and position of the second through-hole T2 can be set as needed. To facilitate the removal of the sacrificial dielectric layer 111, for example, more than or equal to two second through-holes T2 are formed within the same stacked structure 10.

[0073] Figure 3 The planar arrangement of the first through hole T1 and the second through hole T2 in one embodiment is shown. (Refer to...) Figure 3 In this embodiment, the cross-section of the laminated structure 10 is, for example, square. Multiple first through holes T1 penetrating the laminated structure 10 are arranged in multiple rows and columns within the cross-section of the laminated structure 10, with equal row and column spacing. Multiple second through holes T2 are also arranged in multiple rows and columns within the cross-section of the laminated structure 10, with equal row and column spacing. Furthermore, all through holes (including the first through holes T1 and the second through holes T2) are arranged in multiple rows and columns within the cross-section of the laminated structure 10. Figure 3 As shown, the distance between each pair of adjacent first through holes T1 and second through holes T2 is equal. However, the invention is not limited to this; in another embodiment, the first through holes T1 and / or the second through holes T2 may not be uniformly arranged within the cross-section of the laminated structure 10. Furthermore, the cross-sections of the first through holes T1 and the second through holes T2 are not limited to... Figure 3 The circle shown can be any of the two shapes, such as a polygon, an ellipse, or a semicircle. Figures 2A to 2L For example, along Figure 3 The cross section taken from line AA'.

[0074] Reference Figure 1 and Figure 2H The method for manufacturing the capacitor includes step S4: etching the sacrificial dielectric layer 111 to form a gap 30 communicating with the second through hole T2, wherein the gap 30 exposes the surface of the first conductive layer 112 that was originally adjacent to the sacrificial dielectric layer 111.

[0075] Step S4, for example, involves wet etching of the sacrificial dielectric layer 111. By setting suitable etching conditions, the sacrificial dielectric layer 111 can be completely removed. The gap 30 formed at the original location of the sacrificial dielectric layer 111 communicates with the second through-hole T2 and exposes the surfaces of the first conductive layers 112 on both sides. The gap 30 exposes the opposing surfaces of adjacent first conductive layers 112.

[0076] Reference Figure 1 and Figure 2I The method for manufacturing the capacitor includes step S5: forming a capacitor dielectric layer 140 on the inner wall of the second through hole T2 and the gap 30, and filling the second through hole T2 and the gap 30 with a second conductive layer 150, wherein the second conductive layer 150 formed corresponding to the second through hole T2 is the second electrode connection node N2.

[0077] The capacitor dielectric layer 140 can be formed using an ALD (Atomic Layer Deposition) process. The capacitor dielectric layer 140 covers the second through-hole T2 and the inner wall of the gap 30, but does not completely fill the second through-hole T2 and the gap 30. The thickness of the capacitor dielectric layer 140 can be set according to specific requirements. The capacitor dielectric layer 140 can also be formed on the upper surface of the second isolation layer 130. The capacitor dielectric layer 140 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide (HfO), and arsenic oxide (As2O5). Here, as an example, the capacitor dielectric layer 140 uses silicon nitride. To improve capacitance density, the capacitor dielectric layer 140 may use a high-k material.

[0078] The second conductive layer 150 covers and fills the capacitor dielectric layer 140 within the second through-hole T2 and the gap 30. When forming the second conductive layer 150, for example, an ALD process is first used to deposit a conductive material (such as titanium nitride (TiN)) within the second through-hole T2 and the gap 30 and on the upper surface of the second isolation layer 130, so that the second through-hole T2 and the gap 30 are gradually filled and closed. Then, a planarization process (such as CMP) is performed to remove the conductive material outside the second through-hole T2. The remaining conductive material fills the second through-hole T2 and the gap 30, forming the second conductive layer 150. The second conductive layer 150 is used to form the second electrode of the capacitor. The conductive material within the first through-hole T2 serves as the electrode signal terminal of the second electrode, referred to as the second electrode connection node N2.

[0079] After completing the above process, the method for manufacturing the capacitor may further include the following steps:

[0080] like Figure 2J As shown, a third isolation layer 160 is formed covering the second isolation layer 130 and the second electrode connection node N2, for example, the third isolation layer 160 is formed using silicon oxide;

[0081] like Figure 2K As shown, a first metal via VIA1 is formed that penetrates the third isolation layer 160 and the second isolation layer 130 and connects to the first electrode connection node N1. A second metal via VIA2 is also formed that penetrates the third isolation layer 160 and connects to the second electrode connection node N2. For example, by etching, a via penetrating the third isolation layer 160 and the second isolation layer 130 and exposing the first electrode connection node N1 is first formed, and a via penetrating the third isolation layer 160 and exposing the second electrode connection node N2 is formed. Then, a conductive material (such as tungsten) is deposited in the via and on the third isolation layer 160 and a planarization process is performed so that the remaining conductive material is located in the via, thereby forming the first metal via VIA1 and the second metal via VIA2.

[0082] like Figure 2LAs shown, a first electrode interconnect layer 171 and a second electrode interconnect layer 172 are formed on the surface of the third isolation layer 160. The first electrode interconnect layer 171 is connected to each first electrode connection node N1 through a first metal through-hole VIA1, and the second electrode interconnect layer 172 is connected to each second electrode connection node N2 through a second metal through-hole VIA2. As an example, a dielectric layer 104 can be formed on the third isolation layer 160 first, and the first electrode interconnect layer 171 and the second electrode interconnect layer 172 can be formed in the dielectric layer 104 using a damascus process. The first electrode interconnect layer 171 and the second electrode interconnect layer 172 can be formed, for example, using copper.

[0083] In the capacitor formed by the above manufacturing method, the first plate connection node N1 is connected to the first plate interconnection layer 171, and the second plate connection node N2 is connected to the second plate interconnection layer 172. Electrical signals can be input to the two plates of the capacitor through the first plate interconnection layer 171 and the second plate interconnection layer 172 respectively, and the corresponding capacitance density can be obtained.

[0084] Example 2

[0085] Example 2 relates to a method for manufacturing a capacitor, which differs from the method described in Example 1 in that, in the method described in Example 1, both the first plate connection node N1 and the second plate connection node N2 are electrically led out from their ends away from the substrate 100, and their ends facing the substrate 100 contact the first etch barrier layer 102. However, in the method of Example 2, the second plate connection node N2 is electrically led out from its end away from the substrate 102, and the first plate connection node N1 is electrically led out from its end facing the substrate 100. Detailed explanation follows.

[0086] Reference Figure 1 and Figure 4A The method for manufacturing a capacitor in this embodiment (Embodiment 2) includes step S1: forming a stacked structure 10 and a first isolation layer 120 surrounding the side of the stacked structure 10 on a substrate 100. The stacked structure 10 includes a plurality of sacrificial dielectric layers 111 and a plurality of first conductive layers 112 that are alternately stacked along the thickness direction of the substrate 100.

[0087] The execution process of step S1 can be referred to the description of Embodiment 1 above. For example, a pad oxide layer 101, a first etch barrier layer 102, a multilayer film 110 formed by alternating stacking of multiple sacrificial dielectric layers 110 and multiple first conductive layers 111, and a second etch barrier layer 103 can be formed on the substrate 100. Then, an annular trench 20 is formed that penetrates the second etch barrier layer 103 and the multilayer film 110 and exposes the bottom surface of the first etch barrier layer 102. The multilayer film 110 and the second etch barrier layer 103 defined by the annular trench 20 form a stacked structure 10. After that, an isolation material is deposited, and a planarization process is performed with the second etch barrier layer 103 as a stop layer. The remaining isolation material is filled in the annular trench 20 to form a first isolation layer 120.

[0088] like Figure 4A As shown, in this embodiment, an interconnect layer is formed on the surface of the substrate 100 below the first etch barrier layer 102 and for connection with the first electrode plate connection node. This interconnect layer is located below the stacked structure 10 and is referred to as the first electrode plate bottom interconnect layer 105 for distinction. The first electrode plate bottom interconnect layer 105 extends laterally from the region forming the stacked structure 10 to the region forming the first isolation layer 120, facilitating the subsequent formation of metal vias extending from the first electrode plate bottom interconnect layer 105 to above the first isolation layer 120 in the region of the first isolation layer 120.

[0089] Reference Figure 1 and Figure 4B The capacitor manufacturing method of this embodiment includes step S2: forming at least one through-hole T1 of the through-layer structure 10 to expose each first conductive layer 112 from the side, and filling the first through-hole T1 with conductive material to form a first electrode connection node N1 connected to each first conductive layer 112.

[0090] The specific process for forming the first through-hole T1 and the first electrode plate connection node N1 can refer to the above embodiment one. The position and depth of the first through-hole T1 can be set according to the requirements of this embodiment. In this embodiment, the first through-hole T1 is formed corresponding to the bottom interconnect layer 105 of the first electrode plate located below the stacked structure 10, so that after the first through-hole T1 is formed, the bottom surface of the first through-hole T1 exposes the bottom interconnect layer 105 of the first electrode plate. After filling the first through-hole T1 with conductive material to form the first electrode plate connection node N1, the end of the first electrode plate connection node N1 facing the substrate 100 is connected to the bottom interconnect layer 105 of the first electrode plate.

[0091] Reference Figure 1 and Figure 4CThe capacitor manufacturing method of this embodiment includes step S3: forming a second isolation layer 130 covering the stacked structure 10, the first electrode connection node N1 and the first isolation layer 120, and forming at least one second through hole T2 penetrating the second isolation layer 130 and the stacked structure 10, wherein the second through hole T2 exposes each sacrificial dielectric layer 111 and each first conductive layer 112 from the side.

[0092] The process for forming the second isolation layer 130 and the second through-hole T2 can be referred to the description in Embodiment 1. In this embodiment, the second through-hole T2 is subsequently used to form a second electrode connection node, which is electrically led out from the end away from the substrate 100. Therefore, the bottom surface of the second through-hole T2 exposes the first etch barrier layer 102. The planar arrangement of the first through-hole T1 and the second through-hole T2 can be referred to... Figure 3 .

[0093] Reference Figure 1 and Figure 4D The capacitor fabrication method of this embodiment includes step S4: etching the sacrificial dielectric layer 111 to form a gap 30 communicating with the second through-hole T2 between adjacent first conductive layers 112. The gap 30 exposes the surface of the first conductive layer 112 that was originally adjacent to the sacrificial dielectric layer 111. The gap 30 exposes the opposing surfaces of adjacent first conductive layers 112.

[0094] Reference Figure 1 and Figure 4E The capacitor manufacturing method of this embodiment includes step S5: forming a capacitor dielectric layer 140 on the inner wall of the second through hole T2 and the gap 30, and filling the second through hole T2 and the gap 30 with a second conductive layer 150, wherein the second conductive layer 150 formed corresponding to the second through hole T2 is the second electrode connection node N2. The process for steps S4 to S5 can be referred to the above embodiment one.

[0095] After forming the second electrode plate connection node N2, this embodiment may further include the following process.

[0096] Reference Figure 4FA third isolation layer 160 is formed, which covers the second isolation layer 130, the second electrode connection node N2, and the first isolation layer 120. Optionally, the first isolation layer 120 includes silicon oxide, and the second isolation layer 130 includes silicon nitride. To facilitate the subsequent formation of a metal via in the first isolation layer 120 to connect the bottom interconnect layer 105 of the first electrode, before forming the third isolation layer 160, the second isolation layer 130 is etched to expose the upper surface of the first isolation layer 120 (if the upper surface of the second isolation layer 130 is covered by the capacitor dielectric layer 140, the capacitor dielectric layer 140 is etched first, and then the second isolation layer 130 is etched). After that, a nitride layer 161 (such as silicon nitride) is formed that covers the second isolation layer 130 and exposes the first isolation layer 120, and an oxide layer 162 (such as silicon oxide) is covered on the exposed first isolation layer 120 and the nitride layer 161. The nitride layer 161 and the oxide layer 162 constitute the third isolation layer 160.

[0097] Reference Figure 4G Next, a first via 41 is formed, penetrating the third isolation layer 160, the first isolation layer 120, and the first etch barrier layer 102 and exposing the bottom interconnect layer 105 of the first electrode plate. A second via 42 is also formed, penetrating the third isolation layer 160 and exposing the second electrode plate connection node N2. In this embodiment, forming the first via 41 requires sequentially etching the oxide layer 162, the first isolation layer 120 (e.g., silicon oxide), and the first etch barrier layer 102 (e.g., silicon nitride) in the third isolation layer 160. Forming the second via 42 requires sequentially etching the oxide layer 162 and the nitride layer 161 in the third isolation layer 160. Therefore, the oxide layer 162 in the region where the second via 42 is formed and the oxide layer 162 in the region where the first via 41 is formed can be etched simultaneously with the nitride layer 161 and the first etch barrier layer 102 as barrier layers. Then, the nitride layer 161 and the first etch barrier layer 102 can be etched simultaneously to form the first via 41 and the second via 42.

[0098] Reference Figure 4H Then, conductive material (such as tungsten) is filled into the first through hole 41 and the second through hole 42. For example, conductive material is first deposited in the first through hole 41 and the second through hole 42 and on the third isolation layer 160 and planarized so that the remaining conductive material is only located in the first through hole 41 and the second through hole 42, thus forming the third metal through hole VIA3 and the fourth metal through hole VIA4 respectively. The third metal through hole VIA3 penetrates the third isolation layer 160 and the first isolation layer 120 and is connected to the bottom interconnect layer 105 of the first electrode plate. Thus, the third metal through hole VIA3 is connected to the first electrode plate connection node N1 through the bottom interconnect layer 105 of the first electrode plate. The fourth metal through hole VIA4 penetrates the third isolation layer 160 and is connected to the second electrode plate connection node N2.

[0099] Reference Figure 4I Subsequently, a second electrode interconnect layer 172 and a first electrode top interconnect layer 173 are formed on the surface of the third isolation layer 160. The first electrode top interconnect layer 173 is connected to the first electrode bottom interconnect layer 105 located on the surface of the substrate 100 through a third metal via VIA3. The second electrode interconnect layer 172 is connected to the second electrode connection node N2 through a fourth metal via VIA4. As an example, a dielectric layer 104 can be formed on the third isolation layer 160 first, and the second electrode interconnect layer 172 and the first electrode top interconnect layer 173 can be formed in the dielectric layer 104 using a damascus process. The second electrode interconnect layer 172 and the first electrode top interconnect layer 173 can be formed, for example, using copper.

[0100] In this embodiment, the second electrode interconnect layer 172 is connected to the second electrode connection node N2 through the fourth metal through-hole VIA4. Therefore, from a top view, at least a portion of the second electrode interconnect layer 172 is located in the region of the stacked structure 10. The first electrode connection node N1 is connected to the first electrode bottom connection layer 105 located on the surface of the substrate 100, and is connected to the first electrode top interconnect layer 173 located above the first isolation layer 120 through the first electrode bottom connection layer 105 and the third metal through-hole VIA3. Therefore, the first electrode top interconnect layer 173 can be disposed on the periphery of the stacked structure 10. Thus, the second electrode interconnect layer 172 can be formed as a metal block connecting each second electrode connection node N2 above the stacked structure 10. Therefore, in this embodiment, the manufacturing difficulty of the second electrode interconnect layer 172 and the first electrode top interconnect layer 173 is relatively low.

[0101] Using the capacitor fabrication method described in Embodiments 1 and 2 above, a capacitor including a first conductive layer 112, a first electrode connection node N1, a capacitor dielectric layer 140, and a second conductive layer 150 (including a second electrode connection node N2) is formed on a substrate 100. The electrode area of ​​the capacitor is related to the number of layers in the stacked structure 10. The more layers there are, the larger the electrode area is, and thus the higher the capacitance density is. Moreover, the substrate area required to achieve high capacitance density is small, so it is easy to achieve high capacitance density and high integration.

[0102] The present invention also includes a capacitor, which can be formed using the capacitor manufacturing methods described in Embodiments 1 and 2 above.

[0103] Reference Figures 2A to 2L , Figure 3 and Figures 4A to 4IThe capacitor includes a substrate 100, a first insulating layer 120 formed on the substrate 100, a plurality of first conductive layers 112, a first electrode connection node N1, a second insulating layer 130, a capacitor dielectric layer 140, and a second conductive layer 150. The plurality of first conductive layers 112 are respectively laid flat at different heights within the space surrounded by the first insulating layer 120, and there is a gap 30 between adjacent first conductive layers 112 that exposes the surface of the first conductive layer 112. The first electrode connection node N1 is filled with a first through hole T1 to penetrate the plurality of first conductive layers. 112 and connects each of the first conductive layers 112 from the side. The second isolation layer 130 covers the plurality of first conductive layers 112 and the first electrode connection node N1. The second through hole T2 penetrates the second isolation layer 130 and the plurality of first conductive layers 112 and connects the gap 30. The capacitor dielectric layer 140 is formed in the second through hole T2 and the inner wall of the gap 30. The second conductive layer 150 covers the capacitor dielectric layer 140 and fills the second through hole T2 and the gap 30. The second conductive layer 150 formed corresponding to the second through hole T2 is the second electrode connection node N2.

[0104] Optionally, the capacitor further includes a first etch barrier layer 102 and a second etch barrier layer 103. The first etch barrier layer 102 is formed on the surface of the substrate 100, and the first isolation layer 120 and the plurality of first conductive layers 112 are formed above the first etch barrier layer 102. The second etch barrier layer 103 is located above the first conductive layer 112 furthest from the substrate 100, and the first through-hole T1, the first electrode connection node N1, the second through-hole T2, and the second electrode connection node N2 all penetrate the second etch barrier layer 103.

[0105] Reference Figure 2L In some embodiments, both the first electrode connection node N1 and the second electrode connection node N2 are electrically led out from their ends away from the substrate 100. The bottom ends of the first electrode connection node N1 and the second electrode connection node N2 are connected to the first etch barrier layer 102. The capacitor may also include a third isolation layer 160 covering the second isolation layer 130 and the second electrode connection node N2, and a first electrode interconnect layer 171 and a second electrode interconnect layer 172 formed on the surface of the third isolation layer 160. The first electrode interconnect layer 171 is connected to the first electrode connection node N1 through a first metal via VIA1 penetrating the third isolation layer 160 and the second isolation layer 130, and the second electrode interconnect layer 172 is connected to the second electrode connection node N2 through a second metal via VIA2 penetrating the third isolation layer 160.

[0106] Reference Figure 4IIn other embodiments, the second electrode connection node N2 is electrically led out from its end away from the substrate 100, and the first electrode connection node N1 is electrically led out from its end facing the substrate 100. A first electrode bottom interconnect layer 105 is formed on the surface of the substrate 100, located below the first etch barrier layer 102. The first electrode bottom interconnect layer 105 extends from below the first electrode connection node N1 to below the first isolation layer 120. The bottom end of the first electrode connection node N1 is connected to the first electrode bottom interconnect layer 105, and the bottom end of the second electrode connection node N2 is connected to the first etch barrier layer 102. The capacitor may further include a third isolation layer 160 covering the second isolation layer 130 and the second plate connection node N2, and a first plate top interconnection layer 173 and a second plate interconnection layer 172 formed on the surface of the third isolation layer 160. The first plate top interconnection layer 173 is connected to the first plate bottom interconnection layer 105 through a third metal via VIA3 penetrating the third isolation layer 160, the first isolation layer 120 and the first etch barrier layer 102. The second plate interconnection layer 172 is connected to the second plate connection node N2 through a fourth metal via VIA4 penetrating the third isolation layer 160.

[0107] In the capacitor described in this embodiment of the invention, a first electrode connection node N1 is connected to a plurality of first conductive layers 112 surrounded by a first isolation layer 120 to form the first electrode of the capacitor. A second through hole T2 penetrates the plurality of first conductive layers 112 and connects the gaps 30 between the plurality of first conductive layers 112. A capacitor dielectric layer 140 is formed in the second through hole T2 and the inner wall of the gaps 30. A second conductive layer 150 covers the capacitor dielectric layer 140 and forms the second electrode of the capacitor. The electrode area of ​​the capacitor is related to the number of first conductive layers 112. The more layers, the larger the electrode area, and thus the higher the capacitance density. Therefore, it is easy to achieve high capacitance density. Furthermore, by setting a plurality of first conductive layers 112 in the thickness direction of the substrate 100 to obtain high capacitance density, the capacitor structure is compact, the substrate area required to achieve high capacitance density is small, and it is also easy to achieve high integration.

[0108] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Relevant details can be understood by referring to these examples.

[0109] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a capacitor, characterized in that, include: A stacked structure and a first isolation layer surrounding the side of the stacked structure are formed on a substrate. The stacked structure includes a plurality of sacrificial dielectric layers and a plurality of first conductive layers that are alternately stacked along the thickness direction of the substrate. At least one first through-hole is formed through the stacked structure to expose each of the first conductive layers from the side, and the first through-hole is filled with conductive material to form a first electrode connection node connected to each of the first conductive layers; A second isolation layer is formed to cover the stacked structure, the first electrode connection node and the first isolation layer, and at least one second through hole is formed to penetrate the second isolation layer and the stacked structure, the second through hole exposing each of the sacrificial dielectric layers and each of the first conductive layers from the side; The sacrificial dielectric layer is etched to form a gap communicating with the second through-hole, the gap exposing the surface of the first conductive layer that was originally adjacent to the sacrificial dielectric layer; as well as A capacitor dielectric layer is formed on the inner wall of the second through hole and the gap, and a second conductive layer is filled in the second through hole and the gap. The second conductive layer formed corresponding to the second through hole is a second electrode connection node.

2. The manufacturing method as described in claim 1, characterized in that, The formation of a laminated structure on a substrate and a first insulating layer surrounding the side of the laminated structure include: A first etch barrier layer, a multilayer film, and a second etch barrier layer are sequentially formed on the substrate. The multilayer film is formed by alternating stacking of multiple sacrificial dielectric layers and multiple first conductive layers. An annular trench is formed penetrating the second etch barrier layer and the multilayer film, with its bottom surface exposed to the first etch barrier layer. The multilayer film and the second etch barrier layer defined by the annular trench form the stacked structure. An isolation material is deposited within the annular trench and on the stacked structure, and a planarization process is performed using the second etch barrier layer as a stop layer. The remaining isolation material forms the first isolation layer.

3. The manufacturing method as described in claim 2, characterized in that, The bottom surfaces of the first through hole and the second through hole expose the first etch barrier layer; After forming the second electrode plate connection node, the manufacturing method includes: A third isolation layer is formed, covering the second isolation layer and the second electrode plate connection node; as well as A first electrode interconnect layer and a second electrode interconnect layer are formed on the surface of the third isolation layer. The first electrode interconnect layer is connected to the first electrode connection node through a first metal through-hole penetrating the third isolation layer and the second isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a second metal through-hole penetrating the third isolation layer.

4. The manufacturing method as described in claim 2, characterized in that, A first electrode bottom interconnect layer is formed on the substrate surface, located below the first etch barrier layer, and the first electrode interconnect layer extends from the region forming the stacked structure to the region forming the first isolation layer. The bottom surface of the first through hole exposes the bottom interconnect layer of the first electrode plate, the first electrode plate connection node connects to the bottom interconnect layer of the first electrode plate, and the bottom surface of the second through hole exposes the first etching barrier layer.

5. The manufacturing method as described in claim 4, characterized in that, After forming the second electrode plate connection node, the manufacturing method includes: A third isolation layer is formed, the third isolation layer covering the stacked structure and the first isolation layer; and A second electrode interconnect layer and a first electrode top interconnect layer are formed on the surface of the third isolation layer. The first electrode top interconnect layer is connected to the first electrode bottom interconnect layer through a third metal through-hole penetrating the third isolation layer and the first isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a fourth metal through-hole penetrating the third isolation layer.

6. The manufacturing method as described in claim 5, characterized in that, The first isolation layer comprises silicon oxide, and the second isolation layer comprises silicon nitride; after forming the second electrode connection node, the fabrication method includes: The second isolation layer is etched to expose the first isolation layer; Forming a nitride layer that covers the second isolation layer and exposes the first isolation layer; and An oxide layer is covered on the first isolation layer and the nitrided layer, and the nitrided layer and the oxide layer constitute the third isolation layer.

7. The manufacturing method as described in claim 6, characterized in that, Forming the third and fourth metal vias includes: Using the nitride layer and the first etching barrier layer as stop layers, the oxide layer and the first isolation layer are etched to form a via corresponding to the bottom interconnect layer of the first electrode plate and penetrating the oxide layer and the first isolation layer. A via corresponding to the connection node of the second electrode plate and penetrating the oxide layer is also formed. Etching the silicon nitride layer and the first etch barrier layer exposed by the vias forms a first via exposing the bottom interconnect layer of the first electrode plate and a second via exposing the connection node of the second electrode plate, respectively; and The first and second through holes are filled with conductive material to form the third and fourth metal through holes, respectively.

8. A capacitor, characterized in that, include: Base; A first isolation layer and a plurality of first conductive layers are formed on the substrate. The plurality of first conductive layers are respectively laid flat at different heights within the space surrounded by the first isolation layer, and there is a gap between adjacent first conductive layers that exposes the surface of the first conductive layer. The first electrode plate connection node penetrates through the plurality of first conductive layers and is connected to each of the first conductive layers from the side. The second isolation layer covers the plurality of first conductive layers and the first electrode plate connection node; The second through hole penetrates the second isolation layer and the plurality of first conductive layers and connects the gap; A capacitor dielectric layer is formed in the second through hole and the inner wall of the gap; as well as The second conductive layer covers the capacitor dielectric layer and fills the second through hole and the gap. The second conductive layer formed corresponding to the second through hole is the second electrode connection node.

9. The capacitor as claimed in claim 8, characterized in that, Also includes: A first etch barrier layer is formed on the surface of the substrate, and the first isolation layer and the plurality of first conductive layers are formed on the first etch barrier layer; as well as The second etch barrier layer is located above the first conductive layer, which is furthest from the substrate. The first electrode connection node, the second through hole, and the second electrode connection node all penetrate the second etch barrier layer.

10. The capacitor as claimed in claim 9, characterized in that, The bottom ends of the first electrode connection node and the second electrode connection node are connected to the first etching barrier layer; the capacitor further includes: A third isolation layer covers the second isolation layer and the second electrode plate connection node; and A first electrode interconnect layer and a second electrode interconnect layer are formed on the surface of the third isolation layer. The first electrode interconnect layer is connected to the first electrode connection node through a first metal through-hole penetrating the third isolation layer and the second isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a second metal through-hole penetrating the third isolation layer.

11. The capacitor as claimed in claim 9, characterized in that, The substrate surface has a first electrode bottom interconnect layer located below the first etch barrier layer. The first electrode bottom interconnect layer extends from below the first electrode connection node to below the first isolation layer. The bottom end of the first electrode connection node is connected to the first electrode bottom interconnect layer, and the bottom end of the second electrode connection node is connected to the first etch barrier layer.

12. The capacitor as claimed in claim 11, characterized in that, Also includes: The third isolation layer covers the second isolation layer and the second electrode plate connection node; as well as A first electrode top interconnect layer and a second electrode interconnect layer are formed on the surface of the third isolation layer. The first electrode top interconnect layer is connected to the first electrode bottom interconnect layer through a third metal through-hole penetrating the third isolation layer and the first isolation layer. The second electrode interconnect layer is connected to the second electrode connection node through a fourth metal through-hole penetrating the third isolation layer.

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