Manufacturing method for improving clamping voltage capability of TVS (Transient Voltage Suppressor) diode chip

Abstract

The invention provides a manufacturing method for improving the clamping voltage capability of a TVS diode chip, and belongs to the technical field of electronic accessories. Phosphorus diffusion is carried out on the N surface of a P-type substrate to form a P + region, and high-temperature oxidation is carried out to generate a SiO2 film. And after the P-region is formed by P-surface phosphorus diffusion, performing single-surface photoresist treatment and cleaning. And growing an oxide layer / SIPOS layer on the surface of the wafer, and performing phosphorus diffusion on a P + region on the N surface. And photoetching and diffusing the P surface to form a P + region, and carrying out phosphorus diffusion on the other region to form a P-region. And photoetching and boron diffusion are carried out above the P + region to form an N-region. And the N <-> region is subjected to photoetching and boron diffusion to form an N < + > region. The P surface is subjected to photoetching evaporation stripping to form an electrode, and the N surface is ground and evaporated to form an electrode. And performing laser cutting on the wafer to form a tube core, cutting the split into a chip, and testing. And the clamping voltage capability and the voltage resistance stability of the chip are improved. The oxide layer / SIPOS layer enhances surface insulation, the electrode process ensures low contact resistance, the cutting test ensures the consistency of the chip size and the electrical performance, and the high reliability requirement of the TVS diode is met.

Description

Technical Field

[0001] This invention belongs to the field of electronic component technology, specifically relating to a method for improving the clamping voltage capability of a TVS diode chip. Background Technology

[0002] TVS (Transient Voltage Suppressor) is a new product developed based on Zener diode technology. When a TVS diode is subjected to a sudden high-energy surge, its impedance drops abruptly at an extremely high speed, while simultaneously absorbing a large current, clamping the voltage across its terminals to a predetermined value. This ensures that downstream circuit components are protected from damage caused by the transient high-energy surge. TVS chips offer advantages such as fast response time, high transient power, low capacitance, low leakage current, small breakdown voltage deviation, easily controllable clamping voltage, small size, and ease of installation.

[0003] In the fabrication of TVS chips, related technologies are prone to uneven concentration and cross-contamination. In general doping processes, phosphorus or boron sources are often coated manually using drop-coating or simple spin-coating, making it difficult to achieve uniform phosphorus source distribution. This leads to localized excessively high or low concentrations in high-concentration P+ regions, with concentration fluctuations exceeding ±20%. When fabricating doped regions of different concentrations in different areas of the same substrate, impurities from the etching solution or diffusion process can easily infiltrate adjacent unprocessed areas, blurring the boundary between P+ and P- regions. This results in discrete PN junction characteristics, unstable device clamping voltage, and increased clamping voltage deviation within the same batch of products, failing to meet the requirements of high-precision electronic equipment.

[0004] During the photoresist coating process, edge accumulation or pinholes are prone to occur. Improper control of pre-baking parameters can lead to poor adhesion between the photoresist and the substrate. After development, burrs and jagged edges appear on the pattern edges, which amplify these defects during etching and evaporation processes, ultimately leading to device failure.

[0005] The fabrication process of TVS chips using related technologies requires electrode evaporation. The metal layer deposited on the electrode is directly connected to the silicon substrate. After evaporation, the electrode is prone to detachment and peeling, especially during high-temperature diffusion or encapsulation soldering, where the detachment probability can reach over 8%. Highly conductive metal atoms (such as Ag) easily diffuse into the silicon substrate at high temperatures, forming metal silicides, which leads to a gradual increase in electrode contact resistance and a decrease in the conductivity of the device. Summary of the Invention

[0006] This invention provides a method for improving the clamping voltage capability of TVS diode chips, which solves the problems of poor clamping voltage (VC) capability and insufficient voltage regulation accuracy (ZZK / ZZT) in existing technologies under low breakdown voltages of 3-8V. This method can improve the chip's VC resistance to peak pulse current and enhance the chip's voltage regulation accuracy.

[0007] The methods include: S101. Phosphorus diffusion is performed on the N-side of a P-type substrate to form a P+ region, followed by high-temperature oxidation to generate a SiO2 thin film. S102. Phosphorus diffusion is performed on the P-side of the P-type substrate to form a P-region, followed by single-sided photoresist treatment and cleaning. S103. An oxide layer and a SIPOS layer are grown on the wafer surface, and phosphorus diffusion is performed on the N-plane to form a P+ region. S104. A P+ region is formed on the P-side by photolithography, etching and diffusion, and a P- region is formed by phosphorus diffusion in another region of the P-side. S105. An N- region is formed above the P+ region on the P-plane through photolithography, etching, and boron diffusion. S106. An N+ region is formed in the N- region through photolithography, etching, and boron diffusion; S107. Electrodes are formed on the P-side through photolithography, vapor deposition, and lift-off processes; S108. An electrode is formed on the N-side by grinding and vapor deposition; S109. Perform laser cutting and dicing on the wafer to divide it into chips; S110. The die is cut and split using ultraviolet laser to divide it into chips and then tested.

[0008] Preferably, S101 specifically includes the following steps: Surface cleaning treatment is performed on P-type silicon wafers; Photoresist is coated onto the N-side and a pattern is exposed. A P+ region is formed on the N-face through diffusion of a phosphorus source; A two-stage oxidation process was used to generate SiO2 thin films; Perform high-temperature annealing and remove photoresist.

[0009] Preferably, S102 specifically includes the following steps: The P-side of the P-type substrate after S101 treatment is wet-cleaned to remove the natural oxide layer on the surface. After cleaning, photoresist is spin-coated onto the P-side and baked to form a photoresist mask layer covering the P-side. Using the photoresist mask layer as a shield, plasma etching is performed on the area of ​​the P-side not covered to remove the oxide layer in that area; Dissolve and remove the photoresist mask layer to expose the etched P-side region; High-temperature phosphorus diffusion is performed on the exposed P-side to form a low-concentration P-region within the P-type substrate.

[0010] Preferably, S103 specifically includes the following steps: Surface pretreatment is performed on the wafer that has completed step S102 before the growth of the double-sided oxide layer; A first layer of silicon dioxide is grown on both sides of the wafer using a voltage-divided controlled thermal oxidation process. A semi-insulating polycrystalline silicon layer is grown on a silicon dioxide layer by low-temperature chemical vapor deposition; Photoresist is applied and patterned on the N-side of the wafer, and the SIPOS layer and silicon dioxide layer in specific areas of the N-side are selectively removed. P+ regions are formed in the N-side exposed silicon region by diffusion of a solid phosphorus source, followed by removal of photoresist and cleaning.

[0011] Preferably, S104 specifically includes the following steps: The P-side of the wafer in step S103 is subjected to plasma cleaning to remove surface impurities; After cleaning, photoresist is spin-coated onto the P-side and baked to form a photoresist layer. The photoresist layer is exposed and developed to form a photolithographic pattern defining the P+ and P- regions on the P-side. Using the photolithography pattern as a mask, reactive ion etching is performed on the P-side to expose the silicon surface of the defined region; On the exposed silicon surface, P+ and P- regions are simultaneously formed on the P-side by performing boron diffusion and phosphorus diffusion, respectively.

[0012] Preferably, S105 specifically includes the following steps: The P-side of the wafer after step S104 is sequentially cleaned and dried with two solutions to remove surface contaminants. Photoresist is spin-coated onto a clean P-side and pre-baked to form a uniform and defect-free photoresist film layer. Align the N-region pattern of the photomask with the existing P+ region on the P surface, expose and develop it to form the N-region pattern on the photoresist film layer; Using a photoresist layer with N-region patterns as a mask, wet etching is performed on the P-side to remove the oxide layer in the patterned area and remove the photoresist. Boron diffusion is performed on the exposed silicon surface area after etching to form N-regions, and then the residual source introduced by the diffusion process is removed.

[0013] Preferably, S106 specifically includes the following steps: The wafer surface after step S105 is cleaned to remove organic impurities; A new photoresist layer is spin-coated onto a clean wafer surface to cover the N-region; The new photoresist layer is exposed and developed to form a photolithographic pattern defining the N+ region; Using the photolithographic pattern as a mask, the surface of the N-region is etched to expose the silicon substrate; High-temperature boron diffusion is performed on an exposed silicon substrate to form an N+ region.

[0014] Preferably, S107 specifically includes the following steps: Plasma bombardment cleaning and adhesion-enhancing layer treatment were applied to the P-side of the S106 wafer. Thick photoresist is coated and alignment exposure based on infrared and visible light dual-band is performed; Stepped post-baking and spray development are performed to form a photoresist pattern with an inverted trapezoidal cross section; Titanium, nickel, and silver metal stacks were sequentially vapor-deposited under ultra-high vacuum conditions; Ohmic contacts are formed by a two-step chemical stripping and rapid thermal annealing process.

[0015] Preferably, S108 specifically includes the following steps: The N-side of the wafer in step S107 is ground and cleaned to flatten and clean the surface; The N-side is finely ground to achieve the set surface flatness requirements; A titanium adhesion layer is deposited on the ground N-surface; A nickel layer and a silver layer are sequentially vapor-deposited onto the titanium adhesion layer to form an N-side electrode; The N-side electrode is annealed to form a good ohmic contact.

[0016] Preferably, S110 specifically includes the following steps: The back side of the wafer from step S109 is attached to a special film for ultraviolet laser cutting and fixed to the cutting machine; The internal scanning and cutting along the wafer dicing track is performed using an ultraviolet laser to clean the cutting area and pre-cure the cutting film adhesive. The dicing film attached to the wafer is mechanically expanded to separate the dies from each other along the dicing path; Individual chips are picked up and transferred from the expanded cutting membrane based on visual recognition; The transferred chips undergo electrical performance testing and classification, followed by labeling and repackaging.

[0017] As can be seen from the above technical solutions, the present invention has the following advantages: The method for improving the clamping voltage capability of TVS diode chips provided by this invention employs a P+ region phosphorus source spin-coating at 3000 rpm for 15 seconds, combined with a multi-stage temperature control program in a diffusion furnace, such as a heating rate of 4℃ / min and segmented temperature holding, to ensure uniform distribution of the phosphorus / boron source and precise atomic migration. A step-by-step photolithography protection method is used, employing different types of photoresist to mask non-target areas at different doping stages. This invention can keep the concentration uniformity error of each doping region within a controllable range, with clear boundaries between the P+, ​​P-, N+, and N- regions and no cross-contamination.

[0018] This invention uses a binocular camera to capture reference points at the substrate edge, achieving alignment between the photomask and the substrate with alignment deviations within a controlled range. Optimized photoresist coating processes, coupled with precise pre-baking parameters, improve the flatness and adhesion of the photoresist film. Improved adhesion between electrode patterns and target doped regions, resulting in burr-free and jagged edges on the patterns. A Ti / Ni / Ag multilayer vapor deposition structure is employed, with the Ti layer acting as a transition layer to enhance adhesion to the silicon substrate, the Ni layer blocking Ag atom diffusion, and the Ag layer ensuring high conductivity. A bottom-layer release adhesive and an upper-layer photoresist enhance the integrity of the release process. Stepwise laser cutting is used, first forming pre-cut grooves at different depths using an SD laser, followed by high-precision cutting with an ultraviolet laser. During cutting, high-purity nitrogen is continuously blown to cool and remove debris. In the dicing stage, an automated ejector array precisely aligns with the cutting grooves, controlling the ejector's rising speed and applied pressure, while horizontal rollers gently roll to assist dicing. No new microcracks are introduced inside the wafer. The manufacturing process of this invention is based on RCA cleaning, BOE diluent immersion, and ultrasonic cleaning to remove residual impurities, photoresist debris, and silicon oxide layer from each process, thereby reducing the risk of device short circuits and leakage. Attached Figure Description

[0019] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the cross-section of a TVS diode chip; Figure 2 Flowchart of a method for improving the clamping voltage capability of a TVS diode chip. Detailed Implementation

[0021] like Figure 1 The figure shows a cross-sectional schematic diagram of a TVS diode chip fabricated based on a method for improving the clamping voltage capability of TVS diode chips. This invention employs a unique N... N+, P The P+ process uses physical deposition to deposit electrodes, employing a double-sided TiNiAg electrode structure to ensure electrode uniformity and solderability. This ensures that P+ / N+ breakdown occurs on the plane, avoiding lateral breakdown and effectively improving the chip's VC withstand capability against peak pulse currents, thus enhancing the chip's voltage regulation accuracy.

[0022] The following describes in detail the fabrication method for improving the clamping voltage capability of a TVS diode chip according to this application. Specific details, such as particular system structures and techniques, are presented for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details.

[0023] It should be understood that, when used in this specification, the term "comprising" indicates the presence of the described feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0024] The terms "one embodiment" or "some embodiments" used in this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this application do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Please see Figure 2 The diagram shows a flowchart of a method for improving the clamping voltage capability of a TVS diode chip in a specific embodiment. The method includes: S101. Phosphorus diffusion is performed on the N-side of a P-type substrate to form a P+ region, followed by high-temperature oxidation to generate a SiO2 thin film.

[0027] In some embodiments, during phosphorus diffusion, the high-temperature environment allows phosphorus atoms in the phosphorus source to gain energy, breaking through the bonding constraints of silicon atoms on the substrate surface and migrating into the lattice interstices or to sites that replace silicon atoms, gradually forming a high-concentration P+ region. A nitrogen atmosphere isolates the substrate from air, preventing high-temperature oxidation and contamination from external impurities.

[0028] S102. Phosphorus diffusion is performed on the P-side of the P-type substrate to form a P-region, followed by single-sided photoresist treatment and cleaning.

[0029] In some embodiments, the N-side photoresist, after pre-baking and curing, forms a physical barrier that resists the erosion of hydrofluoric acid and cleaning solution, achieving precise protection of the N-side P+ region and SiO2 film. Hydrofluoric acid can chemically react with the P-side SiO2 film to generate water-soluble fluorosilicic acid compounds, thereby removing the P-side oxide layer and exposing the fresh silicon substrate.

[0030] S103. An oxide layer and a SIPOS layer are grown on the wafer surface, and phosphorus diffusion is performed on the N-plane to form a P+ region.

[0031] In some embodiments, under the high-temperature environment inside the oxidation furnace, silicon atoms react with oxygen to generate SiO2. Moist oxygen accelerates oxide layer growth, while dry oxygen improves film density. The low-pressure environment of the LPCVD reaction chamber allows for a more uniform distribution of silane and phosphine molecules. At 600°C, silane decomposes to release silicon atoms, which deposit to form polycrystalline silicon. Phosphorus atoms from the decomposition of phosphine are incorporated into the polycrystalline silicon, disrupting its crystallization sequence and forming a semi-insulating SIPOS layer. After curing, the negative photoresist resists hydrofluoric acid corrosion, protecting the P-side oxide layer and SIPOS layer, exposing the silicon substrate for diffusion.

[0032] S104. A P+ region is formed on the P-side through photolithography, etching, and diffusion, and a P- region is formed in another region of the P-side through phosphorus diffusion.

[0033] In some embodiments, the positive photoresist forms a uniform protective film after pre-baking before spin coating. After exposure to ultraviolet light, the molecular chains in the areas exposed to ultraviolet light break down and are easily dissolved by the developer, while the unexposed areas are retained, achieving precise transfer of the P+ region pattern. Undiluted phosphorus source provides a high concentration of phosphorus atoms at high temperature, forming a high-concentration P+ region; diluted phosphorus source has a low concentration and a shorter diffusion time, forming a low-concentration P- region.

[0034] S105. An N- region is formed above the P+ region on the P-plane through photolithography, etching, and boron diffusion.

[0035] In some embodiments, two RCA cleaning processes decompose organic contaminants and dissolve metallic impurities, respectively, ensuring a clean wafer surface and providing a good substrate for photoresist bonding. Positive photoresist, after pre-spray coating and baking, forms a uniform film layer. Exposure and development via a mask achieve precise transfer of the N-region pattern, ensuring the pattern window is precisely positioned above the P+ region. Boron, as an acceptor impurity, is released from a low-concentration boron source at high temperatures and migrates into the silicon substrate lattice. Due to the low boron source concentration and precise diffusion parameters, a low-concentration N-region is formed.

[0036] S106. An N+ region is formed in the N- region through photolithography, etching, and boron diffusion.

[0037] In some embodiments, the high-temperature cleaning solution decomposes residual organic contaminants and boron source debris through oxidation, dissolving metallic impurities to ensure a clean and residue-free wafer surface. The pattern transfer process of the positive photoresist precisely defines the processing area of ​​the N+ region, ensuring that the N+ region pattern is completely located within the N- region. The BOE etching solution dissolves the protective layer within the window, exposing the silicon substrate in the N- region. Boron doping creates a highly conductive N-type region in this area.

[0038] S107. Electrodes are formed on the P-side through photolithography, vapor deposition, and lift-off processes.

[0039] In some embodiments, the underlying photoresist LOR10B exhibits excellent stripping properties, forming a bilayer structure with the upper positive photoresist, thus preventing excessive adhesion between the deposited metal and the wafer surface. The positive photoresist achieves precise transfer of the electrode pattern through exposure and development, ensuring that the deposited metal is deposited only within the electrode pattern window and on the photoresist surface. The high-vacuum environment of the electron beam evaporation stage prevents metal vapor oxidation, and electron beam bombardment of the metal target vaporizes and deposits metal atoms. The Ti layer enhances the adhesion between the metal and the silicon substrate, the Ni layer blocks Ag atom diffusion, and the Ag layer improves electrode conductivity. NMP stripping solution dissolves the photoresist, allowing the metal layer covering the photoresist surface to be stripped away along with the photoresist, retaining only the electrode pattern within the window.

[0040] S108, An electrode is formed on the N-side by grinding and vapor deposition.

[0041] In some embodiments, the UV-curable protective adhesive undergoes a cross-linking polymerization reaction upon exposure to ultraviolet light, forming a dense and hard film to achieve precise protection of the P-side electrode. Diamond abrasive thins the N-side of the wafer through mechanical cutting, while deionized water cooling prevents high-temperature deformation and secondary scratches from debris. Colloidal silica polishing slurry, through the synergistic effect of mechanical grinding and chemical etching, removes the rough and damaged layers after grinding, improving the flatness of the N-side.

[0042] S109. Perform laser cutting and dicing on the wafer to divide it into dies.

[0043] In some embodiments, the S108-treated wafer is placed in a dedicated cleaning basket and immersed in a 60°C IPA solution for ultrasonic cleaning at 180W for 3 minutes, followed by ultrasonic cleaning with room temperature deionized water for 5 minutes. It is then dried by blowing with a nitrogen gun at a 45° angle and placed on the vacuum adsorption stage of an SD laser dicing stage. The SD laser dicing machine parameters are set as follows: wavelength 1064nm, power 15W, dicing speed 300mm / s, and focused spot diameter 50μm. The dicing path is drawn according to the die design dimensions. The first dicing is performed along the X direction, with the focal point focused 30μm below the surface of the P-type passivation groove. The second dicing is performed along the Y direction, with the focal point focused at 2 / 3 of the wafer thickness. High-purity nitrogen is continuously blown during the dicing process to remove dicing debris and cool the wafer. The diced wafer is transferred to an automatic dicing stage, the ejector pin array is aligned with the dicing groove, and the ejector pin rising speed is set to 0.2mm / s, the maximum pressure to 0.01MPa, and the ejector pin is held for 2 seconds after contacting the back of the wafer. The horizontal rollers are gently turned to allow the wafer to naturally separate into dies along the dicing groove. After dicing, the dies are gently moved with quartz tweezers to ensure there are no remaining connections, and then placed in an anti-static tray. Laser dicing results in a narrow kerf, less silicon material loss, and improved wafer utilization.

[0044] S110. The die is cut and split using ultraviolet laser to divide it into chips and then tested.

[0045] In some embodiments, the shorter wavelength and better focusing of the ultraviolet laser enable higher precision cutting, while the smaller spot size results in a narrower kerf, reducing chip size deviation. BOE diluent dissolves residual silicon oxide and tiny silicon debris after cutting, hot air drying quickly removes moisture, and high-frequency ultrasonic vibration removes minute impurities. An optical microscope provides high-magnification visualization of microscopic defects in the chip. An IV tester detects the integrity and electrical characteristics of the PN junction by applying a specific current / voltage; a clamping voltage tester simulates real-world operating scenarios to evaluate the chip's clamping capability.

[0046] In one embodiment of the present invention, based on step S101, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S101 specifically includes the following steps: S1011: Perform surface cleaning treatment on P-type silicon wafers.

[0047] In some embodiments, the original P-type silicon wafer is immersed in an acetone solution for ultrasonic cleaning for 15 minutes, then transferred to an isopropanol solution for a second cleaning for 10 minutes, and finally rinsed with deionized water and dried with nitrogen. During the cleaning process, the solution temperature should be controlled at 25±2℃, and the ultrasonic frequency should be set to 40kHz to ensure the removal of surface grease and particles.

[0048] S1012: Coat the N-side with photoresist and perform pattern exposure.

[0049] In some embodiments, a positive photoresist is uniformly coated onto the N-side using a spin coater at a speed of 3000 rpm, with the coating thickness controlled at 1.2-1.5 μm. After the photoresist has partially cured, it is exposed using a stepper lithography machine at a linewidth of 25 μm, with an ultraviolet light source wavelength of 365 nm and an exposure energy of 450 mJ / cm². After exposure, development is performed for 80 seconds to form a mask pattern for diffusion.

[0050] S1013: A P+ region is formed on the N-face through phosphorus source diffusion.

[0051] In some embodiments, the processed silicon wafer is placed in a diffusion furnace, and a mixture of N2 and PH3 gas (PH3 concentration 500 ppm) is introduced. The furnace temperature is raised to 1250°C and held for 45 hours. A gradient heating strategy is used during phosphorus source diffusion, initially heating to 800°C at a rate of 5°C / min, and then accelerating to the target temperature. After diffusion, the wafer is cooled to below 200°C in the furnace before being removed. High-temperature, long-duration diffusion allows for sufficient phosphorus atom penetration, and the gradient heating reduces lattice damage, resulting in a uniform doping concentration gradient distribution in the formed P+ region, with a depth reaching 2-3 μm.

[0052] S1014: A two-stage oxidation process is used to generate SiO2 thin films.

[0053] In some embodiments, a first stage introduces moist oxygen and maintains a furnace temperature of 1100°C for 5 hours to form an initial oxide layer; the second stage switches to dry oxygen and continues oxidation at the same temperature for 1 hour. In this two-stage oxidation process, the moist oxygen stage promotes rapid oxide layer growth, while the dry oxygen stage eliminates porosity through a densification reaction. The final SiO2 film has a thickness of 10000±500 Å and a surface roughness Ra<20 Å, meeting the process requirements for the mechanical strength and electrical insulation of the oxide layer.

[0054] S1015: Perform high-temperature annealing and remove photoresist.

[0055] In some embodiments, the oxidized silicon wafer is placed in a rapid thermal processing system and heated to 950°C at a rate of 15°C / s, held for 30 minutes. During annealing, a N2+O2 mixed gas is introduced to repair point defects generated during diffusion. Immediately after annealing, the remaining photoresist is removed by immersion in acetone solution, with the immersion time controlled within 120 seconds. High-temperature annealing restores lattice integrity through a thermal activation mechanism, and combined with oxygen partial pressure control, it reduces interface state density. The rapid removal process avoids photoresist residue affecting the process.

[0056] In one embodiment of the present invention, based on step S102, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S102 specifically includes the following steps: S1021: Perform surface pretreatment on the P-type substrate after S101 treatment. Immerse the P-side of the P-type substrate in a 5% hydrofluoric acid solution for 2 minutes to remove any natural oxide layer and impurities that may exist on the P-side. Then rinse thoroughly with plenty of deionized water and dry with high-purity nitrogen.

[0057] S1022: Uniformly apply photoresist to the P-side of the P-type substrate. Using spin coating, drop the photoresist onto the P-side, set the spin coater speed to 3000 rpm, and continue for 30 seconds to ensure the photoresist is evenly distributed across the P-side, forming a photoresist layer approximately 1.5 micrometers thick. Then, place the photoresist-coated substrate in an oven and bake at 90°C for 15 minutes to cure the photoresist.

[0058] S1023: Perform single-sided oxide layer removal operation. Using a plasma etching device, the substrate is placed in the device cavity, and after being evacuated to a certain pressure, a mixture of oxygen and carbon tetrafluoride is introduced. The gas flow rate ratio and radio frequency power are adjusted so that the plasma etches the non-photoresist-covered area, i.e., the area where the oxide layer needs to be removed, removing the oxide layer in part of the P-side area. The etching time is 5 minutes.

[0059] S1024: Remove photoresist. Immerse the plasma-etched substrate in a dedicated photoresist removal solution for 10 minutes to dissolve the photoresist, then rinse thoroughly with deionized water.

[0060] The photoresist remover solution of this embodiment specifically dissolves photoresist. After immersion, the photoresist gradually dissolves in the remover solution. Rinsing with deionized water removes residual remover solution and dissolved photoresist, ensuring a clean substrate surface. The photoresist remover solution reacts chemically with the photoresist, causing it to dissolve.

[0061] S1025: Phosphorus diffusion is performed to form the P-region. The treated substrate is placed in a high-temperature diffusion furnace, and a phosphorus source is placed inside the furnace. A solid phosphorus doping source is used, and the diffusion temperature is set to 1200℃. Nitrogen gas is introduced into the diffusion furnace as a protective gas, carrying phosphorus atoms to diffuse to the substrate surface. The diffusion time is 20 hours, forming a phosphorus doping concentration of 1×10¹ on the P-surface of the P-type substrate. 0 / cm³ of P-region.

[0062] In this embodiment, a solid phosphorus dopant source decomposes or sublimates at high temperature in a high-temperature diffusion furnace to generate phosphorus atoms. Nitrogen gas acts as a protective gas to prevent other impurities from entering, while simultaneously carrying phosphorus atoms to diffuse towards the substrate surface. Under a set temperature and time, phosphorus atoms diffuse into the P-side of the P-type substrate, forming a P-region of a specific concentration, meeting the requirements of TVS diode chips for P-side doping concentration.

[0063] In one embodiment of the present invention, based on step S103, the following is a possible embodiment and its specific implementation is described in a non-limiting manner. Regarding step S103, which involves growing an oxide layer and a SIPOS layer on the wafer surface and performing phosphorus diffusion on the N-plane to form a P+ region, the specific implementation includes the following steps: S1031: Perform surface pretreatment on the wafer that has completed step S102 before growing a double-sided oxide layer.

[0064] In some embodiments, the wafer processed in step S102 is placed in a quartz wafer holder and sent into a cleaning tank. Ammonia, hydrogen peroxide, and deionized water are mixed in a volume ratio of 1:1:5 and cleaned at 75°C for 10 minutes to remove organic residues and some metal ions.

[0065] In this embodiment, the wafer was immersed in a diluted hydrofluoric acid solution for 30 seconds to remove the natural oxide layer formed on the wafer surface during previous storage or transport. Further removal of metal ions was achieved by rinsing with a solution of hydrochloric acid, hydrogen peroxide, and deionized water in a 1:1:6 volume ratio at 75°C for 10 minutes. The wafer was then subjected to megasonic rinsing with deionized water at a frequency of 0.8 MHz for 5 minutes, followed by drying with nitrogen gas and immediate transfer to the oxidation furnace sample chamber.

[0066] S1032: The first layer of silicon dioxide is grown on both sides of the wafer using a voltage-controlled thermal oxidation process.

[0067] In some embodiments, the wafer is pushed from the sample inlet into the isothermal zone of the oxidation furnace, which has been stabilized at 920°C. First, high-purity nitrogen gas is introduced into the furnace tube at a flow rate of 5 L / min for 10 minutes to ensure uniform wafer temperature and remove air.

[0068] The gas was switched to oxygen-containing nitrogen, with an oxygen volume fraction of 25%, and the total flow rate was maintained at 5 L / min. The furnace pressure was controlled at 0.5 atmospheres for 30 minutes of dry oxygen oxidation, forming an initial oxide layer of approximately 200 angstroms. Water vapor was then introduced into the gas, generated by bubbling high-purity nitrogen through 95°C hot water. The partial pressure of the water vapor was adjusted to 0.3 atmospheres, the total pressure was increased to 1 atmosphere, and the oxidation temperature was raised to 1000°C for 300 minutes of wet oxygen oxidation.

[0069] During the oxidation process, the thickness of the oxide layer is monitored in real time using an infrared laser thickness gauge. When the thickness reaches about 5000 angstroms, the water vapor is stopped and dry oxygen oxidation is switched to again. The temperature is lowered to 920℃ and oxidation continues for 60 minutes, eventually making the silicon dioxide layer thickness reach about 5500 angstroms and the surface dense.

[0070] S1033: A semi-insulating polycrystalline silicon layer is grown on a silicon dioxide layer by low-temperature chemical vapor deposition.

[0071] In some embodiments, the silicon dioxide wafer with grown silicon dioxide is transferred to the reaction chamber of a chemical vapor deposition (CVD) apparatus. The reaction chamber temperature is set to 620°C and the pressure is controlled at 150 Pa. A mixture of silane and nitrous oxide is introduced into the reaction chamber at a flow rate of 100 sccm for silane and 300 sccm for nitrous oxide, while diluted phosphine (PH3) is introduced as a dopant.

[0072] In this embodiment, the gas undergoes thermal decomposition and chemical reaction at high temperature. Silane decomposes to provide silicon atoms, and nitrous oxide decomposes to provide oxygen atoms, depositing an oxygen-doped amorphous or polycrystalline silicon thin film, i.e., a SIPOS layer, on the silicon dioxide surface. The deposition rate is approximately 100 Å / min, and the deposition time is 50 minutes, resulting in an SIPOS layer with a thickness of approximately 5000 Å. After deposition, the film is annealed in a nitrogen atmosphere at a temperature of 650°C for 15 minutes to reduce film stress.

[0073] S1034: Photoresist coating and patterning are performed on the N-side of the wafer, and the SIPOS layer and silicon dioxide layer are selectively removed from specific areas of the N-side.

[0074] In some embodiments, with the N-side of the wafer facing upwards, a positive photoresist is applied using a spin coater. The photoresist is spread out by rotating at 500 rpm for 5 seconds and then at 3000 rpm for 30 seconds to obtain a photoresist film with a thickness of approximately 1.5 micrometers.

[0075] The photomask was pre-baked at 90°C for 5 minutes on a hot plate. Using a contact lithography machine, the mask with the P+ region window pattern was aligned with the N-side of the wafer, and the exposure energy was 140 mJ / cm². After exposure, it was post-baked at 110°C for 1 minute on a hot plate. Developed with a 0.3% tetramethylammonium hydroxide solution for 60 seconds to form the patterned photoresist mask.

[0076] The SIPOS layer in the window region was removed using reactive ion etching. The etching gas was a mixture of CF4 and O2, with flow rates of 40 sccm and 10 sccm, respectively. The RF power was 200 W, the pressure was 10 Pa, and the etching time was controlled based on endpoint detection, stopping when characteristic SiO2 spectral lines were detected. In this embodiment, the exposed silicon dioxide layer was removed by wet etching with a buffered hydrofluoric acid solution until the silicon surface was exposed.

[0077] It should be noted that contact lithography alignment ensures precise alignment between the pattern on the mask and the existing P-regions and other structures on the wafer. Exposure energy is strictly controlled to ensure sufficient photodecomposition of the photosensitive compounds in the exposed areas. After development, the photoresist in the unexposed areas remains, forming a barrier resistant to chemical corrosion. During reactive ion etching of the SIPOS layer, CF4 gas decomposes in the plasma to generate fluorine radicals. These fluorine radicals react with silicon in the SIPOS to form volatile SiF4. Adding a small amount of O2 can suppress polymer formation and improve etching anisotropy.

[0078] S1035: A P+ region is formed in the silicon region exposed on the N-side by diffusion of a solid phosphorus source, followed by removal of photoresist and cleaning.

[0079] In some embodiments, the wafer is placed in a quartz boat within the diffusion furnace, with the N-side facing upwards. A solid phosphorus trioxide source wafer is placed 5 mm above the wafer. The quartz boat is then pushed into the isothermal zone of the diffusion furnace, which has been preheated to 1000°C. High-purity nitrogen is introduced for 5 minutes, and the temperature is increased to 1250°C at a rate of 5°C per minute, and maintained at 1250°C for 4 hours to perform phosphorus diffusion.

[0080] After diffusion in this embodiment, the wafer is pulled to the furnace opening and cooled to 800°C, then removed. After cooling, the wafer is immersed in acetone solution and sonicated for 5 minutes to loosen the photoresist, then soaked in stripping solution at 80°C for 10 minutes to completely remove the photoresist. In this embodiment, a mixture of sulfuric acid and hydrogen peroxide is used to clean the wafer at 120°C for 10 minutes to remove organic residues and possible metal contamination, followed by rinsing with deionized water and drying.

[0081] In this embodiment, the silicon wafer is fed into the furnace at 1000°C and slowly heated to 1250°C to avoid slip dislocations or warping caused by rapid temperature changes. Maintaining this high temperature of 1250°C for 4 hours results in a phosphorus diffusion coefficient in silicon on the order of 10^-12 cm² / s, enabling the formation of deep junctions with a depth of 3-5 micrometers. The prolonged high-temperature diffusion also allows phosphorus atoms to fully occupy silicon lattice sites, with the surface concentration approaching the solid solubility limit of phosphorus in silicon.

[0082] Optionally, the silicon wafer is slowly cooled to 800°C at the furnace opening before being removed. This allows the silicon wafer to slowly pass through the plastic-elastic transition temperature zone of silicon under nitrogen protection, reducing lattice defects caused by thermal stress.

[0083] Sulfuric acid and hydrogen peroxide cleaning: hot concentrated sulfuric acid can carbonize any remaining organic residue, while hydrogen peroxide oxidizes it into carbon dioxide and water. The high boiling point and strong acidity of sulfuric acid can dissolve a variety of metal oxides.

[0084] In one embodiment of the present invention, based on step S104, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S104 specifically includes the following steps: S1041: Perform P-side pretreatment on the wafer after completing step S103. In this embodiment, a plasma cleaning device is used. The wafer is placed in the device cavity, and after evacuation, argon gas is introduced. Under the action of radio frequency power, plasma is generated to clean the P-side for a short time to remove any impurities and contaminants that may be present on the surface. The cleaning time is 3 minutes.

[0085] S1042: Uniformly coat the cleaned P-side with photoresist. In this embodiment, a spraying method is used to uniformly spray the photoresist onto the P-side, then place it on a horizontal platform and rotate it at a low speed (500 rpm) for 10 seconds to initially spread the photoresist, then rotate it at a high speed (4000 rpm) for 30 seconds to form a uniform photoresist layer with a thickness of approximately 1.2 micrometers. The photoresist-coated wafer is then placed in an oven and baked at 110°C for 10 minutes to cure the photoresist.

[0086] S1043: Perform photolithography. In this embodiment, the baked wafer is placed in a photolithography machine, and the photoresist is exposed using a pre-designed mask for 8 seconds. After exposure, the wafer is placed in a developing solution for 1 minute to form a specific photolithographic pattern on the P-side. This pattern defines the areas for forming P+ regions and the areas that need to be retained for phosphorus diffusion to form P- regions.

[0087] S1044: Perform etching operation. In this embodiment, the developed wafer is placed in a reactive ion etching apparatus, a mixture of carbon tetrafluoride and oxygen is introduced, the gas flow rate ratio and radio frequency power are adjusted, and the area not protected by photoresist is etched for 4 minutes to remove the oxide layer and part of the silicon material in the area, exposing the silicon surface.

[0088] In the reactive ion etching apparatus of this embodiment, a mixture of carbon tetrafluoride and oxygen gas generates plasma under the action of radio frequency power. The active particles in the plasma etch the silicon surface that is not protected by photoresist. By adjusting the gas flow rate ratio and radio frequency power, the etching rate and etching depth can be controlled to remove the oxide layer and part of the silicon material.

[0089] S1045: Perform diffusion operation. In this embodiment, the etched wafer is placed in a high-temperature diffusion furnace. For the region where a P+ region needs to be formed, a boron source is placed in the diffusion furnace. A solid boron-doped source is used, the diffusion temperature is set to 1050°C, nitrogen gas is introduced as a protective gas and carrier gas, and the diffusion time is 15 hours to form a P+ region. For the other region where a P- region needs to be formed, a phosphorus source is placed in the diffusion furnace. Liquid phosphoric acid is used, the diffusion temperature is set to 1200°C, nitrogen gas is introduced as a protective gas and carrier gas, and the diffusion time is 20 hours to form a P- region.

[0090] In this embodiment, within a high-temperature diffusion furnace, to form the P+ region, a solid boron dopant source decomposes or sublimates at high temperature to generate boron atoms. Nitrogen gas, acting as a carrier gas, carries these boron atoms to the exposed silicon surface, where they diffuse into the silicon interior, forming a P+ region of a specific concentration at a set temperature and time. To form the P- region, liquid phosphoric acid decomposes to generate phosphorus atoms, which are then carried by nitrogen gas and diffuse into the silicon interior, forming the P- region. Accurately forming both P+ and P- regions on the P-side allows for adjustment of the electrical performance of the TVS diode chip's P-side, meeting the chip's design requirements.

[0091] In one embodiment of the present invention, based on step S105, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S105 specifically includes the following steps: S1051: Take the wafer after S104 treatment and immerse it in two cleaning solutions in sequence.

[0092] Specifically, the wafer is immersed in a 1:2:8 (v / v) NH4OH-H2O2-H2O mixture for 12 minutes, turning it over every 3 minutes with quartz tweezers. After removal, it is rinsed with deionized water at a flow rate of 3 L / min for 10 minutes, then immersed in a 1:2:10 (v / v) HCl-H2O2-H2O mixture for 10 minutes. Finally, it is rinsed with deionized water until the pH is neutral, and the wafer surface is purged with high-purity nitrogen at a 45° angle at a flow rate of 6 L / min until completely dry.

[0093] S1052: Fix the wafer with the P-side facing up on the vacuum stage of the spin coater. Take 3.5 ml of positive photoresist AZ6130 and drop it onto the center of the P-side using a pipette. Spin coat at 3200 rpm for 20 seconds, then reduce the speed to 600 rpm for 6 seconds. After spin coating, transfer the wafer to a 110℃ hot plate for pre-baking for 4 minutes. After naturally cooling to room temperature, observe the photoresist film layer under an optical microscope to ensure there are no pinholes or bubbles.

[0094] S1053: Take a quartz mask with the N-region pattern. Using the alignment system of the lithography machine, align the center of the mask pattern with the center of the P+ region already formed on the P-side of the wafer. After ensuring a tight fit, place the wafer into the contact lithography machine. Use ultraviolet light at a wavelength of 365nm, an exposure energy of 15mJ / cm², and an exposure time of 10 seconds. After exposure, immerse the wafer in 2.38% TMAH developer for 70 seconds, gently agitating the developing tank. Remove the wafer and rinse with deionized water for 12 minutes. Dry it with nitrogen gas and confirm again under a microscope that the edges of the N-region pattern are free of jagged edges and misalignment.

[0095] S1054: Place the developed wafer into a PTFE container filled with BOE etching solution and immerse it at 23°C for 5 minutes, gently rotating the wafer every 40 seconds during this time. After removal, rinse the P-side with deionized water for 8 minutes until the pH of the rinsing solution reaches 7. Then immerse the wafer in acetone solution and ultrasonically clean it at 90°C for 4 minutes to remove residual photoresist; after removal, rinse thoroughly with deionized water and dry with nitrogen.

[0096] S1055: Using liquid borosilicate glass as the boron source, add anhydrous ethanol at a mass ratio of 1:15 and stir with a magnetic stirrer for 15 minutes to prepare a low-concentration boron source. Drop the boron source into the etched N-region window on the P-side of the wafer and spin-coat at 2600 rpm for 16 seconds, then transfer to a 75°C preheating stage and hold for 3 minutes. Place the wafer in the constant temperature zone of the quartz tube of the diffusion furnace and purge the air with 5 L / min of high-purity nitrogen for 15 minutes. Increase the temperature to 800°C at 5°C / min and hold for 2 hours, then increase the temperature to 1200°C at 3°C / min and hold for 25 hours. After diffusion, allow it to cool naturally to room temperature, immerse the wafer in a 5% hydrofluoric acid solution for 6 minutes to remove residual boron source, rinse with deionized water, and dry with nitrogen.

[0097] In one embodiment of the present invention, based on step S106, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S106 specifically includes the following steps: S1061: Perform surface cleaning on the wafer that has completed step S105 and has an N-region.

[0098] Specifically, the wafer is placed in a container filled with acetone solution and soaked for 5 minutes to dissolve and remove any organic impurities such as photoresist that may remain on the surface. The wafer is then picked up with tweezers, rinsed with plenty of deionized water to remove the acetone solution, and then dried with high-purity nitrogen gas.

[0099] S1062: On the cleaned wafer surface, a new photoresist is applied over the N-region. In this embodiment, a dropper is used to apply the photoresist to the wafer surface, and the application is carried out at 3000 rpm for 30 seconds to ensure uniform coverage of the N-region and related surfaces, forming a photoresist layer with a thickness of approximately 1.2 micrometers. The wafer is then placed in an oven and baked at 95°C for 15 minutes to cure the photoresist.

[0100] S1063: Perform photolithography. Place the designed photomask onto the photoresist-coated wafer surface, ensuring accurate positioning. Place the wafer in the photolithography machine and expose the photoresist using ultraviolet light of a suitable wavelength for 7 seconds. After exposure, immediately immerse the wafer in the developer for 1 minute to form a precise pattern on the photoresist, exposing the N- regions where the N+ regions will form. Define the area where the N+ regions will form, providing an accurate template for etching and diffusion, ensuring that the position and shape of the N+ regions meet design requirements.

[0101] S1064: Etching Step. The photolithographically etched wafer is placed in a reactive ion etching machine. A mixture of carbon tetrafluoride and argon is introduced into the machine. The gas flow rate ratio and RF power are adjusted to etch the N-region surface not protected by photoresist for 2.5 minutes. This removes a certain thickness of material from the surface, allowing for more complete exposure of the silicon substrate and creating favorable conditions for boron diffusion. Active particles in the plasma react chemically and physically with the silicon. This removes unwanted material, fully exposing the silicon substrate and improving the effectiveness of boron diffusion and the formation quality of the N+ region.

[0102] S1065: Perform boron diffusion to form N+ regions. Place the etched wafer in a high-temperature diffusion furnace, and place a boron source inside the furnace, using triethyl borate as the liquid boron source. Purge nitrogen into the furnace as a carrier gas and protective gas, set the diffusion temperature to 1250°C, and allow the diffusion time to last for 25 hours, enabling boron atoms to fully diffuse into the exposed silicon substrate and form N+ regions with the required concentration.

[0103] In this embodiment, the diffusion of matter at high temperatures involves boron atoms diffusing from high-concentration regions to low-concentration regions within the silicon. An N+ region is accurately formed within the N- region, and the electrical performance of the TVS diode chip is adjusted to meet the chip's design requirements, ensuring that the chip possesses good clamping voltage capability and other performance indicators.

[0104] In one embodiment of the present invention, based on step S107, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S107 specifically includes the following steps: S1071: Perform plasma bombardment cleaning and adhesion layer treatment on the P-side of the wafer that has completed step S106.

[0105] In some embodiments, the wafer is loaded into the cavity of the reactive ion etching machine, and the cavity is pre-evacuated to 5 × 10⁻⁶. - 5Argon gas was introduced at a flow rate of 50 sccm to maintain a chamber pressure of 10 mTorr. Argon plasma was generated by applying 300 W of radio frequency power to physically bombard the P-side of the wafer for 120 seconds. Subsequently, the radio frequency power was turned off, and the argon flow rate was maintained to stabilize the chamber temperature at 150°C. Hexamethyldisilazane vapor was then introduced into the chamber through a gas injection system at a flow rate of 20 sccm for 60 seconds. After treatment, the wafer was cooled to below 80°C under a nitrogen atmosphere and removed.

[0106] Step S1072: Coat a thick photoresist and perform alignment exposure based on dual infrared and visible light bands.

[0107] In some embodiments, on a spin coater, the wafer is first rotated at 800 rpm while 1.5 ml of cyclohexanone solution is dropped onto the center of the P-side, and then rotated for 5 seconds to spread the coating. Without stopping the spin coater, the process is switched to applying positive photoresist AZ4620, with the spin speed increased in two steps: first at 1000 rpm for 10 seconds, then at 500 rpm for 30 seconds. The coated wafer is then pre-baked on a 100°C hot plate for 3 minutes to obtain a photoresist film with a thickness of approximately 6.5 micrometers. Using a stepper lithography machine equipped with a dual-band alignment system, an infrared light source is first used to penetrate the photoresist layer and perform coarse alignment with the alignment marks on the lower layer inside the silicon wafer. Then, the process is switched to the visible light band to perform fine alignment with the dedicated alignment marks on the photoresist surface. After the overlay accuracy is calibrated, exposure is performed using ultraviolet light with a wavelength of 365 nm and an exposure energy of 320 mJ / cm².

[0108] Step S1073: Perform stepped post-baking and spray development to form a photoresist pattern with an inverted trapezoidal cross section.

[0109] In some embodiments, the exposed wafer is immediately placed on a hot plate at 115°C for a first-stage post-bake of 45 seconds. Subsequently, the hot plate temperature is raised to 130°C for a second-stage post-bake of 90 seconds. Development is performed using a spray developer, employing a solution of AZ400K developer diluted with deionized water at a 1:3 volume ratio as the developer. The development process consists of three steps: spraying the developer at low pressure for 15 seconds, followed by allowing it to swell for 45 seconds, and then spraying the developer at higher pressure for 30 seconds while simultaneously rinsing with deionized water. After development, the wafer is hard-baked on a hot plate at 100°C for 5 minutes, ultimately forming a photoresist window pattern on the P-side with a bottom width slightly larger than the top and a sidewall angle of approximately 70 degrees.

[0110] Step S1074: Sequentially vapor-deposit titanium, nickel, and silver metal stacks under ultra-high vacuum conditions.

[0111] In some embodiments, a wafer with a photoresist pattern is mounted into a sample holder of an electron beam evaporation stage, the sample holder being at a 15-degree angle to the evaporation source. The system is evacuated to a baseline vacuum level better than 5 × 10⁻⁶.-7 Torr. First, a titanium layer was deposited by evaporation: an electron beam was focused onto a high-purity titanium ingot, and the beam current was adjusted to stabilize the evaporation rate of titanium at 1.0 Å / s. This was monitored using a quartz crystal film thickness gauge, and the baffle was closed when the thickness reached 1800 Å. Next, without breaking the vacuum, the sample holder was rotated above the nickel evaporation source to deposit a nickel layer, with the evaporation rate controlled at 1.2 Å / s, stopping when the thickness reached 2800 Å. Similarly, without breaking the vacuum, the holder was rotated above the silver evaporation source to deposit a silver layer, with the evaporation rate controlled at 6.5 Å / s, stopping when the thickness reached 8500 Å. Throughout the entire evaporation process, the wafer temperature was maintained at 45±5℃ using helium cooling in the back cavity.

[0112] The selection and deposition conditions of the electrode metal stack in this embodiment directly determine the electrode's adhesion, contact resistance, solderability, and anti-migration capability. The three-layer structure of titanium / nickel / silver each has a clear function. When titanium is deposited onto a clean silicon surface under ultra-high vacuum, it undergoes a strong interfacial reaction with silicon to form titanium silicide. This is a metallurgical bonding process that provides excellent ohmic contact and adhesion, and acts as a diffusion barrier layer. Compared to sputtering, electron beam evaporation has moderate metal particle energy, resulting in a dense film with minimal damage to the substrate. Controlling the extremely low evaporation rate allows sufficient surface migration time for titanium atoms to form a thin film. The nickel layer, as a transition layer, has good compatibility with the underlying titanium and effectively blocks the rapid diffusion of silver atoms into silicon. The vapor-deposited silver layer is the primary conductive and solderable layer due to its lowest volume resistivity among all metals. Cooling the wafer to 45°C throughout the process prevents excessively high substrate temperatures from causing photoresist deformation, flow, or gas release, which could damage the formed pattern or contaminate the film.

[0113] Step S1075: An ohmic contact is formed by two-step chemical stripping and rapid thermal annealing.

[0114] In some embodiments, the vapor-deposited wafer is immersed in N-methylpyrrolidone and ultrasonically treated at a constant temperature of 75°C for 15 minutes to separate most of the metal layer covering the photoresist from the substrate. Subsequently, it is transferred to a second stripping solution and immersed at 60°C with mechanical agitation for 10 minutes to thoroughly remove all residual photoresist and attached metal. After stripping, the wafer is placed in a rapid thermal annealing furnace and heated to 420°C at a rate of 100°C / s in a forming gas atmosphere, held at this temperature for 2 minutes, and then allowed to cool naturally.

[0115] This embodiment removes most of the host metal and photoresist. A mixture of dimethyl sulfoxide (DMSO) and tetramethylammonium hydroxide (TMAH) is used. DMSO further dissolves colloidal fragments remaining after NMP treatment, while trace amounts of TMAH neutralize and remove any acidic residues and more stubborn organic matter. Annealing eliminates stress within the metal film, improves grain structure, and enhances the mechanical stability and conductivity of the electrode. A nitrogen-hydrogen mixture is used to provide a reducing atmosphere during annealing, preventing metal surface oxidation and passivating some interface states on the silicon surface. This results in low contact resistance, high adhesion strength, excellent conductivity, and a p-side electrode.

[0116] In one embodiment of the present invention, based on step S108, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S108 specifically includes the following steps: S1081: Pre-process the N-side of the wafer after S107. Place the wafer on a special grinding stage and use coarse abrasive to perform preliminary grinding on the N-side to remove any surface irregularities and impurity layers. The grinding time is 5 minutes. Afterward, immerse the wafer in an alkaline cleaning solution at 60°C for 8 minutes to remove debris and residual impurities generated during the grinding process. Then rinse with plenty of deionized water and dry with high-purity nitrogen.

[0117] S1082: Perform fine grinding on the pretreated N-surface. Select fine abrasive and grind the N-surface on a precision grinding machine, controlling the grinding pressure at 0.5 MPa, the grinding speed at 20 rpm, and the grinding time at 10 minutes, to achieve the required flatness and roughness of the N-surface. After grinding, rinse again with deionized water and dry with high-purity nitrogen.

[0118] S1083: An adhesion layer is coated onto the finely ground N-side. Using magnetron sputtering equipment at a vacuum level of 5 × 10⁻³ Pa, with titanium (Ti) as the target, a sputtering power of 200 W, and a sputtering time of 10 minutes, a titanium adhesion layer with a thickness of approximately 500 Å is formed on the N-side, enhancing the adhesion between the electrode material and the N-side. The titanium adhesion layer effectively enhances the adhesion between the electrode material and the N-side, preventing electrode detachment.

[0119] S1084: Electrode material deposition. The wafer coated with the adhesion layer is placed in an electron beam evaporation stage. When the vacuum level reaches ≤3×10⁻⁶ Torr, a nickel (Ni) layer and a silver (Ag) layer are deposited sequentially. First, a nickel layer with a thickness of 2500 Å is deposited at a pot rotation speed of 4 rpm and a deposition rate of 1 Å / s; then, a silver layer with a thickness of 8000 Å is deposited at a pot rotation speed of 5 rpm and a deposition rate of 7 Å / s.

[0120] In some embodiments, electron beam heating causes the material to vaporize and deposit. The vapor deposition process of the electrode material is controlled to form an electrode with good conductivity, meeting the electrical requirements of the chip.

[0121] S1085: Post-processing of the N-side after electrode deposition. Place the wafer in an annealing furnace, under a nitrogen protective atmosphere, set the annealing temperature to 300°C and the annealing time to 30 minutes, to ensure good ohmic contact between the electrode material and the N-side, and then allow it to cool naturally to room temperature.

[0122] In some embodiments, atomic diffusion and reaction at high temperatures form ohmic contacts. This reduces the contact resistance between the electrode and the N-side, improving the chip's electrical performance and stability.

[0123] In one embodiment of the present invention, based on step S110, the following is a possible embodiment and its specific implementation will be described in a non-limiting manner. S110 specifically includes the following steps: S1101: Attach the UV laser cutting special film to the back of the wafer with shallow grooves obtained in S109 and load it.

[0124] In some embodiments, a semi-automatic laminating machine is used to attach the N-sided electrode surface to a flat vacuum chuck. A 100-micron thick blue cutting film with a polyolefin substrate and UV-curable acrylic adhesive is pulled from a reel and smoothly applied to the back of the wafer. A soft silicone roller is used to roll the film three times at a uniform speed from the center to the edge of the wafer, ensuring no air bubbles between the film and the wafer. The wafer with the film attached is transferred to the annular glass frame of the UV laser cutter, and the edges of the film are held in place by vacuum to maintain uniform tension. Finally, the entire frame is loaded onto the vacuum chuck of the cutter's worktable, with the chuck temperature set to 23°C.

[0125] S1102: Based on a 355nm wavelength ultraviolet solid-state laser, with a pulse frequency set to 80kHz and a single pulse energy of 12μJ. The laser beam is converted into a rectangular spot with an aspect ratio of 10:1 by a beam shaper and focused by a 20x objective lens. The focal point is precisely positioned inside the wafer, approximately 30 micrometers below the P-side device structure within the silicon material. Following a pre-defined kerf map, the stage is controlled to scan and cut at a speed of 700mm / s, with the laser scanning each kerf three times. Simultaneously, a coaxially integrated high-speed airflow nozzle sprays filtered, dry air with a dew point of -60°C onto the cutting location to remove any generated dust. After cutting, the entire frame is moved to an ultraviolet exposure station, where the cut film is irradiated from the back with ultraviolet light at a wavelength of 365nm and an intensity of 150mJ / cm² for 30 seconds to initially cure the adhesive and reduce its stickiness.

[0126] S1103: Move the frame to the biaxial expansion machine. The upper expansion ring descends to press down on the frame, while the lower expansion ring moves downwards by 15 mm at a speed of 5 mm / s, causing the diced film to be uniformly stretched in the XY plane with a stretching rate of approximately 105%. In this embodiment, the gap between dies is expanded from approximately 10 micrometers to approximately 25 micrometers. After confirming that all dicing paths have been clearly separated, the frame is transferred to a precision expansion stage with an independently controlled pin array. The 256 micro pins on the bottom array of the expansion stage selectively rise according to the chip position map, pressing against the corresponding positions of the diced film on the back of the single or multiple dies that need to be separated. The outer ring of the expansion stage continues to stretch the film outwards.

[0127] S1104: A camera captures images, and pattern recognition software identifies the precise boundaries of each chip, the orientation of the P-side electrode, and whether there are defects such as chipped edges or missing corners. A six-axis robotic arm is equipped with a multi-channel vacuum nozzle at its end, with a contour-following design to match the non-flat surface contour of the chip's P-side electrode area. Guided by the vision system's coordinates, the robotic arm moves above the qualified chip. The nozzle descends, and just before contacting the chip, a brief burst of clean nitrogen gas at a pressure of 0.2 bar is released from the nozzle's central channel to blow away any electrostatic dust that may be adhering to the chip surface. The nozzle then adheres to the chip, applying a 60 kPa vacuum suction force to pick up the chip, lift it, and transfer it to an intermediate stage or test socket.

[0128] Step S1105: Automatically insert the chip into the temperature-controlled test socket, with the socket temperature precisely controlled at 25±0.5℃. Using a semiconductor parameter analyzer, first apply a 1mA forward current and measure the forward voltage drop Vf. Then perform a dynamic pulse test: apply a rectangular current pulse with a rise time of 1ns, a pulse width of 100ns, and a peak current of 100A, while simultaneously measuring the clamping voltage waveform across the chip using a high-speed oscilloscope, recording the peak clamping voltage Vc and overshoot amplitude. Apply a reverse bias voltage in 10V / step steps and measure the reverse leakage current Ir until the maximum operating voltage specified in the datasheet is reached. The test system automatically classifies the chip into different grades based on parameters such as Vf, Vc, and Ir.

[0129] A six-axis robotic arm removes the chips from the test socket based on the sorting results and transfers them to a laser marking machine. A fiber laser is used to engrave QR codes and text containing model, batch, and grade codes on the non-functional areas of the N-sided electrodes, with an engraving depth of approximately 5 micrometers. Chips of different grades are placed in separate gel packaging boxes. A high-energy laser is used to instantly vaporize or change the color of the surface material, forming identification marks.

[0130] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0131] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for improving the clamping voltage capability of a TVS diode chip, characterized in that, The methods include: S101. Phosphorus diffusion is performed on the N-side of a P-type substrate to form a P+ region, followed by high-temperature oxidation to generate a SiO2 thin film. S102. Phosphorus diffusion is performed on the P-side of the P-type substrate to form a P-region, followed by single-sided photoresist treatment and cleaning. S103. An oxide layer and a SIPOS layer are grown on the wafer surface, and phosphorus diffusion is performed on the N-plane to form a P+ region. S104. A P+ region is formed on the P-side by photolithography, etching and diffusion, and a P- region is formed by phosphorus diffusion in another region of the P-side. S105. An N- region is formed above the P+ region on the P-plane through photolithography, etching, and boron diffusion. S106. An N+ region is formed in the N- region through photolithography, etching, and boron diffusion; S107. Electrodes are formed on the P-side through photolithography, vapor deposition, and lift-off processes; S108. An electrode is formed on the N-side by grinding and vapor deposition; S109. Perform laser cutting and dicing on the wafer to divide it into chips; S110. The die is cut and split using ultraviolet laser to divide it into chips and then tested.

2. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S101 specifically includes the following steps: Surface cleaning treatment is performed on P-type silicon wafers; Photoresist is coated onto the N-side and a pattern is exposed. A P+ region is formed on the N-face through diffusion of a phosphorus source; A two-stage oxidation process was used to generate SiO2 thin films; Perform high-temperature annealing and remove photoresist.

3. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S102 specifically includes the following steps: The P-side of the P-type substrate after S101 treatment is wet-cleaned to remove the natural oxide layer on the surface. After cleaning, photoresist is spin-coated onto the P-side and baked to form a photoresist mask layer covering the P-side. Using the photoresist mask layer as a shield, plasma etching is performed on the area of ​​the P-side not covered to remove the oxide layer in that area; Dissolve and remove the photoresist mask layer to expose the etched P-side region; High-temperature phosphorus diffusion is performed on the exposed P-side to form a low-concentration P-region within the P-type substrate.

4. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S103 specifically includes the following steps: Surface pretreatment is performed on the wafer that has completed step S102 before the growth of the double-sided oxide layer; A first layer of silicon dioxide is grown on both sides of the wafer using a voltage-divided controlled thermal oxidation process. A semi-insulating polycrystalline silicon layer is grown on a silicon dioxide layer by low-temperature chemical vapor deposition; Photoresist is applied and patterned on the N-side of the wafer, and the SIPOS layer and silicon dioxide layer in specific areas of the N-side are selectively removed. P+ regions are formed in the N-side exposed silicon region by diffusion of a solid phosphorus source, followed by removal of photoresist and cleaning.

5. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S104 specifically includes the following steps: The P-side of the wafer in step S103 is subjected to plasma cleaning to remove surface impurities; After cleaning, photoresist is spin-coated onto the P-side and baked to form a photoresist layer. The photoresist layer is exposed and developed to form a photolithographic pattern defining the P+ and P- regions on the P-side. Using the photolithography pattern as a mask, reactive ion etching is performed on the P-side to expose the silicon surface of the defined region; On the exposed silicon surface, P+ and P- regions are simultaneously formed on the P-side by performing boron diffusion and phosphorus diffusion, respectively.

6. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S105 specifically includes the following steps: The P-side of the wafer after step S104 is sequentially cleaned and dried with two solutions to remove surface contaminants. Photoresist is spin-coated onto a clean P-side and pre-baked to form a uniform and defect-free photoresist film layer. Align the N-region pattern of the photomask with the existing P+ region on the P surface, expose and develop it to form the N-region pattern on the photoresist film layer; Using a photoresist layer with N-region patterns as a mask, wet etching is performed on the P-side to remove the oxide layer in the patterned area and remove the photoresist. Boron diffusion is performed on the exposed silicon surface area after etching to form N-regions, and then the residual source introduced by the diffusion process is removed.

7. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S106 specifically includes the following steps: The wafer surface after step S105 is cleaned to remove organic impurities; A new photoresist layer is spin-coated onto a clean wafer surface to cover the N-region; The new photoresist layer is exposed and developed to form a photolithographic pattern defining the N+ region; Using the photolithographic pattern as a mask, the surface of the N-region is etched to expose the silicon substrate; High-temperature boron diffusion is performed on an exposed silicon substrate to form an N+ region.

8. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S107 specifically includes the following steps: Plasma bombardment cleaning and adhesion-enhancing layer treatment were applied to the P-side of the S106 wafer. Thick photoresist is coated and alignment exposure based on infrared and visible light dual-band is performed; Stepped post-baking and spray development are performed to form a photoresist pattern with an inverted trapezoidal cross section; Titanium, nickel, and silver metal stacks were sequentially vapor-deposited under ultra-high vacuum conditions; Ohmic contacts are formed by a two-step chemical stripping and rapid thermal annealing process.

9. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S108 specifically includes the following steps: The N-side of the wafer in step S107 is ground and cleaned to flatten and clean the surface; The N-side is finely ground to achieve the set surface flatness requirements; A titanium adhesion layer is deposited on the ground N-surface; A nickel layer and a silver layer are sequentially vapor-deposited onto the titanium adhesion layer to form an N-side electrode; The N-side electrode is annealed to form a good ohmic contact.

10. The method for improving the clamping voltage capability of a TVS diode chip according to claim 1, characterized in that, S110 specifically includes the following steps: The back side of the wafer from step S109 is attached to a special film for ultraviolet laser cutting and fixed to the cutting machine; The internal scanning and cutting along the wafer dicing track is performed using an ultraviolet laser to clean the cutting area and pre-cure the cutting film adhesive. The dicing film attached to the wafer is mechanically expanded to separate the dies from each other along the dicing path; Individual chips are picked up and transferred from the expanded cutting membrane based on visual recognition; The transferred chips are subjected to electrical performance testing and classification, and then labeled and packaged.

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