High-voltage fast recovery diode structure and manufacturing method thereof

Abstract

The invention relates to the technical field of power semiconductor devices, and provides a high-voltage fast recovery diode structure and a manufacturing method thereof, and the high-voltage fast recovery diode structure is a back hole controlled injection diode with a fine groove array in a back active region. The diode structure specifically comprises a front active region and a front edge terminal region, wherein the front active region consists of a front p + anode region and a p-type buffer layer; the front edge terminal region is used for improving the voltage resistance requirement; and the back surface comprises an n-type buffer layer, a floating p + region located in a back surface active region, a non-planar n + cathode region in a fine groove array form, and a p + doped region located in a back surface edge region. In the reverse recovery process of the diode, holes can be injected into the back face, the reverse recovery softness can be effectively improved, and tripping and oscillation of reverse recovery current are restrained. The invention provides a technical scheme and a manufacturing method in the whole technological process. The manufacturing method comprises the steps of grooving, ion implantation, diffusion and the like. The method is also suitable for other semiconductor materials.

Description

[Technical Field]

[0001] This invention relates to a power semiconductor device, and more specifically to a high-voltage fast recovery diode and its manufacturing method. [Background Technology]

[0002] High-voltage fast recovery diodes have wide applications in ultra-high voltage power transmission, new energy technologies, and aerospace technologies. The most common high-voltage fast recovery diode is the PIN diode, whose basic structure consists of p... + Anode region, n - Drift region and n + The cathode region is characterized by low doping and a relatively large thickness in the drift region to improve the breakdown voltage and meet application requirements. As a freewheeling diode, the PIN diode forms a circuit with the load to suppress high voltages generated during power device turn-off, improving the stability and reliability of the device and circuit. Based on the application conditions and purpose, PIN diodes need to have short turn-on and turn-off times, surge current and dynamic avalanche resistance, and good reverse recovery softness.

[0003] During the turn-off (reverse recovery) process of power devices, a snap-off phenomenon occurs. This refers to a sudden drop in current during reverse recovery, often causing high-frequency oscillations and generating overshoot voltage. The snap-off phenomenon poses a challenge to the stability and reliability of the circuit, reducing the reverse recovery softness of the diode, leading to overvoltage breakdown, device burnout, and excessive electromagnetic noise. The sudden voltage and current fluctuations can also impact other components in the circuit, affecting system reliability. Therefore, it is necessary to suppress the snap-off phenomenon.

[0004] To address the current interruption phenomenon, researchers proposed the back-side hole-controlled injection diode (CIBH) and the field charge extraction diode (FCE). Both can suppress the interruption of reverse recovery current in diodes. The principle is that during the reverse recovery process, holes are injected into the p-region on the back side, allowing the reverse recovery current to be maintained without interruption and suppressing current oscillations.

[0005] As shown in the figure Figure 1 and Figure 2 These are schematic diagrams of the FCE diode and the CIBH diode, respectively. They differ in their back-side structure; the former introduces n-type diodes in parallel on the back side in an alternating manner. + cathode region and p + Doped region; while the back side p of the latter + The doped region is floating, and the bottom is a complete n-type region. +Cathode region. The FCE diode forms a parasitic pnp structure, which to some extent affects the conductance modulation in the n-type drift region; while the CIBH diode forms a parasitic pnpn structure, which, due to the latch-up effect, does not affect the conductance modulation, thus making its forward DC characteristics superior to those of the FCE diode.

[0006] When a high-voltage fast recovery diode is forward-biased, lateral hole injection and accumulation occur at the edge of the p-type main junction in the active region. During reverse recovery, the radial concentration of current occurs when the injected hole charge is extracted, potentially causing localized overheating and device burnout. To address this issue, researchers introduced a lateral resistive region at the edge of the main junction. This is a p-type region located between the anode electrode and the edge of the main junction. During forward conduction, the voltage division effect of the lateral resistive region reduces the junction bias at the edge of the main junction, thereby reducing lateral hole injection and effectively solving the aforementioned problem.

[0007] The fabrication of the p-type floating layer region on the back side of traditional CIBH diodes is quite complex, involving sophisticated techniques such as high-energy ion implantation or a combination of back-side epitaxy and ion implantation. For details, see the paper "The CIBHDiode - Great Improvement for Ruggedness and Softness of High Voltage Diodes" by HPFelsl et al., 20th International Symposium on Power Semiconductor Devices and ICs (ISPSD'08), IEEE, Piscataway, NJ, USA, 18 May 2008, pages 173-176, and US Patent 2023 / 0187488. Therefore, there is a need to provide an optimized structure for CIBH diodes and a simplified manufacturing method. [Summary of the Invention]

[0008] To address the aforementioned problems in the fabrication of CIBH diodes, this invention provides a simple process for a non-planar n-type diode with a fine trench array configuration. + The structure and manufacturing method of the CIBH-type high-voltage fast recovery diode in the cathode region are characterized by forming a non-planar cathode structure using a doping and grooving method in the active region on the back side. Furthermore, in addition to the most common silicon power devices, the manufacturing method of this invention can also be extended to other power semiconductor materials such as SiC. The following description mainly focuses on silicon materials, but its technical concepts and process steps are also applicable to other semiconductor materials.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] A non-planar n + The CIBH-type high-voltage fast recovery diode structure in the cathode region includes a diode structure consisting of an anode metal 4 and a p-type cathode metal 6. + The front active region 101 consists of an anode region 5, a p-type buffer layer 6, a p-type lateral resistance region 103, and an isolation oxide layer 7; the front edge termination region 102 improves the withstand voltage requirement, which can be a field ring or field plate, such as a field ring 3, a metal field plate 8, and an isolation oxide layer 7, or other forms such as lateral doping, junction termination extension, or resistive field plate; a low-doped n-type drift region 1; an n-type buffer layer 2; and multiple p-type buffer layers arranged in a regular pattern. + The floating region 9 and the non-planar n in the form of a fine slot array + The back-side active region 201, formed by the cathode region 10, is composed of p + The back edge region 201 is formed by the doped region 11; and the cathode metal 12 at the bottom (usually composed of multiple layers of metal).

[0011] Preferably, the present invention provides a non-planar n + CIBH type high-voltage fast recovery diode structure with cathode region, p-type on the back side. + The surface doping concentration of floating region 9 is 1×10⁻⁶. 18 ~1×10 19 cm -3 The knot depth is 2–5 μm and the width is 100–300 μm; adjacent floating p + The distance between regions 9 is 300-1000 μm; the regular arrangement can be uniform or sparse from the center of the active region to the edge.

[0012] Preferably, the present invention provides a non-planar n + The cathode region of the CIBH-type high-voltage fast recovery diode structure has a p-type cathode region on the back edge. + The surface doping concentration of doped region 11 is 1×10⁻⁶. 18 ~1×10 19 cm -3 The junction depth is 2–5 μm.

[0013] Preferably, the present invention provides a non-planar n + The cathode region CIBH type high-voltage fast recovery diode structure features a non-planar n-type fine trench array. + The surface doping concentration of cathode region 10 is 1×10⁻⁶. 19 ~5×10 20 cm -3 The junction depth is 0.5–2 μm; the width of a single fine cell is 0.3–1 μm, and the distance between adjacent fine cells is 0.3–1 μm.

[0014] A non-planar n +A first method for manufacturing a CIBH-type high-voltage fast recovery diode in the cathode region includes the following steps: (1) Take N-type single crystal silicon as the substrate, and its main body constitutes a low-doped n-type drift region 1; (2) Phosphorus ion implantation is performed on the back side, followed by high-temperature push-bonding diffusion to form an n-type buffer layer 2; (3) Fabricate the front-side structure of the diode, including the front-side active region (i.e., the right boundary from the left edge of the diode to the right edge of the lateral resistance region 103) 101 and the front-side edge termination region 102, but the p-type structure has not yet been formed. + Anode region and anode metal; (4) Boron ions are injected into the front and back sides and thermal diffusion occurs simultaneously to form front p + Anode region 5 and back side p + Doped region 11; (5) Through photolithography and etching processes, a fine array of silicon trenches arranged in a regular pattern is etched within the back active region (i.e., the back part corresponding to the front active region) 201. The etching depth is greater than that of the back p region. + Doped region 11 junction depth will allow for a large area of ​​p + The p is divided into array form. + The region, at this time each p + The districts are all isolated islands; (6) Perform photolithography, retaining photoresist in the back edge region 201 to expose the back active region 201. Use the photoresist as a masking layer to perform high-dose n-type impurity ion implantation on the back side, then remove the photoresist and perform rapid thermal annealing to form a non-planar n-type impurity ion array in the form of a fine trench array within the back active region 201. + Cathode region 10, simultaneously causing isolated p + The isolated islands formed by the doped regions become p + Floating Zone 9; (7) The anode metal 4 is made of aluminum or other metal on the front side, and the cathode metal 12, which is usually made of multiple layers of metal, is made on the back side. (8) Perform light particle irradiation and annealing treatment to achieve global or local lifetime control.

[0015] Preferably, the present invention provides a non-planar n + The first method for manufacturing a CIBH-type high-voltage fast recovery diode in the cathode region, wherein in step (2), the surface doping concentration of the n-type buffer layer 2 is 1×10⁻⁶. 15 ~1×10 16 cm -3 The diffusion junction depth is 10–20 μm.

[0016] A non-planar n + A second method for manufacturing a CIBH-type high-voltage fast recovery diode in the cathode region includes the following steps: (1) Take N-type single crystal silicon as the substrate, and its main body constitutes a low-doped n-type drift region 1; (2) Fabricate the front-side structure of the diode, including the front-side active region (i.e., the right boundary from the left edge of the diode to the right edge of the lateral resistance region 103) 101 and the front-side edge termination region 102, but the p-type structure has not yet been formed. + Anode region and anode metal; (3) Boron ions are injected into the front and back sides and thermal diffusion occurs simultaneously to form front p + Anode region 5 and back side p + Doped region 11; (4) Through photolithography and etching processes, a fine array of silicon trenches arranged in a regular pattern is etched within the back active region (i.e., the back part corresponding to the front active region) 201. The etching depth is greater than that of the back p region. + Doped region 11 junction depth will allow for a large area of ​​p + The p is divided into array form. + The region, at this time each p + The districts are all isolated islands; (5) Perform photolithography, retaining photoresist in the back edge region 201 to expose the back active region 201. Use the photoresist as a masking layer to perform high-dose n-type impurity ion implantation on the back side, then remove the photoresist and perform rapid thermal annealing to form a non-planar n-type impurity ion array in the form of a fine trench array within the back active region 201. + Cathode region 10, simultaneously causing isolated p + The isolated islands formed by the doped regions become p + Floating Zone 9; (6) The anode metal 4 is made of aluminum or other metal on the front side, and the cathode metal 12, which is usually made of multiple layers of metal, is made on the back side. (7) The back side is subjected to multiple hydrogen ion implantations with different energies and doses, followed by low-temperature annealing to form a multi-peak distributed n-type buffer layer 2. (8) Perform light particle irradiation and annealing treatment to achieve global or local lifetime control.

[0017] Preferably, the present invention provides a non-planar n + The second manufacturing method of the CIBH type high-voltage fast recovery diode in the cathode region, in step (6), hydrogen ions are injected into the diode, and the surface doping concentration of the formed n-type buffer layer 2 is 1×10⁻⁶. 15 ~1×10 16 cm -3 The junction depth is 20–60 μm.

[0018] Compared with the closest existing technology, the technical solution provided by this invention has the following superior effects:

[0019] The non-planar n provided by this invention +The manufacturing method for CIBH-type high-voltage fast recovery diodes in the cathode region avoids the complex techniques of high-energy ion implantation or a combination of back-side epitaxy and ion implantation used in existing methods. It employs a doping and trenching method within the active region on the back side to form a non-planar cathode structure, significantly reducing cost and manufacturing difficulty. Furthermore, because the width of each fine trench is very narrow, the silicon trench can be filled after the back metal is fabricated, thus not affecting the planarization of the back metal.

[0020] In summary, the non-planar n provided by this invention + The CIBH-type high-voltage fast recovery diode with cathode region and its manufacturing method involve mature and widely used technologies in the power semiconductor field, with each manufacturing step involving specific processes and procedures. Those skilled in the field of power semiconductor devices can complete the manufacturing of the CIBH diode by following the technical concept, manufacturing steps, and parameter range of this invention, and designing the specific material and process parameters for each manufacturing step based on the device's voltage withstand requirements, static and dynamic performance specifications. Therefore, this invention is a practically feasible manufacturing method. Furthermore, the manufacturing method and technical concept of this invention are also applicable to other semiconductor materials such as SiC. [Attached Image Description]

[0021] Figure 1 This is a schematic diagram of an FCE diode. Figure 2 This is a schematic diagram of the CIBH diode structure.

[0022] Figure 3-9 The non-planar n provided by the present invention + A schematic diagram of the manufacturing process steps for a CIBH-type high-voltage fast recovery diode in the cathode region.

[0023] in: 1—Low-doped n-type drift region 2-n type buffer layer 3—Field Ring 4—Anode Metal 5—p + Anode area 6-p type buffer layer 7—Isolation Oxide Layer 8—Metal Field Plate 9—p + Floating area 10—Non-planar n in the form of fine slot array + cathode region 11—p + Doped region 12—Cathode Metal 13—Photoresist 101—Front-side active region 102—Front Edge Terminal Area 103-p type lateral resistance region 201—Active Area on the Back 202—Rear Terminal Area

Detailed Implementation Methods

[0024] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] This invention provides a method with non-planar n + The CIBH-type high-voltage fast recovery diode structure in the cathode region includes a diode structure consisting of an anode metal 4 and a p-type cathode metal 6. + The front active region 101 consists of anode region 5, p-type buffer layer 6, p-type lateral resistance region 103, and isolation oxide layer 7; the front edge terminal region 102 consists of p-type field ring 3, metal field plate 8, and isolation oxide layer 7; the low-doped n-type drift region 1; the n-type buffer layer 2; and multiple p-type field rings arranged in a regular pattern. + The floating region 9 and the non-planar n in the form of a fine slot array + The back-side active region 201, which is formed by the cathode region 10, is composed of p + The back edge region 201 is formed by the doped region 11, and the cathode metal 12 at the bottom (usually composed of multiple layers of metal).

[0026] p + The function of the floating region is to inject holes into the diode during reverse recovery to prevent current interruption and oscillation. Simultaneously, p... + The floating area and the non-plane n below it + The cathode region and the pn structure above it form a parasitic pnpn structure. Due to the latch-up effect, the carrier concentration in the bulk can be maintained without affecting the conductance modulation.

[0027] p + The floating region is indirectly manufactured using a doping and grooving method within the back-side active region. In terms of process, the etched silicon grooves need to be arranged according to a certain pattern; this can be a uniform arrangement or a sparse arrangement that changes from the center to the edge of the active region. The groove depth must be greater than p. + The depth of the zone ensures that the p is etched through. + District. Forming p + In front of the floating area, a large area of ​​p + The district was divided into isolated islands.

[0028] Non-planar n +The cathode region is manufactured using a back-side active region ion implantation method. Photoresist is used as a masking layer to cover the back-side edge region. After ion implantation, the photoresist is removed, followed by rapid thermal annealing. This process creates a structure where non-planar n-type electrons are present only in the back-side active region. + CIBH diode in the cathode region.

[0029] The fabrication process for n-type buffer layers can utilize ion implantation combined with push-junction diffusion; or, after fabrication of p-type buffer layers... + After the floating region is established, hydrogen ions are injected into the diode. The diffusion junction depth of the buffer layer formed by ion implantation is 10–20 μm, while the junction depth of the buffer layer formed by hydrogen implantation is 20–60 μm.

[0030] The present invention provides a non-planar n + The first method for manufacturing a CIBH-type high-voltage fast recovery diode in the cathode region includes the following steps: Step 1: Based on the different voltage withstand requirements of the diodes, N-type single crystal silicon of different thicknesses is used as the substrate, with a doping concentration of 1×10⁻⁶. 12 ~5×10 13 cm -3 The low-doped n-type drift region; Step two involves implanting phosphorus ions onto the back side of the silicon wafer, followed by push-diffusion at 1100–1200°C for 750–850 minutes to ensure uniform distribution of phosphorus atoms, forming a diffusion junction depth of 10–20 μm and a surface doping concentration of 1 × 10⁻⁶. 15 ~1×10 16 cm -3 n-type buffer layer; (see Figure 3 ) Step 3: Fabricate the front-side structure of the diode, including the front-side active region and the front-side edge termination region, but the anode metal and p-type are not yet formed. + Anode region and metal field plate. For example, boron ion implantation forms a p-type buffer layer, a p-type field ring; photolithography and etching isolate the oxide layer; (see...) Figure 4 ) Step four: Boron ions are implanted on both the front and back sides, and thermal diffusion is simultaneously performed at 1050–1100℃ for 20–40 minutes to form front p-type ions. + The anode region and junction depth are 2–5 μm, and the surface doping concentration is 1 × 10⁻⁶. 18 ~1×10 19 cm -3 The back of p + Doped regions; (see) Figure 5 ) Step 5: Using photolithography and etching processes, a uniformly distributed array of fine silicon trenches is etched within the back active region (i.e., the back portion corresponding to the front active region), with an etching depth greater than that of the back p-type region. +The doped region has a deep junction, which will allow for a large area of ​​p + Divide into multiple isolated p + The region, at this time each p + The regions are all isolated islands. The width of an isolated island is 100–300 μm, and the distance between adjacent isolated islands is 300–1000 μm; (see...) Figure 6 ) Step 6: Perform photolithography, leaving photoresist at the edge of the back side to expose the active area. Use the photoresist as a masking layer to perform photolithography on the back side with a dose of 1×10⁻⁶. 15 ~5×10 16 cm -2 The process involves implanting n-type impurity ions at energies of 50–200 keV, followed by resist removal and rapid thermal annealing at 1000–1100 °C for 10–60 seconds to form a junction depth of 0.5–2 μm and a surface doping concentration of 1 × 10⁻⁶ keV in the back-side active region. 19 ~5×10 20 cm -3 Non-planar n-type fine slot array + The cathode region (the width of a single fine cell is 0.3–1 μm, and the distance between adjacent fine cells is 0.3–1 μm) simultaneously makes p + The isolated islands formed by the doped regions become p + Floating area; (see) Figure 7 and Figure 8 ) Step 7: An aluminum electrode or other metal is deposited on the front side of the diode as the anode metal, and a Ti / Ni / Ag or V / Ni / Ag multilayer metal is deposited on the back side as the cathode metal. Step 8, use a dose of 1×10 10 ~1×10 12 cm -2 The diode is subjected to light particle irradiation (such as electrons or helium ions) with an energy of 0.5 to 2 MeV, followed by annealing at 250 to 400°C for 10 to 30 minutes to control the global or local lifetime of the diode.

[0031] The present invention provides a non-planar n + A second method for manufacturing a CIBH-type high-voltage fast recovery diode in the cathode region includes the following steps: Step 1: Based on the different voltage withstand requirements of the diodes, N-type single crystal silicon of different thicknesses is used as the substrate, with a doping concentration of 1×10⁻⁶. 12 ~5×10 13 cm -3 The low-doped n-type drift region; Step two involves fabricating the front-side structure of the diode, including the front-side active region and the front-side edge termination region, but the anode metal and p-type are not yet formed. +Anode region and metal field plate. For example, boron ion implantation to form a p-type buffer layer, p-type field ring; photolithography and etching to isolate the oxide layer; Step 3: Boron ions are implanted on both the front and back sides, and thermal diffusion is simultaneously performed at 1050–1100℃ for 20–40 minutes to form front-side p-type ions. + The anode region and junction depth are 2–5 μm, and the surface doping concentration is 1 × 10⁻⁶. 18 ~1×10 19 cm -3 The back of p + Doped regions; Step four: Using photolithography and etching processes, a uniformly distributed array of fine silicon trenches is etched within the back active region (i.e., the back portion corresponding to the front active region), with an etching depth greater than that of the back p-type region. + The doped region has a deep junction, which will allow for a large area of ​​p + Divide into multiple isolated p + The region, at this time each p + The regions are all isolated islands. The width of an isolated island is 100–300 μm, and the distance between adjacent isolated islands is 300–1000 μm; Step 5: Perform photolithography, leaving photoresist at the edge of the back side to expose the active area. Use the photoresist as a masking layer to perform photolithography on the back side with a dose of 1×10⁻⁶. 15 ~5×10 16 cm -2 The process involves implanting n-type impurity ions at energies of 50–200 keV, followed by resist removal and rapid thermal annealing at 1000–1100 °C for 10–60 seconds to form a junction depth of 0.5–2 μm and a doping concentration of 1 × 10⁻⁶ within the back-side active region. 19 ~5×10 20 cm -3 Non-planar n-type fine slot array + The cathode region (the width of a single fine cell is 0.3–1 μm, and the distance between adjacent fine cells is 0.3–1 μm) simultaneously makes p + The isolated islands formed by the doped regions become p + Floating area; Step six: Aluminum electrode or other metal is deposited on the front side of the diode as the anode metal, and Ti / Ni / Ag or V / Ni / Ag multilayer metal is deposited on the back side as the cathode metal. Step 7: Administer a single dose of 1×10 13 ~5×10 14 cm -2Multiple hydrogen ion implantations with a single energy of 0.5–5 MeV, followed by low-temperature annealing at 300–400 °C for 90–120 minutes, form a multi-peaked n-type buffer layer distribution that gradually changes from the back side to the bulk. The junction depth of the n-type buffer layer is 20–60 μm, and the surface concentration is 1 × 10⁻⁶. 15 ~1×10 16 cm -3 . Step 8, use a dose of 1×10 10 ~1×10 12 cm -2 The diode is subjected to light particle irradiation (such as electrons or helium ions) with an energy of 0.5 to 2 MeV, followed by annealing at 250 to 400°C for 10 to 30 minutes to control the global or local lifetime of the diode.

[0032] Example 1.

[0033] The following section combines the first manufacturing method to examine non-planar n... + The fabrication of the CIBH-type high-voltage fast recovery diode in the cathode region is described in detail.

[0034] Example 1 consists of the following steps: Step 1: Use 300μm N-type single crystal silicon as a substrate, with a bulk doping concentration of 1×10⁻⁶. 13 cm -3 The low-doped n-type drift region; Step two involves implanting phosphorus ions onto the back side of the silicon wafer, followed by diffusion at 1200°C for 800 minutes to ensure uniform distribution of phosphorus atoms, forming a diffusion junction depth of 15 μm and a surface doping concentration of 1 × 10⁻⁶. 16 cm -3 n-type buffer layer; Step 3: Fabricate the front-side structure of the diode, including the front-side active region and the front-side edge termination region, but the anode metal and p-type are not yet formed. + Anode region and metal field plate. For example, boron ion implantation to form a p-type buffer layer, p-type field ring; photolithography and etching to isolate the oxide layer; Step four: Boron ions are implanted on both the front and back sides, and thermal diffusion is simultaneously performed at 1100℃ for 30 minutes to form front p-type ions. + The anode region and junction depth are 3 μm, and the surface doping concentration is 1 × 10⁻⁶. 19 cm -3 The back of p + Doped regions; Step 5: Using photolithography and etching processes, a uniformly distributed array of fine silicon trenches is etched within the back active region (i.e., the back portion corresponding to the front active region), with an etching depth greater than that of the back p-type region. + The doped region has a deep junction, which will allow for a large area of ​​p +Divide into multiple isolated p + The region, at this time each p + Each region consists of isolated islands. The width of an isolated island is 100 μm, and the distance between adjacent isolated islands is 300 μm. Step 6: Perform photolithography, leaving photoresist at the edge of the back side to expose the active area. Use the photoresist as a masking layer to perform photolithography on the back side with a dose of 1×10⁻⁶. 16 cm -2 The process involves implanting n-type impurity ions with an energy of 100 keV, followed by resist removal and rapid thermal annealing at 1100℃ for 30 seconds to form a junction with a depth of 1 μm and a surface doping concentration of 1 × 10⁻⁶ within the active region on the back side. 20 cm -3 Non-planar n-type fine slot array + The cathode region (each fine cell is 0.5 μm wide, and the distance between adjacent fine cells is 0.5 μm) simultaneously isolates p + The isolated islands formed by the doped regions become p + Floating area; Step 7: An aluminum electrode is deposited on the front side of the diode as the anode metal, and a Ti / Ni / Ag multilayer metal is deposited on the back side as the cathode metal. Step 8, use a dose of 1×10 12 cm -2 The diode's local lifetime is controlled by helium ion irradiation with an energy of 1.5 MeV followed by annealing at 300°C for 20 minutes.

[0035] Example 2.

[0036] The following section combines the second manufacturing method to examine non-planar n... + The fabrication of the CIBH-type high-voltage fast recovery diode in the cathode region is described in detail. Its structure and manufacturing steps are basically the same as in Example 1, except that the ion implantation method in step two is replaced with hydrogen implantation to form a buffer layer, which is placed after the metal fabrication. Specifically, the hydrogen implantation method involves a single dose of 1×10⁻⁶. 13 ~5×10 14 cm -2 Five hydrogen ion implantations with single energies ranging from 0.5 to 5 MeV were performed, followed by low-temperature annealing at 350°C for 120 minutes to form a multi-peaked n-type buffer layer distribution that gradually changes from the back side to the bulk. The junction depth of the n-type buffer layer was 40 μm, and the surface concentration was 1 × 10⁻⁶. 16 cm -3 .

[0037] The present invention has a non-planar n +The CIBH-type high-voltage fast recovery diode in the cathode region is simple to manufacture. It uses a back-side active region doping and trenching method to form a non-planar cathode structure, avoiding the complex techniques of high-energy ion implantation or a combination of back-side epitaxy and ion implantation, significantly reducing manufacturing difficulty and cost. In addition, because the width of a single fine trench is very narrow, the silicon trench can be filled after the back metal is fabricated, thus achieving back metal planarization.

[0038] Finally, it should be noted that the above embodiments are only used to illustrate the present invention and not to limit the technical solutions and manufacturing methods described in the present invention. Therefore, although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or substitutions can still be made to the present invention. All technical solutions and manufacturing methods and their improvements that do not depart from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A high-voltage fast recovery diode structure, characterized in that: The diode structure comprises an anode metal (4), a p + The front active region (101) is composed of an anode region (5), a p-type buffer layer (6), a p-type lateral resistance region (103), and an isolation oxide layer (7); the front edge termination region (102) improves the withstand voltage; the low-doped n-type drift region (1); the n-type buffer layer (2); and multiple p-type buffer layers arranged in a regular pattern. + The floating region (9) and the non-planar n in the form of a fine slot array + The back-side active region (201) formed by the cathode region (10) is composed of p + The back edge region (201) formed by the doped region (11), and the cathode metal (12) at the bottom.

2. The high-voltage fast recovery diode structure according to claim 1, characterized in that: The back side p + The surface doping concentration of the floating region (9) is 1×10 18 ~1×10 19 cm -3 The knot depth is 2–5 μm and the width is 100–300 μm; adjacent floating p + The distance between regions (9) is 300–1000 μm.

3. The high-voltage fast recovery diode structure according to claim 1, characterized in that: The back edge region p + The surface doping concentration of the doped region (11) is 1×10 18 ~1×10 19 cm -3 The junction depth is 2–5 μm.

4. The high-voltage fast recovery diode structure according to claim 1, characterized in that: The non-planar n-shaped fine slot array + The surface doping concentration of the cathode region (10) is 1×10⁻⁶. 19 ~5×10 20 cm -3 The junction depth is 0.5–2 μm; the width of a single fine cell is 0.3–1 μm, and the distance between adjacent fine cells is 0.3–1 μm.

5. A method for manufacturing the high-voltage fast recovery diode according to claim 1, characterized in that: The manufacturing method includes the following steps: (1) N-type single crystal silicon is used as the substrate, and its main body constitutes a low-doped n-type drift region (1); (2) Phosphorus ion implantation is performed on the back side, followed by high-temperature push-bonding diffusion to form an n-type buffer layer (2); (3) Fabricate the front-side structure of the diode, including the front-side active region (101) and the front-side edge termination region (102), but the p-side structure has not yet been formed. + Anode region and anode metal; (4) Boron ions are injected into the front and back sides and thermal diffusion occurs simultaneously to form front p + Anode region (5) and back p + Doped region (11); (5) Through photolithography and etching processes, a fine array of silicon trenches arranged in a regular pattern is etched within the active region (201) on the back side, with an etching depth greater than or equal to that on the back side p. + The doped region (11) has a deep junction, which will allow for a large area of ​​p + The p is divided into array form. + district; (6) Perform photolithography, retaining photoresist in the back edge region (201) to expose the back active region (201). Use the photoresist as a masking layer to perform high-dose n-type impurity ion implantation on the back side, then remove the photoresist and perform rapid thermal annealing to form a non-planar n-type impurity ion array in the form of a fine trench array within the back active region (201). + Cathode region (10), while simultaneously isolating p + The doped region becomes p + Floating area (9); (7) The anode metal (4) is made on the front side and the cathode metal (12) is made on the back side; (8) Perform light particle irradiation and annealing treatment to achieve global or local lifetime control.

6. The method for manufacturing a high-voltage fast recovery diode according to claim 5, characterized in that: In step (2), the surface doping concentration of the n-type buffer layer (2) is 1×10⁻⁶. 15 ~1×10 16 cm -3 The diffusion junction depth is 10–20 μm.

7. A method for manufacturing the high-voltage fast recovery diode according to claim 1, characterized in that: Unlike the manufacturing method described in claim 5, the manufacturing method may include the following steps: (1) N-type single crystal silicon is used as the substrate, and its main body constitutes a low-doped n-type drift region (1); (2) Fabricate the front-side structure of the diode, including the front-side active region (101) and the front-side edge termination region (102), but the p-side structure has not yet been formed. + Anode region and anode metal; (3) Boron ions are injected into the front and back sides and thermal diffusion occurs simultaneously to form front p + Anode region (5) and back p + Doped region (11); (4) Through photolithography and etching processes, a fine array of silicon trenches arranged in a regular pattern is etched within the active region (201) on the back side, with an etching depth greater than that on the back side p. + The doped region (11) has a deep junction, which will allow for a large area of ​​p + The p is divided into array form. + district; (5) Perform photolithography, retaining photoresist in the back edge region (201) to expose the back active region (201). Use the photoresist as a masking layer to perform high-dose n-type impurity ion implantation on the back side, then remove the photoresist and perform rapid thermal annealing to form a non-planar n-type impurity ion array in the form of a fine trench array within the back active region (201). + Cathode region (10), while simultaneously isolating p + The doped region becomes p + Floating area (9); (6) The anode metal (4) is made on the front side and the cathode metal (12) is made on the back side; (7) Multi-energy, multi-dose hydrogen ion implantation is performed on the back side, followed by low-temperature annealing to form a multi-peak distributed n-type buffer layer (2); (8) Perform light particle irradiation and annealing treatment to achieve global or local lifetime control.

8. The method for manufacturing a high-voltage fast recovery diode according to claim 7, characterized in that: In step (7), the surface doping concentration of the n-type buffer layer (2) is 1×10⁻⁶. 15 ~1×10 16 cm -3 The junction depth is 20–60 μm.

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