A semiconductor device and a method of fabricating the same

Abstract

A semiconductor device and a method of manufacturing the same, including: providing a substrate, the substrate including a substrate and a dielectric layer on the substrate; the dielectric layer having a via formed therein, the via penetrating the dielectric layer in a direction perpendicular to the substrate, the via including a first hole and a second hole arranged in the direction perpendicular to the substrate and in communication, the second hole being located on a side of the first hole away from the substrate; the substrate further including a covering material layer covering inner walls of the via; thinning the covering material layer using a wet etching process, the wet etching process being configured to control at least a reaction time to be less than a preset value, so that a thinned thickness of a portion of the covering material layer located on the inner wall of the second hole is greater than a thinned thickness of a portion of the covering material layer located on the inner wall of the first hole. The present application improves the consistency of the thickness of the covering material layer, thereby improving the consistency of the performance of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its fabrication method. Background Technology

[0002] With the increasing integration of functions and the growing demand for higher storage density in mobile consumer electronics, the design and manufacturing of MOS transistors have gradually transitioned from traditional planar to three-dimensional structures, and channels have also moved from planar to vertical three-dimensional. In this context, the fabrication of high-quality channel layers has become increasingly important.

[0003] To achieve good gate control performance in MOS transistors, the channel layer typically needs to be fabricated as a thin and uniform film. A thin film restricts grain growth during annealing, inducing smaller grains and making the film prone to voids, leading to performance degradation. Furthermore, the fabricated channel material layer often exhibits a significant thickness difference between the bottom of the channel hole and near the opening. When forming a thicker channel material layer and then thinning it to form the channel layer, the channel layer at the bottom of the channel hole can easily become too thin, resulting in excessively high local resistance. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, one aspect of the present invention provides a method for fabricating a semiconductor device, the method comprising:

[0006] A substrate is provided, the substrate comprising a substrate and a dielectric layer located on the substrate;

[0007] Through-holes are formed in the dielectric layer and penetrate the dielectric layer in a direction perpendicular to the substrate. The through-holes include a first hole and a second hole arranged and connected in a direction perpendicular to the substrate, and the second hole is located on the side of the first hole away from the substrate.

[0008] The substrate further includes a covering material layer that covers the inner wall of the through hole;

[0009] The cover material layer is thinned using a wet etching process, wherein the wet etching process is configured to control the reaction time to be less than a preset value, such that the portion of the cover material layer located on the inner wall of the second hole is thinned to a thickness greater than the portion of the cover material layer located on the inner wall of the first hole.

[0010] In one embodiment, the material of the cover material layer includes polycrystalline silicon, and the thinning of the cover material layer using a wet etching process includes:

[0011] S1. A self-limiting oxidant solution is provided from the opening on the side of the through hole away from the substrate, and the self-limiting oxidant solution is brought into contact with the surface of the cover material layer away from the inner wall of the through hole for a first reaction time to perform oxidation treatment and form an oxidized cover material layer. The oxidized cover material layer includes a remaining cover material layer and an oxide material layer located on the surface of the remaining cover material layer away from the inner wall of the through hole. The oxide material layer includes silicon oxide and has a first thickness. The first reaction time is controlled such that the ratio of unsaturated silicon oxide to saturated silicon oxide in the oxide material layer in the first hole is greater than that in the oxide material layer in the second hole.

[0012] S2. An acidic etchant is provided, and the acidic etchant contacts the surface of the oxidized cover material layer away from the inner wall of the via for a second reaction time to form a thinned cover material layer. The thinned cover material layer includes the remaining cover material layer and a remaining oxide material layer located on the surface of the remaining cover material layer away from the inner wall of the via. The acidic etchant is capable of removing silicon oxide, and the rate of removal of saturated silicon oxide is greater than the rate of removal of unsaturated silicon oxide. The second reaction time is controlled so that the remaining oxide material layer is present in the first hole, and the remaining oxide material layer includes unsaturated silicon oxide.

[0013] The reaction time includes the first reaction time and the second reaction time.

[0014] In one embodiment, the self-limiting oxidant solution comprises O3 water, and the acidic etchant comprises a hydrofluoric acid solution.

[0015] In one embodiment, the concentration of the O3 water is 10ppm-50ppm, and the first reaction time is 20s-360s;

[0016] The concentration of the hydrofluoric acid solution is 0.5%wt-5%wt, and the second reaction time is 5s-80s.

[0017] In one embodiment, steps S1 and S2 are repeated in combination for N cycles, where N ≥ 2, until the covering material layer is thinned to a second thickness.

[0018] In the 2nd to Nth cycles, step S1, which involves contacting the self-limiting oxidant solution with the surface of the covering material layer away from the inner wall of the through hole for a first reaction time to perform oxidation treatment and form an oxidized covering material layer, includes:

[0019] The self-limiting oxidant solution is brought into contact with the surface of the thinned covering material layer formed in step S2 of the previous cycle away from the inner wall of the through hole for a first reaction time to perform oxidation treatment.

[0020] In one embodiment, the substrate further includes a conductive structure located between the substrate and the dielectric layer, the bottom surface of the first hole exposing the conductive structure, and the cover material layer further covering the bottom surface of the first hole.

[0021] In one embodiment, providing the substrate includes:

[0022] The substrate and a conductive structure are provided, wherein the conductive structure is located on the surface of the substrate;

[0023] A stacked structure is formed on the substrate, the stacked structure including a first dielectric layer and a patterned gate conductor layer stacked sequentially from the substrate, forming a first via through the patterned gate conductor layer, the first via extending to a portion of the depth of the first dielectric layer;

[0024] A gate insulating material layer and a first capping layer are sequentially formed on the inner wall of the first via. The first capping layer includes amorphous silicon. Anisotropic etching is used to form a second via. On the orthographic projection of the substrate, the second via is located inside the first via. The second via penetrates the stacked structure and exposes the conductive structure. The anisotropic etching does not remove the entire thickness of the portion of the first capping layer located on the sidewall of the first via. The anisotropic etching does not remove the portion of the gate insulating material layer located on the sidewall of the first via.

[0025] A second capping layer is formed on the inner wall of the second through hole, the second capping layer comprising amorphous silicon;

[0026] The annealing process causes the amorphous silicon in the first and second capping layers to crystallize and transform into polycrystalline silicon.

[0027] The cover material layer includes an annealed first cover layer and a second cover layer, and the cover material layer surrounds the entire surface of the first via and the second via to form the via. The dielectric layer includes the remaining stacked structure and the remaining gate insulating material layer.

[0028] In one embodiment, in the step of providing the substrate:

[0029] The second hole includes a segment of the through hole corresponding to the remaining first capping layer after the anisotropic etching, and the first hole includes a segment of the through hole located between the second hole and the conductive structure;

[0030] The diameter of the second hole is larger than that of the first hole, and the thickness of the covering material layer in the second hole is greater than that in the first hole.

[0031] In one embodiment, the value of N ranges from 10 to 40.

[0032] Another aspect of the present invention provides a semiconductor device, which is prepared using the method described above.

[0033] According to the semiconductor device and its fabrication method provided by the present invention, the quality of the cover material layer can be improved by depositing a thicker cover material layer and then thinning it using a wet etching process. By controlling the reaction time of the wet etching process to be less than a preset value, the thickness of the cover material layer located on the inner wall of the second hole can be thinned to be greater than the thickness of the portion located on the inner wall of the first hole, thereby achieving differentiated thinning at different depths of the via and optimizing the electrical performance and consistency of the semiconductor device. Attached Figure Description

[0034] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0035] In the attached image:

[0036] Figures 1A to 1E A cross-sectional schematic diagram is shown of a device obtained by sequentially performing the steps according to a semiconductor device fabrication method in the related art;

[0037] Figure 1F A three-dimensional schematic diagram showing pinholes appearing in a covering material layer formed according to a manufacturing method of the related technology is shown;

[0038] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of the present invention is shown;

[0039] Figures 3A to 3F A cross-sectional schematic diagram of a semiconductor device fabrication method according to a specific embodiment of the present invention is shown, showing the device obtained by sequentially performing each step.

[0040] Figure 3G A perspective view of the cover material layer before and after thinning according to a manufacturing method of an embodiment of the present invention is shown;

[0041] Figure 4 A schematic diagram illustrating a cyclic oxidation-etching process to thin the overlay material layer according to an embodiment of the present invention is shown. Detailed Implementation

[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0043] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0045] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] In related technologies, firstly, such as Figure 1A As shown, a substrate 100 and a conductive structure 102 are provided, the conductive structure 102 being located on the surface of the substrate 100; a stacked structure is formed on the substrate 100, the stacked structure including a first dielectric layer 101 and a patterned gate conductor layer 103 stacked sequentially from the substrate; a first via 104 is formed through the patterned gate conductor layer 103, the first via 104 extending to a portion of the depth of the first dielectric layer 101.

[0048] Next, as Figure 1B As shown, a gate insulating material layer 105 and a first capping layer 106 are sequentially formed on the inner wall of the first through hole 104, and the first capping layer 106 includes amorphous silicon.

[0049] Next, as Figure 1C As shown, anisotropic etching is used to form a second via 107. In the orthographic projection of the substrate 100, the second via 107 is located inside the first via 104, and the second via 107 exposes the conductive structure 102.

[0050] Next, as Figure 1D As shown, a second capping layer 108 is formed on the inner wall of the second through hole 107, and the second capping layer 108 includes amorphous silicon.

[0051] Finally, as Figure 1E As shown, the annealing process causes the amorphous silicon in the first capping layer 106 and the second capping layer 108 to crystallize and transform into polycrystalline silicon, thereby forming the capping material layer 109.

[0052] In the above scheme, the total thickness of the first capping layer 106 and the second capping layer 108 can be controlled to be less than 10 nm to obtain a capping material layer 109 (as a channel layer) with the required thickness. However, during the annealing process, the grain growth process is limited by the increase of free energy, which easily induces smaller grains, resulting in high grain boundary density and lattice scattering; and, as Figure 1E , Figure 1FAs shown, thin amorphous silicon films are prone to pinholes. After annealing, the film volume shrinks, making the pinholes more noticeable. This results in a non-uniform distribution of electron channels in the channel, leading to excessively high local resistance. Both of these factors weaken the electrical performance of the channel.

[0053] In the above scheme, the total thickness of the first capping layer 106 and the second capping layer 108 can be controlled to be large (e.g., greater than 10 nm), and a channel layer with a thickness of less than 10 nm can be obtained by thinning after annealing and crystallization. The capping material layer 109 before thinning has different thicknesses at different depth positions. However, the reaction time required to achieve the expected thickness reduction by one-time wet etching is long, resulting in the thinning thickness of the film at different depth positions being consistent. The remaining capping material layer 109 near the bottom of the hole is too thin, which affects the electrical properties of the device and the electrical connection with the conductive structure 102.

[0054] In view of the aforementioned technical problems, Embodiment 1 of the present invention proposes a semiconductor device and a method for fabricating the same, such as... Figure 2 As shown, the preparation method includes:

[0055] In step 201, a substrate is provided, the substrate including a base plate and a dielectric layer located on the base plate;

[0056] Through-holes are formed in the dielectric layer and penetrate the dielectric layer in a direction perpendicular to the substrate. The through-holes include a first hole and a second hole arranged and connected in a direction perpendicular to the substrate, and the second hole is located on the side of the first hole away from the substrate.

[0057] The substrate also includes a cover material layer that covers the inner walls of the through-holes;

[0058] In step 202, a wet etching process is used to thin the cover material layer. The wet etching process is configured such that the reaction time is controlled to be less than a preset value, so that the thickness of the portion of the cover material layer located on the inner wall of the second hole is thinned to be greater than the thickness of the portion of the cover material layer located on the inner wall of the first hole.

[0059] The semiconductor device fabrication method provided in this invention improves the quality of the cover material layer by depositing a thick cover material layer and then thinning it using a wet etching process. By controlling the reaction time of the wet etching process to be less than a preset value, under certain wet reaction conditions, the diffusion of etchant and reaction products is limited in a short time due to the narrow space of the via, making it impossible to achieve uniform etching. By controlling the reaction time of the wet etching process to be less than the preset value, the thickness of the cover material layer thinned at the inner wall of the second via is greater than the thickness thinned at the inner wall of the first via, thereby achieving differentiated thinning at different depths of the via and optimizing the electrical performance and consistency of the semiconductor device.

[0060] The preset value is determined based on at least one of the reaction rate determined by the wet etching conditions (e.g., etchant supply concentration, reaction temperature, etc.) and the required degree of differential thinning, and can be determined experimentally. For example, the preset value is inversely proportional to the reaction rate determined by the wet etching process conditions, and inversely proportional to the degree to which the thickness of the portion of the cover material layer located on the inner wall of the second hole is thinned is greater than the thickness of the portion of the cover material layer located on the inner wall of the first hole.

[0061] The substrate material includes, but is not limited to, at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. It can also be a multilayer structure composed of these semiconductor materials, or silicon-on-insulator (SOI), strained silicon-on-insulator (SSOI), strained silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). It can also be a double-side polished wafer (DSP), or a substrate with an insulating surface. For example, the substrate includes a silicon wafer and an insulating layer on the surface of the silicon wafer, with semiconductor devices formed in the silicon wafer and metal wiring formed in the insulating layer. It can also be an insulating substrate. The substrate material is not limited to the examples above and can be chosen according to actual needs.

[0062] The dielectric layer may include a single insulating dielectric layer or an insulating dielectric layer composed of alternating stacked materials, such as a stacked dielectric layer of alternating silicon oxide and silicon nitride; the dielectric layer may include a stack of insulating and conductive layers, or a stack of alternating insulating and conductive layers, such as a stack of alternating silicon oxide and tungsten. It is not limited to these, and the material of the dielectric layer can be selected according to actual needs.

[0063] Through holes can be used as channel holes or conductive plug through holes, etc. The path of the through hole vertically penetrating the dielectric layer can be straight or curved. The diameter of the through hole along the vertical direction can be constant or variable. The horizontal cross-sectional shape of the through hole can be circular, polygonal, elongated or irregular. The first hole and the second hole are two segments of the through hole. Their horizontal cross-sectional shapes and dimensions can be the same or different, and can be specifically set according to actual needs.

[0064] The cover material layer covers the inner wall of the via, meaning it does not completely fill the via. The cover material layer may only cover the sidewalls of the via, or it may cover both the sidewalls and the bottom surface of the via. In one embodiment, the cover material layer is used to thin in subsequent steps to form the channel layer of a transistor; the cover material layer may include a semiconductor material, such as polysilicon. In another embodiment, the cover material layer is used to thin in subsequent steps to form an isolation layer between a vertically conductive plug and the via; the cover material layer may include an insulating material, such as silicon oxide, silicon nitride, or a high-dielectric-constant material. In yet another embodiment, the inner wall of the via includes an insulating material, and the cover material layer is used to thin in subsequent steps to form an adhesion layer between the vertically conductive plug and the via; the cover material layer may include a material that can improve the adhesion between the metal and the dielectric material, such as titanium nitride. The material of the cover material layer can be selected according to actual needs; further examples are not provided here.

[0065] In wet etching, selective etching removes a portion of the cover material layer without damaging the dielectric layer. Under specific wet reaction conditions, the limited diffusion of etchant and reaction products within the confined space of the via allows for controlled wet etching time to be kept below a preset value. This results in a greater reduction in thickness of the cover material layer located on the inner wall of the second via than that of the inner wall of the first via. This differentiated thinning at different depths of the via optimizes the electrical performance and consistency of the semiconductor device. The preset value is determined experimentally based on the via dimensions (e.g., depth and width), wet etching conditions (e.g., etchant concentration, reaction temperature), reaction rate, and the required degree of differentiated thinning.

[0066] Preferably, to achieve more precise control, the present invention provides Embodiment Two, which, based on Embodiment One, further employs a wet etching process combining self-limiting oxidation and selective wet etching to remove oxides. Specifically, when the material of the overlay layer is polycrystalline silicon, the thinning process includes the following steps:

[0067] In step S1, a self-limiting oxidation process is performed: a self-limiting oxidant solution is provided from the opening (i.e., the top opening) on ​​the side of the via away from the substrate, allowing it to contact the surface of the cover material layer away from the inner wall of the via for a first reaction time t1 to perform oxidation and form an oxidized cover material layer. The oxidized cover material layer includes a remaining cover material layer and an oxide material layer located on the surface of the remaining cover material layer away from the inner wall of the via. The oxide material layer includes silicon oxide and has a first thickness.

[0068] That is, after the self-limiting oxidation of polycrystalline silicon in step S1, a certain thickness of polycrystalline silicon is oxidized to form silicon oxide, and the thickness of silicon oxide is the first thickness. The first reaction time t1 causes the self-limiting oxidation thickness on the surface of the covering material layer to reach its maximum value and automatically stop, forming an oxide material layer with the maximum thickness (i.e., the first thickness).

[0069] The reason for choosing a self-limiting oxidant is that it can form a silicon oxide layer with a relatively stable thickness on the surface of the covering material layer, without increasing indefinitely in thickness with the extension of reaction time. This self-limiting characteristic is the basis for achieving a fixed thickness removal in each cycle, ensuring the repeatability and accuracy of the process.

[0070] During oxidation, such as Figure 4 As shown, the first reaction time t1 is controlled such that the ratio of unsaturated silicon oxide 3091 to saturated silicon oxide 3092 in the first thickness silicon oxide layer formed in the first hole 310 is higher than that in the silicon oxide layer formed in the second hole. The reason why the proportion of unsaturated silicon oxide 3091 is higher in the first hole and lower in the second hole is due to the following reasons:

[0071] First, after the self-limiting oxidant solution (such as O3 water) flows in from the top of the through-hole, it mainly relies on molecular diffusion to transport to the bottom. During the downward diffusion process, the oxidant preferentially reacts with the upper polycrystalline silicon surface and is continuously consumed, resulting in a lower effective oxidant concentration in the first hole at the bottom compared to the upper region, causing the first hole to be in a state of insufficient reactant supply. In addition, the first hole is located deeper than the second hole in the through-hole, and the depth restricts the convection and renewal of the reaction liquid, making it difficult to replenish reactants and also making it difficult for byproducts generated by the oxidation reaction (such as hydrogen ions and hydrated silicon species) to be discharged, thus creating a local chemical environment that inhibits further oxidation.

[0072] The formation of saturated silicon oxide requires each silicon atom to be fully bonded with a sufficient number of oxygen atoms. However, in the first pore, due to the aforementioned reasons, the oxidant supply is insufficient, and the oxidation reaction remains largely at the incomplete oxidation stage, producing unsaturated silicon oxide. Therefore, within the same process time, the oxidation process in the first pore is essentially carried out under conditions of low reactant concentration, high byproduct concentration, and inhibited reaction kinetics. This results in a higher proportion of unsaturated silicon oxide in the oxide layer formed in the first pore compared to the second pore, where reaction conditions are more abundant.

[0073] As an example, the self-limiting oxidant solution includes O3 water, i.e., an aqueous ozone solution, with a concentration of 10ppm-50ppm, and the first reaction time t1 is 20s-360s. The self-limiting oxidation of 10ppm-50ppm O3 water reaches oxide layer thickness saturation within 20s-360s, that is, it oxidizes a certain thickness of polycrystalline silicon to form silicon oxide and then self-limits, with the formed silicon oxide having a certain corresponding thickness.

[0074] When the first reaction time t1 is too long, for example, more than 360s, the oxide material layer is basically composed entirely of saturated silicon oxide, and the content of unsaturated silicon oxide is almost zero. When the first reaction time t1 is too short, for example, less than 20s, the oxide material layer cannot reach the maximum thickness of self-limiting oxidation, and the oxide material layer is basically composed entirely of unsaturated silicon oxide, with the content of saturated silicon oxide being almost zero. This makes it impossible to guarantee the repeatability and accuracy of the process, and the differential etching in the subsequent step S2 cannot be accurately achieved.

[0075] Subsequently, in step S2, an acidic etchant is provided to contact the surface of the oxidized cover material layer away from the inner wall of the via (i.e., the surface exposed to the acidic etchant) for a second reaction time t2, forming a thinned cover material layer. The thinned cover material layer includes the remaining cover material layer and the remaining oxide material layer located on the surface of the remaining cover material layer away from the inner wall of the via; that is, the acidic etchant retains a portion of the remaining oxide material layer.

[0076] The selection criteria for acidic etchants include: the ability to remove silicon oxide, and the removal rate of saturated silicon oxide being greater than the removal rate of unsaturated silicon oxide. Therefore, as... Figure 4 As shown, by controlling the second reaction time t2, a residual oxide material layer can be formed in the first pore, the residual oxide material layer including unsaturated silicon oxide 3091.

[0077] Accordingly, the reaction time includes a first reaction time t1 and a second reaction time t2. That is, controlling the reaction time to be less than a preset value includes controlling the first reaction time t1 and the second reaction time t2.

[0078] As an example, the acid etchant includes diluted hydrofluoric acid (DHF) at a concentration of 0.5%wt-5%wt, with a second reaction time t2 of 5s-80s.

[0079] In existing technologies, alkaline etchants are typically used for wet etching to thin polysilicon layers. However, alkaline etchants can cause surface damage or texturing of the polysilicon layer, affecting the electrical properties of semiconductor devices. This embodiment uses an acidic etchant to avoid these drawbacks.

[0080] When the second reaction time t2 is too long, for example, more than 80 s, after the unsaturated silicon oxide is removed, the saturated silicon oxide is also largely or completely removed, and the thickness difference of the remaining oxide material layer between the first hole and the second hole is reduced or non-existent; when the second reaction time t2 is too short, for example, less than 5 s, the unsaturated silicon oxide in the first hole and the second hole is not completely removed, and the thickness difference of the remaining oxide material layer between the first hole and the second hole is reduced or non-existent.

[0081] The combination of steps S1 and S2 can be performed only once. To achieve the target thinning thickness, this invention also provides an embodiment three based on embodiment two: the combination of steps S1 and S2 can be repeated N times, where N≥2, thereby achieving the target thinning thickness, as shown below. Figure 4 As shown. In the 2nd to Nth cycles, in step S1, the self-limiting oxidant solution is brought into contact with the surface of the thinned cover material layer formed in step S2 of the previous cycle, away from the inner wall of the via, for a first reaction time for oxidation treatment. Then, in step S2 of the current cycle, the oxide material layer generated by the oxidation treatment is differentially removed. The above differential oxidation etching process is repeated in each cycle. After multiple cycles, the total thickness of the cover material layer thinned on the inner wall of the second via is greater than the total thickness thinned on the inner wall of the first via, thus achieving gradient thinning, correcting the inconsistency of the initial thickness distribution, and ultimately making the thickness distribution of the cover material layer within the via more uniform.

[0082] Furthermore, since the thinned cover material layer formed in step S2 of the previous cycle includes at least an oxide material layer located in the first hole, by contacting the self-limiting oxidant solution with the surface of the thinned cover material layer formed in step S2 of the previous cycle away from the inner wall of the via for a first reaction time in step S1 to perform oxidation treatment, the content of saturated silicon oxide in the first hole can be further increased, thereby further increasing the difference in saturated silicon oxide content between the first hole and the second hole and improving the amplitude of differential etching.

[0083] In one embodiment, a conductive structure is further disposed on the substrate, the conductive structure being located between the dielectric layer and the substrate. For example, a cover material layer is used to form a channel layer, and the conductive structure can be used to form a conductive connection with the channel layer. The conductive structure can be disposed on the substrate surface, i.e., the conductive structure is exposed by a via, or the conductive structure is exposed on the substrate surface, and correspondingly, the cover material layer covers the bottom surface of the first via. The material of the conductive structure includes, but is not limited to, semiconductors, metals, metal silicides, etc.; wherein, the semiconductor material may include polycrystalline silicon; the metal material may include tungsten (W) or copper (Cu).

[0084] Below, for reference Figures 3A to 3G The preparation method of Embodiment 4 of the present invention will be described in detail, wherein, Figures 3A to 3FA cross-sectional schematic diagram of a semiconductor device fabrication method according to a specific embodiment of the present invention is shown, showing the device obtained by sequentially performing each step. Figure 3G A perspective view of the cover material layer before and after thinning according to a manufacturing method of an embodiment of the present invention is shown; Figure 4 A schematic diagram illustrating a cyclic oxidation-etching process to thin the overlay material layer according to an embodiment of the present invention is shown.

[0085] like Figure 3E As shown, a substrate is provided, the substrate including a substrate 300 and a dielectric layer located on the substrate 300, and a conductive structure 302 located on the surface of the substrate 300. Through holes are formed in the dielectric layer, the through holes expose the conductive structure 302, and a cover material layer covers the inner wall of the through holes.

[0086] In this embodiment, the material of the substrate 300 is not specifically limited. The dielectric layer includes a first dielectric layer 301 and a patterned gate conductor layer 303. The material of the covering material layer includes polysilicon. The conductive structure 302 is used to electrically connect with the subsequently formed channel layer.

[0087] In this embodiment, the step of providing a substrate includes providing a substrate 300 and a conductive structure 302, forming a stacked structure on the substrate 300, the stacked structure including a first dielectric layer 301 and a patterned gate conductor layer 303 stacked sequentially from the substrate 300.

[0088] The material of the first dielectric layer 301 includes silicon oxide or other suitable dielectric materials. The first dielectric layer 301 can be deposited by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition processes. The first dielectric layer 301 may comprise a combination of one or more dielectric materials.

[0089] The gate conductor layer includes a conductive host layer, the material of which may include conductive metals such as tungsten or copper, or polysilicon or other conductive materials. Exemplarily, the gate conductor layer further includes a barrier layer located on the side of the conductive host layer facing the first dielectric layer 301. The barrier layer prevents the material of the conductive host layer from diffusing into the first dielectric layer 301, thereby improving the stability and reliability of the semiconductor device. The material of the barrier layer includes, but is not limited to, titanium nitride.

[0090] Next, the gate conductor layer is patterned to form a patterned gate conductor layer 303. Specifically, a photoresist layer is formed on the gate conductor layer, and the gate conductor layer is etched using the patterned photoresist layer as a mask to form the patterned gate conductor layer 303.

[0091] Exemplarily, after etching to form the patterned gate conductor layer 303, a second dielectric layer (not shown) is formed covering the patterned gate conductor layer 303. The material of the second dielectric layer includes silicon oxide or other suitable dielectric materials. The second dielectric layer can be deposited by atomic layer deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes. The second dielectric layer may include a combination of one or more dielectric materials.

[0092] Next, a first via 304 is formed penetrating the patterned gate conductor layer 303, extending to a portion of the depth of the first dielectric layer 301. Specifically, a patterned mask layer is first formed on the stacked structure. The mask layer may include an amorphous carbon layer, an anti-reflective coating, and a photoresist layer formed sequentially. The photoresist layer is then patterned, and using the patterned photoresist layer as a mask, a first via 304 is formed vertically through the patterned gate conductor layer 303 and a portion of the depth of the first dielectric layer 301 via a dry etching process. The cross-section of the first via 304 may be circular. After etching, the mask layer can be removed by at least one of the following processes: ashing, wet etching, chemical mechanical polishing, etc.

[0093] Next, as Figure 3B As shown, a gate insulating material layer 305 is formed on the inner wall of the first through hole 304. The material of the gate insulating material layer 305 includes, but is not limited to, silicon oxide. The gate insulating material layer 305 can be formed by deposition methods commonly used in the art, such as chemical vapor deposition, physical vapor deposition (PVD), or atomic layer deposition.

[0094] Next, a first capping layer 306 is formed over the gate insulating material layer 305, the material of the first capping layer 306 including amorphous silicon. In one embodiment, amorphous silicon may be deposited using a plasma-enhanced chemical vapor deposition process.

[0095] Next, as Figure 3C As shown, anisotropic etching is used to form a second via 307. In the orthographic projection of the substrate 300, the second via 307 is located within the first via 304. The second via 307 penetrates the stacked structure and exposes the conductive structure 302. The anisotropic etching does not remove the entire thickness of the portion of the first capping layer 306 located on the sidewall of the first via 304, nor does it remove the portion of the gate insulating material layer 305 located on the sidewall of the first via 304.

[0096] Specifically, the first capping layer 306, the gate insulating material layer 305, and the first dielectric layer 301 located at the bottom of the first via 304 are etched to form a second via 307 exposing the conductive structure 302. Anisotropic etching can be performed using a dry etching process along a direction perpendicular to the substrate 300. During the etching process, the gate insulating material layer 305 and the first capping layer 306 on the sidewalls of the first via 304 are not damaged or are essentially undamaged because they are parallel to the etching direction. The first capping layer 306 further protects the surface of the vertically extending gate insulating material layer 305 from damage during etching, while the first capping layer 306 and the gate insulating layer 305 located at the bottom of the first via 304 are removed because they are perpendicular to the etching direction.

[0097] Next, as Figure 3D As shown, a second capping layer 308 is formed on the inner wall of the second through-hole 307, and the second capping layer 308 comprises amorphous silicon. The second capping layer 308 can be formed using the same process as the first capping layer 306.

[0098] Next, as Figure 3E As shown, an annealing process is performed to crystallize and transform the amorphous silicon in the first capping layer 306 and the second capping layer 308 into polycrystalline silicon, forming a capping material layer 309. The capping material layer 309 includes the annealed first capping layer 306 and the second capping layer 308. The surface of the capping material layer 309 facing the first via 304 and the second via 307 forms a via. The dielectric layer includes the remaining stacked structure and the remaining gate insulating material layer. The capping material layer 309 is connected to the conductive structure 302.

[0099] Specifically, a rapid thermal annealing (RTA) process can be used, in which the temperature is rapidly increased to a range that can induce amorphous silicon crystallization under an inert atmosphere, and then maintained at that temperature for a preset annealing time. During this process, amorphous silicon atoms gain enough energy to rearrange themselves, transforming from a disordered amorphous state to an ordered polycrystalline state, and grains begin to nucleate and grow.

[0100] In this embodiment of the invention, a thicker amorphous silicon layer is deposited first, followed by recrystallization. After recrystallization, a wet etching process can be used to thin the polycrystalline silicon layer. Compared to directly depositing a thinner amorphous silicon layer and then recrystallizing, this improves the film quality of the polycrystalline silicon layer. Specifically, the thicker amorphous silicon layer provides more material volume and more relaxed spatial constraints for grain nucleation and growth, which helps reduce grain boundary density and promotes the formation of larger and higher-quality polycrystalline silicon grains. Furthermore, as... Figure 3G As shown, a thicker amorphous silicon layer can effectively suppress or eliminate discontinuities such as pinholes that are easily generated due to excessively thin films. Figure 1FAs shown in the figure, a dense, uniform and complete initial polycrystalline silicon thin film is formed.

[0101] In this embodiment of the invention, the surface of the cover material layer 309 facing the entire first and second through holes forms a through hole. The through hole includes a first hole 310 and a second hole 311. The second hole 311 is located on the side of the first hole 310 away from the substrate 300, that is, the second hole 311 is located above the first hole 310. The second hole 311 includes a segment of the through hole corresponding to the remaining first cover layer after anisotropic etching. The first hole 310 includes a segment of the through hole located between the second hole 311 and the conductive structure 302. The diameter of the second hole 311 is larger than the diameter of the first hole 310.

[0102] Since the covering material layer 309 in the second hole 311 is obtained by crystallizing the first covering layer 306 and the second covering layer 308, and the covering material layer 309 in the first hole 310 is obtained by crystallizing the second covering layer 308, the thickness of the covering material layer 309 in the second hole 311 is greater than the thickness of the covering material layer 309 in the first hole 310.

[0103] Next, as Figure 3F As shown, the wet etching process of any one of Examples 1 to 3 is performed to thin the cover material layer 309 and form a trench layer. Figure 4 As shown, the thickness of the covering material layer 309 in the first hole 310 and the second hole 311 is gradually reduced from a large difference to a basically the same thickness.

[0104] Furthermore, since the aperture of the first hole 310 is smaller than that of the second hole 311, the diffusion of the etchant and reaction products in the first hole 310 is further restricted, which reduces the degree of thinning of the cover material layer 309 in the first hole 310 and is conducive to the formation of a uniform channel layer.

[0105] Preferably, the wet etching process in Embodiment 3 is performed to thin the cover material layer 309, wherein the number of combined cycles of steps S1 and S2 is set according to the thickness of the cover material layer 309 to be thinned. In one example, the value of N ranges from 10 to 40.

[0106] By using the method in Example 4 to prepare a semiconductor device, the channel layer grain size can meet the electrical requirements, while ensuring that the channel layer at the bottom of the via is not too thin and improving the electrical connection between the channel layer and the conductive structure 302.

[0107] Thus, the process steps of the semiconductor device fabrication method according to the embodiment of the present invention are completed. It is understood that the semiconductor device fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0108] In summary, the method for fabricating the semiconductor device according to embodiments of the present invention is as follows:

[0109] The quality of the cover material layer can be improved by depositing a thicker cover material layer and then thinning it using a wet etching process.

[0110] By controlling the reaction time of the wet etching process to be less than a preset value, the thickness of the portion of the cover material layer located on the inner wall of the second hole can be reduced to be greater than the thickness of the portion located on the inner wall of the first hole. This enables differentiated thinning at different depths of the via, improves the uniformity of the cover material layer thickness, and optimizes the electrical performance and consistency of the semiconductor device.

[0111] By utilizing the principles of self-limiting oxidation and digital etching, high-precision quantitative thinning can be achieved, resulting in excellent on-wafer uniformity and significantly improving the consistency of device performance.

[0112] Compared to dry etching, which is prone to causing damage, or wet etching with a single alkaline solution, which results in rough surfaces, the oxidation etching cycle process used in this embodiment of the invention is gentler and causes less damage to the thin film. Moreover, this principle can be extended to other thin film preparation processes that require precise thinning.

[0113] This invention also provides a semiconductor device, which can be prepared by the methods described in the foregoing embodiments, but is not limited thereto.

[0114] Below, refer to Figure 3F The semiconductor device of the present invention will be described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For a detailed explanation and description, please refer to the description in Embodiment 1.

[0115] Specifically, the semiconductor device in this embodiment of the invention includes:

[0116] The substrate includes a substrate 300 and a dielectric layer located on the substrate 300;

[0117] Through-holes are formed in the dielectric layer and penetrate the dielectric layer in a direction perpendicular to the substrate 300. The through-holes include a first hole 310 and a second hole 311 arranged and connected in a direction perpendicular to the substrate 300. The second hole 311 is located on the side of the first hole 310 away from the substrate 300.

[0118] The substrate also includes a cover material layer 309 that covers the inner wall of the through hole;

[0119] The surface of the covering material layer 309 has a stepped structure located between the first hole 310 and the second hole 311.

[0120] The semiconductor device of the present invention is prepared by the above method and therefore has similar advantages.

[0121] A third aspect of the present invention also provides an electronic device, including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0122] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, navigator, digital photo frame, camera, camcorder, and voice recorder, or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0123] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the substrate comprising a substrate and a dielectric layer located on the substrate; Through-holes are formed in the dielectric layer and penetrate the dielectric layer in a direction perpendicular to the substrate. The through-holes include a first hole and a second hole arranged and connected in a direction perpendicular to the substrate, and the second hole is located on the side of the first hole away from the substrate. The substrate further includes a cover material layer covering the inner wall of the through-hole, the material of the cover material layer including polycrystalline silicon; The cover material layer is thinned using a wet etching process, wherein the wet etching process is configured to control the reaction time to be less than a preset value, such that the portion of the cover material layer located on the inner wall of the second hole is thinned to a thickness greater than the portion of the cover material layer located on the inner wall of the first hole. The method of thinning the cover material layer using a wet etching process includes: S1. A self-limiting oxidant solution is provided from the opening on the side of the through hole away from the substrate, and the self-limiting oxidant solution is brought into contact with the surface of the cover material layer away from the inner wall of the through hole for a first reaction time to perform oxidation treatment and form an oxidized cover material layer. The oxidized cover material layer includes a remaining cover material layer and an oxide material layer located on the surface of the remaining cover material layer away from the inner wall of the through hole. The oxide material layer includes silicon oxide and has a first thickness. The first reaction time is controlled such that the ratio of unsaturated silicon oxide to saturated silicon oxide in the oxide material layer in the first hole is greater than that in the oxide material layer in the second hole. S2. An acidic etchant is provided, and the acidic etchant contacts the surface of the oxidized cover material layer away from the inner wall of the via for a second reaction time to form a thinned cover material layer. The thinned cover material layer includes the remaining cover material layer and a remaining oxide material layer located on the surface of the remaining cover material layer away from the inner wall of the via. The acidic etchant is capable of removing silicon oxide, and the rate of removal of saturated silicon oxide is greater than the rate of removal of unsaturated silicon oxide. The second reaction time is controlled so that the remaining oxide material layer is present in the first hole, and the remaining oxide material layer includes unsaturated silicon oxide. The reaction time includes the first reaction time and the second reaction time.

2. The preparation method according to claim 1, characterized in that, The self-limiting oxidant solution includes O3 water, and the acidic etchant includes hydrofluoric acid solution.

3. The preparation method according to claim 2, characterized in that, The concentration of the O3 water is 10ppm-50ppm, and the first reaction time is 20s-360s; The concentration of the hydrofluoric acid solution is 0.5%wt-5%wt, and the second reaction time is 5s-80s.

4. The preparation method according to claim 1, characterized in that, Repeat steps S1 and S2 in combination for N cycles, where N ≥ 2, until the covering material layer is thinned to a second thickness; In the 2nd to Nth cycles, step S1, which involves contacting the self-limiting oxidant solution with the surface of the covering material layer away from the inner wall of the through hole for a first reaction time to perform oxidation treatment and form an oxidized covering material layer, includes: The self-limiting oxidant solution is brought into contact with the surface of the thinned covering material layer formed in step S2 of the previous cycle away from the inner wall of the through hole for a first reaction time to perform oxidation treatment.

5. The preparation method according to claim 4, characterized in that, The substrate further includes a conductive structure located between the substrate and the dielectric layer, the bottom surface of the first hole exposes the conductive structure, and the cover material layer also covers the bottom surface of the first hole.

6. The preparation method according to claim 5, characterized in that, The substrate includes: The substrate and a conductive structure are provided, wherein the conductive structure is located on the surface of the substrate; A stacked structure is formed on the substrate, the stacked structure including a first dielectric layer and a patterned gate conductor layer stacked sequentially from the substrate, forming a first via through the patterned gate conductor layer, the first via extending to a portion of the depth of the first dielectric layer; A gate insulating material layer and a first capping layer are sequentially formed on the inner wall of the first via. The first capping layer includes amorphous silicon. Anisotropic etching is used to form a second via. On the orthographic projection of the substrate, the second via is located inside the first via. The second via penetrates the stacked structure and exposes the conductive structure. The anisotropic etching does not remove the entire thickness of the portion of the first capping layer located on the sidewall of the first via. The anisotropic etching does not remove the portion of the gate insulating material layer located on the sidewall of the first via. A second capping layer is formed on the inner wall of the second through hole, the second capping layer comprising amorphous silicon; The annealing process causes the amorphous silicon in the first and second capping layers to crystallize and transform into polycrystalline silicon. The cover material layer includes an annealed first cover layer and a second cover layer, and the cover material layer surrounds the entire surface of the first via and the second via to form the via. The dielectric layer includes the remaining stacked structure and the remaining gate insulating material layer.

7. The preparation method according to claim 6, characterized in that, In the step of providing the substrate: The second hole includes a segment of the through hole corresponding to the remaining first capping layer after the anisotropic etching, and the first hole includes a segment of the through hole located between the second hole and the conductive structure; The diameter of the second hole is larger than that of the first hole, and the thickness of the covering material layer in the second hole is greater than that in the first hole.

8. The preparation method according to claim 7, characterized in that, The value of N ranges from 10 to 40.

9. A semiconductor device, characterized in that, The semiconductor device is prepared using the method described in any one of claims 1-8.

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