Transistor and display device including same

Abstract

A transistor and a display device including the same are provided. The display device includes a substrate including an active area and a non-active area. The first transistor is disposed in the active region and includes a first gate electrode, a first a source-drain electrode, a first b source-drain electrode, and a first active layer. The first gate insulating layer is disposed between the first gate electrode and the first active layer. The first gate insulating layer includes a first portion disposed adjacent to an edge outer portion of the first gate electrode but not overlapping the gate electrode, and a second portion disposed to overlap the first gate electrode. And the thickness of the first part is different from that of the second part. By adjusting the thickness of the gate insulating layer, the structure may contribute to controlling the dopant distribution and improving the electrical stability and reliability of the first transistor.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0139703, filed on October 14, 2024, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This disclosure relates to transistors and display devices including such transistors, and more particularly, to transistors that can improve reliability and display devices including such transistors. Background Technology

[0004] Display devices used in various modes and types to display images in televisions (TV), monitors, smartphones, tablet PCs, and laptops.

[0005] The display device includes a display panel comprising a plurality of light-emitting devices for realizing an image and transistors for controlling the operation of each of the light-emitting devices or the operation of a liquid crystal, and fully displays the image to be displayed by the plurality of light-emitting devices or the liquid crystal.

[0006] The display device includes multiple pixels and multiple driving elements and switching elements for driving and controlling the pixels. The driving elements and switching elements can each be configured as transistors, and transistors are widely used in integrated circuits and pixels.

[0007] Recently, various research and development efforts have been underway to improve the performance and reliability of transistors. Summary of the Invention

[0008] This disclosure relates to a transistor structure in which a gate insulating layer has different thicknesses in different regions, including a central region below the gate electrode, an edge adjacent to the gate, and an outer portion. This thickness variation is used to control the dopant implantation depth, allowing the peak dopant concentration to be located within a non-active layer (e.g., a gate insulating layer or a buffer layer). By preventing the peak dopant concentration from entering the channel region, this structure reduces threshold voltage offset and minimizes the reduction in effective channel length due to thermal diffusion.

[0009] This approach is particularly useful for switching transistors with shorter channels, where dopant diffusion has a more significant impact on electrical performance. In contrast, driving transistors with longer channels are less affected and can maintain a uniform gate insulation thickness. The structure allows for selective control of electrical characteristics across different transistor types without requiring additional components or process complexity.

[0010] This configuration allows for the formation of switches and drive transistors using the same materials and process steps, while achieving different electrical profiles through physical design and doping control. This supports improved reliability and lower power consumption in display devices and promotes efficient manufacturing practices that reduce process steps and material usage, thus contributing to environmental and operational advantages.

[0011] For example, embodiments of this disclosure provide a transistor that can improve reliability and a display device including the transistor.

[0012] Embodiments of this disclosure provide a display device in which, when forming a transistor comprising an oxide semiconductor, the reduction of the effective channel length can be prevented, and thus the threshold voltage (Vth) of the transistor can be prevented from shifting in the negative (-) direction in the initial stage.

[0013] Therefore, embodiments of this disclosure provide a transistor and a display device including the transistor, wherein the thickness of the gate insulating layer can be set differently, the peak value of the Gaussian distribution of the dopant can be controlled to be set in a layer different from the active layer, and the length of the effective channel can be prevented from decreasing due to diffusion of the dopant based on heat treatment.

[0014] Therefore, embodiments of this disclosure can be implemented without adding separate components and the thickness of the gate insulating layer can be set differently, and thus the driving stability and reliability of transistors and display devices can be improved and power consumption can be reduced, thereby achieving environmental, social and governance (ESG) goals.

[0015] To achieve these technical effects and other advantages, and for the purposes of this disclosure, as embodied and broadly described herein, the display device includes: a substrate including an active region and an active region; a first transistor disposed in the active region and including a first gate electrode, a first a source-drain electrode, a first b source-drain electrode, and a first active layer; and a first gate insulating layer disposed between the first gate electrode and the first active layer, wherein the thickness of a first portion of the first gate insulating layer that does not overlap with the first gate electrode but is adjacent to the outer edge portion of the first gate electrode is different from the thickness of a second portion that overlaps with the first gate electrode.

[0016] In the first gate insulating layer, the thickness of the third portion disposed outside the first portion and overlapping with the first active layer may be different from the thickness of the first portion.

[0017] The first active layer may include source-drain regions, wherein the dopant is doped in regions that do not overlap with the first gate electrode, and in regions that overlap with the first portion, the peak of the Gaussian distribution of the dopant concentration is set in a layer that may be different from the first active layer.

[0018] The thickness of the first part can be greater than the thickness of the second part, and the thickness of the third part can be less than the thickness of the first part, and the first gate insulating layer can have a peak value of a Gaussian distribution of dopants doped on the first active layer in the first part.

[0019] In the first active layer, the peak value of the Gaussian distribution of the dopant doped in the first active layer can be set at a portion spaced apart from the edge of the first gate electrode.

[0020] The thickness of the first part can be greater than the thickness of the second part, but less than the sum of the thicknesses of the second part and the first gate electrode.

[0021] The display device may further include a first buffer layer between the substrate and the first active layer, wherein the thickness of the first portion may be less than the thickness of the second portion, the thickness of the third portion may be greater than the thickness of the first portion, and the first buffer layer may have a peak value of a Gaussian distribution of dopants doped on the first active layer in the region overlapping with the first portion.

[0022] The thickness of the first part can be less than the thickness of the second part, but can also be greater than 1 / 10 of the thickness of the second part.

[0023] The first active layer may include an oxide semiconductor.

[0024] The display device may further include a second transistor disposed in an active region and including a second gate electrode, a second a source-drain electrode, a second b source-drain electrode, and a second active layer, wherein the length of the channel formed in the first active layer of the first transistor may be shorter than the length of the channel formed in the second active layer of the second transistor.

[0025] The display device may further include a second gate insulating layer disposed between the second gate electrode and the second active layer, wherein the thickness of the portion of the second gate insulating layer disposed outside the second gate electrode and not overlapping with each other may be equal to the thickness of the portion disposed at the portion overlapping with the second gate electrode.

[0026] The location of the maximum peak of the Gaussian distribution of the dopant on the first transistor may be different from the location of the maximum peak of the Gaussian distribution of the dopant on the second transistor.

[0027] The location where the maximum peak is formed in the Gaussian distribution of the dopant on the first transistor can be set in a layer different from the first active layer, and the location where the maximum peak is formed in the Gaussian distribution of the dopant on the second transistor can be set in the second active layer.

[0028] The display device may further include a light-emitting device disposed on a first transistor and a second transistor in an active region, and includes a first electrode, an organic light-emitting layer and a second electrode, and one of the first transistor and the second transistor may be electrically connected to the first electrode.

[0029] In another aspect of this disclosure, the transistor includes: a first active layer comprising an oxide semiconductor material and including a channel region disposed between a first a source-drain region and a first b source-drain region; a gate electrode disposed on the first active layer to overlap with the first channel region; a first a source-drain electrode and a first b source-drain electrode respectively connected to the first a source-drain region and the first b source-drain region; and a first gate insulating layer disposed between the first gate electrode and the first active layer, wherein the thickness of a first portion of the first gate insulating layer that does not overlap with the first gate electrode but is adjacent to the edge of the first gate electrode is different from the thickness of a second portion disposed at the portion that overlaps with the first gate electrode.

[0030] In the first gate insulating layer, the thickness of the third portion disposed outside the first portion and overlapping with the first active layer may be different from the thickness of the first portion.

[0031] The dopant can be doped in the first a source-drain region and the first b source-drain region in the first active layer, and in the region overlapping with the first part, the peak of the Gaussian distribution of the dopant concentration can be set in a layer different from the first active layer.

[0032] The thickness of the first part can be greater than the thickness of the second part, the thickness of the third part can be less than the thickness of the first part, and the first gate insulating layer can have a peak value of a Gaussian distribution of dopants doped on the first active layer in the first part.

[0033] In the first active layer, the peak value of the Gaussian distribution of the dopant doped in the first active layer can be set at a portion spaced apart from the edge of the first gate electrode.

[0034] The transistor may further include a first buffer layer between the substrate and the first active layer, wherein the thickness of the first portion may be less than the thickness of the second portion, the thickness of the third portion may be greater than the thickness of the first portion, and the first buffer layer may have a peak value of a Gaussian distribution of dopants doped on the first active layer in the region overlapping with the first portion. Attached Figure Description

[0035] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0036] Figure 1 These are diagrams used to describe embodiments of the display device applicable to this disclosure;

[0037] Figure 2 It is a diagram illustrating an embodiment of a circuit diagram suitable for a display device according to the present disclosure;

[0038] Figure 3 It is used to describe what is applicable to and Figure 2 A cross-sectional view of the first embodiment of the transistor corresponding to the switching transistor in the diagram;

[0039] Figure 4 It is used to describe what is applicable to and Figure 2 A cross-sectional view of the second embodiment of the transistor corresponding to the switching transistor in the diagram;

[0040] Figure 5 It is used to describe what is applicable to and Figure 2 A cross-sectional view of an embodiment of the second transistor corresponding to the driving transistor in the diagram;

[0041] Figure 6 It is a diagram used to describe the process of forming the channel region of a transistor;

[0042] Figure 7 It is used to describe in reference Figure 5 A diagram illustrating the dopant concentration formed in the second transistor;

[0043] Figure 8 It is used to describe according to the reference Figure 3 A graph showing the dopant concentration formed in the first transistor of the first embodiment described;

[0044] Figure 9 It is used to describe according to the reference Figure 4 A graph showing the dopant concentration formed in the first transistor of the second embodiment described; and

[0045] Figure 10 This is a diagram illustrating an embodiment of a display device that utilizes a first transistor and a second transistor. Detailed Implementation

[0046] In the following text, each embodiment will be described in detail with reference to the accompanying drawings.

[0047] Similar reference numerals denote similar elements. Furthermore, for ease of description, the thickness, scale, and dimensions of each element described herein are shown as partially enlarged or reduced. For ease of description, the scale of each element shown in the accompanying drawings of this disclosure may differ from the actual scale, but is not limited to the scale shown in the drawings.

[0048] In this disclosure, when any element (or region, layer, part, etc.) is described as “on,” “connected,” or “coupled,” this may indicate that the arbitrary element can be directly connected to / coupled to another element, or that a third element may be placed therein.

[0049] For further clarification, as used herein, the term "connection" is intended to have the broadest possible meaning. Specifically, the phrase "A connected to B" encompasses both direct connections (where no intermediate parts or elements exist) and indirect connections (where one or more intermediate parts or elements exist between A and B). In other words, "A connected to B" includes both direct physical or electrical coupling and indirect coupling achieved through one or more intermediate parts. Unless otherwise expressly stated, these terms do not require direct physical or electrical contact. The terms "coupled" and "contact" should be interpreted in the same manner.

[0050] The term "and / or" can include all of one or more combinations that can be defined by the relevant elements.

[0051] Terms such as first and second may be used to describe various elements, but elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the spirit and scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Singular terms may include plural forms unless otherwise indicated.

[0052] The terms “below,” “under,” “above,” and “over” can be used to describe the relationship between elements shown in the accompanying drawings. These terms can be relative concepts and can be described relative to the direction shown in the drawings. For example, one or more other elements may be positioned between two elements unless “only” or “directly” is used. The spatially relative terms “below,” “under,” “down,” “above,” and “over” can be used herein to readily describe the relationship of one or more devices or elements as shown in the accompanying drawings to other devices or elements. Thus, for example, “below” and “down” can be relative to a first element as “above” and “over”.

[0053] It should be understood that spatial relative terms are terms that include not only the orientations shown in the figures but also the different orientations of the elements in use or operation. For example, if the device in the figures is flipped, an element described as being "below" or "under" other elements can be placed "above" other elements. Thus, the exemplary term "below" can include both "below" and "above" orientations. Similarly, the exemplary terms "above" or "on" can include both "above" and "below" orientations.

[0054] It should be understood that "includes", "contains", "includes" or "comprises" means that an attribute, area, fixed number, step, process, element and / or component is specified, but does not exclude other attributes, areas, fixed number, steps, processes, elements and / or components.

[0055] Features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate with and be technically driven by each other in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0056] In the following description, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0057] Figure 1 These are diagrams used to describe embodiments of the display device applicable to this disclosure, and Figure 2 This is a diagram illustrating an embodiment of a circuit diagram suitable for a display device according to the present disclosure.

[0058] Reference Figure 1 and Figure 2 The display device according to the embodiments of the present disclosure may include a display panel 10, and the display panel 10 includes an active region AA and an inactive region NA.

[0059] The active region AA is the area where the image is displayed. Multiple subpixels SP can be set within the active region AA, and the active region AA can display the image using multiple subpixels SP. The area with multiple subpixels SP can be the active region AA, and the area other than the active region AA can be the non-active region NA.

[0060] The non-active region NA can be set in the edge region surrounding the active region AA of the displayed image. At least one driver for driving multiple sub-pixels SP can be set in the non-active region NA.

[0061] Various additional elements can also be set in the non-active region NA to drive the sub-pixel SP of the active region AA.

[0062] For example, such as Figure 2 As shown in (a) or (b), at least one sub-pixel SP among a plurality of pixels may include a first transistor TR1, a second transistor TR2, a capacitor Cst, and a light-emitting device OLED.

[0063] For example, the first transistor TR1 can be a switching transistor, and the second transistor TR2 can be a driving transistor.

[0064] The first electrode (e.g., drain electrode) of the first transistor TR1 can be electrically connected to the data line DL, the second electrode (e.g., source electrode) of the first transistor TR1 can be electrically connected to the first node N1, and the gate electrode of the first transistor TR1 can be electrically connected to the gate line GL. The first transistor TR1 can transmit a data signal supplied through the data line DL to the first node N1 in response to a scan signal supplied through the gate line GL.

[0065] The capacitor Cst can be electrically connected to the first node N1 and can be charged using the voltage applied to the first node N1.

[0066] The first electrode (e.g., drain electrode) of the second transistor TR2 can be supplied with a high-level driving voltage EVDD, and the second electrode (e.g., source electrode) of the second transistor TR2 can be electrically connected to the first electrode of the light-emitting device OLED. The amount of driving current flowing in the light-emitting device OLED can be controlled based on the voltage applied to the gate electrode of the second transistor TR2.

[0067] The active layer of the first transistor TR1 and / or the second transistor TR2 may include oxides such as indium gallium zinc oxide (IGZO), but is not limited thereto.

[0068] OLEDs (Optical Display Panels) emit light corresponding to the driving current. OLEDs can emit light corresponding to one of the colors red, green, blue, and white.

[0069] An OLED (Optical Display Panel) device may include an anode electrode, an emitting layer disposed on the anode electrode, and a cathode electrode supplying a common voltage. The emitting layer may be configured to emit the same color of light, such as white light, for each pixel, or it may be configured to emit different colors of light, such as red, green, or blue light, for each sub-pixel (SP).

[0070] The light-emitting device OLED can be a top-emitting diode or a bottom-emitting diode.

[0071] exist Figure 2In (a), for example, a case is shown where the second transistor TR2 corresponding to the driving transistor is directly connected to the light-emitting device OLED, but the present disclosure is not limited thereto, and as shown in (a), Figure 2 As shown in (b), the second transistor TR2 can be connected to the light-emitting device OLED via the third transistor TR3, which acts as a switching transistor.

[0072] In detail, as in Figure 2 In (b), the third transistor TR3 can be disposed between the second transistor TR2 and the light-emitting device OLED. The first electrode of the third transistor TR3 can be connected to the second electrode of the second transistor TR2, and the second electrode of the third transistor TR3 can be electrically connected to the first electrode of the light-emitting device OLED. In response to the emission signal EM applied to the gate electrode of the second transistor TR2, the third transistor TR3 can control the on / off state of the driving current applied from the second transistor TR2 to the light-emitting device OLED.

[0073] Furthermore, despite Figure 2 Not shown in (a) and (b), but a compensation circuit for compensating the threshold voltage of the second transistor TR2 corresponding to the driving transistor may also be included in the sub-pixel SP. The compensation circuit may include at least one transistor connected to the second transistor TR2 and may be disposed in the sub-pixel SP.

[0074] Depending on the configuration type, the compensation circuit can have a 3T1C structure in which three transistors and one capacitor Cst are included in the sub-pixel SP, or a 4T2C structure in which four transistors and two capacitors Cst are included in the sub-pixel SP, or various structures such as 5T2C, 6T1C, 6T2C, 7T1C and 7T2C.

[0075] In a sub-pixel SP, the channel length can be different, or the thickness of the portion of the gate insulating layer disposed between the gate electrode and the active layer can be different, because the purposes of controlling the second transistor TR2, which acts as a driving transistor, and the first and third transistors, which act as switching transistors, are different. This will be described in detail below.

[0076] Figure 3 It is used to describe applicable Figure 2 A cross-sectional view of a first embodiment of a transistor corresponding to a switching transistor. Figure 4 It is used to describe applicable Figure 2 A cross-sectional view of a second embodiment of the transistor corresponding to the switching transistor, and... Figure 5 It is used to describe applicable Figure 2 A cross-sectional view of an embodiment of the second transistor corresponding to the driving transistor.

[0077] Figure 3 and Figure 4 The transistor configuration shown can be applied to switching transistors such as the first transistor TR1 or the third transistor TR3. The first transistor TR1 or the third transistor TR3, as switching transistors, may include a first gate electrode G1, a first active layer ACT1, a first a source-drain electrode SD1a, a first b source-drain electrode SD1b, a first gate insulating layer GI1, a first interlayer insulating layer ILD1, and a first buffer layer BUF1 disposed in the active region AA.

[0078] The first active layer ACT1 may include an oxide semiconductor material such as IGZO. The first active layer ACT1 may include a first channel region AC1, a first a source-drain region ASD1a, and a first b source-drain region ASD1b, wherein the first channel region AC1 is disposed between the first a source-drain region ASD1a and the first b source-drain region ASD1b.

[0079] The first channel region AC1 can be located at the portion overlapping with the first gate electrode G1, and the first a source-drain region ASD1a and the first b source-drain region ASD1b can be located in the region outside the first channel region AC1 that does not overlap with the first gate electrode G1.

[0080] The first channel region AC1 may have a doping concentration that is relatively lower than that of each of the first a source-drain regions ASD1a and the first b source-drain regions ASD1b, and may have a conductivity corresponding to the voltage applied to the first gate electrode G1, and may form a channel that enables carrier movement based on the application of voltage.

[0081] The doping concentration of the first a-source-drain region ASD1a and the first b-source-drain region ASD1b can be relatively higher than that of the first channel region AC1, and therefore each can be formed with a high conductivity conductive region.

[0082] The first channel region AC1 may have a first channel length LC1 between the first a source-drain region ASD1a and the first b source-drain region ASD1b, and may have a length less than the second channel length LC2 of the second channel region AC2 of the second transistor TR2 described below.

[0083] The first gate electrode G1 may be disposed separately from the first active layer ACT1 and may overlap with the first channel region AC1. The first gate electrode G1 may include a conductive material. For example, the first gate electrode G1 may include metals such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). The first gate electrode G1 may be insulated from the first active layer ACT1 through a first gate insulating layer GI1.

[0084] A first gate insulating layer GI1 may be disposed between the first gate electrode G1 and the first active layer ACT1 for insulating between the first gate electrode G1 and the first active layer ACT1, and may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy). For example, SiOx may include silicon dioxide (SiO2).

[0085] A first interlayer insulating layer ILD1 may be disposed on the first gate electrode G1. The first interlayer insulating layer ILD1 may extend to the outer portion of the first gate electrode G1. The side surface of the first gate electrode G1 may be covered by the first interlayer insulating layer ILD1. The first interlayer insulating layer ILD1 may extend along the first gate insulating layer GI1. The first interlayer insulating layer ILD1 may include an insulating material. For example, the first interlayer insulating layer ILD1 may include SiOx or SiOxNy.

[0086] Each of the first a-source-drain electrode SD1a and the first b-source-drain electrode SD1b is disposed on the first interlayer insulating layer ILD1, and the first a-source-drain electrode SD1a and the first b-source-drain electrode SD1b can penetrate a portion of the first interlayer insulating layer ILD1 and can contact the first a-source-drain region ASD1a and the first b-source-drain region ASD1b, respectively. Each of the first a-source-drain electrode SD1a and the first b-source-drain electrode SD1b can be insulated from the first gate electrode G1 through the first interlayer insulating layer ILD1.

[0087] Each of the first a source-drain electrode SD1a and the first b source-drain electrode SD1b may include at least one metal such as Al, Cr, Cu, Ti, Mo and W, and may include a material different from the material of the first gate electrode G1.

[0088] The first buffer layer BUF1 can be disposed below the first active layer ACT1, and for example, it can be disposed on the substrate (see...). Figure 10 Between the 100th layer and the first active layer ACT1. The first buffer layer BUF1 can prevent contamination caused by the substrate during the formation of the drive circuit.

[0089] The first buffer layer BUF1 may include an insulating material. For example, the first buffer layer BUF1 may include an inorganic insulating material such as SiOx or SiNx. The first buffer layer BUF1 may have a multilayer structure. For example, the first buffer layer BUF1 may have a multilayer stacked structure comprising different materials.

[0090] like Figure 3 and Figure 4As shown, the thickness T1a or T1b of the first portion GI1a and the thickness T2 of the second portion GI1b of the first gate insulating layer GI1 can be set differently, and the thickness of the third portion GI1c and the thickness T1a or T1b of the first portion GI1a can be set differently.

[0091] For example, in the first gate insulating layer GI1 according to the present disclosure, the thickness T1a or T1b of the first portion GI1a may be greater than or less than the thickness T2 of the second portion GI1b, and the thickness of the third portion GI1c may be equal to the thickness T2 of the second portion GI1b.

[0092] In the first gate insulating layer GI1, the first portion GI1a may be a portion that does not overlap with the first gate electrode G1 but is adjacent to the outer edge portion EOP of the first gate electrode G1 (e.g., in a plan view), the second portion GI1b may be a portion disposed at the portion that overlaps with the first gate electrode G1 (e.g., in a plan view), and the third portion GI1c may be a portion disposed outside the first portion GI1a in the first gate insulating layer GI1 and overlapping with the first active layer ACT1.

[0093] For example, such as Figure 3 As shown in this disclosure, in the first gate insulating layer GI1, the thickness T1a of the first portion GI1a can be greater than the thickness T2 of the second portion GI1b. For example, in the first gate insulating layer GI1, the thickness T1a of the first portion GI1a can be greater than the thickness T2 of the second portion GI1b, and can be less than the sum of the thickness T2 of the second portion GI1b and the thickness of the first gate electrode G1.

[0094] Here, as in Figure 3 In the first gate insulating layer GI1, the thickness of the third portion GI1c, which is disposed outside the first portion GI1a having a thickness T1a and overlaps with the first active layer ACT1, may be different from the thickness T1a of the first portion GI1a, and may, for example, be equal to the thickness T2 of the second portion GI1b.

[0095] Alternative locations, such as Figure 4 As shown, in the first gate insulating layer GI1, the thickness T1b of the first portion GI1a can be less than the thickness T2 of the second portion GI1b. For example, the thickness T1b of the first portion GI1a can be greater than 1 / 10 of the thickness T2 of the second portion GI1b, and can be less than the thickness T2 of the second portion GI1b.

[0096] Here, as in Figure 4In the first gate insulating layer GI1, the thickness of the third portion GI1c, which is disposed outside the first portion GI1a having a thickness T1b and overlaps with the first active layer ACT1, may be different from the thickness T1b of the first portion GI1a, and may, for example, be equal to the thickness T2 of the second portion GI1b.

[0097] in Figure 3 and Figure 4 The configuration in which the thickness T1a or T1b of the first portion GI1a in the first gate insulating layer GI1 of the transistor shown is greater than or less than the thickness T2 of the second portion GI1b can be applied to a switching transistor.

[0098] Therefore, it can be applied to it. Figure 2 The first transistor TR1 in (a) and Figure 2 The configuration in (b) where the thickness T1a or T1b of the first portion GI1a of the first gate insulating layer GI1 included in at least one of the first transistor TR1 and the third transistor TR3 is greater than or less than the thickness T2 of the second portion GI1b.

[0099] Alternative locations, and Figure 2 Unlike the illustration, when the sub-pixel SP includes other switching transistors besides the first transistor TR1 and the third transistor TR3, the configuration where the thickness T1a or T1b of the first part GI1a is greater than or less than the thickness T2 of the second part GI1b can be applied to the other switching transistors.

[0100] Figure 5 The transistor shown can be used to drive transistors. Therefore, Figure 5 The transistor shown can be applied to Figure 2 The second transistor TR2 in (a) corresponds to the driving transistor.

[0101] like Figure 5 As shown, the second transistor TR2, which serves as the driving transistor, can supply a driving current corresponding to the data signal to the light-emitting device OLED, and may include a second gate electrode G2, a second active layer ACT2, a second a source-drain electrode SD2a, a second b source-drain electrode SD2b, a second gate insulating layer GI2, a second interlayer insulating layer ILD2, a second buffer layer BUF2, and a light blocking pattern LS disposed in the active region AA.

[0102] The second active layer ACT2 may include an oxide semiconductor material such as IGZO. Alternatively, unlike the first active layer ACT1, the second active layer ACT2 may include low-temperature polycrystalline silicon (LTPS).

[0103] The second active layer ACT2 may include a second channel region AC2, a second a source-drain region ASD2a, and a second b source-drain region ASD2b, wherein the second channel region AC2 is disposed between the second a source-drain region ASD2a and the second b source-drain region ASD2b. The second channel region AC2 may be disposed at the portion overlapping with the second gate electrode G2, and the second a source-drain region ASD2a and the second b source-drain region ASD2b may be disposed in a region outside the second channel region AC2 that does not overlap with the second gate electrode G2.

[0104] The second channel region AC2 may have a doping concentration that is relatively lower than that of each of the second a source-drain region ASD2a and the second b source-drain region ASD2b, and may have a conductivity corresponding to the voltage applied to the second gate electrode G2.

[0105] The doping concentration of the second a-source-drain region ASD2a and the second b-source-drain region ASD2b can be relatively higher than that of the second channel region AC2, and thus can be formed independently of conductive regions with high conductivity.

[0106] The second channel length LC2 of the second channel region AC2 can be longer than the first channel length LC1 of the first channel region AC1. That is, the second channel length LC2 between the second a source-drain region ASD2a and the second b source-drain region ASD2b can be longer than the first channel length LC1 between the first a source-drain region ASD1a and the first b source-drain region ASD1b.

[0107] The second gate electrode G2 may be disposed separately from the second active layer ACT2 and may overlap with the second channel region AC2. The second gate electrode G2 may include a conductive material. For example, the second gate electrode G2 may include metals such as Al, Cr, Cu, Ti, Mo, and W.

[0108] The second gate insulating layer GI2 can be disposed between the second gate electrode G2 and the second active layer ACT2, and can insulate the second gate electrode G2 from the second active layer ACT2. The second gate insulating layer GI2 may include at least one of SiOx, SiNx, and SiOxNy. For example, SiOx may include SiO2.

[0109] Furthermore, the second gate insulating layer GI2 may comprise the same material as the first gate insulating layer GI1 to simplify the manufacturing process. However, this disclosure is not limited thereto.

[0110] A second interlayer insulating layer (ILD2) may be disposed on the second gate electrode G2. The second interlayer insulating layer (ILD2) may extend to the outer portion of the second gate electrode G2. The side surface of the second gate electrode G2 may be covered by the second interlayer insulating layer (ILD2). The second interlayer insulating layer (ILD2) may extend along the second gate insulating layer G12. The second interlayer insulating layer (ILD2) may include an insulating material. For example, the second interlayer insulating layer (ILD2) may include SiOx or SiOxNy.

[0111] Furthermore, the second interlayer insulating layer ILD2 may comprise the same material as the first interlayer insulating layer ILD1 to simplify the manufacturing process. However, this disclosure is not limited thereto.

[0112] Each of the second a-source-drain electrode SD2a and the second b-source-drain electrode SD2b may be disposed on the second interlayer insulating layer ILD2, and the second a-source-drain electrode SD2a and the second b-source-drain electrode SD2b may penetrate a portion of the second interlayer insulating layer ILD2 and may respectively contact the second a-source-drain region ASD2a and the second b-source-drain region ASD2b. Each of the second a-source-drain electrode SD2a and the second b-source-drain electrode SD2b may be insulated from the second gate electrode G2 through the second interlayer insulating layer ILD2.

[0113] Each of the second a source-drain electrode SD2a and the second b source-drain electrode SD2b may include at least one metal such as Al, Cr, Cu, Ti, Mo and W, and may include a material different from the material of the second gate electrode G2.

[0114] The second buffer layer BUF2 can be disposed below the second active layer ACT2, and for example, it can be disposed between the substrate and the second active layer ACT2. The second buffer layer BUF2 can prevent contamination caused by the substrate during the formation of the drive circuit.

[0115] The second buffer layer BUF2 may include an insulating material. For example, the second buffer layer BUF2 may include an inorganic insulating material such as SiOx or SiNx. The second buffer layer BUF2 may have a multilayer structure. For example, the second buffer layer BUF2 may have a multilayer structure including a second a buffer layer BUF2a and a second b buffer layer BUF2b.

[0116] The light-blocking pattern LS can be disposed separately from the second active layer ACT2 in the second buffer layer BUF2. For example, the light-blocking pattern LS can be disposed between the second a buffer layer BUF2a and the second b buffer layer BUF2b. The light-blocking pattern LS can block external light that passes through the substrate and travels in parallel to the second active layer ACT2, and thus can stabilize the driving characteristics of the second transistor TR2.

[0117] The light blocking pattern LS can have a larger size than the second active layer ACT2. At least a portion of the light blocking pattern LS can overlap with the second active layer ACT2, and the light blocking pattern LS can be electrically connected to the second active layer ACT2 via one of the second a source-drain electrodes SD2a and the second b source-drain electrodes SD2b.

[0118] The light-blocking pattern LS may include a conductive material, and may include metals such as Al, Cr, Cu, Ti, Mo and W.

[0119] In the second gate insulating layer GI2, which serves as the driving transistor TR2, the thickness T3a of the portion GI2a that is configured not to overlap with the outer edge portion EPO of the second gate electrode G2 but to overlap with the second active layer ACT2 can be equal to the thickness T3b of the portion GI2b that overlaps with the second gate electrode G2 (for example, as can be seen in the plan view).

[0120] Unlike the first transistor TR1 and the third transistor TR3, in the second gate insulating layer GI2 of the second transistor TR2, the portion GI2a that does not overlap with the second gate electrode G2 but overlaps with the second active layer ACT2 may not have a step height of thickness.

[0121] As in Figures 3 to 5 In this embodiment of the present disclosure, the display device can be designed in a free form such that the thickness of the first gate insulating layer GI1 has a stepped height in the first transistor TR1 or the third transistor TR3, the channel length of the first transistor TR1 or the third transistor TR3 is relatively smaller than that of the second transistor TR2, and therefore the thickness of the first gate insulating layer GI1 is characterized in that the second portion GI1b overlapping with the first gate electrode G1 and the first portion GI1a adjacent to the outer edge portion of the first gate electrode G1 have at least different thicknesses.

[0122] In detail, as in Figure 3 In the first gate insulating layer GI1 of the first transistor TR1 or the third transistor TR3, the thickness T1a of the first part GI1a, which is the part closest to the edge of the first gate electrode G1, can be greater than the thickness T2 of the second part GI1b, and the thickness of the third part GI1c can be different from the thickness T1a of the first part GI1a.

[0123] In addition, Figure 3 In the first gate insulating layer GI1, the thickness of the third portion GI1c disposed outside the first portion GI1a can be less than the thickness T1a of the first portion GI1a. For example, in Figure 3In the first gate insulating layer GI1, the thickness of the third part GI1c can be equal to the thickness T2 of the second part GI1b.

[0124] Alternative locations, such as in Figure 4 In the first transistor TR1 or the third transistor TR3, the thickness T1b of the first portion GI1a of the first gate insulating layer GI1 can be less than the thickness T2 of the second portion GI1b.

[0125] In addition, Figure 4 In the first gate insulating layer GI1, the thickness of the third portion GI1c disposed outside the first portion GI1a can be greater than the thickness T1b of the first portion GI1a. For example, in the first gate insulating layer GI1, the thickness of the third portion GI1c can be equal to the thickness T2 of the second portion GI1b. As described above, the first transistor TR1 or the third transistor TR3 can prevent the following phenomenon: since the peaks of the Gaussian distribution representing the ion doping concentration are set in a layer different from the first active layer ACT1, ion diffusion occurs in the portions where the Gaussian distribution peaks appear, and thus the effective channel narrows. Therefore, the operational reliability of the switching transistor can be further enhanced.

[0126] In the first gate insulating layer GI1, a first portion GI1a with different thicknesses T1a and T1b can be disposed in the region of the first gate insulating layer GI1 that overlaps with the first active layer ACT1, at the outermost portion closest to the edge of the gate electrode G1. Therefore, it is possible to prevent a reduction in the length of the channel formed in the first active layer ACT1 that overlaps with the second portion GI1b of the first gate insulating layer GI1. In the first transistor TR1 or the third transistor TR3, the first portion GI1a of the first gate insulating layer GI1 closest to the edge of the gate electrode G1 can have a thickness T1a that is thicker than the thickness T2 of the second portion GI1b.

[0127] In embodiments of this disclosure, the thickness T1a or T1b of the first portion GI1a of the first gate insulating layer GI1 can be different from the thickness T2 of the second portion GI1b, and thus can prevent the effective channel from being narrower than the designed length, thereby further enhancing the operational reliability of the switching transistor.

[0128] This will refer to Figures 6 to 9 To provide a more detailed description.

[0129] Figure 6 It is a diagram used to describe the process of forming the channel region of a transistor. Figure 7 It is used to describe in reference Figure 5 A graph depicting the dopant concentration formed in the second transistor. Figure 8 It is used to describe according to the reference Figure 3A graph showing the dopant concentration formed in the first transistor of the first embodiment described, and Figure 9 It is used to describe according to the reference Figure 4 A graph showing the dopant concentration formed in the first transistor of the second embodiment described.

[0130] In detail, Figure 6 (a) is a diagram illustrating the conductivity provision process of doping ions on the deposited layer DL in a state where the buffer layer BUF, the deposited layer DL, and the gate insulating layer GI are stacked in sequence, and Figure 6 (b) is a diagram used to describe the channel formation process of forming channels through a heat treatment process.

[0131] The deposition layer DL can provide conductivity and channel formation processes as referenced above. Figures 3 to 5 The formation of the active layer is described. Figure 6 The conductivity provisioning process and channel formation process can be applied to all of the switching transistors and driving transistors.

[0132] exist Figure 6 In (a), the structure in which the gate electrode G is located is omitted, and only the deposited layer is shown, but as in Figure 6 In (b), the conductivity provisioning process can be performed while the gate electrode G is formed therein. Figure 6 In this process, the deposited layer DL may include an oxide semiconductor material. For example, the deposited layer DL may include an oxide semiconductor material such as IGZO.

[0133] With a gate insulating layer GI containing hydrogen present, boron ions B are implanted into the location where the source-drain region of the deposited layer DL is to be formed, for example, using an ion implantation device (not shown). Figure 6 As shown in (a), boron ions B can collide with oxygen O bonded to the metal material M, and thus the bond MO between the metal and oxygen can be broken.

[0134] Metallic material M whose bonds with oxygen O have broken can form oxygen voids Vo, and boron ions B can bond to the broken oxygen O, thus preventing the rebonding of metal and oxygen MO in the deposited layer DL.

[0135] As in Figure 6 In (a), where oxygen voids Vo are formed at the location where the source-drain region of the deposited layer DL is to be formed, hydrogen H migrating from the gate insulating layer GI can bond to the oxygen voids Vo of the deposited layer DL and can diffuse in the deposited layer DL through a thermal processing process.

[0136] Deposition layer DL can be passed Figure 6The conductivity provisioning process and channel formation process are formed by the active layer ACT of the transistor. That is, the outer portions of the two edges of the gate electrode G in the deposition layer DL can be formed by the source-drain region ASD with a high boron dopant concentration, and the portion of the source-drain region ASD that overlaps with the gate electrode G can be formed by the channel region AC with a relatively low boron dopant concentration.

[0137] At this moment, as if in Figure 6 In (a), during ion implantation, the dopant can be implanted at a slight angle, rather than in a precise vertical direction, and as in Figure 6 In (b), oxygen voids Vo can be partially formed in the portion of the gate electrode G that overlaps with the two edges.

[0138] Therefore, as in Figure 6 In (b), based on the thermal treatment process, hydrogen can bond to the oxygen voids Vo formed in the two edges of the gate electrode G, and can travel from the two edges of the channel region AC in the direction of the center of the channel region AC, and thus, an offset region ΔL (not shown) in which the concentration of dopant gradually decreases can be formed.

[0139] At this point, the ion implantation device can control the accelerating voltage to control the projection distance of the dopant, resulting in a high dopant concentration in the source-drain region ASD. Furthermore, the projection distance of the dopant through the ion implantation device can vary based on the thickness of the gate insulating layer GI disposed on the active layer. The active layer of each of the driving transistor and the switching transistor can be referenced above. Figure 6 The described conductivity provides the process and the channel formation process.

[0140] Here, the length of the channel region can vary based on the length of the offset region ΔL, and the length of the offset region ΔL can vary based on the concentration of dopant doped on the active layer. The concentration of dopant doped on the active layer can vary based on the distribution of dopant doped on the deposited layer DL, and the distribution of dopant can vary based on the projected distance of the dopant implanted during ion implantation.

[0141] In this disclosure, based on such features, a method can be proposed to control the distribution of dopants by changing the thickness of the gate insulating layer, and thus the first channel length LC1 of the switching transistors such as the first transistor TR1 and the third transistor TR3 is equal to the designed length. Figure 7 It is used to describe in reference Figure 5 A graph depicting the dopant concentration formed in the second transistor. Figure 8 It is used to describe according to the reference Figure 3 A graph showing the dopant concentration formed in the first transistor of the first embodiment described, and Figure 9It is used to describe according to the reference Figure 4 A graph showing the dopant concentration formed in the first transistor of the second embodiment described.

[0142] exist Figures 7 to 9 In each of the diagrams, (a) shows the cross-sectional structure of the transistor excluding the source-drain electrodes, and (b) is a Gaussian distribution of dopants injected into the gate insulating layer, active layer, and buffer layer included in the transistor shown in (a). One axis DC represents the dopant concentration DC, and another axis z intersecting this axis represents the location of the gate insulating layer, active layer, and buffer layer.

[0143] like Figure 7 As shown, a driving transistor such as the second transistor TR2 can have a second channel length LC2 that is relatively longer than that of a switching transistor such as the first transistor TR1 and the third transistor TR3.

[0144] In having as in Figure 7 In the second transistor TR2, which has a relatively long second channel length LC2, the remaining space for forming the channel allows for sufficient formation of the desired channel length even when dopant distribution is formed in the second a-source-drain region ASD2a and the second b-source-drain region ASD2b of the second active layer ACT2. Furthermore, the second transistor TR2 can operate at the desired threshold voltage. In other words, when doping with dopant using the second gate electrode G2 as a mask, the overlap width between the second gate electrode G2 and the second active layer ACT2 can be relatively long. Therefore, regardless of the extent to which dopant diffuses from the edge of the second gate electrode G2 into the inner region of the second active layer ACT2, the effective channel length can be almost not reduced or can be reduced due to the small diffusion across the width of the second gate electrode G2.

[0145] Therefore, it is not necessary to form the second transistor TR2 with different thicknesses of the first portion GI2a and the second portion GI2b of the second gate insulating layer GI2, and as in Figure 7 In (a), the thickness T3a of the first portion GI2a, which is configured not to overlap with the outer edge portion of the second gate electrode G2, in the second gate insulating layer GI2 can be equal to the thickness T3b of the second portion GI2b, which is disposed at the portion overlapping with the second gate electrode G2.

[0146] During the ion implantation process to form the second transistor TR2, the projection distance RP2 of the ions can be controlled, so that the Gaussian distribution of the dopant has a peak Pd in ​​the second active layer ACT2. Therefore, as in Figure 7In (b), the position of the peak Pd formed in the Gaussian distribution of the dopant doped on the second transistor TR2 can be in the second a source-drain region ASD2a and the second b source-drain region ASD2b of the second active layer ACT2, and the dopant concentration in the second gate insulating layer GI2 or the second buffer layer BUF2 can have a lower dopant concentration than the dopant concentration in each of the second a source-drain region ASD2a and the second b source-drain region ASD2b.

[0147] On the other hand, switching transistors such as the first transistor TR1 and the third transistor TR3 can have a relatively short first channel length LC1. For example, in the first transistor TR1 and the third transistor TR3, when the offset region ΔL varies with dopant diffusion in the shorter first channel length LC1, the effective channel can be reduced, and the rate of change of the offset region ΔL with respect to the designed first channel length LC1 (ΔL / LC1) can be increased. Furthermore, in the driving transistor with a longer channel length, the rate of change of the offset region ΔL with respect to the second channel length LC2 (ΔL / LC2) can be increased. Therefore, the threshold voltage Vth of the switching transistor tends to shift in the negative (-) direction due to the effect of dopant diffusion more than that of the driving transistor. Moreover, when the threshold voltage shifts in the negative (-) direction, the turn-off current can increase, and consequently, the operational reliability of the transistor can decrease. In other words, when the actual channel length differs from the designed channel length, the threshold voltage Vth of the transistor can vary, and consequently, the operational reliability of the transistor can decrease.

[0148] Furthermore, when the active layer comprises an oxide semiconductor material, the active layer can be rich in indium (In), and therefore, oxygen voids Vo can be easily formed when dopants are implanted, thereby facilitating the diffusion of conductive regions.

[0149] Based on this, the present disclosure can control the dopant distribution in the device so that the actual channel length formed in the switching transistor is maximized to be equal to the designed channel length.

[0150] Therefore, in this disclosure, the position of the peak of the Gaussian distribution of the dopant on the first transistor TR1 may be different from the position of the peak of the Gaussian distribution of the dopant on the second transistor TR2.

[0151] Specifically, the peak value formed in the Gaussian distribution of the dopant on the first transistor TR1 can be in a film or layer different from the first active layer ACT1, and the peak value Pd formed in the Gaussian distribution of the dopant on the second transistor TR2 can be in the second active layer ACT2.

[0152] In other words, in this disclosure, the thickness T1a or T1b of the first portion GI1a of the first gate insulating layer GI1 of the switching transistors such as the first transistor TR1 and the third transistor TR3 can be different from the thickness T2 of the second portion GI1b, and the thickness of the third portion GI1c can be different from the thickness T1a or T1b of the first portion GI1a. Therefore, the projection distance of the dopant can be adjusted to be binary. Thus, the dopant distribution in the device can be controlled, and consequently, the actual channel length formed in the switching transistor can be maximized to be equal to the designed channel length.

[0153] As described above, the first portion GI1a of the first gate insulating layer GI1 can represent the portion that does not overlap with the first gate electrode G1 but is closest to the outer edge of the first gate electrode G1, the second portion GI1b can represent the portion that overlaps with the first gate electrode G1, and the third portion GI1c can represent the portion disposed outside the first portion GI1a in the first gate insulating layer GI1 and overlapping with the first active layer ACT1.

[0154] In detail, as in Figure 8 In the first embodiment of the first transistor TR1 shown, the thickness T1a of the first portion GI1a of the first gate insulating layer GI1 can be greater than the thickness T2 of the second portion GI1b. Furthermore, as referred to above... Figure 3 As described, the thickness of the third portion GI1c in the first gate insulating layer GI1 can be less than the thickness T1a of the first portion GI1a, and for example, can be equal to the thickness T2 of the second portion GI1b.

[0155] Therefore, as Figure 8 As shown, during ion implantation, the present disclosure can perform control such that the ion projection distances of the first and second portions are binarized into RP1a and RP1b.

[0156] In other words, the ion projection distance RP1b can be controlled so that the implanted ions remain in the first gate insulating layer GI1 based on the thickness T1a of the first part GI1a, which is relatively larger than the thickness of the third part GI1c. In the third part GI1c, the ion projection distance RP1a can be controlled so that the implanted ions remain in the first active layer ACT1 based on the thickness T1a of the first part GI1a, which is relatively smaller than the thickness of the first part GI1a.

[0157] Therefore, in the region overlapping with the first part GI1a, the peak of the Gaussian distribution of the doped dopant can be found in the first gate insulating layer GI1, which is a layer different from the first active layer ACT1.

[0158] In detail, the first gate insulating layer GI1 may have a peak value Ps2 of a Gaussian distribution of dopant on the first active layer ACT1 in the first portion GI1a, and the first active layer ACT1 may have a peak value Ps1 of a Gaussian distribution of dopant on the first active layer ACT1 in the portion of the first portion GI1a spaced apart from the edge of the first gate electrode G1.

[0159] Therefore, in the region where the first active layer ACT1 overlaps with the first portion GI1a of the first gate insulating layer GI1, the dopant distribution can be controlled so that the dopant concentration is lower than the concentration of the dopant doped on the first gate insulating layer GI1.

[0160] In addition, such as in Figure 9 In the second embodiment of the first transistor TR1 shown, the thickness T1b of the first portion GI1a of the first gate insulating layer GI1 can be less than the thickness T2 of the second portion GI1b, and the thickness of the third portion GI1c can be greater than the thickness T1b of the first portion GI1a. Furthermore, as referred to above... Figure 4 The thickness of the third portion GI1c, which is disposed outside the first portion GI1a having a thickness T1b in the first gate insulating layer GI1 and overlaps with the first active layer ACT1, can be greater than the thickness T1b of the first portion GI1a, and for example, can be equal to the thickness T2 of the second portion GI1b.

[0161] Therefore, during ion implantation, this disclosure allows for control to binarize the ion projection distances of the first and second portions into RP1a and RP1c. Specifically, the ion projection distance RP1c can be controlled such that the implanted ions remain in the first buffer layer BUF1 based on a thickness T1b of the first portion GI1a, which is relatively smaller than the thickness of the third portion GI1c. Furthermore, within the third portion GI1c, the ion projection distance RP1a can be controlled such that the implanted ions remain in the first active layer ACT1 based on a thickness T1b, which is relatively larger than the thickness of the first portion GI1a.

[0162] Therefore, in the region overlapping with the first part GI1a, the peak of the Gaussian concentration of the doped dopant can be in the first buffer layer BUF1, which is a layer different from the first active layer ACT1.

[0163] In detail, the first buffer layer BUF1 may have a peak value Ps4 of the Gaussian distribution of the dopant on the first active layer ACT1 in the region overlapping with the first portion GI1a, and the first active layer ACT1 may have a peak value Ps3 of the Gaussian distribution of the dopant on the first active layer ACT1 in the portion of the first portion GI1a spaced apart from the edge of the first gate electrode G1.

[0164] Therefore, in the region where the first active layer ACT1 overlaps with the first portion GI1a of the first gate insulating layer GI1, the dopant distribution can be controlled so that the dopant concentration is lower than the concentration of the dopant doped on the first buffer layer BUF1.

[0165] This disclosure allows for controllable distribution such that the dopant concentration of the first active layer ACT1 in the region overlapping with the first portion GI1a is relatively lower than the dopant concentration of the first buffer layer BUF1 or the first gate insulating layer GI1, and thus minimizes the width of the offset region ΔL formed between the first channel region AC1 and the first a source-drain region ASD1a and the first b source-drain region ASD1b, thereby allowing the actual channel length formed in the switching transistor to be formed to be as close as possible to the designed channel length.

[0166] Therefore, when forming a switching transistor including an oxide semiconductor, this disclosure can prevent the channel length from decreasing, and thus can prevent the threshold voltage (Vth) of the initial transistor from shifting in the negative (-) direction, thereby preventing degradation.

[0167] Furthermore, the thickness of the gate insulating layer can be set differently, and control can be performed such that the peak of the Gaussian distribution of the dopant is set in a layer different from the active layer, and thus the reduction in the length of the effective channel can be prevented by diffusion of the dopant based on heat treatment.

[0168] This disclosure allows for the elimination of the need for separate components and the different thicknesses of the gate insulating layer, thereby enhancing the driving stability and reliability of transistors and display devices, thus achieving environmental, social, and governance (ESG) goals.

[0169] The following will describe an example of a display device that uses a switching transistor such as the first transistor TR1 and a driving transistor such as the second transistor TR2 as described above.

[0170] Figure 10 This is a diagram illustrating an embodiment of a display device that utilizes a first transistor and a second transistor.

[0171] exist Figure 10 In this process, substrate 100 may include a flexible plastic material and may have flexible properties, and furthermore, substrate 100 may include a glass material with a flexible thickness.

[0172] The substrate 100 may have a multilayer structure including an insulating material. For example, such as Figure 10As shown, the substrate 100 may have a structure in which a first substrate layer 101, a substrate insulating layer 102, and a second substrate layer 103 are stacked sequentially, and the first substrate layer 101 and the second substrate layer 103 may include a polymer material such as polyimide (PI). The substrate insulating layer 102 may include an insulating material.

[0173] A first insulating layer 110 can be disposed in the active region AA and the non-active region NA of the substrate 100. The first insulating layer 110 can be referred to as a buffer layer. The first insulating layer 110 can be disposed on the substrate 100 to protect structures on the substrate 100 susceptible to water transport from water penetration through the substrate 100, and can also planarize the surface of the substrate 100. The first insulating layer 110 can be formed of an inorganic monolayer, or as shown in... Figure 10 In this configuration, the first insulating layer 110 may include a first a insulating layer 111 and a first b insulating layer 112, wherein the plurality of inorganic layers are formed in a multilayer structure. For example, each of the first a insulating layer 111 and the first b insulating layer 112 may include one or more inorganic layers of SiOx, SiNx, and SiOxNy.

[0174] A second insulating layer 130 may be disposed on the first insulating layer 110. The second insulating layer 130 may serve as an interlayer insulating layer for each transistor (not shown) configuring a gate driver (not shown) disposed in the non-active region NA. The second insulating layer 130 may comprise an inorganic material. The inorganic material may comprise, for example, SiNx.

[0175] To improve the response speed of the first transistor TR1, a bottom gate electrode BOT connected to the first gate electrode G1 can be disposed between the first insulating layer 110 and the second insulating layer 120. The bottom gate electrode BOT may include a metal material different from the metal material of the first gate electrode G1, and may include the same material as the gate electrode of another transistor, which is formed on the same layer as the bottom gate electrode BOT.

[0176] A device buffer layer 140 can be disposed on the second insulating layer 130. The device buffer layer 140 can completely cover the active region AA of the substrate 100 and can include an insulating material. For example, the device buffer layer 140 can include an inorganic insulating material such as SiOx or SiNx. Figure 10 In this configuration, the device buffer layer 140 may include a multilayer structure in which a first device buffer layer 141 and a second device buffer layer 142 are stacked. The first device buffer layer 141 and the second device buffer layer 142 may include the same material or may include different materials.

[0177] A first active layer ACT1, serving as a switching transistor (TR1), and a second active layer ACT2, serving as a driving transistor (TR2), can be formed on the device buffer layer 140. For example, in... Figure 10 In this process, when the first transistor TR1 and the second transistor TR2 are disposed on the same device buffer layer 140, the manufacturing process can be further simplified.

[0178] However, not all switching transistors and driving transistors can be formed on the same device buffer layer 140, and this disclosure is not limited thereto. For example, some of the plurality of switching transistors and driving transistors can be formed on the same device buffer layer 140, or various modifications can be made to the cross-sectional structure in which only one of the switching transistors and driving transistors is formed on the device buffer layer 140.

[0179] As in Figure 10 In this context, when the first active layer ACT1 of the first transistor TR1 and the second active layer ACT2 of the second transistor TR2 are disposed on the same device buffer layer 140, the device buffer layer 140 can be used as the reference mentioned above. Figure 3 and Figure 4 The first buffer layer BUF1 of the first transistor TR1 and the above reference Figure 5 The second buffer layer BUF2 of the second transistor TR2 is described.

[0180] When device buffer layer 140 is used as the second buffer layer BUF2 of the second transistor TR2, the second b buffer layer BUF2b of the second transistor TR2 can be the same as the second device buffer layer 142, and the second a buffer layer BUF2a of the second transistor TR2 can be the same as the first device buffer layer 141.

[0181] The first transistor TR1 and the second transistor TR2 can be disposed on the device buffer layer 140.

[0182] The first transistor TR1 may include a first active layer ACT1, a first gate electrode G1, a first a source-drain electrode SD1a, a first b source-drain electrode SD1b, a first gate insulating layer GI1, and a first interlayer insulating layer ILD1 disposed on the device buffer layer 140.

[0183] exist Figure 10For example, it is shown that the thickness T1a of the first portion GI1a in the first gate insulating layer GI1 included in the first transistor TR1 is greater than the thickness T2 of the second portion GI1b. However, this can be an implementation, and in the first transistor TR1, the thicknesses of the first and second portions of the first gate insulating layer GI1, as well as the first active layer ACT1, the first gate electrode G1, the first a source-drain electrode SD1a, the first b source-drain electrode SD1b, and the first gate insulating layer GI1 ( Figure 10 The middle layer is 150) and the first interlayer insulation layer ILD1 ( Figure 10 The structure of each of the 200 values ​​can be related to... Figure 3 , Figure 4 , Figure 8 and Figure 9 The description is the same.

[0184] Therefore, the thickness T1a or T1b of the first portion GI1a in the first gate insulating layer GI1 included in the first transistor TR1 can be greater than or less than the thickness T2 of the second portion GI1b, and the peak value Ps1 or Ps3 of the Gaussian distribution of the dopant doped in the first a source-drain region ASD1a or the first b source-drain region ASD1b can be less than the peak value Ps2 of the Gaussian distribution of the dopant doped in the first gate insulating layer GI1, or can be less than the peak value Ps4 of the Gaussian distribution of the dopant doped in the first buffer layer BUF1.

[0185] The second transistor TR2 may include a second active layer ACT2 disposed on the device buffer layer 140, a second gate electrode G2, a second a source-drain electrode SD2a, a second b source-drain electrode SD2b, and a second gate insulating layer GI2. Figure 10 The middle layer is 150) and the second interlayer insulating layer ILD2 ( Figure 10 (200 in the middle). A light-blocking pattern LS can be provided between the first device buffer layer 141 and the second device buffer layer 142, which is electrically connected to one of the second a source-drain electrode SD2a and the second b source-drain electrode SD2b of the second transistor TR2.

[0186] The second active layer ACT2, the second gate electrode G2, the second a-source-drain electrode SD2a, the second b-source-drain electrode SD2b, the second gate insulating layer GI2, the second interlayer insulating layer ILD2, and the light-blocking pattern LS of the second transistor TR2 can be combined with... Figure 5 and Figure 7 The description is the same.

[0187] Therefore, the second channel length LC2 formed in the second active layer ACT2 in the second transistor TR2 can be longer than the first channel length LC1 formed in the first active layer ACT1 in the first transistor TR1.

[0188] In addition, as referred to above Figure 5 and Figure 7 As described, the thickness of the portion of the second gate insulating layer GI2 that is configured not to overlap with the outer edge portion of the second gate electrode G2 can be equal to the thickness of the portion disposed at the portion overlapping with the second gate electrode G2.

[0189] The position of the maximum peak Pd of the Gaussian distribution of the dopant doped in the second transistor TR2 may be different from the position of the maximum peak Ps1 or Ps3 of the Gaussian distribution of the dopant doped in the first transistor TR1.

[0190] In addition, such as Figure 10 As shown, when the first transistor TR1 and the second transistor TR2 are disposed on the same device buffer layer 140, the first gate insulating layer GI1 of the first transistor TR1 and the second gate insulating layer GI2 of the second transistor TR2 can be formed from the same gate insulating layer 150. Therefore, the first gate insulating layer GI1 of the first transistor TR1 and the second gate insulating layer GI2 of the second transistor TR2 can include the same material, which simplifies the manufacturing process.

[0191] Furthermore, the thickness of the gate insulating layer between the first active layer ACT1 and the first gate electrode G1 in the first transistor TR1 can be equal to the thickness of the gate insulating layer between the second active layer ACT2 and the second gate electrode G2 in the second transistor TR2. However, this disclosure is not limited thereto.

[0192] Furthermore, when the first transistor TR1 and the second transistor TR2 are disposed on the same device buffer layer 140, such as Figure 10 As shown, the first interlayer insulating layer ILD1 of the first transistor TR1 and the second interlayer insulating layer ILD2 of the second transistor TR2 can be formed from the same interlayer insulating layer 200. Therefore, the first interlayer insulating layer ILD1 of the first transistor TR1 and the second interlayer insulating layer ILD2 of the second transistor TR2 can include the same material, which simplifies the manufacturing process.

[0193] As in Figure 10 In this process, when the first transistor TR1 and the second transistor TR2 are disposed on the same device buffer layer 140, the first buffer layer BUF1 and the second buffer layer BUF2, the first gate insulating layer GI1 and the second gate insulating layer GI2, and the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 can be formed from the same materials using the same process, and thus the process steps can be realized. Therefore, the process steps can be simplified, the production energy used to manufacture the display device can be reduced, and the generation of greenhouse gases caused by the manufacturing process can be reduced, thereby achieving ESG.

[0194] In each pixel region, a first planarization layer 300 and a second planarization layer 400 may be stacked sequentially between the light-emitting device OLED and circuit elements such as a first transistor TR1 and a second transistor TR2. For example, a first electrode 610 (e.g., an anode electrode), an emission layer 620, and a second electrode 630 (e.g., a cathode electrode) of each pixel region PA may be stacked sequentially on the second planarization layer 400 of the corresponding pixel region PA.

[0195] The first planarization layer 300 and the second planarization layer 400 can eliminate the step height caused by the driving circuit. For example, the upper surface of the light-emitting device OLED facing each pixel region PA of the second planarization layer 400 can be a flat surface. The first planarization layer 300 and the second planarization layer 400 may include an insulating material. The first planarization layer 300 and the second planarization layer 400 may include a material with high fluidity. For example, the first planarization layer 300 and the second planarization layer 400 may include an organic insulating material. The second planarization layer 400 may include a material different from that of the first planarization layer 300. Therefore, in the display device according to the embodiments of the present disclosure, the step height caused by the driving circuit can be effectively eliminated.

[0196] The center electrode CE2 of the second transistor TR2 can be disposed between the first planarization layer 300 and the second planarization layer 400 in each pixel region PA. Furthermore, depending on the situation, the center electrode CE1 of the first transistor TR1 can be disposed between the first planarization layer 300 and the second planarization layer 400 for circuit configuration with another transistor (not shown).

[0197] The center electrode CE2 of the second transistor TR2 can be electrically connected to one of the second source-drain electrodes SD2a and SD2b of the second transistor TR2. Figure 10 For example, the second source / drain electrode SD2a is shown to be connected to the center electrode CE2 of the second transistor TR2.

[0198] Furthermore, the center electrode CE2 of the second transistor TR2 can be electrically connected to the first electrode 610 of the light-emitting device 600. For this purpose, the first electrode 610 of the light-emitting device 600 can pass through the second planarization layer 400 and can be connected to the center electrode CE2 of the second transistor TR2. The center electrode CE2 of the second transistor TR2 can include a conductive material. For example, the center electrode CE2 of the second transistor TR2 can include metals such as Al, Cr, Cu, Ti, Mo, and W. The center electrode CE2 of the second transistor TR2 can include a material different from the materials of the second a-source-drain electrode SD2a, the second b-source-drain electrode SD2b, and the first electrode 610.

[0199] The dam insulating layer 500 may be disposed on the second planarization layer 400 of each pixel region PA. The dam insulating layer 500 may include an insulating material. For example, the dam insulating layer 500 may include an organic insulating material.

[0200] The dam insulating layer 500 may include a material different from that of each of the first planarization layer 300 and the second planarization layer 400. The dam insulating layer 500 may cover the edge of the first electrode 610. The emitter layer 620 and the second electrode 630 may be stacked on the portion of the first electrode 610 exposed by the dam insulating layer 500. For example, the dam insulating layer 500 may define an emitter region in each pixel region PA.

[0201] The light-emitting device 600 can be disposed in the emitting region and can include a first electrode 610, an emitting layer 620, and a second electrode 630.

[0202] In the light-emitting device (OLED) 600, the first electrode 610 may include a conductive material. The first electrode 610 may have high reflectivity. For example, the first electrode 610 may include metals such as Al and silver (Ag). The first electrode 610 may have a multilayer structure. For example, the first electrode 610 may have a structure in which reflective electrodes of metal are disposed between transparent electrodes comprising transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0203] The emitting layer 620 can generate light with a brightness corresponding to the voltage difference between the first electrode 610 and the second electrode 630. For example, the emitting layer 620 may include an emissive material layer (EML) containing an emissive material. The emissive material may include organic materials, inorganic materials, or a mixture of materials. For example, the emitting layer 620 may include an emissive material layer containing an organic material.

[0204] The emitter layer 620 may include at least one of a first emitter common layer (not shown) disposed between the first electrodes 610 and a second emitter common layer (not shown) disposed between the second electrodes 630. Each of the first emitter common layer (not shown) and the second emitter common layer (not shown) may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0205] The second electrode 630 may include a conductive material. The second electrode 630 may include a material different from that of the first electrode 610. For example, the second electrode 630 may be a transparent electrode comprising a transparent conductive material such as ITO or IZO. The second electrode 630 may have a higher transmittance than the first electrode 610. Therefore, in a display device according to an embodiment of this disclosure, light generated by the emitting layer 620 can be emitted through the second electrode 630.

[0206] Encapsulation component 700 can be disposed on the light-emitting device (OLED) 600 and the insulating layer 500 in each pixel region PA. Encapsulation component 700 can prevent damage to the light-emitting device 600 caused by external impact and water. Encapsulation component 700 can have a multilayer structure. For example, encapsulation component 700 can be provided by alternately stacking encapsulation layers comprising inorganic insulating materials and encapsulation layers comprising organic insulating materials. For example, encapsulation layers comprising inorganic insulating materials can be disposed between encapsulation layers comprising organic insulating materials.

[0207] Therefore, in the display device according to the embodiments of the present disclosure, damage to the light-emitting device (OLED) 600 caused by external impact and water can be effectively prevented. The step height caused by the light-emitting device (OLED) 600 in each pixel region PA can be eliminated by the encapsulation member 700. For example, the upper surface of the encapsulation member 700 opposite to the device substrate 100 can be a flat surface.

[0208] exist Figure 10 For example, the case shown illustrates a first transistor TR1 as a switching transistor and a second transistor TR2 as a driving transistor connected to a light-emitting device OLED, but the present disclosure is not limited thereto.

[0209] As mentioned above Figure 2 As described in (b), when a third transistor TR3 is provided as a switching transistor, the second transistor TR2 can be electrically connected to the third transistor TR3, and the third transistor TR3 can be electrically connected to the light-emitting device OLED.

[0210] Furthermore, in embodiments of this disclosure, for example, it has been described that the thickness T1a or T1b of the first portion GI1a of the first gate insulating layer GI1 of a switching transistor such as the first transistor TR1 included in the active region AA is different from the thickness T2 of the second portion GI1b, but this disclosure is not limited thereto.

[0211] For example, in Figure 1In this context, a GIP driver (e.g., a gate drive circuit) for supplying control signals to sub-pixels SP can be disposed in the non-active region NA of substrate 100, and a configuration in which the thickness T1a or T1b of the first portion GI1a of the gate insulating layer is different from the thickness T2 of the second portion GI1b can also be applied to switching elements included in the drive circuit.

[0212] As described above, in the display device according to the embodiments of the present disclosure, in the switching transistor having a short channel length, the thickness T1a or T1b of the first portion GI1a of the gate insulating layer can be different from the thickness T2 of the second portion GI1b, and thus a desired channel length can be formed, thereby improving the driving stability and reliability of the switching transistor.

[0213] Embodiments of this disclosure may set the thickness of the first portion and the thickness of the second portion of the gate insulating layer of the switching transistor differently, and thus the distribution of the components can be controlled, thereby further enhancing the driving stability and reliability of the switching transistor.

[0214] Embodiments of this disclosure provide a display device in which, when forming a transistor comprising an oxide semiconductor, the reduction of the effective channel length can be prevented, and thus the threshold voltage (Vth) of the initial transistor can be prevented from shifting in the negative (-) direction.

[0215] Embodiments of this disclosure provide a transistor and a display device including the transistor, wherein the thickness of the gate insulating layer can be set differently, the peak value of the Gaussian distribution of the dopant can be controlled to be set in a layer different from the active layer, and the length of the effective channel can be prevented from decreasing due to diffusion of the dopant based on heat treatment.

[0216] The embodiments of this disclosure can be implemented without adding separate components and the thickness of the gate insulating layer can be set differently, and therefore, the driving stability and reliability of transistors and display devices can be improved and power consumption can be reduced, thereby achieving ESG.

[0217] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0218] Although this disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure.

[0219] The various embodiments described above can be combined to provide other embodiments. Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of equivalents enjoyed by such claims. Therefore, the claims are not limited to the disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including an active region and an active region; A first transistor is disposed in the active region and includes a first gate electrode, a first a source-drain electrode, a first b source-drain electrode, and a first active layer; as well as A first gate insulating layer is disposed between the first gate electrode and the first active layer. In the first gate insulating layer, the thickness of the first portion that does not overlap with the first gate electrode but is adjacent to the outer edge of the first gate electrode is different from the thickness of the second portion that overlaps with the first gate electrode.

2. The display device according to claim 1, wherein, In the first gate insulating layer, the thickness of the third portion disposed outside the first portion and overlapping with the first active layer is different from the thickness of the first portion.

3. The display device according to claim 2, wherein, The first active layer includes source-drain regions, in which dopants are present in regions that do not overlap with the first gate electrode. In the region overlapping with the first portion, the peak of the Gaussian distribution of the dopant concentration is set in a layer different from the first active layer.

4. The display device according to claim 2, wherein, The thickness of the first portion is greater than the thickness of the second portion, and the thickness of the third portion is less than the thickness of the first portion. The peak of the Gaussian distribution of the dopant in the first active layer is located in the region of the first gate insulating layer corresponding to the first portion.

5. The display device according to claim 2, wherein, In the first active layer, the peak of the Gaussian distribution of the dopant doped in the first active layer is set at a portion spaced apart from the edge of the first gate electrode from the first portion.

6. The display device according to claim 4, wherein, The thickness of the first portion is greater than the thickness of the second portion, but less than the sum of the thicknesses of the second portion and the first gate electrode.

7. The display device according to claim 2, further comprising a first buffer layer between the substrate and the first active layer, in, The thickness of the first portion is less than the thickness of the second portion, and the thickness of the third portion is greater than the thickness of the first portion. The first buffer layer has a peak value of the Gaussian distribution of the dopant doped on the first active layer in the region overlapping with the first portion.

8. The display device according to claim 7, wherein, The thickness of the first part is less than the thickness of the second part, but greater than 1 / 10 of the thickness of the second part.

9. The display device according to claim 1, wherein, The first active layer includes an oxide semiconductor.

10. The display device according to claim 1, further comprising a second transistor, the second transistor being disposed in the active region and including a second gate electrode, a second a source-drain electrode, a second b source-drain electrode, and a second active layer. in, The length of the channel formed in the first active layer of the first transistor is shorter than the length of the channel formed in the second active layer of the second transistor.

11. The display device according to claim 10, further comprising a second gate insulating layer disposed between the second gate electrode and the second active layer. in, The thickness of the portion of the second gate insulating layer disposed outside the second gate electrode and not overlapping with the second gate electrode is equal to the thickness of the portion overlapping with the second gate electrode.

12. The display device according to claim 10, wherein, The location of the maximum peak of the Gaussian distribution of the dopant on the first transistor is different from the location of the maximum peak of the Gaussian distribution of the dopant on the second transistor.

13. The display device according to claim 10, wherein, The location where the maximum peak is formed in the Gaussian distribution of the dopant in the first transistor is set in a layer different from the first active layer, and The location where the maximum peak is formed in the Gaussian distribution of the dopant in the second transistor is set in the second active layer.

14. The display device according to claim 10, further comprising a light-emitting device disposed on the first transistor and the second transistor in the active region, the light-emitting device comprising a first electrode, an organic light-emitting layer, and a second electrode, and One of the first transistor or the second transistor is electrically connected to the first electrode.

15. A transistor, comprising: The first active layer includes an oxide semiconductor material and includes a first channel region, a first a source-drain region, and a first b source-drain region, wherein the first channel region is disposed between the first a source-drain region and the first b source-drain region. A first gate electrode is disposed on the first active layer to overlap with the first channel region; The first a-source-drain electrode and the first b-source-drain electrode are respectively connected to the first a-source-drain region and the first b-source-drain region; as well as A first gate insulating layer is disposed between the first gate electrode and the first active layer. In the first gate insulating layer, the thickness of the first portion that does not overlap with the first gate electrode but is adjacent to the edge of the first gate electrode is different from the thickness of the second portion disposed at the portion that overlaps with the first gate electrode.

16. The transistor of claim 15, wherein, In the first gate insulating layer, the thickness of the third portion disposed outside the first portion and overlapping with the first active layer is different from the thickness of the first portion.

17. The transistor of claim 15, wherein, Dopant is doped in the first a-source-drain region and the first b-source-drain region in the first active layer, and In the region overlapping with the first portion, the peak of the Gaussian distribution representing the doping concentration of the dopant is set in a layer different from the first active layer.

18. The transistor of claim 16, wherein, The thickness of the first portion is greater than the thickness of the second portion, and the thickness of the third portion is less than the thickness of the first portion. The peak of the Gaussian distribution of the dopant in the first active layer is located in the region of the first gate insulating layer corresponding to the first portion.

19. The transistor of claim 16, wherein, In the first active layer, the peak of the Gaussian distribution of the dopant doped in the first active layer is set at a portion spaced apart from the edge of the first gate electrode from the first portion.

20. The transistor of claim 16, further comprising a substrate and a first buffer layer between the substrate and the first active layer. in, The thickness of the first portion is less than the thickness of the second portion, and the thickness of the third portion is greater than the thickness of the first portion. The first buffer layer has a peak value of the Gaussian distribution of the dopant doped on the first active layer in the region overlapping with the first portion.

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