Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method thereof
By employing a split gate design in SiC MOSFETs, the electric field at the gate-gate oxide interface is reduced, improving the electrostatic discharge and short-circuit withstand capability and reliability of SiC MOSFETs, thus solving the problem of insufficient withstand capability in existing technologies.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2026-04-14
AI Technical Summary
SiC MOSFETs have poor tolerance to electrostatic discharge and short circuits, partly because the chip area is small and the current density is high, resulting in an excessively high electric field at the gate. This makes the gate oxide layer at the interface prone to degradation and failure, affecting reliability.
The design employs a split gate design, which involves forming two gates on the gate oxide layer, extending inward to the isolation oxide layer on both sides, forming a special split gate structure to reduce the electric field at the interface between the gate and the gate oxide layer.
This effectively reduces the electric field at the gate-gate oxide interface, improves the electrostatic discharge and short-circuit withstand capability and reliability of SiC MOSFETs, and solves the reliability problem in the prior art.
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Figure CN121865674A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to silicon carbide metal oxide semiconductor field-effect transistors (SiC MOSFETs), and more particularly, to a silicon carbide MOSFET having a split gate and a method for manufacturing the same. Background Technology
[0002] Silicon carbide (SiC) is a wide-bandgap third-generation semiconductor material with better physical and chemical properties than silicon, such as high power, high switching frequency, low switching loss, high temperature resistance, high breakdown voltage, and high current density. Therefore, it can be widely used in electronic systems that require high frequency, high power density, and high reliability, including power conversion systems for electric vehicles, power converters such as inverters, chargers and uninterruptible power supplies, energy management systems, and industrial drive systems. It plays an increasingly important role in high-performance electronic devices.
[0003] Metal-oxide-semiconductor field-effect transistors (SiC MOSFETs, hereinafter referred to as such) made of silicon carbide are expected to replace commonly used insulated-gate bipolar transistors (IGBTs) power devices. Besides offering high voltage withstand capability, high-frequency drive, and low on-resistance, they can significantly reduce switching losses and facilitate chip miniaturization. However, despite these advantages, SiC MOSFETs have poor tolerance to electrostatic discharge (ESD) and short circuits. This is partly due to the small chip area and high current density of SiC MOSFETs, which leads to excessively high electric fields at the gate during operation, causing the gate oxide layer at the interface to easily degrade and fail, resulting in reliability issues. Therefore, those skilled in the art need to further improve the structure of SiC MOSFETs to address these problems. Summary of the Invention
[0004] In view of the problems encountered in the prior art, the present invention proposes a novel SiC MOSFET structure, characterized by a split gate design, which can significantly reduce the electric field at the gate-gate oxide interface and effectively improve the reliability of SiC MOSFET.
[0005] One aspect of the present invention is to provide a silicon carbide metal-oxide-semiconductor field-effect transistor, comprising: a silicon carbide substrate; a gate oxide layer located on the silicon carbide substrate; an isolation oxide layer located on the gate oxide layer; two gates respectively located on the gate oxide layer on both sides of the isolation oxide layer in a first direction, wherein each of the two gates has an extension extending inwardly into the isolation oxide layer in the first direction; two sources respectively located in the silicon carbide substrate on both sides of the gate oxide layer in the first direction; and a drain contact metal located on the other side of the silicon carbide substrate opposite to the gate oxide layer.
[0006] Another aspect of the present invention is to provide a method for manufacturing a silicon carbide metal-oxide-semiconductor field-effect transistor, comprising: providing a silicon carbide substrate having two sources facing each other in a first direction; forming a gate oxide layer on the silicon carbide substrate between the two sources; forming a first gate material layer on the gate oxide layer; performing a first photolithography process to pattern the first gate material layer into two lower gate patterns, the two lower gate patterns being located on the edge portions of the gate oxide layer on both sides in the first direction; forming an isolation oxide layer between the two lower gate patterns; forming a second gate material layer on the two lower gate patterns and the isolation oxide layer; and performing a second photolithography process to pattern the second gate material layer into two upper gate patterns, the two upper gate patterns being located on the two lower gate patterns and having extension portions extending inward in the first direction to the isolation oxide layer, the two upper gate patterns and the corresponding two lower gate patterns forming a first gate and a second gate, respectively.
[0007] These and other objects of the present invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description
[0008] Figure 1 This is a cross-sectional schematic diagram of a SiC MOSFET according to Embodiment 1 of the present invention; and
[0009] Figures 2 to 10 This is a cross-sectional schematic diagram of the fabrication process of the SiC MOSFET in Embodiment 1 of the present invention.
[0010] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.
[0011] Symbol Explanation
[0012] 100 base
[0013] 102 Drift Zone
[0014] 104 P-type trap
[0015] 106 Gate oxide layer
[0016] 108 First gate material layer
[0017] 108a, 108b lower gate patterns
[0018] 110 Photoresist
[0019] 112 Space
[0020] 114. Insulation Material Layer
[0021] 114a isolation oxide layer
[0022] 116 Photoresist
[0023] 118 Second gate material layer
[0024] Gate patterns of 118a and 118b
[0025] 120 Photoresist
[0026] 122 Space
[0027] 124 Passivation layer
[0028] 126 Extension
[0029] 128 Source Contact Metal
[0030] B base
[0031] D drain contact metal
[0032] d1 First direction
[0033] G1 (first) gate
[0034] G2 (Second) Gate
[0035] JFET (Junction Field-Effect Transistor)
[0036] P1 First photolithography process
[0037] P2 Second photolithography process
[0038] P3 Third Photolithography Process
[0039] S source pole Detailed Implementation
[0040] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are merely illustrative and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.
[0041] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" not only means "directly on" something, but also includes being "on" something with an intervening feature or layering structure. Similarly, "above" or "above" not only means "above" or "above" something, but also includes being "above" or "above" something without an intervening feature or layering structure (i.e., directly on something). Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.
[0042] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any opposing horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layered structure, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.
[0043] Readers can generally understand the terminology used in this invention, at least in part, from its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "described" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.
[0044] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.
[0045] The text uses designations such as "N" and "P," generally referring to "N-type" and "P-type" to indicate donor and acceptor dopants that promote electron-hole exchange as the primary carriers. Examples include P-type boron (B) atoms and N-type phosphorus (P) and arsenic (As) atoms. A dopant type ending in "++" indicates a higher doping concentration than dopants ending in "+". Conversely, a dopant type ending in "-" indicates a lower doping concentration than dopants without a suffix.
[0046] First, please refer to... Figure 1 This is a cross-sectional schematic diagram of a SiC MOSFET according to an embodiment of the present invention. As shown in the figure, the SiC MOSFET of the present invention includes a substrate 100 as the basis for the components to be formed thereon. In this embodiment of the present invention, the substrate 100 is made of silicon carbide (SiC) with a thickness of approximately 175 μm, wherein it is heavily doped (N+) with N-type dopants such as phosphorus (P) and arsenic (As), and the doping concentration is approximately 1 × 10⁻⁶. 19 cm -3To improve conductivity, reduce drain contact resistance, and adjust its bandgap, a drain contact metal D (i.e., drain) is provided on the back side of the substrate 100, which is in direct contact with the substrate 100 to output current to an operating voltage. The drain contact metal D can be made of a metal with high conductivity, such as aluminum (Al), nickel (Ni), or gold (Au). On the other hand, a drift region 102 is formed on the front side of the substrate 100, which is grown on the surface of the silicon carbide substrate 100 by an epitaxial fabrication process, with a thickness of approximately 12 μm. The drift region 102 may be lightly doped with N-type dopant, with a doping concentration of approximately 1 × 10⁻⁶. 16 cm -3 The thickness and doping concentration of the drift region 102 partially determine the cutoff voltage of the device. A lower doping concentration reduces the probability of carrier recombination, ensuring that carriers in the device can effectively move and drift under the influence of an electric field, thereby maintaining a high current density in a high-voltage environment. It should be noted that in some embodiments, one or more buffer layers (not shown) may be formed between the drift region 102 and the substrate 100 to alleviate stress and improve crystal quality. On the other hand, a current distribution layer (not shown), such as a doped layer with a higher doping concentration than the drift region 102, may also be formed on the drift region 102 to uniformly distribute the current laterally across the horizontal cross-section of the substrate during operation and reduce on-resistance.
[0047] Rereference Figure 1 A gate oxide layer 106 is formed on the surface of the drift region 102. The material can be silicon oxide or a high-dielectric-constant material, such as hafnium oxide (HfO2), with a thickness of approximately 40 nm. A P-well 104 is formed in each of the drift regions 102 on both sides of the gate oxide layer 106 in the first direction d1. This P-well can be formed by P-type doping of these regions, such as by doping with boron (B), with a doping concentration of approximately 1 × 10⁻⁶. 18 cm -3 The depth can be 0.7 μm. The P-type well 104 helps to more effectively control the current flow in the N-type SiC MOSFET device channel, avoid interference between different devices, and adjust the device's critical voltage. In an embodiment, the P-type well 104 overlaps with a portion of the gate oxide layer 106 in the vertical direction. The drift region 102 between the two P-type wells 104 serves as the junction field-effect transistor (JFET) region of the device, with a width of approximately 2 μm. It can control the on and off of the device channel, improve the switching speed of the device, and reduce switching losses. Furthermore, each P-type well 104 also forms a source S and a base B. In an embodiment, the source S is formed in the P-type well 104 outside the gate oxide layer 106 in the first direction d1, and it can partially overlap with the gate oxide layer 106 in the vertical direction. The source S can be formed by heavily doping the P-type well 104 with N-type doping (N+), with a doping concentration of approximately 5 × 10⁻⁶.19 cm -3 The doping concentration is greater than that of the drift region 102, and the depth can be 0.2 μm. The source S serves as the current input terminal and can be connected to a reference voltage, such as ground, through the source contact metal 128. The P-type well 104 between the source S and the JFET region is the channel region, and its length can be 0.5 μm. The base B is formed in the P-type well 104 outside the source S in the first direction d1. It can be directly connected to the source S and can be formed by heavily doping the P-type well 104 with P+, with a doping concentration of approximately 1 × 10⁻⁶. 19 cm -3 The doping concentration is greater than that of the P-type well 104, and the depth can be 0.2 μm. The base B serves as the pick-up terminal of the P-type well 104, and it can be connected to a reference voltage together with the source S through a source contact metal 128. The pitch of the entire device in the first direction d1 can be 14 μm.
[0048] Rereference Figure 1 Regarding components above the gate oxide layer 106, in this embodiment of the invention, an isolation oxide layer 114a is formed on the gate oxide layer 106. The isolation oxide layer 114a is preferably formed in the center of the entire SiC MOSFET device, so that the components and features of the entire device are mirror-symmetrical about the isolation oxide layer 114a in the first direction d1. The isolation oxide layer 114a can be made of silicon oxide, and its thickness in the vertical direction is less than the thickness of the two gates G1, G2 in the vertical direction. The function of the isolation oxide layer 114a in this invention is to create split gates (i.e., gates G1, G2) in the fabrication process, which is an important technical feature of this invention. In this embodiment, gates G1, G2 are respectively formed on the gate oxide layers 106 on both sides of the isolation oxide layer 114a in the first direction d1, and their sidewalls can be flush with the sidewalls of the gate oxide layer 106 below. The material can be N-type heavily doped polysilicon. Gates G1 and G2 can overlap with their corresponding P-type wells 104 and source S portions below them, with the source S and base B located on their outer sides. Thus, gates G1 and G2 are arranged as separate gates on both sides of the device, corresponding to their respective source S and base B, and can be connected to the device's power supply voltage via contacts (not shown). In terms of height, the gates G1 and G2 are higher than the height of the central isolation oxide layer 114a. A key feature of this invention is that both gates G1 and G2 have an extension 126 extending inward in the first direction d1 onto the isolation oxide layer 114a, but the two extensions 126 are not connected to each other.
[0049] Rereference Figure 1In this embodiment, a passivation layer 124 covers the gates G1 and G2 to provide protection and isolate them from the source contact metal 128 above. The passivation layer 124 may be made of the same material as the isolation oxide layer 114a, such as silicon oxide, and fills the space between the two extensions 126 to ensure isolation of both gates G1 and G2. Furthermore, the passivation layer 124 exposes a portion of the surrounding source S region, allowing the source S to connect to the source contact metal 128. In this embodiment, the source contact metal 128 may cover and surround the passivation layer 124, and connects to both the source S and the base B on both sides to connect the source S and the base B to an external reference voltage. The source contact metal 128 may be made of the same material as the drain contact metal D on the other side of the substrate, such as a highly conductive metal like aluminum (Al), nickel (Ni), or gold (Au).
[0050] In this invention, the specially designed separated gates G1 and G2 with extensions 126 can alter the electric field topography of the gate region, preventing excessive concentration of the electric field in specific areas. Compared to a typical single gate design without extensions, it can significantly reduce the electric field at the gate-gate oxide interface. For example, in a high-temperature gate bias test (HTGB) with a gate voltage of 20V and other terminals grounded, the electric field of the gate oxide layer 106 can be reduced from 4.64MV / cm to 1.05MV / cm, and the electric field of the silicon carbide drift region 102 near the gate can be reduced from 0.32MV / cm to 0.18MV / cm. This undoubtedly effectively improves the electrostatic discharge and short-circuit withstand capability and reliability of the SiC MOSFET, solving the problems of the prior art, which is the novelty and progress of this invention.
[0051] Having described the structure of the SiC MOSFET of the present invention above, the following embodiments will be referred to in sequence. Figures 2 to 10 The following diagrams illustrate the fabrication process of the SiC MOSFET of this invention. These diagrams will show the evolution and formation of the various components and features of the SiC MOSFET during the fabrication process in cross-sectional views. It should be noted that the fabrication processes for the aforementioned doped regions will be omitted in these diagrams to avoid obscuring the focus of this invention.
[0052] First, please refer to... Figure 2The fabrication process begins with a substrate 100 as the basis for the SiC MOSFET device of this invention. In this embodiment, the substrate 100 is made of silicon carbide (SiC), in which an epitaxial layer serving as the drift region 102 has been pre-formed using an epitaxial fabrication process, and doped regions such as the aforementioned drift region (N-) 102, P-type well (P) 104, source (N+) S, and base (P+) are formed therein using an ion implantation or diffusion fabrication process. The P-type well 104, source S, and base B on both sides are mirror-symmetrical about the centerline of the device in the first direction d1. The doping concentration of the P-type well 104 is approximately 1 × 10⁻⁶. 18 cm -3 The doping depth can be 0.7 μm. The doping concentration of the source S and base B is approximately 5 × 10⁻⁶. 19 cm -3 The depth can be 0.2μm.
[0053] Please refer to Figure 3 After preparing the substrate 100, a gate oxide layer 106 and a first gate material layer 108 are sequentially formed on the substrate 100, which can be deposited by CVD process. The gate oxide layer 106 is made of silicon oxide, and its pattern is defined by photolithography so that its two sides in the first direction d1 partially overlap with the P-type well 104 and the source S in the vertical direction. The area where the gate oxide layer 106 overlaps with the P-type well 104 is the channel region of the device. The first gate material layer 108 can be made of heavily N-type doped polysilicon, covering the entire gate oxide layer 106 and the surface of the substrate 100.
[0054] Please refer to Figure 4 After the gate oxide layer 106 and the first gate material layer 108 are formed, a first photolithography process P1 is performed to remove portions of the first gate material layer 108, defining the lower gate patterns 108a and 108b on both sides of the device. More specifically, this step first forms a photoresist 110 with the lower gate patterns on the first gate material layer 108, and then uses the photoresist 110 as an etching mask to perform an anisotropic etching process, removing the first gate material layer 108 not covered by the photoresist 110 until the lower gate oxide layer 106, the source S, and the base B are exposed. The formed lower gate patterns 108a and 108b are located at both ends of the gate oxide layer 106 in the first direction d1, and their outer walls are preferably flush with the sidewalls of the lower gate oxide layer 106. A space 112 is formed between the lower gate patterns 108a and 108b for the subsequent isolation oxide layer.
[0055] Please refer to Figure 5After the lower gate patterns 108a and 108b are formed, the photoresist 110 is removed, and then an isolation material layer 114 is formed on the lower gate patterns 108a and 108b and the substrate 100. The isolation material layer 114 can be made of silicon oxide, which can be deposited by a CVD process. In this embodiment, the isolation material layer 114 fills the space 112 between the lower gate patterns 108a and 108b to serve as the material for the subsequent isolation oxide layer.
[0056] Please refer to Figure 6 After the isolation material layer 114 is formed, a second photolithography process P2 is performed to pattern the isolation material layer 114 to form an isolation oxide layer 114a. More specifically, this step first forms a photoresist 116 with an isolation oxide pattern on the isolation material layer 114, and then uses the photoresist 116 as an etching mask to perform an anisotropic etching process to remove the isolation material layer 114 not covered by the photoresist 116 until the lower gate patterns 108a, 108b, the source S, and the base B are exposed. The formed isolation oxide layer 114a is preferably located between the lower gate patterns 108a, 108b, and its height is higher than the height of the lower gate patterns 108a, 108b, so as to achieve the effect of isolating the two.
[0057] Please refer to Figure 7 After the isolation oxide layer 114a is formed, the photoresist 116 is removed, and then a second gate material layer 118 is formed on the substrate 100. The second gate material layer 118 is made of the same material as the first gate material layer 108, which can be N-type heavily doped (N+) polysilicon, deposited by CVD process. The second gate material layer 118 covers the isolation oxide layer 114a, the lower gate patterns 108a and 108b, the source S, and the base B surface. In this embodiment, the second gate material layer 118 is integrated with the lower gate patterns 108a and 108b, serving together as the material layer for the gate to be formed subsequently.
[0058] Please refer to Figure 8After the second gate material layer 118 is formed, a third photolithography process P3 is performed to remove portions of the second gate material layer 118, defining the upper gate patterns 118a and 118b on both sides of the device. More specifically, this step first forms a photoresist 120 with upper gate patterns on the second gate material layer 118, and then uses the photoresist 120 as an etching mask to perform an anisotropic etching process to remove the second gate material layer 118 not covered by the photoresist 120 until the source S and base B below are exposed. The formed upper gate patterns 118a and 118b are located on the lower gate patterns 108a and 108b on both sides of the isolation oxide layer 114a in the first direction d1, respectively, and their outer sidewalls are preferably flush with the sidewalls of the lower gate patterns 108a and 108b. A space 122 is provided on the isolation oxide layer 114a between the upper gate patterns 118a and 118b. In this embodiment, the formed upper gate patterns 118a and 118b each have an extension 126 extending inward in the first direction d1 onto the isolation oxide layer 114a, but they are not connected to each other. Furthermore, the upper gate pattern 118a and the lower gate pattern 108a form a first gate G1, and the upper gate pattern 118b and the lower gate pattern 108b form a second gate G2. Thus, the first gate G1 and the second gate G2 are in a split-gate configuration, located on opposite sides of the isolation oxide layer 114a, and the overlapping P-type well 104 below them serves as the channel region of the device.
[0059] Please refer to Figure 9 After the first gate G1 and the second gate G2 are formed, the photoresist 120 is removed, and then a passivation layer 124 is formed on the first gate G1, the second gate G2, and the substrate 100. The passivation layer 124 can be made of silicon oxide and can be deposited using a CVD process. In this embodiment, the passivation layer 124 covers the entire first gate G1 and the second gate G2 and fills the space 122 between the two extensions 126 to provide protection. The passivation layer 124 can also isolate the first gate G1 and the second gate G2 from the source contact metal 128 to be formed subsequently.
[0060] Please refer to Figure 10After the passivation layer 124 is formed, a source contact metal 128 is formed on top of the passivation layer 124. More specifically, in this step, a photolithography process is first performed to remove a portion of the passivation layer 124 to expose a portion of the source S and base B on the substrate 100. Then, a source contact metal material layer is formed on the patterned passivation layer 124. This material can be a highly conductive metal such as aluminum (Al), nickel (Ni), or gold (Au), and can be formed using a PVD process. Finally, a photolithography process is performed to pattern the source contact metal material layer into the source contact metal 128. The formed source contact metal 128 is electrically connected to the source S and base B on the substrate 100 to connect these terminals to a reference voltage. In some embodiments, the source S and base B on both sides of the element can also be connected to the reference voltage through their respective source contact metals. On the other hand, a corresponding drain contact metal D is also formed on the back side of the substrate. Its fabrication process can be the same as that of the source contact metal 128, such as by PVD fabrication, and the material is the same, such as a metal with high conductivity, such as aluminum (Al), nickel (Ni), or gold (Au). In this invention, the drain contact metal D may also be formed before or after the source contact metal 128, and is not limited thereto.
[0061] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A silicon carbide metal-oxide-semiconductor field-effect transistor, comprising: Silicon carbide substrate; A gate oxide layer is located on the silicon carbide substrate; An isolation oxide layer is located on the gate oxide layer; Two gates are respectively located on the gate oxide layer on both sides of the isolation oxide layer in the first direction, wherein both gates have extensions that extend inward in the first direction to the isolation oxide layer; Two sources are located in the silicon carbide substrate on both sides of the gate oxide layer in the first direction; as well as The drain contact metal is located on the opposite side of the silicon carbide substrate relative to the gate oxide layer.
2. The silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 1 further comprises two base electrodes located in the silicon carbide substrate outside the first direction and in direct contact with the two source electrodes.
3. The silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 2, wherein the two bases are heavily p-type doped regions.
4. The silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 1, wherein the two source poles are N-type heavily doped regions.
5. The silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 1, further comprising two P-type wells located in the silicon carbide substrate on both sides of the isolation oxide layer in the first direction, wherein the two sources are respectively located in the two P-type wells.
6. The silicon carbide metal oxide semiconductor field-effect transistor of claim 1, further comprising an N-type lightly doped drift region located in the silicon carbide substrate, wherein the gate oxide layer and the two sources are located on the N-type drift region.
7. The silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 1, wherein the two gates are made of N-type heavily doped polycrystalline silicon.
8. The silicon carbide metal oxide semiconductor field-effect transistor of claim 1, wherein the drain is a metal layer.
9. The silicon carbide metal oxide semiconductor field-effect transistor of claim 1, further comprising a passivation layer covering the two gates and the silicon carbide substrate.
10. The silicon carbide metal oxide semiconductor field-effect transistor of claim 9, further comprising a source contact metal located on the passivation layer and connecting the two sources.
11. A method for manufacturing a silicon carbide metal-oxide-semiconductor field-effect transistor, comprising: A silicon carbide substrate is provided, wherein two source electrodes are opposite each other in a first direction; A gate oxide layer is formed on the silicon carbide substrate between the two sources; A first gate material layer is formed on the gate oxide layer; The first photolithography process is used to pattern the first gate material layer into two lower gate patterns, which are located on the edge portions of the gate oxide layer on both sides of the first direction. An isolation oxide layer is formed between the two lower gate patterns; A second gate material layer is formed on the two lower gate patterns and the isolation oxide layer; as well as The second photolithography process is used to pattern the second gate material layer into two upper gate patterns. The two upper gate patterns are located on the two lower gate patterns and have extensions that extend inward in the first direction to the isolation oxide layer. The two upper gate patterns and the corresponding two lower gate patterns constitute the first gate and the second gate, respectively.
12. The method of manufacturing a silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 11, further comprising forming a drain contact metal on the side of the silicon carbide substrate opposite to the gate oxide layer.
13. The method for manufacturing a silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 11, further comprising forming base electrodes in the silicon carbide substrate on the outer side of the first direction, wherein the two base electrodes are in direct contact with the corresponding two source electrodes.
14. The method for manufacturing a silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 11, further comprising forming P-type wells in the silicon carbide substrate on both sides of the isolation oxide layer in the first direction, wherein the two sources are respectively located in the two P-type wells.
15. The method for manufacturing a silicon carbide metal-oxide-semiconductor field-effect transistor as claimed in claim 11, further comprising forming an N-type lightly doped drift region in the silicon carbide substrate, wherein the gate oxide layer and the two sources are located on the N-type drift region.
16. The method of manufacturing a silicon carbide metal-oxide-semiconductor field-effect transistor as claimed in claim 11, wherein the step of forming the isolation oxide layer between the two lower gate patterns comprises: An isolation material layer is formed on the two lower gate patterns and the silicon carbide substrate; and The third photolithography process removes the isolation material layer that is not located between the two lower gate patterns.
17. The method of manufacturing a silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 11, further comprising forming a passivation layer covering the first gate, the second gate, and the silicon carbide substrate.
18. The method for manufacturing a silicon carbide metal oxide semiconductor field-effect transistor as claimed in claim 17, further comprising forming a source contact metal on the passivation layer, the source contact metal connecting the two sources.