Simplified tellurium-cadmium-mercury detector chip processing method

Abstract

The invention discloses a simplified tellurium-cadmium-mercury detector chip processing method, and belongs to the technical field of semiconductor device manufacturing. The method comprises a marking process and an injection process, and synchronously completes Mark mark making, n-type MCT layer forming, and embedded whole-process data acquisition and real-time analysis; marking and injecting, synchronously completing Mark mark manufacturing and n-type MCT layer forming, and embedding full-process data acquisition and real-time analysis; the method directly reduces the use frequency of core equipment for photoetching, cleaning and the like, can improve the overall production efficiency, shortens the process circulation time, reduces the consumption of auxiliary materials and the manual operation cost, effectively solves the problems of redundant processes and high equipment occupancy rate of the traditional process, improves the equipment utilization rate, and reduces the production cost. According to the method, the equipment investment and maintenance cost are reduced, the process stability of batch production is further guaranteed by combining a quality control mechanism of whole-process data acquisition and real-time analysis, and the economic benefits and market competitiveness of enterprises are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically a simplified method for fabricating a mercury cadmium telluride detector chip. Background Technology

[0002] Mercury cadmium telluride (MCC) has become a key material in the field of infrared detection due to its core advantages of large absorption coefficient, high quantum efficiency, and continuously adjustable bandgap. The planar n-on-p structure MCC infrared detector chip is the mainstream product form in this field. From top to bottom, it includes a zinc cadmium telluride substrate, a p-type MCT absorption layer, an n-type MCT layer formed by ion implantation, a ZnS or CdTe / ZnS composite passivation layer, a Cr / Pt / Au composite metal contact layer, and an indium pillar interconnect layer. The various structures work together to realize the functions of infrared light absorption, signal conversion, and circuit interconnection.

[0003] However, existing processing techniques have significant technical flaws: On the one hand, the Mark process is only used as a positioning reference and is not a necessary structure for chip function, yet it occupies 1 / 5 of the entire processing flow, requiring core equipment such as photolithography, etching, and cleaning. This not only wastes equipment capacity but also increases the risk of chip contamination and damage due to the additional complete process, leading to a decrease in product yield. On the other hand, the n-type MCT layer formed by ion implantation only changes the electrical properties of the material without any visible morphological changes. Subsequent processes such as hole opening and metallization rely on Mark marking to achieve precise overlay, making this redundant process indispensable in traditional processes. The increased consumption of auxiliary materials, labor costs, and high equipment investment and maintenance costs brought about by multiple processes further restrict the economic benefits and market competitiveness of large-scale production.

[0004] To address the aforementioned technical shortcomings, a solution is proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a simplified method for fabricating mercury cadmium telluride detector chips to solve the problems mentioned above.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a simplified method for fabricating a mercury cadmium telluride detector chip, comprising the following steps:

[0007] S1, the marking and injection process, simultaneously completes the creation of Mark markers and the formation of n-type MCT layers, embedding full-process data acquisition and real-time analysis;

[0008] S2, the marking and injection process, simultaneously completes the creation of Mark markers and the formation of n-type MCT layers, embedding full-process data acquisition and real-time analysis;

[0009] S3, metallization process, based on Mark overlay, deposits a composite metal layer to form an electrode;

[0010] S4. Indium pillar fabrication: Precise positioning is achieved using Mark markers, followed by electroplating / evaporation to form interconnect indium pillars, thus completing chip fabrication.

[0011] Furthermore, the data recorded during the process of the Mark alignment marking region and Imp pixel functional region on the target detector chip passing through multiple key sub-stages are obtained, and these data are summarized into a labeled comprehensive dataset. Then, a single data normalization transformation is performed on the dataset to uniformly map data of different dimensions and different numerical ranges to the 0 and 1 intervals.

[0012] Furthermore, five standard pixels are randomly selected as reference regions in both the Mark alignment area and the Imp pixel function area. The reference regions are enlarged into pixel grid images and grayscale transformation is performed. The grayscale value of each pixel grid is collected and compared with the grayscale threshold. If the grayscale value of the current reference region is greater than or equal to the grayscale threshold, it is determined that the corresponding area is a residual area where the photoresist has not been removed and is marked as a valid graphic pixel grid. If the grayscale value of the current reference region is less than the grayscale threshold, it is determined that the corresponding area is an area where the photoresist has been removed and is marked as an invalid background pixel grid.

[0013] Furthermore, a standard grayscale image of a qualified wafer is retrieved from a preset process database as a reference. The current image is compared pixel by pixel with the corresponding reference area in the standard image. The effective graphic pixels that overlap between the current image and the standard image are marked as normal pixels. The total number of pixels in a single reference area in the standard image is counted. The number of normal pixels is subtracted from the total number of pixels to obtain the graphic offset value.

[0014] Analyze the absolute value of the difference between the two gray values ​​in each normal cell, then sum these absolute values ​​for all normal cells, and finally divide the sum by the total number of normal cells to obtain the color difference value of the image. Analyze the ratio of the color difference value to the maximum range of gray values, and then multiply it by the hidden defect weight. Add these two results together and subtract the sum from 1 to obtain the image quality coefficient.

[0015] Furthermore, the average value of the photoresist film thickness at several feature monitoring points is analyzed, and then the difference between the photoresist thickness value at each monitoring point and the average value is analyzed. Each difference is squared and summed. The sum is divided by the number of monitoring points, and the square root of the result is taken to obtain the standard deviation of the film thickness. Finally, the standard deviation is divided by the average film thickness to obtain the film thickness uniformity deviation. The pre-stored film thickness deviation threshold is retrieved and compared with the film thickness uniformity deviation: if the film thickness uniformity deviation is less than the film thickness deviation threshold, the photoresist film thickness uniformity is judged to be qualified; if the film thickness uniformity deviation is greater than or equal to the film thickness deviation threshold, the photoresist film thickness uniformity is judged to be unqualified.

[0016] Furthermore, the actual collected values ​​of developer concentration, temperature, and time are first converted into normalized values ​​between 0 and 1. The actual values ​​are then subtracted from the minimum allowable value of the process, and then divided by the difference between the maximum and minimum allowable values ​​of the process. The three normalized parameters are multiplied by their corresponding weights and summed. Finally, the sum is subtracted from 1 to obtain the stability deviation of the developer parameters.

[0017] The actual collected values ​​of beam intensity, energy, and time of ion implantation are converted into normalized values ​​between 0 and 1. The three normalized parameters are multiplied by their corresponding weights and summed. Then, the sum is subtracted from 1 to obtain the stability deviation of the implantation parameters.

[0018] Furthermore, weights are assigned to the film thickness uniformity deviation, the development parameter stability deviation, and the injection parameter stability deviation. First, the weights of (1 minus film thickness uniformity deviation) multiplied by the film thickness weight, (1 minus development parameter stability deviation) multiplied by the development weight, and (1 minus injection parameter stability deviation) multiplied by the injection weight are analyzed. After adding these three results, they are multiplied by the correction factor a to obtain the comprehensive process stability coefficient.

[0019] Furthermore, the entire exposure process is divided into 10 isochronous sub-time periods, each lasting 0.1 seconds. Four alignment deviation data are recorded for each sub-time period. The alignment deviation data include the X / Y axis deviation between the Mark and the wafer reference, and the X / Y axis overlay deviation between the Imp pattern and the Mark. For each sub-time period, the four alignment deviation data are squared, the four squared results are summed, and finally the square root of the sum is taken to obtain the positioning deviation index for each sub-time period.

[0020] Furthermore, the absolute value of the difference between the positioning deviation indexes of two adjacent sub-time periods is analyzed, and all these absolute values ​​of difference are organized into a deviation span set. The preset floating deviation span threshold is retrieved and set according to the positioning accuracy requirements of chip processing. The ratio of the floating deviation span value to the preset threshold is subtracted from 1 to obtain the positioning accuracy coefficient.

[0021] Furthermore, the graphic quality coefficient, process stability comprehensive coefficient, and positioning accuracy coefficient are weighted and calculated according to different weights to generate a comprehensive process evaluation coefficient. Based on the historical process data of several qualified wafers, three-level target data are generated through statistical analysis and compared with the comprehensive process evaluation coefficient to generate process excellent signal, process qualified signal, process fine-tuning signal, or process rework signal.

[0022] The beneficial effects of this invention are:

[0023] 1. This invention simplifies and innovates the process by integrating the traditionally separate Mark and Imp processes into a single integrated process. It simultaneously completes the alignment mark fabrication and n-type MCT layer formation through a single photolithography, etching, and ion implantation process, reducing the original five photolithography steps to four. This directly reduces the frequency of using core equipment such as photolithography and cleaning equipment, and is expected to improve overall production efficiency. It also shortens process turnaround time, reduces auxiliary material consumption and labor costs, and effectively solves the pain points of redundant processes and high equipment occupancy rates in traditional processes.

[0024] 2. This invention significantly reduces the probability of defects such as contamination and damage introduced at each stage by eliminating one complete photolithography process, which includes spin coating, exposure, development, etching, and resist removal. It is expected to improve product yield by 3-5%, which is of great significance for the manufacturing of expensive mercury cadmium telluride infrared detector chips. The simplified process reduces the occupation of expensive semiconductor equipment such as photolithography machines and cleaning equipment, improves equipment utilization, and reduces equipment investment and maintenance costs. Combined with a quality control mechanism of full-process data acquisition and real-time analysis, it further ensures the process stability of mass production and significantly improves the economic benefits and market competitiveness of enterprises. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of the method of the present invention;

[0027] Figure 2 This is a schematic diagram of the wafer lithography processing structure that simultaneously incorporates mark and imp lithography patterns according to the present invention.

[0028] Figure 3 This is a schematic diagram of the structure of the mercury cadmium telluride wafer after etching, which has both mark and imp lithography patterns according to the present invention.

[0029] Figure 4 This is a schematic diagram of the structure of the mercury cadmium telluride wafer pixel region after ion implantation according to the present invention.

[0030] Figure 5 This is a schematic diagram of the mercury cadmium telluride wafer structure after the mark & ​​imp process of this invention has been completed and the resist has been removed. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Example 1: Please refer to Figure 1 - Figure 5 As shown, this embodiment is a simplified method for fabricating a mercury cadmium telluride detector chip, including the following steps:

[0033] S1, the marking and implantation process, simultaneously completes the fabrication of the mark and the formation of the n-type MCT layer, embedding full-process data acquisition and real-time analysis; on the wafer after the passivation layer preparation, the marking and implantation photolithography is obtained through spin coating, exposure, and development, and then ZnS is removed by etching or etching to a depth of about 200nm to see the physical traces of the mark, thus forming the mark, such as... Figure 3 As shown; using an ion implanter to implant boron ions (B+), n-type MCT processing of the pixel area is achieved, such as... Figure 4 As shown; by immersing the wafer in acetone, the photoresist is removed according to the principle of similar compatibility, thus simultaneously completing the mark & ​​imp process, as follows. Figure 5 As shown;

[0034] S1.1 Based on the six key sub-processes in step S1, namely, homogenization, exposure, development, etching, ion implantation and resist removal, the data collection scope is used to obtain the data recorded during the process of the Mark alignment marking area and Imp pixel functional area on the target detector chip through multiple sets of key sub-processes, and summarize them into a labeled comprehensive dataset.

[0035] Among them, such as Figure 2 As shown, the Mark alignment marking area represents the cross-shaped reference area distributed on the edge region of the target detector chip, and the Imp pixel functional area represents the evenly spaced dots deployed in the central region of the target detector chip. The surface of the target detector chip is divided into six key sub-processing areas by marking. The nine feature points on the surface of the target detector chip are marked as key points for photoresist film thickness: one point at the center of the area, one point at each of the four corners, and four points at the midpoint of the edge. The center line of the cross marked by Mark and the boundary line of the Imp pixel array are marked as key lines for exposure pattern transfer. The cross intersection point marked by Mark and five random pixel centers in the Imp area are marked as etching depth monitoring points. The Imp area is divided into nine monitoring sub-regions according to a 3×3 grid and marked as ion implantation dose monitoring areas.

[0036] We acquire multiple core basic data points from the labeled comprehensive dataset and perform individual data normalization transformation on them, mapping data of different dimensions and numerical ranges to the 0 and 1 intervals using a formula. ,in, This represents the normalized result of the i-th basic data item, where i is a natural number greater than zero. This represents the actual collected value of the i-th basic data item. Let the minimum allowable value for the process be represented by the i-th data item. This represents the maximum allowable value for the process of the i-th data item. The closer the value is to 1, the closer the parameter is to the optimal value for the process. The closer the parameter is to 0, the closer it is to the critical value of the process, indicating a risk of defects.

[0037] S1.2. Randomly select five standard pixel areas in both the Mark alignment area and the Imp pixel function area, one at each of the four corners and the center, and mark them as reference areas. Enlarge the reference areas into pixel grid images and perform grayscale transformation. Collect the grayscale value of each pixel grid, with the grayscale value ranging from 0 to 255, where 0 is black and 255 is white. This reflects the outline sharpness and surface smoothness of the image after development. Determine the pre-stored grayscale threshold based on the optical characteristics of the photoresist after development. The grayscale threshold can be set to 128. Compare and analyze the grayscale value of each pixel grid with the grayscale threshold.

[0038] If the gray value of the current reference area is greater than or equal to the gray value threshold, then the area corresponding to the photoresist that has not been removed is determined to be a residual area and marked as a valid graphic pixel grid.

[0039] If the grayscale value of the current reference area is less than the grayscale threshold, it is determined that the corresponding area has had its photoresist removed and is marked as an invalid background pixel.

[0040] S1.3. Retrieve a standard grayscale image of a qualified wafer from the preset process database as a reference. Compare the corresponding reference area in the standard image with the currently acquired image pixel by pixel. Mark the effective graphic pixels that overlap between the current image and the standard image as normal pixels. Count the total number of pixels in a single reference area in the standard image. Subtract the number of normal pixels from the total number of pixels to obtain the graphic offset value. This value directly reflects the degree of incompleteness of the graphic after development. The larger the value, the higher the probability of the graphic having obvious defects such as missing corners or bridging.

[0041] All normal cells are marked, and their gray values ​​in the current image and the standard image are extracted respectively. The absolute value of the difference between the two gray values ​​of each normal cell is analyzed. Then, these absolute values ​​of all normal cells are summed. Finally, the sum is divided by the total number of normal cells to obtain the color difference value of the image. This value reflects the degree of blurring of the image edge and the residual hidden photoresist. The larger the value, the more serious the hidden defects caused by incomplete development or over-development.

[0042] Since explicit defects have a more direct impact on subsequent processes than implicit defects, different weights are assigned to them. The weight of the graphic offset value can be 0.7, and the weight of the graphic color difference value can be 0.3. All weight values ​​are greater than 0, and the weight of explicit defects is higher than that of implicit defects. The ratio of the graphic offset value to the total number of pixels in the reference area of ​​the standard image is analyzed and then multiplied by the weight of explicit defects.

[0043] Analyze the ratio of the color difference value to the maximum range of grayscale values ​​in the image, and then multiply it by the weight of latent defects. Add these two results together and subtract the sum from 1 to obtain the image quality coefficient. The value of this coefficient ranges from 0 to 1. The closer the value is to 1, the better the image quality. If the value is less than 0.7, the image is judged to have serious defects.

[0044] S1.4. Photoresist thickness values ​​are collected at 9 feature monitoring points. Each feature monitoring point is collected 3 times consecutively, and the average value is taken. The difference between the center point and the edge point of each feature monitoring point is obtained, reflecting the film thickness uniformity. This data is summarized and labeled as photoresist film thickness distribution data (JMF). The average photoresist film thickness at the 9 feature monitoring points is analyzed. Then, the difference between the photoresist thickness value at each monitoring point and the average value is analyzed. Each difference is squared and summed. The sum is divided by the number of monitoring points, and the square root of the result is taken to obtain the standard deviation of the film thickness. Finally, the standard deviation is divided by the average film thickness to obtain the film thickness uniformity deviation. The pre-stored film thickness deviation threshold is retrieved and compared with the film thickness uniformity deviation. If the film thickness uniformity deviation is less than the film thickness deviation threshold, the photoresist film thickness uniformity is considered acceptable. If the film thickness uniformity deviation is greater than or equal to the film thickness deviation threshold, the photoresist film thickness uniformity is considered unacceptable.

[0045] S1.5 First, convert the actual collected values ​​of developer concentration, temperature, and time into normalized values ​​between 0 and 1. Subtract the minimum allowable value from the actual value, and then divide by the difference between the maximum and minimum allowable values. Assign different weights to the three parameters, with concentration weighted at 0.4, temperature weighted at 0.3, and time weighted at 0.3. Multiply the normalized three parameters by their corresponding weights and sum them. Subtract the sum from 1 to obtain the developer parameter stability deviation. Retrieve the pre-stored developer parameter threshold and compare it with the developer parameter stability deviation. If the developer parameter stability deviation is less than the developer parameter threshold, the developer parameter stability is considered acceptable. If the developer parameter stability deviation is greater than or equal to the developer parameter threshold, the developer parameter stability is considered unacceptable.

[0046] S1.6. Convert the actual collected values ​​of beam intensity, energy, and time during ion implantation into normalized values ​​between 0 and 1. Assign weights to the three parameters, with beam intensity weighted at 0.5, energy weighted at 0.3, and time weighted at 0.2. Multiply the normalized three parameters by their respective weights and sum them. Subtract the sum from 1 to obtain the implantation parameter stability deviation. Retrieve the pre-stored implantation parameter threshold and compare it with the implantation parameter stability deviation: if the implantation parameter stability deviation is less than the implantation parameter threshold, the implantation parameter stability is considered acceptable; if the implantation parameter stability deviation is greater than or equal to the implantation parameter threshold, the implantation parameter stability is considered unacceptable.

[0047] S1.7. Weights are assigned to film thickness uniformity deviation, developing parameter stability deviation, and injection parameter stability deviation, respectively. The weight for film thickness uniformity deviation is 0.3, the weight for developing parameter stability deviation is 0.4, and the weight for injection parameter stability deviation is 0.3. A correction factor 'a' with a value of 1.05 is introduced to compensate for the impact of equipment system errors on the results. First, the results of (1 minus film thickness uniformity deviation) multiplied by film thickness weight, (1 minus developing parameter stability deviation) multiplied by developing weight, and (1 minus injection parameter stability deviation) multiplied by injection weight are analyzed. These three results are then added together and multiplied by the correction factor 'a' to obtain the comprehensive process stability coefficient. The value of this coefficient ranges from 0 to 1.05. The closer the value is to 1.05, the better the process stability.

[0048] S1.8 Divide the entire exposure process into 10 isochronous sub-time periods, each with a duration of 0.1 seconds. Record four alignment deviation data within each sub-time period. The alignment deviation data include the X / Y axis deviation between the Mark and the wafer reference, and the X / Y axis overlay deviation between the Imp pattern and the Mark.

[0049] For each sub-time period, the four alignment deviation data are squared separately, the four squared results are summed, and the square root of the sum is taken to obtain the positioning deviation index for each sub-time period. The positioning deviation index comprehensively reflects the positioning accuracy of the image transfer at a single moment. The smaller the value, the more accurate the positioning.

[0050] Plot the positioning deviation index variation curve with the sub-time period number as the horizontal axis and the positioning deviation index of each sub-time period as the vertical axis; analyze the absolute value of the difference between the positioning deviation indices of two adjacent sub-time periods, organize all these absolute values ​​of difference into a deviation span set, find the maximum and minimum values ​​in the set, and subtract the minimum value from the maximum value to obtain the floating deviation span value.

[0051] Retrieve the preset floating deviation span threshold, which can be set to 5nm, based on the positioning accuracy requirements of chip processing. Subtract the ratio of the floating deviation span value to the preset threshold from 1 to obtain the positioning accuracy coefficient. The value of this coefficient ranges from 0 to 1.

[0052] When the floating deviation span value is less than or equal to the preset threshold, the coefficient is greater than or equal to 0, and the positioning accuracy is judged to be qualified.

[0053] When the floating deviation span value is greater than the preset threshold, the coefficient is less than 0, indicating that the positioning accuracy is seriously abnormal.

[0054] S1.9 The graphic quality coefficient, process stability comprehensive coefficient, and positioning accuracy coefficient are weighted and calculated to generate a comprehensive process evaluation coefficient. The weights are set according to the degree of influence of each dimension on the process quality: graphic quality directly affects the subsequent overlay accuracy, with a weight of 0.4; process stability determines the consistency of batch production, with a weight of 0.35; positioning accuracy affects the matching degree of functional areas, with a weight of 0.25. If the positioning accuracy coefficient is negative, it is counted as 0. That is, when the positioning is seriously abnormal, the comprehensive coefficient is directly lowered. The graphic quality coefficient is multiplied by 0.4, the process stability comprehensive coefficient is multiplied by 0.35, and the positioning accuracy coefficient (if negative, it is taken as 0) is multiplied by 0.25 to finally obtain the comprehensive process evaluation coefficient. The value of this coefficient is between 0 and 1.05. The larger the value, the better the comprehensive quality of the S1 process.

[0055] S1.10. Based on the historical process data of 1000 qualified wafers, three-level target data are generated through statistical analysis as a benchmark for subsequent comparison. The 95th percentile of the comprehensive process evaluation coefficient in the historical data of 1000 qualified wafers is extracted and set to 1.00. This value represents the ideal process level of the S1 process, corresponding to a processing state with no defects, high stability, and high precision.

[0056] Extract the 75th percentile of the comprehensive process evaluation coefficient from the historical data, and take the value of 0.85. This value represents the pass / fail threshold of process S1, corresponding to a processing state with slight deviations that is compatible with subsequent processes.

[0057] Extract the quintile of the comprehensive process evaluation coefficient from the historical data, and set it to 0.70. This value represents the rework threshold of process S1, corresponding to a processing state with significant deviations that requires rework and repair.

[0058] S1.11. When the comprehensive process evaluation coefficient is greater than or equal to the optimal target value of 1.00, and the pattern quality coefficient is greater than or equal to 0.95, the comprehensive process stability coefficient is greater than or equal to 1.00, and the positioning accuracy coefficient is greater than or equal to 0.90, a process excellence signal is generated. This process excellence signal indicates that the S1 process has completely reached the ideal state, the Mark marker and Imp pattern are defect-free, the process parameters are stable, and the positioning accuracy is extremely high. Keeping all current process parameters unchanged, the parameter combination is solidified into a baseline process parameter package. The parameter package is synchronized to the production management system as the baseline parameters for the mass production of the same type of chip. Every 50 wafers produced, the core process parameters are reviewed to ensure the process stability during the mass production process.

[0059] S1.12 When the comprehensive process evaluation coefficient is greater than or equal to the qualified target value of 0.85 and less than the optimal target value of 1.00, and the data of the three dimensions are not lower than their respective critical values, a process qualification signal is generated. The process qualification signal indicates that the S1 process meets the requirements of the subsequent process, and there is a slight deviation but it does not affect the core function. Minor corrections are made to the weak items of the three dimensions of graphic quality, process stability and positioning accuracy, without changing the core process parameters.

[0060] S1.13 When the comprehensive process evaluation coefficient is greater than or equal to the critical target value of 0.70 and less than the qualified target value of 0.85, or when the single dimension data is lower than the critical value, such as the graphic quality coefficient being less than 0.70, the comprehensive process stability coefficient being less than 0.80, or the positioning accuracy coefficient being less than 0.70, a process fine-tuning signal is generated. The process fine-tuning signal indicates that there are local defects in the S1 process, and the process parameters need to be adjusted accordingly.

[0061] When the comprehensive process evaluation coefficient is less than the critical target value of 0.70, or when two or more dimensions of data are below the critical value, a process rework signal is generated. The process rework signal indicates that there is a serious defect in the S1 process, and the Mark markers and n-type MCT layers processed in sync do not meet the design requirements and need to be reworked.

[0062] Example 2: S2, Opening process: Based on the Mark mark generated in S1, the passivation layer is removed to form a contact hole; according to the relative position of the Mark mark prepared in the previous step, the opening pattern is formed on the passivation layer by homogenization, exposure, and development; the ZnS passivation layer is removed by wet etching or etching to expose the underlying MCT layer; finally, the photoresist is removed to obtain the area where the MCT and UBM can contact.

[0063] S2.1. Based on the Mark mark positioning data and comprehensive process evaluation coefficient generated in S1, dynamically adjust the aperture process parameters. If the S1 process generates an excellent or qualified process signal, use standard aperture parameters, specifically: spin coating speed 2800 rpm, exposure dose 80 mJ / cm², etchant concentration 6%, and etching time 40 seconds. If the S1 process generates a process fine-tuning signal, correct the etching time according to the Mark mark etching depth data. If the etching depth is 10 nm lower than the target value (200 nm), extend the etching time by 3 seconds to ensure sufficient removal of the passivation layer.

[0064] S3. Metallization process: Based on mark overlay, a composite metal layer is deposited to form an electrode; according to the relative position of the mark, a UBM pattern is formed by spin coating, exposure, and development; a composite metal layer such as Cr / Pt / Au is deposited by magnetron sputtering or electron beam evaporation; and a metal electrode is formed by a lift-off process.

[0065] S3.1. Based on the Imp pattern opening size deviation data and comprehensive process evaluation coefficient from process S1, optimize the metal deposition parameters. If the Imp pattern opening size deviation does not exceed 3% and the comprehensive process evaluation coefficient is greater than or equal to 0.85, adopt the standard magnetron sputtering parameters, specifically Cr target power 100W, Pt target power 120W, Au target power 150W, and metal deposition rate 1nm / s. If the Imp pattern opening size deviation is between 3% and 8% and the comprehensive process evaluation coefficient is greater than or equal to 0.70, reduce the metal deposition rate to 0.8nm / s and extend the deposition time accordingly to ensure that the metal layer completely covers the contact hole and ensures the contact effect between the electrode and the MCT layer.

[0066] S4. Indium pillar fabrication: Precisely positioned according to the Mark markers, indium pillars are formed by electroplating / evaporation to complete chip fabrication; Based on the relative positions of the Mark markers, indium pillar patterns are formed through photoresist coating, exposure, and development; indium pillars are fabricated by electroplating or evaporation; finally, the photoresist is removed to complete chip fabrication.

[0067] S4.1. Referencing the positioning deviation data and comprehensive process evaluation coefficient of process S1, calibrate the indium pillar forming parameters: If the positioning deviation data of process S1 does not exceed 20nm and the comprehensive process evaluation coefficient is greater than or equal to 0.85: adopt the standard electroplating parameters, specifically a current density of 15mA / cm² and an electroplating time of 12 minutes; If the positioning deviation data of process S1 is between 20-50nm and the comprehensive process evaluation coefficient is greater than or equal to 0.70: add positioning compensation parameters to the electroplating pattern mask, with a compensation amount of 50% of the positioning deviation value, to correct the forming position of the indium pillar.

[0068] The above description is merely an example and illustration of the structure of the present invention. Those skilled in the art can make various modifications or additions to the specific embodiments described, or use similar methods to replace them, as long as they do not deviate from the structure of the invention or exceed the scope defined in the claims, all of which should fall within the protection scope of the present invention.

[0069] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0070] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A simplified method for fabricating a mercury cadmium telluride detector chip, characterized in that, Includes the following steps: S1, the marking and injection process, simultaneously completes the creation of Mark markers and the formation of n-type MCT layers, embedding full-process data acquisition and real-time analysis; S2, the marking and injection process, simultaneously completes the creation of Mark markers and the formation of n-type MCT layers, embedding full-process data acquisition and real-time analysis; S3, metallization process, based on Mark overlay, deposits a composite metal layer to form an electrode; S4. Indium pillar fabrication: Precise positioning is achieved using Mark markers, followed by electroplating / evaporation to form interconnect indium pillars, thus completing chip fabrication.

2. The simplified method for fabricating a mercury cadmium telluride detector chip according to claim 1, characterized in that, Data recorded during multiple key sub-steps in the Mark alignment marking region and Imp pixel functional region on the target detector chip are acquired and summarized into a labeled comprehensive dataset. Single data normalization transformation is then performed on the dataset to uniformly map data of different dimensions and numerical ranges to the 0 and 1 intervals.

3. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 1, characterized in that, Five standard pixels are randomly selected as reference areas in the Mark alignment area and Imp pixel function area respectively. The reference areas are enlarged into pixel grid images and grayscale transformation is performed. The grayscale value of each pixel grid is collected and compared with the grayscale threshold. If the grayscale value of the current reference area is greater than or equal to the grayscale threshold, it is determined that the area corresponds to the residual area of ​​photoresist that has not been removed and is marked as a valid graphic pixel grid. If the grayscale value of the current reference area is less than the grayscale threshold, it is determined that the corresponding area has had its photoresist removed and is marked as an invalid background pixel.

4. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 3, characterized in that, The standard grayscale image of a qualified wafer is retrieved from the preset process database as a reference. The current image is compared pixel by pixel with the corresponding reference area in the standard image. The effective graphic pixels that overlap between the current image and the standard image are marked as normal pixels. The total number of pixels in a single reference area in the standard image is counted. The number of normal pixels is subtracted from the total number of pixels to obtain the graphic offset value. Analyze the absolute value of the difference between the two gray values ​​in each normal cell, then sum these absolute values ​​for all normal cells, and finally divide the sum by the total number of normal cells to obtain the color difference value of the image. Analyze the ratio of the color difference value to the maximum range of gray values, and then multiply it by the hidden defect weight. Add these two results together and subtract the sum from 1 to obtain the image quality coefficient.

5. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 1, characterized in that, Analyze the average value of the photoresist film thickness at several feature monitoring points, then analyze the difference between the photoresist thickness value at each monitoring point and the average value. Square each difference and sum them. Divide the sum by the number of monitoring points and take the square root of the result to obtain the standard deviation of the film thickness. Finally, divide the standard deviation by the average film thickness to obtain the film thickness uniformity deviation. Retrieve the pre-stored film thickness deviation threshold and compare it with the film thickness uniformity deviation: if the film thickness uniformity deviation is less than the film thickness deviation threshold, the photoresist film thickness uniformity is considered qualified; if the film thickness uniformity deviation is greater than or equal to the film thickness deviation threshold, the photoresist film thickness uniformity is considered unqualified.

6. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 1, characterized in that, First, convert the actual collected values ​​of developer concentration, temperature, and time into normalized values ​​between 0 and 1. Subtract the minimum value allowed by the process from the actual value, and then divide by the difference between the maximum and minimum values ​​allowed by the process. Multiply the three normalized parameters by their corresponding weights and sum them. Then subtract the sum from 1 to obtain the stability deviation of the developer parameters. The actual collected values ​​of beam intensity, energy, and time of ion implantation are converted into normalized values ​​between 0 and 1. The three normalized parameters are multiplied by their corresponding weights and summed. Then, the sum is subtracted from 1 to obtain the stability deviation of the implantation parameters.

7. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 6, characterized in that, Weights are assigned to film thickness uniformity deviation, development parameter stability deviation, and injection parameter stability deviation. First, the results of (1 minus film thickness uniformity deviation) multiplied by film thickness weight, (1 minus development parameter stability deviation) multiplied by development weight, and (1 minus injection parameter stability deviation) multiplied by injection weight are analyzed. These three results are then added together and multiplied by the correction factor a to obtain the comprehensive process stability coefficient.

8. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 7, characterized in that, The entire exposure process was divided into 10 isochronous sub-time periods, each lasting 0.1 seconds. Four alignment deviation data were recorded for each sub-time period. The alignment deviation data included the X / Y axis deviation between the Mark and the wafer reference, and the X / Y axis overlay deviation between the Imp pattern and the Mark. For each sub-time period, the four alignment deviation data were squared, the four squared results were summed, and the square root of the sum was taken to obtain the positioning deviation index for each sub-time period.

9. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 8, characterized in that, Analyze the absolute value of the difference between the positioning deviation index of two adjacent sub-time periods, organize all these absolute values ​​of difference into a deviation span set, retrieve the preset floating deviation span threshold, set it according to the positioning accuracy requirements of chip processing, and subtract the ratio of the floating deviation span value to the preset threshold from 1 to obtain the positioning accuracy coefficient.

10. A simplified method for fabricating a mercury cadmium telluride detector chip according to claim 1, characterized in that, The graphic quality coefficient, process stability coefficient, and positioning accuracy coefficient are weighted and calculated according to different weights to generate a comprehensive process evaluation coefficient. Based on the historical process data of several qualified wafers, three-level target data are generated through statistical analysis and compared with the comprehensive process evaluation coefficient to generate process excellent signal, process qualified signal, process fine-tuning signal, or process rework signal.

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