Chip, wafer, electronic equipment and manufacturing method of chip
By matching the thermal expansion coefficient of the package with that of the substrate, the wafer warpage problem was solved, the chip processing accuracy and yield were improved, the chip became thinner and more stable, and its lifespan was extended.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HONOR DEVICE CO LTD
- Filing Date
- 2024-09-30
- Publication Date
- 2026-04-14
AI Technical Summary
During chip manufacturing, the difference in thermal expansion coefficients of different materials can cause wafer warping, affecting processing accuracy and yield, and making it difficult to achieve chip thinning and mounting on circuit boards.
The package adopts a design with a thermal expansion coefficient similar to that of the substrate, so that the thermal expansion coefficients of the package and the substrate are on the same order of magnitude. Functional layers and redistribution layers are set in the package to prevent wafer warping, and stable connection between the chip and the circuit board is achieved through soldering material layers and conductive components.
It improves chip processing precision and yield, reduces warpage, enables chip thinning, enhances protection against external environments, and extends service life.
Smart Images
Figure CN121865950A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more particularly to a chip, wafer, electronic device, and a method for manufacturing the chip. Background Technology
[0002] Chips are essential electronic components widely used in electronic devices. In chip manufacturing, wafer dicing is typically used for mass production. Because the circuit layers within a wafer are usually formed using multiple materials with significantly different coefficients of thermal expansion, the inconsistent thermal expansion of these materials during chip fabrication can cause wafer warping. This warping affects the chip's processing precision and ultimately its yield. Summary of the Invention
[0003] This application provides a chip, a wafer, an electronic device, and a method for manufacturing the chip, which addresses the problem of how to improve the processing accuracy of chips.
[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:
[0005] In a first aspect, embodiments of this application provide a chip, which includes a substrate, a functional layer, a redistribution layer, and a package. The substrate includes a first surface and a second surface facing away from each other. The functional layer is disposed on the first surface. The redistribution layer is stacked on the side of the functional layer facing away from the second surface and is electrically connected to the functional layer. The package has a third surface facing the first surface, and the third surface has a groove. The package is bonded to the substrate, and the functional layer and the redistribution layer are located within the groove. The thermal expansion coefficient of the package is on the same order of magnitude as that of the substrate.
[0006] The chip provided in this application embodiment has a similar coefficient of thermal expansion between the package and the substrate. This ensures that during the wafer dicing process to form the chip, the thermal expansion of the package structure (wafer package) matches that of the substrate structure (wafer substrate). This mitigates the problem of wafer warpage caused by the significant difference in thermal expansion between the redistribution layer and the wafer substrate. This helps ensure the accuracy of wafer alignment before dicing and the accuracy of chip dicing, thereby guaranteeing chip processing precision and yield. It also reduces the difficulty of mounting the chip to other components (such as circuit boards). Furthermore, it allows for setting the dicing path on the package structure (wafer package) during wafer dicing. Since the wafer package does not delaminate, it prevents chip damage caused by delamination at the dicing interface, further ensuring chip yield.
[0007] Furthermore, reduced wafer warpage also helps to reduce substrate thickness, thereby enabling chip thinning. Finally, since the functional layer and redistribution layer are located within the recesses of the package, the package can protect these layers, preventing external moisture and dust from entering and damaging the chip, thus extending its lifespan.
[0008] In some possible implementations of the first aspect, the package further has a fourth surface opposite to the third surface, and the package further has a first through-hole penetrating the groove wall and the fourth surface. The redistribution layer has a first conductive element. The chip also includes a second conductive element, at least a portion of which is disposed within the first through-hole, one end of which is fixed to and electrically connected to the first conductive element, and the other end is exposed on the fourth surface.
[0009] In this way, the functional layer of the chip can be electrically connected to other components outside the package through the redistribution layer and the second conductive element, so as to facilitate the transmission of electrical signals between the chip and other components.
[0010] In some possible implementations of the first aspect, the second conductive element is a metallic structure. The chip also includes a solder layer connecting the second conductive element and the first conductive element.
[0011] In this way, the first and second conductive components are fixed and electrically connected by welding material layers, resulting in a strong connection between them that can withstand significant stress concentration. Furthermore, the connection is achieved simply by heating the welding material to melt it, simplifying the process and increasing chip manufacturing efficiency.
[0012] In some possible implementations of the first aspect, the chip also includes a welding structure disposed on the fourth surface and fixed to and electrically connected with the second conductive element.
[0013] In this way, the chip can be electrically connected to other components (such as circuit boards) through a soldering structure, resulting in a better connection strength between the chip and other components, and the ability to withstand greater stress concentration.
[0014] In some possible implementations of the first aspect, along the stacking direction of the functional layer and the redistribution layer, the projections of the second conductive element and the welding structure on the functional layer are all located within the functional layer.
[0015] In this way, the signal travels along the functional layer, redistribution layer, second conductive element and solder structure to other components (such as circuit board) connected to the chip, which reduces losses and ensures the quality of signal transmission.
[0016] In some possible implementations of the first aspect, the chip further includes a metal layer. The metal layer is disposed on the third surface and located on the periphery of the groove, and the metal layer is bonded to the substrate.
[0017] In some possible implementations of the first aspect, a metal layer is disposed on the first surface and located on the periphery of the functional layer, and the metal layer is bonded to the package body.
[0018] In some possible implementations of the first aspect, the material of the metal layer includes at least one of gold, germanium, aluminum, tin, and indium.
[0019] This bonding method results in a compact package with high thermal stability, mechanical strength, and good thermal conductivity, facilitating the timely dissipation of heat generated during chip operation. Furthermore, using a metal layer to bond the substrate and package requires a lower bonding temperature, is easier to implement, and has less impact on wafer warpage.
[0020] In some possible implementations of the first aspect, the absolute value of the difference between the thermal expansion coefficient of the package and the thermal expansion coefficient of the substrate is less than 10 × 10⁻⁶. -6 / ℃. In this way, both the thermal expansion coefficient of the package and the thermal expansion coefficient of the substrate are relatively small, resulting in less deformation when heated. During the chip fabrication process, the wafer warpage is also small, which can further ensure the chip processing accuracy and yield.
[0021] In some possible implementations of the first aspect, the substrate material includes at least one of silicon, silicon nitride, silicon carbide, gallium arsenide, gallium nitride, and glass ceramic.
[0022] In some possible implementations of the first aspect, the material of the package includes at least one of silicon, silicon nitride, silicon carbide, gallium arsenide, gallium nitride, and glass ceramic.
[0023] In some possible implementations of the first aspect, the substrate is made of at least one of silicon, silicon nitride, silicon carbide, gallium arsenide, gallium nitride, and glass ceramic; the package is made of at least one of silicon, silicon nitride, silicon carbide, and glass ceramic.
[0024] In some possible implementations of the first aspect, the package and the substrate are made of the same material. This facilitates material sourcing and design, improving chip manufacturing efficiency. Furthermore, the identical coefficients of thermal expansion between the package and the substrate help prevent wafer warping during chip fabrication.
[0025] In some possible implementations of the first aspect, the package also has a fourth surface opposite to the third surface. The distance between the second and fourth surfaces is less than or equal to 50 micrometers.
[0026] Secondly, embodiments of this application provide a wafer comprising a wafer substrate, multiple functional layers, multiple redistribution layers, and a wafer package. The multiple functional layers are spaced apart on one surface of the wafer substrate. A redistribution layer is stacked on the side of a functional layer facing away from the wafer substrate and is electrically connected to the functional layer. The wafer package is bonded to the wafer substrate; the surface of the wafer package facing the wafer substrate has multiple grooves, each groove accommodating one functional layer and one redistribution layer, with a dicing path between adjacent grooves; the coefficient of thermal expansion of the wafer package is on the same order of magnitude as that of the wafer substrate. The dicing path divides the wafer into multiple chip units.
[0027] Since the wafer provided in this application embodiment is used to cut and form the chip as described above, both can solve the same problem and achieve the same effect, which will not be repeated here.
[0028] In some possible implementations of the second aspect, the spacing between two adjacent grooves is greater than or equal to 60 micrometers.
[0029] Thirdly, embodiments of this application provide an electronic device, which includes a chip and a circuit board. The chip is the chip described in any of the above implementations. The chip is disposed on the circuit board.
[0030] Since the electronic device provided in this application embodiment includes the chip described in the above implementation, both can solve the same problem and achieve the same effect, and will not be described again here.
[0031] Fourthly, embodiments of this application provide a method for fabricating a chip packaging structure, comprising: providing a structure to be packaged, the structure including a wafer substrate blank, a plurality of spaced functional layers disposed on one surface of the wafer substrate blank, and a redistribution layer disposed on the surface of a functional layer opposite to the wafer substrate blank, the redistribution layer being electrically connected to the functional layers; providing a package structure including a wafer package, a plurality of spaced grooves on one surface of the wafer package; the thermal expansion coefficient of the wafer package is on the same order of magnitude as that of the wafer substrate blank; bonding the wafer package to the wafer substrate blank to obtain a first wafer structure; wherein the opening of the groove faces the wafer substrate blank, and one groove accommodates one functional layer and one redistribution layer; dicing the first wafer structure along a dicing path to obtain a plurality of chips; wherein the dicing path is located on the periphery of the groove, a portion of the wafer substrate blank forms the substrate of the chip, a portion of the wafer package forms the package of the chip, and the chip has one functional layer and one redistribution layer.
[0032] The chip fabrication method provided in this application has the advantage that, since the thermal expansion coefficients of the wafer package and the wafer substrate are similar, the degree of thermal expansion of the wafer package and the wafer substrate is consistent when heat is generated during wafer dicing to form the chip. This mitigates the problem of wafer warpage caused by the large difference in thermal expansion between the redistribution layer and the wafer substrate, thus ensuring the accuracy of wafer alignment before dicing and the accuracy of chip dicing, thereby guaranteeing chip processing precision and yield. It also reduces the difficulty of mounting the formed chip to other components (such as circuit boards). Furthermore, it facilitates setting the dicing path on the wafer package during wafer dicing to form the chip. Since the wafer package does not delaminate, it prevents chip damage caused by delamination at the dicing interface, further ensuring chip yield. Additionally, reduced wafer warpage also helps to reduce the thickness of the wafer substrate, thereby achieving chip thinning.
[0033] In some possible implementations of the fourth aspect, providing a package structure includes: providing a wafer package having a plurality of spaced grooves on one surface; forming a wafer metal layer on one surface of the wafer package, the wafer metal layer being located around the grooves; and bonding the wafer package to a wafer substrate blank to obtain a first wafer structure, including: bonding the wafer metal layer to the wafer substrate blank.
[0034] In some possible implementations of the fourth aspect, providing the structure to be packaged includes: providing a wafer substrate blank; forming a plurality of spaced functional layers and a plurality of redistribution layers on one surface of the substrate blank; forming a wafer metal layer on one surface of the wafer substrate blank, the wafer metal layer being located around the functional layers; and bonding a wafer package to the wafer substrate blank to obtain a first wafer structure, including: bonding the wafer metal layer to the wafer package.
[0035] This bonding method results in a compact package with high thermal stability, mechanical strength, and good thermal conductivity, which helps to dissipate heat generated during chip processing. Furthermore, using a metal layer to bond the wafer substrate and wafer package requires a lower bonding temperature, is easier to implement, and has less impact on wafer warpage.
[0036] In some possible implementations of the fourth aspect, the redistribution layer has a first conductive element on which solder material is disposed. Providing the package structure includes: providing a wafer package blank; forming a plurality of spaced grooves on the wafer package blank; forming a first through-hole on the bottom wall of the groove, the first through-hole penetrating the surface of the package blank opposite to the bottom wall of the groove to obtain a wafer package; and disposing of a second conductive element within the first through-hole, the second conductive element being a metal structural component, one end of the second conductive element being exposed on the surface of the wafer package opposite to the bottom wall of the groove. Before dicing the first wafer structure along a dicing path to obtain multiple chips, the method further includes: melting the solder material to connect the first conductive element and the second conductive element. This results in a better connection strength between the first and second conductive elements, capable of withstanding greater stress concentration.
[0037] In some possible implementations of the fourth aspect, the redistribution layer has a first conductive element. Providing the package structure includes: providing a wafer package blank; forming a plurality of spaced-apart grooves on the wafer package blank; forming a first through-hole on the bottom wall of the groove, the first through-hole penetrating a surface of the package blank opposite to the bottom wall of the groove to obtain a wafer package. After bonding the wafer package to a wafer substrate blank to form a first wafer structure, and before dicing the first wafer structure along a dicing path to obtain multiple chips, the method further includes: filling the first through-hole with a conductive material to form a second conductive element, and fixing and electrically conducting the second conductive element to the first conductive element, with one end of the second conductive element away from the first conductive element exposed on the surface of the wafer package opposite to the bottom wall of the groove.
[0038] This prevents the risk of the bonding material layer remelting due to excessively high bonding temperature during the bonding of the wafer package and the wafer substrate, allowing for flexible selection of the bonding temperature and reducing the difficulty of chip manufacturing.
[0039] In some possible implementations of the fourth aspect, the method further includes: providing a welding structure on the surface of the wafer package opposite to the bottom wall of the trench, and fixing the welding structure to the second conductive element and making it electrically conductive.
[0040] In some possible implementations of the fourth aspect, after setting multiple welding structures on the surface of the wafer package opposite to the bottom wall of the trench, and before cutting the first wafer structure along the cutting path to obtain multiple chips, the method further includes: thinning the wafer substrate blank. Attached Figure Description
[0041] Figure 1 Schematic diagrams of the structure of electronic devices provided in some embodiments of this application;
[0042] Figure 2 for Figure 1A partial structural diagram of the electronic device shown;
[0043] Figure 3 for Figure 1 and Figure 2 A schematic diagram of a chip structure in the electronic device shown.
[0044] Figure 4 This application provides a schematic diagram of the structure of a wafer for some embodiments;
[0045] Figure 5 for Figure 1 and Figure 2 Another schematic diagram of the chip structure of the electronic device shown;
[0046] Figure 6 for Figure 1 and Figure 2 Another schematic diagram of the chip structure of the electronic device shown;
[0047] Figure 7 for Figure 1 and Figure 2 Another schematic diagram of the chip structure of the electronic device shown;
[0048] Figure 8 This is a schematic diagram of the wafer structure provided in other embodiments of this application;
[0049] Figure 9 for Figure 5 One of the structural schematic diagrams of a chip fabrication method is shown;
[0050] Figure 10 for Figure 5 The second schematic diagram of a chip manufacturing method is shown.
[0051] Figure 11 for Figure 5 One of the schematic diagrams of another method for fabricating the chip shown;
[0052] Figure 12 for Figure 5 Another structural schematic diagram of the chip manufacturing method shown;
[0053] Figure 13 for Figure 6 One of the structural schematic diagrams of the chip fabrication method shown;
[0054] Figure 14 for Figure 6 The second schematic diagram of the chip manufacturing method shown.
[0055] Figure label:
[0056] 100 - Electronic devices;
[0057] 10 - Shell;
[0058] 20 - Circuit board;
[0059] 30-Chip; 31-Substrate; 31a-First surface; 31b-Second surface; 32-Functional layer; 33-Redistribution layer; 331-Insulating layer; 332-Metal pattern layer; 333-First conductive element; 34-Bond structure; 35-Passivation layer; 35a-Second via; 351-First metal pad; 36-Package; 36a-Third surface; 36a1-Groove; 36b-Fourth surface; 36c-First via; 37-Second conductive element; 371-Embedded portion; 372-Connection portion; 38-Bond material layer; 38A-Bond material; 39-Metal layer;
[0060] 200 - Wafer; 200A - Structure to be packaged; 200B - Package structure; 200C - First wafer structure; 210 - Wafer substrate; 210A - Wafer substrate blank; 220 - Wafer functional layer; 230 - Wafer redistribution layer; 240 - Wafer passivation layer; 250 - Wafer package; 250A - Wafer package blank; 260 - Wafer metal layer. Detailed Implementation
[0061] In the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation" and "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.
[0062] In the embodiments of this application, it should be understood that the directional terms mentioned, such as "up", "down", "left", "right", "inner", "outer", etc., are only for reference to the direction of the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.
[0063] In the embodiments of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," "third," and "fourth" may explicitly or implicitly include one or more of that feature.
[0064] In embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0065] In the embodiments of this application, "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.
[0066] In the embodiments of this application, it should be noted that the descriptions of "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range. This error range can be a range with a deviation angle of less than or equal to 5°, 8° or 10° relative to absolute verticality and absolute parallelism, respectively, and is not specifically limited here.
[0067] This application provides an electronic device, including but not limited to mobile phones, tablet computers, laptop computers, personal digital assistants (PDAs), personal computers, laptops, in-vehicle devices, wearable devices, servers, and base stations. Wearable devices include, but are not limited to, smart bracelets, smartwatches, smart head-mounted displays, and smart glasses. This application does not impose any special limitations on the specific form of this electronic device.
[0068] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of an electronic device 100 provided in some embodiments of this application. Figure 2 for Figure 1 The diagram shows a partial structural schematic of the electronic device 100. The electronic device 100 may include a housing 10, a circuit board 20, and a chip 30. The circuit board 20 and the chip 30 are disposed within the housing 10, which protects the circuit board 20, the chip 30, and other components of the electronic device 100.
[0069] The circuit board 20 can be fixed inside the housing 10 by means of snap-fit, threaded connection, or adhesive bonding. The circuit board 20 can be the main circuit board of the electronic device 100. The circuit board 20 is used to house electronic components, which can be electrically connected to the circuit board 20. The electronic components can include multiple chips 30, including but not limited to system on a chip (SoC), dynamic random access memory, and power management IC (PMIC). Figure 2 In the illustrated embodiment, the chip 30 can be soldered onto and electrically connected to the circuit board 20. The circuit board 20 can be a rigid circuit board, a flexible circuit board, or a rigid-flex circuit board; this application does not limit this. In other embodiments, the circuit board 20 can also be other circuit boards of the electronic device 100.
[0070] Please see Figure 3 , Figure 3 for Figure 1 and Figure 2 This is a schematic diagram of a chip 30 in an electronic device 100. The chip 30 includes a substrate 31, a functional layer 32, a redistribution layer 33, and a bonding structure 34. The substrate 31 supports the functional layer 32 and the redistribution layer 33. The substrate 31 can be made of at least one of silicon, silicon carbide, silicon nitride, gallium arsenide, gallium nitride, and glass-ceramic. This results in a low coefficient of thermal expansion for the substrate 31; for example, silicon has a coefficient of thermal expansion of 2.6 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of silicon carbide is 3.2 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of silicon carbide is 4.0 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of gallium arsenide is 5.9 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of gallium nitride is 5.6 × 10⁻⁶. -6 The coefficient of thermal expansion of glass-ceramics can be controlled by adjusting the content and proportion of different oxides and compounds, as well as the parameters of their heat treatment. Therefore, during the fabrication of chip 30, warpage and deformation of the wafer and chip caused by temperature changes can be reduced.
[0071] In some examples, the substrate 31 can be a silicon substrate, which has good thermal conductivity so that the heat generated by the chip 30 can be dissipated in a timely manner, which is beneficial to improving the performance and lifespan of the chip 30. In addition, the substrate 31 also has a lower production cost, so that the cost of the chip 30 is lower.
[0072] In other examples, substrate 31 may be a silicon carbide substrate, thus having high thermal stability to enable chip 30 to withstand higher power and temperature, high breakdown electric field strength to enable chip 30 to increase the power density of the device, excellent electrical insulation properties to enable chip 30 to be used in high-frequency circuits, low density to make chip 30 lighter, and excellent chemical stability to give chip 30 good corrosion resistance.
[0073] In some other examples, the substrate 31 can be a silicon nitride substrate, thus the substrate 31 has high thermal conductivity so that the heat generated by the chip 30 can be dissipated in time to ensure the performance of the chip 30. The substrate 31 also has high hardness and strength so that the chip 30 has good wear resistance and strength.
[0074] In some other examples, substrate 31 may also be a glass-ceramic substrate, in which case substrate 31 has high strength so that chip 30 has high strength, substrate 31 also has good thermal properties so that chip 30 can maintain good dimensional stability, substrate 31 also has good chemical stability so that chip 30 has good corrosion resistance, substrate 31 also has good light transmittance and insulation so that chip 30 has good light transmittance and applicability in high-frequency circuits.
[0075] In some other examples, substrate 31 can be a gallium arsenide substrate, thus having a high electron mobility so that chip 30 can be a high-speed electronic device, good optoelectronic properties so that chip 30 can be an optoelectronic device, and good hardness so that chip 30 can withstand higher pressure and impact.
[0076] In some other examples, substrate 31 can be a gallium nitride substrate, thus having high thermal conductivity so that the heat generated by chip 30 can be dissipated in a timely manner, high thermal stability so that chip 30 can be a high-temperature resistant electronic device, and high electrical conductivity so that chip 30 can be a high-frequency and high-speed electronic component.
[0077] In some other examples, the substrate 31 may be a composite stack structure formed by two or more of the following: a silicon layer, a silicon carbide layer, a silicon nitride layer, a gallium arsenide layer, a gallium nitride layer, and a glass-ceramic layer, thereby giving the chip 30 superior overall performance.
[0078] The substrate 31 has a first surface 31a and a second surface 31b facing away from each other. A functional layer 32 (also referred to as a functional region) is disposed on the first surface 31a of the substrate 31. The functional layer 32 is used for integrated circuit devices (such as transistors). In some examples, the functional layer 32 can be a metal functional layer 32, and the material of the metal functional layer 32 can be one or more of copper, aluminum, nickel, gold, silver, and titanium, including but not limited to. The functional layer 32 can include one metal functional layer or multiple metal functional layers. When the functional layer 32 includes multiple metal functional layers, adjacent metal functional layers are separated by an insulating dielectric layer and can be electrically connected through conductive vias. The material of the insulating dielectric layer can be, but is not limited to, silicon dioxide. The functional layer 32 can be formed on the substrate 31 by deposition, etching, or other methods. Figure 3 In the illustrated embodiment, the first surface 31a of the substrate 31 is planar, and the distance between the surface of the functional layer 32 facing away from the second surface 31b and the second surface 31b is greater than the thickness of the substrate 31. In other embodiments, the first surface 31a of the substrate 31 may have a functional groove (not shown in the figure), the functional layer 32 is formed in the functional groove, and the surface of the functional layer 32 facing away from the second surface 31b may be partially coplanar with the first surface 31a surrounding the functional groove.
[0079] Chip 30 also includes a passivation layer 35, which is formed by deposition on the surface of the second surface 31b of the functional layer 32 opposite to the substrate 31. The passivation layer 35 passivates the surface of the functional layer 32, thereby isolating moisture and providing protection against moisture, contamination, and static electricity, thus protecting the circuitry within the functional layer 32. The passivation layer 35 can be made of inorganic or organic materials; this application does not limit this. In some other embodiments, chip 30 may not include the passivation layer 35.
[0080] The redistribution layer 33 is disposed on the side of the functional layer 32 opposite to the second surface 31b. Figure 3In the illustrated embodiment, the redistribution layer 33 may be disposed on the surface of the passivation layer 35 opposite to the second surface 31b. In other embodiments, when the chip 30 does not include the passivation layer 35, the redistribution layer 33 may be disposed on the surface of the functional layer 32 opposite to the second surface 31b. The redistribution layer 33 includes an insulating layer 331 and a metal pattern layer 332 disposed within the insulating layer 331. The insulating layer 331 may be formed on the surface of the passivation layer 35 by a deposition process, and the metal pattern layer 332 may be formed within the insulating layer 331 by etching the insulating layer 331 and then depositing a metal material. The material of the insulating layer 331 may include, but is not limited to, one or more of polyimide (PI), polybenzoxazole (PBO), and benzocyclobutene (BCB). The material of the metal pattern layer 332 may include, but is not limited to, one or more of copper, aluminum, nickel, gold, silver, and titanium. Figure 3 In the illustrated embodiment, the redistribution layer 33 has three layers, and the metal pattern contacts within adjacent redistribution layers 33 are electrically connected. In other embodiments, the redistribution layer 33 may also have one, two, four, or other layers, and this application does not limit this number.
[0081] Based on this, the passivation layer 35 has a second through-hole 35a, within which a first metal pad 351 is disposed. The first metal pad 351 is electrically connected to the functional layer 32 and also electrically connected to the metal pattern layer 332 within the redistribution layer 33, meaning the redistribution layer 33 is electrically connected to the functional layer 32. Furthermore, the redistribution layer 33 has a first conductive element 333. The first conductive element 333 can be part of the metal pattern layer 332 or a metal pad protruding from the surface of the insulating layer 331 of the redistribution layer 33 and electrically connected to the metal pattern layer. A welding structure 34 is disposed on the surface of the redistribution layer 33 facing away from the substrate 31 and is fixed to and electrically connected to the first conductive element 333.
[0082] The soldering structure 34 can be a solder ball formed by a ball-planting process. The soldering structure 34 is used to solder the chip 30 to other components (such as the circuit board 20). There can be one or more soldering structures 34. Specifically, the material of the soldering structure 34 can include tin. The material of the soldering structure 34 can also include, but is not limited to, one or more of Ag (silver), gold (Au), copper, Bi (bismuth), nickel, and lead. Solder paste can be first coated on the surface of the first conductive component 333. Solid tin-containing solder balls can then be implanted onto the solder paste on the first conductive component 333 using a ball-planting process. The tin-containing solder balls and solder paste are then heated and melted, fusing together to form the soldering structure 34. Because the tin-containing solder balls will flatten to some extent when heated and melted, the soldering structure 34 presents a certain shape. Figure 3The shape shown is a spherical notch or approximately spherical notch. Here, "spherical notch" refers to a portion of a sphere cut off by a plane. In other embodiments, the welded structure 34 may also have other shapes, which are not limited in this application.
[0083] Please refer to the following: Figure 3 and Figure 4 , Figure 4 This is a schematic diagram of the structure of a wafer 200 provided for some embodiments of this application. The wafer 200 is used to cut and form multiple... Figure 3 The chip 30 shown is a wafer 200, which includes a wafer substrate 210, a wafer functional layer 220, a wafer redistribution layer 230, a wafer passivation layer 240, and multiple bonding structures 34. The material of the wafer substrate 210 can be referenced to the material of the substrate 31 of the aforementioned chip 30, and will not be repeated here. The wafer functional layer 220 is disposed on one surface of the wafer substrate 210. The wafer passivation layer 240 is stacked on the surface of the wafer functional layer 220 opposite to the wafer substrate 210, and the wafer redistribution layer 230 is stacked on the side of the wafer functional layer 220 opposite to the wafer substrate 210. The wafer functional layer 220, the wafer passivation layer 240, and the wafer redistribution layer 230 are all continuous integral structure layers. The bonding structures 34 are disposed on the surface of the wafer redistribution layer 230 opposite to the wafer substrate 210.
[0084] Based on this, wafer 220 has a dicing path M, which divides wafer 200 into multiple chip units. Wafer 200 is diced along dicing path M, and one chip unit can form a chip. Figure 3 The chip 30 shown. That is, a portion of the wafer substrate 210 forms the substrate 31 of the chip 30, a portion of the wafer functional layer 220 forms the functional layer 32 of the chip 30, a portion of the wafer passivation layer 240 forms the passivation layer 35 of the chip 30, a portion of the wafer redistribution layer 230 forms the redistribution layer 33 of the chip 30, and at least one bonding structure 34 of the wafer 200 forms the bonding structure 34 of the chip 30.
[0085] Therefore, the heat generated during wafer 200 dicing and the heating required during the formation of the bonding structure 34 via ball-mounting processes cause thermal expansion and deformation in all parts of the wafer 200. Due to the significant difference in the coefficients of thermal expansion between the substrate 31 and the redistribution layer 33, the degree of deformation between them also differs considerably, leading to wafer 200 warping. The larger the wafer 200, the more layers of redistribution layer 33, and the thinner the wafer 200, the more severe the warping. This makes it more difficult to align and identify the dicing path M and accurately dicing along it to obtain the chip 30, resulting in lower processing accuracy and limiting the chip's thinness. Furthermore, the warped chip 30 makes it difficult to mount it onto the circuit board 20.
[0086] To resolve the above issues, please refer to Figure 5 , Figure 5 for Figure 1 and Figure 2 Another schematic diagram of the structure of chip 30 in the electronic device 100 shown. Figure 5 The illustrated embodiments and Figure 3 The difference in the illustrated embodiment is that the chip 30 further includes a package 36 and a second conductive element 37. The package 36 has a third surface 36a facing the first surface 31a and a fourth surface 36b opposite to the third surface 36a. The third surface 36a has a groove 36a1, the package 36 is bonded to the substrate 31, and the functional layer 32 and the redistribution layer 33 are located within the groove 36a1. The coefficient of thermal expansion of the package 36 is on the same order of magnitude as that of the substrate 31. The coefficient of thermal expansion of the package 36 can be greater than, equal to, or less than that of the substrate 31. It should be noted that the coefficient of thermal expansion of the package 36 and that of the substrate 31 being on the same order of magnitude means that both the coefficient of thermal expansion of the package 36 and that of the substrate 31 can be expressed as a power of 10 multiplied by a number greater than or equal to 1 and less than 10, and the two powers are the same.
[0087] In this way, when the wafer 200 is heated during the formation of the bonding structure 34 by ball bonding or during dicing, the thermal expansion of the package 36 is approximately the same as that of the substrate 31. This mitigates the problem of wafer 200 warping caused by the large difference in thermal expansion between the redistribution layer 33 and the substrate 31. This helps ensure the accuracy of wafer 200 alignment before dicing and the accuracy of dicing to form the chip 30, thereby guaranteeing the processing accuracy and yield of the chip 30, and reducing the difficulty of mounting the chip 30 onto the circuit board 20. Furthermore, it allows for setting the dicing path on the components forming the package 36 on the wafer 200 during dicing to form the chip 30. Since the package 36 does not delaminate, it prevents chip 30 damage caused by delamination at the dicing interface, further ensuring the yield of the chip 30.
[0088] Furthermore, the reduced warpage of wafer 200 also helps to reduce the thickness of substrate 31, thereby enabling the chip 30 to be thinner. Finally, the package 36 can protect the functional layer 32 and redistribution layer 33 of chip 30, preventing external moisture and dust from entering the functional layer 32 and redistribution layer 33 and damaging chip 30, thus extending the lifespan of chip 30.
[0089] Based on this, the distance between the fourth surface 36b of the package 36 and the second surface 31b of the substrate 31 is less than or equal to 50 micrometers, meaning the thickness of the chip 30 is less than or equal to 50 micrometers. For example, the thickness of the chip 30 can be 50 micrometers, 45 micrometers, 40 micrometers, etc.
[0090] The material of package 36 may include at least one of silicon, silicon nitride, silicon carbide, gallium arsenide, gallium nitride, and glass-ceramic. Specifically, the absolute value of the difference between the thermal expansion coefficient of package 36 and the thermal expansion coefficient of substrate 31 is less than 10 × 10⁻⁶. -6 / ℃. In this way, the coefficients of thermal expansion of both the package 36 and the substrate 31 are small, resulting in less deformation when heated. When the chip 30 is formed, the warpage of the wafer 200 is small, which can further ensure the processing accuracy and yield of the chip 30.
[0091] The package 36 and the substrate 31 can be made of the same material. This ensures that the thermal expansion coefficients of the package 36 and the substrate 31 are completely identical, resulting in better reduction of wafer 200 warpage. Furthermore, having the package 36 and the substrate 31 made of the same material facilitates material sourcing and design, thereby improving the manufacturing efficiency of the chip 30. In some other embodiments, the package 36 and the substrate 31 can be made of different materials.
[0092] Based on this, the redistribution layer 33 and the recess 36a1 of the package 36 are fitted with a clearance. The clearance between the groove wall of the recess 36a1 and the surface of the redistribution layer 33 can be greater than or equal to 0, that is, the shape and size of the recess 23a1 are adapted to the shape and size of the redistribution layer 33. In this way, when the ball-mounting structure 34 is formed, the package 36 can limit the thermal expansion of the redistribution layer 33, thereby reducing the stress exerted by the redistribution layer 33 on the substrate 31, thus reducing the degree of warpage of the wafer 200 and ensuring the processing accuracy of the chip 30. In addition, when the chip 30 is connected to other components (such as the circuit board 20) through the welding structure 34 and the chip 30 is at a high operating temperature, the package 36 can also limit the thermal expansion of the redistribution layer 33, thereby reducing the stress exerted by the redistribution layer 33 on the welding structure 34 and ensuring the reliability of the connection between the chip 30 and other components (such as the circuit board 20).
[0093] The package 36 also has a first through hole 36c, which penetrates the groove wall of the groove 36a1 and the fourth surface 36b. Figure 5 In the illustrated embodiment, there are two first through holes 36c. In other embodiments, the number of first through holes 36c may be one, three, four, five, or more. Based on this, a second conductive element 37 corresponds one-to-one with each of the first through holes 36c, and at least a portion of the second conductive element 37 is disposed within the first through hole 36c. The second conductive element 37 includes an embedding portion 371 and a connecting portion 372. The embedding portion 371 is located within the first through hole 36c, and one end of the embedding portion 371 facing the substrate 31 is fixed to and electrically connected to the first conductive element 333 of the redistribution layer 33, i.e., one end of the second conductive element 37 is fixed to and electrically connected to the first conductive element 333 of the redistribution layer 33. The connecting portion 372 may be generally plate-shaped, located on the side of the fourth surface 36b facing away from the substrate 31 and connected to and electrically connected to the embedding portion 371, i.e., the other end of the second conductive element 37 is exposed on the fourth surface 36b. In this way, the functional layer 32 of the chip 30 can be electrically connected to other components outside the package 36 through the redistribution layer 33 and the second conductive element 37, so as to realize the transmission of electrical signals between the chip 30 and other components.
[0094] The second conductive element 37 can be a metal structure, meaning both the embedded portion 371 and the connecting portion 372 are metal structures. The material of the second conductive element 37 includes, but is not limited to, gold, silver, copper, aluminum, titanium, molybdenum, tungsten, nickel, and chromium. It can be filled in the first through-hole 36c and formed on the fourth surface 36b through processes such as electroplating and deposition. Based on this, the chip 30 also includes a welding material layer 38, which corresponds one-to-one with the second conductive element 37 and connects the second conductive element 37 and the first conductive element 333. Welding material can be first applied to one of the first conductive element 333 and the second conductive element 37 through electroplating or deposition, and then heated and melted to form the welding material layer 38, thereby fixing and electrically conducting the first conductive element 333 and the second conductive element 37. In this way, the welding material layer 38 fixes and electrically conducts the first conductive element 333 and the second conductive element 37, resulting in a better connection strength between the first conductive element 333 and the second conductive element 37, capable of withstanding greater stress concentration. Furthermore, the first conductive element 333 and the second conductive element 37 can be fixedly connected simply by heating to melt the welding material, which simplifies the processing and makes the chip 30 production more efficient.
[0095] The solder layer 38 may be made of tin (Sn) and / or indium (In), and may also include one or more of Ag (silver), gold (Au), copper, Bi (bismuth), nickel, and lead. In some examples, the solder layer includes a tin-silver (SnAg) alloy. In other examples, the solder layer includes a stacked copper layer and a tin-silver alloy layer, i.e., Cu / SnAg. In still other examples, the solder layer includes a tin-lead (SnPb) alloy. In yet other examples, the solder layer includes a copper layer, a nickel layer, and a tin-silver alloy layer stacked sequentially, i.e., Cu / Ni / SnAg. In still other examples, the solder layer includes a copper layer, a nickel layer, a copper layer, and a tin-silver alloy layer stacked sequentially, i.e., Cu / Ni / Cu / SnAg.
[0096] Please see Figure 6 , Figure 6 for Figure 1 and Figure 2This diagram illustrates another structural design of the chip 30 in the electronic device 100. During the fabrication of the second conductive element 37, the second conductive element 37 can be directly formed on the surface of the first conductive element 333 through electroplating, deposition, or other methods. This achieves fixation and electrical conductivity between the second conductive element 37 and the first conductive element 333, preventing the risk of remelting of the welding material layer 38 due to excessively high bonding temperatures during the bonding of the package 36 and the substrate 31. It also facilitates flexible selection of the aforementioned bonding temperature, reducing the fabrication difficulty of the chip 30. In other embodiments, the embedding portion 371 of the second conductive element 37 can also be a structural component made of other conductive materials such as graphene, and the connecting portion 372 can be a metal structural component. In other embodiments, the second conductive element 37 may not include the connecting portion 372.
[0097] Based on the above, please continue to refer to the following: Figure 5 and Figure 6 The welding structure 34 is disposed on the fourth surface 36b of the package 36 and is fixed to and electrically conductive with the second conductive element 37. Figure 5 and Figure 6 In the illustrated embodiment, the welding structure 34 can be disposed at the connection portion 372 of the second conductive element 37, that is, the welding structure 34 is indirectly disposed on the fourth surface 36b through the second conductive element 37. The manner in which the welding structure 34 is disposed on the second conductive element 37 can be referred to... Figure 3 In the embodiment shown, the welding structure 34 is disposed on the first conductive element 333 in a manner that will not be described again here.
[0098] Please continue reading. Figure 5 and Figure 6 Along the stacking direction of functional layer 32 and redistribution layer 33, the projections of the second conductive element 37 and the welding structure 34 on functional layer 32 are both located within functional layer 32. Figure 5 and Figure 6 In the illustrated embodiment, the first through-hole 36c penetrates the bottom wall of the groove 36a1 and the fourth surface 36b, and the second conductive element 37 extends along the stacking direction of the functional layer 32 and the redistribution layer 33. This shortens the signal transmission path along the functional layer 32, redistribution layer 33, second conductive element 37, and soldering structure 34 to other components connected to the chip 30 (such as the circuit board 20), reducing signal loss and ensuring signal transmission quality. In other embodiments, the first through-hole 36c may also penetrate the sidewall of the groove 36a1, and the extension direction of the first through-hole 36c may intersect with the stacking direction of the functional layer 32 and the redistribution layer 33.
[0099] Please continue reading. Figure 5 and Figure 6The chip 30 also includes a metal layer 39. The metal layer 39 is disposed on the third surface 36a of the package 36 and located on the periphery of the groove 36a1, and is bonded to the substrate 31. Alternatively, the metal layer 39 is disposed on the first surface 31a of the substrate 31 and located on the periphery of the functional layer 32, and is bonded to the package 36. That is, the package 36 and the substrate 31 are bonded together through the metal layer 39. In this way, when the substrate 31, the package 36, and the metal layer 39 are heated to the bonding temperature, the metal layer 39 and the substrate 31 melt simultaneously to form a eutectic alloy, thereby achieving a bonded connection between the substrate 31 and the package 36. This bonding method results in a compact package, and the formed connection has high thermal stability and mechanical strength, as well as good thermal conductivity, which is beneficial for timely heat dissipation during chip 30 operation. In addition, the bonding temperature required to bond the substrate 31 and the package 36 using the metal layer 39 is lower, making it easier to achieve, and it has less impact on the warpage of the wafer 200.
[0100] The metal layer 39 is made of at least one of gold, germanium, aluminum, tin, and indium, and can be deposited on the substrate 31 or the package 36 by electroplating, deposition, or other methods. In some examples, the metal layer 39 can be a gold layer or a gold-germanium alloy layer, with a bonding temperature to silicon of approximately 370°C to 400°C. In other examples, the metal layer 39 can be an aluminum-germanium alloy layer, with a bonding temperature to silicon of approximately 424°C. In still other examples, the metal layer 39 can be a gold-tin alloy layer, with a bonding temperature to silicon of approximately 280°C. In some examples, the metal layer 39 can be a gold-indium alloy layer, with a bonding temperature to silicon of approximately 495°C.
[0101] In some other embodiments, the substrate 31 and the package 36 may also be bonded together by an adhesive at a bonding temperature of approximately 150°C. In still other embodiments, see [reference needed]. Figure 7 , Figure 7 for Figure 1 and Figure 2 Another structural schematic diagram of the chip 30 of the electronic device 100 shown. Figure 7 The illustrated embodiments and Figure 5 The difference in the embodiment shown is that the substrate 31 and the package 36 can also be directly bonded.
[0102] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a wafer 200 provided for other embodiments of this application. Figure 8 The illustrated embodiments and Figure 4The difference in the illustrated embodiment is that the wafer functional layer 220 includes a plurality of functional layers 32 spaced apart from each other. The wafer redistribution layer 230 includes a plurality of redistribution layers 33 spaced apart from each other, with one redistribution layer 33 stacked on the side of a functional layer 32 facing away from the wafer substrate 210 and electrically connected to the functional layer 32. Furthermore, the wafer 200 also includes a wafer package 250 bonded to the wafer substrate 210. The surface of the wafer package 250 facing the wafer substrate 210 has a plurality of grooves 36a1, each groove 36a1 accommodating a functional layer 32 and a redistribution layer 33. A dicing path M is provided between adjacent grooves 36a1. The coefficient of thermal expansion of the wafer package 250 is on the same order of magnitude as that of the wafer substrate 210. The dicing path M divides the wafer 200 into multiple chip units, and dicing the wafer 200 along the dicing path allows the multiple chip units to form multiple chips 30, which can be the aforementioned... Figures 5-7 The chip 30 shown.
[0103] In this way, since the coefficient of thermal expansion of the wafer package 250 is the same as that of the wafer substrate 210, when the wafer 200 is heated due to the formation of the bonding structure 34 by ball bonding or the dicing of the wafer 200, the degree of thermal expansion of the wafer package 250 is consistent with that of the wafer substrate 210. This can improve the wafer 200 warpage caused by the large difference in thermal expansion between the wafer redistribution layer 230 and the wafer substrate 210, thereby ensuring the accuracy of the alignment of the wafer 200 before dicing and the accuracy of dicing to form the chip 30, and thus ensuring the processing accuracy of the chip 30. In addition, the reduced warpage of the wafer 200 also helps to reduce the thickness of the wafer substrate 210, that is, to reduce the thickness of the substrate 31 of the chip 30, thereby realizing the thinning and miniaturization of the chip 30.
[0104] Based on the above, the spacing between two adjacent grooves 36a1 is greater than or equal to 60 micrometers, meaning the minimum distance between the sidewalls of two adjacent grooves 36a1 is greater than or equal to 60 micrometers. For example, the spacing between two adjacent grooves 36a1 can be 60 micrometers, 70 micrometers, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 120 micrometers, etc. This results in a larger bonding area between the wafer package 250 and the wafer substrate 210, which helps reduce the warpage of the wafer 200. Furthermore, the wafer package 250 has higher rigidity and stronger resistance to deformation, thus making the overall rigidity of the wafer 200 higher and its resistance to deformation stronger.
[0105] Please see Figure 9 and Figure 10 , Figure 9 for Figure 5One of the structural schematic diagrams of a method for fabricating chip 30 is shown. Figure 10 for Figure 5 The second schematic diagram shows a method for fabricating chip 30. The chip fabrication method includes steps S10-S70.
[0106] S10: Provide a structure to be packaged 200A. The structure to be packaged 200A includes a wafer substrate blank 210A. A plurality of spaced functional layers 32 are disposed on one surface of the wafer substrate blank 210A. A redistribution layer 33 is disposed on the surface of one functional layer 32 facing away from the wafer substrate blank 210A. The redistribution layer 33 is electrically connected to the functional layer 32. The specific connection method can be found in [reference needed]. Figures 5-7 The chip 30 shown here will not be described in detail here. Figure 9 and Figure 10 In the illustrated embodiment, the number of functional layers 32 and redistribution layers 33 is three. In other embodiments, the number of functional layers 32 and redistribution layers 33 may also be two, four, five, etc., and this application does not limit this. For details, please refer to... Figure 9 In (a), step S10 includes steps S11-S13.
[0107] S11: Provide wafer substrate blank 210A.
[0108] S12: A plurality of spaced functional layers 32 and a plurality of redistribution layers 33 are formed on one surface of a wafer substrate blank 210A, wherein the redistribution layer 33 has a first conductive element 333.
[0109] S13: Apply welding material to the first conductive element 333. The material of the welding material 38A can be referred to the material of the aforementioned welding material layer 38, and will not be repeated here.
[0110] S20: A package structure 200B is provided, which includes a wafer package 250. One surface of the wafer package 250 has a plurality of spaced grooves 36a1. The coefficient of thermal expansion of the wafer package 250 is on the same order of magnitude as that of the wafer substrate blank 210A. The materials of the wafer substrate blank 210A and the wafer package 250 can be referenced to the materials of the substrate 31 and the package 36 mentioned above, and will not be repeated here. For details, please refer to... Figure 9 In (b), providing the package structure 200B includes steps S21-S25.
[0111] S21: Provides wafer package blank 250A.
[0112] S22: A spaced groove 36a1 is formed on the wafer package blank 250A. Specifically, the groove 36a1 can be formed on the surface of the package blank 250A by a dry etching process.
[0113] S23: A first through-hole 36c is formed on the bottom wall of the groove 36a1. The first through-hole 36c penetrates the surface of the package blank 250A opposite to the bottom wall of the groove 36a1 to obtain the wafer package 250. Specifically, the first through-hole 36c can be formed on the surface of the package blank 250A by a dry etching process.
[0114] S24: A second conductive element 37 is provided in the first through hole 36c. The second conductive element 37 is a metal structural component. One end of the second conductive element 37 is exposed on the surface of the wafer package 250 opposite to the bottom wall of the groove 36a1.
[0115] S25: A wafer metal layer 260 is formed on one surface of the wafer package 250, and the wafer metal layer 260 is located on the periphery of the groove 36a1. The material of the wafer metal layer 260 can refer to the material of the aforementioned metal layer 39, and the formation method of the wafer metal layer 260 can refer to the formation method of the aforementioned metal layer 39, which will not be repeated here.
[0116] It should be noted that step S25 can be performed before or after step S23 or step S24, and this application does not limit this.
[0117] S30: The wafer package 250 is bonded to the wafer substrate blank 210A to obtain a first wafer structure 200C. The opening of the recess 36a1 faces the wafer substrate blank 210A, and one recess 36a1 accommodates a functional layer 32 and a redistribution layer 33. Specifically, step S30 includes step S31.
[0118] S31: Bond the wafer metal layer 260 to the wafer substrate blank 210A. The specific bonding temperature is the same as the bonding temperature of the corresponding material of the aforementioned metal layer 39, and will not be repeated here. The technical effect of eutectic bonding between the wafer substrate blank 210A and the wafer package 250 via the metal layer is as described above, and will not be repeated here.
[0119] S40: Melt the welding material to form a welding material layer 38 connecting the first conductive element 333 and the second conductive element 37.
[0120] It should be noted that steps S30 and S40 can be performed sequentially or simultaneously, and this application does not limit this.
[0121] S50: A plurality of welding structures 34 are provided on the surface of the wafer package 250 opposite to the bottom wall of the groove 36a1, and one welding structure 34 is fixed to and electrically connected to a second conductive element 37. Specifically, the welding structure 34 can be formed on the second conductive element 37 by a ball-mounting process.
[0122] S60: The wafer substrate blank 210A is thinned to obtain the wafer substrate 210, and the first wafer structure 200C is formed after thinning. Figure 8 The wafer 200 shown has a portion of the wafer substrate blank 210A forming the wafer substrate 210.
[0123] S70: The thinned first wafer structure 200c (wafer 200) is cut along the cutting path M to obtain multiple chips 30. The cutting path M is located on the circumferential outer side of the groove 36a1. A portion of the wafer substrate blank 210A forms the substrate 31 of the chip 30, and a portion of the wafer package 250 forms the package 36 of the chip 30. The chip 30 has a functional layer 32 and a redistribution layer 33.
[0124] In some other embodiments, the method of fabricating chip 30 may not include S60. In this case, wafer substrate blank 210A is the wafer substrate 210 of wafer 200, and first wafer structure 200c is wafer 200. In step S70, the first wafer structure 200c is directly cut to obtain multiple chips 30.
[0125] Please see Figure 11 and Figure 12 , Figure 11 for Figure 5 This is one of the structural schematic diagrams illustrating another method for fabricating chip 30. Figure 12 for Figure 5 Another structural schematic diagram of the fabrication method of the chip 30 shown. Figure 11 and Figure 12 The illustrated embodiments and Figure 9 and Figure 10 The difference in the illustrated embodiment is that:
[0126] Please see Figure 11 In (b) of the above, step S20 does not include step S25.
[0127] Please see Figure 11 In (a), step S10 includes steps S11-S14, wherein steps S11-S13 can be referred to Figure 9 and Figure 10 The illustrated embodiment.
[0128] S14: A wafer metal layer 260 is formed on one surface of a wafer substrate blank 210A, the wafer metal layer 260 being located on the periphery of the functional layer 32.
[0129] S31: Bond the wafer metal layer 260 to the wafer package 250.
[0130] Please see Figure 13 and Figure 14 , Figure 13 for Figure 6 One of the structural schematic diagrams of the fabrication method of chip 30 shown. Figure 14 for Figure 6 The second schematic diagram of the fabrication method of chip 30 shown. Figure 13 and Figure 14 The illustrated embodiments and Figure 9 and Figure 10 The difference in the illustrated embodiment is that:
[0131] Please see Figure 13 In (a) of the above, step S10 does not include step S13. Please refer to [link / reference]. Figure 13 In (b) of the above, step S20 does not include step S24.
[0132] S40: The first through hole 36c is filled with conductive material by electroplating or deposition to form a second conductive element 37, and the second conductive element 37 is fixed and electrically connected to the first conductive element 333. The end of the second conductive element 37 away from the first conductive element 333 is exposed on the surface of the wafer 200 package 36 opposite to the bottom wall of the groove 36a1.
[0133] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A chip, characterized in that, include: The substrate includes a first surface and a second surface that are opposite to each other; A functional layer is disposed on the first surface; A redistribution layer is stacked on the side of the functional layer opposite to the second surface and is electrically connected to the functional layer. The package has a third surface facing the first surface, the third surface having a groove, the package being bonded to the substrate, the functional layer and the redistribution layer being located within the groove; the thermal expansion coefficient of the package is on the same order of magnitude as that of the substrate.
2. The chip according to claim 1, characterized in that, The package also has a fourth surface opposite to the third surface, and the package also has a first through hole that penetrates the groove wall and the fourth surface. The redistribution layer has a first conductive element; The chip also includes: The second conductive element is disposed in the first through hole, at least a portion of which is fixed to the first conductive element and electrically conductive, and the other end is exposed on the fourth surface.
3. The chip according to claim 2, characterized in that, The second conductive component is a metal structural component; The chip also includes a soldering material layer, which is connected between the second conductive element and the first conductive element.
4. The chip according to claim 2 or 3, characterized in that, The chip also includes: A welding structure is disposed on the fourth surface and is fixed to and electrically conductive with the second conductive element.
5. The chip according to claim 4, characterized in that, Along the stacking direction of the functional layer and the redistribution layer, the projections of the second conductive element and the welding structure on the functional layer are both located within the functional layer.
6. The chip according to any one of claims 1-5, characterized in that, The chip also includes: A metal layer, wherein the metal layer is disposed on the third surface and located on the periphery of the groove, and the metal layer is bonded to the substrate; or, the metal layer is disposed on the first surface and located on the periphery of the functional layer, and the metal layer is bonded to the package.
7. The chip according to claim 6, characterized in that, The metal layer is made of at least one of gold, germanium, aluminum, tin, and indium.
8. The chip according to any one of claims 1-7, characterized in that, The absolute value of the difference between the thermal expansion coefficient of the package and the thermal expansion coefficient of the substrate is less than 10 × 10⁻⁶. -6 / ℃.
9. The chip according to claim 8, characterized in that, The substrate is made of at least one of silicon, silicon nitride, silicon carbide, gallium arsenide, gallium nitride, and glass-ceramic; and / or, The material of the package includes at least one of silicon, silicon nitride, silicon carbide, gallium arsenide, gallium nitride, and glass ceramic.
10. The chip according to any one of claims 1-9, characterized in that, The package is made of the same material as the substrate.
11. The chip according to any one of claims 1-10, characterized in that, The groove is fitted with the redistribution layer with a clearance.
12. The chip according to any one of claims 1-11, characterized in that, The package also has a fourth surface opposite to the third surface; The distance between the second surface and the fourth surface is less than or equal to 50 micrometers.
13. A wafer, characterized in that, include: Wafer substrate; Multiple functional layers are disposed at intervals on one surface of the wafer substrate; Multiple redistribution layers, wherein one redistribution layer is stacked on the side of one of the functional layers opposite to the wafer substrate and is electrically connected to the functional layer; A wafer package is bonded to a wafer substrate; the surface of the wafer package facing the wafer substrate has multiple grooves, each groove accommodating a functional layer and a redistribution layer, and a dicing path is provided between adjacent grooves; the coefficient of thermal expansion of the wafer package is on the same order of magnitude as that of the wafer substrate. The cutting path divides the wafer into multiple chip units.
14. The wafer according to claim 13, characterized in that, The spacing between two adjacent grooves is greater than or equal to 60 micrometers.
15. An electronic device, characterized in that, include: The chip is the chip according to any one of claims 1-12; A circuit board, wherein the chip is disposed on the circuit board.
16. A method for manufacturing a chip, characterized in that, include: A structure to be packaged is provided, the structure to be packaged includes a wafer substrate blank, a plurality of mutually spaced functional layers are disposed on one surface of the wafer substrate blank, and a redistribution layer is disposed on the surface of one of the functional layers opposite to the wafer substrate blank, the redistribution layer being electrically connected to the functional layers; A package structure is provided, the package structure including a wafer package, one surface of the wafer package having a plurality of spaced grooves; the coefficient of thermal expansion of the wafer package is on the same order of magnitude as the coefficient of thermal expansion of the wafer substrate blank; The wafer package is bonded to the wafer substrate blank to obtain a first wafer structure; wherein the opening of the groove faces the wafer substrate blank, and one groove accommodates one of the functional layers and one of the redistribution layers; The first wafer structure is cut along a cutting path to obtain multiple chips; wherein the cutting path is located on the periphery of the groove, a portion of the wafer substrate blank forms the substrate of the chip, a portion of the wafer package forms the package of the chip, and the chip has a functional layer and a redistribution layer.
17. The method according to claim 16, characterized in that, The package structure includes: A wafer package is provided, wherein one surface of the wafer package has a plurality of spaced grooves; A wafer metal layer is formed on one surface of the wafer package, the wafer metal layer being located on the periphery of the groove; Bonding the wafer package to the wafer substrate blank to obtain a first wafer structure includes: The wafer metal layer is bonded to the wafer substrate blank.
18. The method according to claim 16, characterized in that, The provided packaging structure includes: Provide wafer substrate blanks; A plurality of spaced functional layers and a plurality of redistribution layers are formed on one surface of the wafer substrate blank; A wafer metal layer is formed on one surface of the wafer substrate blank, the wafer metal layer being located on the periphery of the functional layer; Bonding the wafer package to the wafer substrate blank to obtain a first wafer structure includes: The wafer metal layer is bonded to the wafer package.
19. The method according to any one of claims 16-18, characterized in that, The redistribution layer has a first conductive element, and the first conductive element is provided with soldering material. The package structure includes: Provide wafer package blanks; Multiple spaced grooves are formed on the wafer package blank; A first through hole is formed on the bottom wall of the groove, and the first through hole penetrates the surface of the wafer package blank opposite to the bottom wall of the groove to obtain a wafer package; A second conductive element is disposed in the first through hole. The second conductive element is a metal structural component, and one end of the second conductive element is exposed on the surface of the wafer package that is opposite to the bottom wall of the trench. Before dicing the first wafer structure along the dicing path to obtain multiple chips, the method further includes: The welding material is melted to connect the first conductive element and the second conductive element.
20. The method according to any one of claims 16-18, characterized in that, The redistribution layer has a first conductive element; The package structure includes: Provide wafer package blanks; Multiple spaced grooves are formed on the wafer package blank; A first through hole is formed on the bottom wall of the groove, and the first through hole penetrates the surface of the wafer package blank opposite to the bottom wall of the groove to obtain a wafer package; After bonding the wafer package to the wafer substrate blank to obtain a first wafer structure, and before dicing the first wafer structure along a dicing path to obtain multiple chips, the method further includes: The first through hole is filled with conductive material to form a second conductive element, and the second conductive element is fixed to the first conductive element and electrically conductive. The end of the second conductive element away from the first conductive element is exposed on the surface of the wafer package opposite to the bottom wall of the trench.
21. The method according to claim 19 or 20, characterized in that, The method further includes: A welding structure is provided on the surface of the wafer package opposite to the bottom wall of the trench, and the welding structure is fixed to the second conductive element and electrically conductive.
22. The method according to claim 21, characterized in that, After providing multiple welding structures on the surface of the wafer package opposite to the bottom wall of the trench, and before cutting the first wafer structure along the cutting path to obtain multiple chips, the method further includes: The wafer substrate blank is thinned.