Photoelectric co-packaging method and photoelectric co-packaging structure

Abstract

The invention discloses a photoelectric co-packaging method and a photoelectric co-packaging structure, and the method comprises the steps: S1, respectively preparing a photonic integrated circuit die, an electronic integrated circuit die and an interposer wafer, and enabling the photonic integrated circuit die to be provided with an optical connection port; s2, bonding the bare photonic integrated circuit and the bare electronic integrated circuit to the interposer wafer through the micro bumps by flip chip bonding; s3, performing plastic packaging on the bonded interposer wafer so as to provide mechanical support; s4, thinning the top of the interposer wafer after plastic package, and removing at least part of the plastic package material to expose the optical connector of the photonic integrated circuit die; step S5, cutting the thinned interposer wafer into an interposer bare wafer; and step S6, preparing a packaging substrate, and bonding the interposer bare chip to the packaging substrate through the micro bumps by flip chip bonding.

Description

Technical Field

[0001] This application relates to the field of optical interconnect technology, and in particular to an optoelectronic co-packaging method and optoelectronic co-packaging structure. Background Technology

[0002] With the development of information technology, the requirements for data transmission speed and efficiency are increasing, especially in fields such as data centers, high-performance computing (HPC), and telecommunications networks. Traditional electrical interconnect technologies, due to problems such as signal attenuation, bandwidth limitations, and electromagnetic interference, are unable to meet the demands of future high-speed data communication. Therefore, optical interconnect technology has received widespread attention as an efficient data transmission solution.

[0003] In the field of optical interconnects, co-packaged optoelectronics (CPO) technology has become a research hotspot due to its ability to significantly reduce power consumption and improve data transmission rates and densities. However, current CPO technology faces several technical challenges: current 2.5D packaging technology still uses wire bonding, which significantly impacts the quality of high-speed signal transmission; because the molding compound is a light-shielding material that blocks the optical connector, current CPO technology cannot be molded, resulting in poor mechanical properties of the chip module; and there are also heat dissipation issues in CPO. Summary of the Invention

[0004] To address at least some of the technical problems, this application provides an optoelectronic co-packaging method and structure. The method utilizes flip-chip bonding to bond photonic integrated circuit wafers (PIC), electronic integrated circuit wafers (EIC), interposers, and packaging substrates together to improve the quality of high-speed signal transmission. Furthermore, the method uses molding compound to encapsulate the photonic integrated circuit wafers and electronic integrated circuit wafers to provide mechanical support.

[0005] The first aspect of this application discloses an optoelectronic co-packaging method, comprising the following steps: Step S1, preparing a photonic integrated circuit wafer, an electronic integrated circuit wafer, and an interposer wafer, wherein the photonic integrated circuit wafer has an optical connector; Step S2, bonding the photonic integrated circuit wafer and the electronic integrated circuit wafer to the interposer wafer via microbumps using flip-chip bonding; Step S3, encapsulating the bonded interposer wafer to provide mechanical support; Step S4, thinning the top of the encapsulated interposer wafer to remove at least part of the encapsulation material to expose the optical connector of the photonic integrated circuit wafer; Step S5, dicing the thinned interposer wafer into interposer wafers; Step S6, preparing a packaging substrate and bonding the interposer wafers to the packaging substrate via microbumps using flip-chip bonding.

[0006] According to the optoelectronic co-packaging method of this application, by using full flip-chip bonding process to replace traditional wire bonding, the parasitic inductance and resistance caused by wires are eliminated, significantly improving the transmission quality of high-speed signals; through innovative molding and selective thinning processes, while providing sufficient mechanical support, the optical path of the optical connector is ensured to be unobstructed, solving the problem of poor mechanical performance caused by the inability to use molding materials in traditional optoelectronic co-packaging.

[0007] In the optoelectronic co-packaging method disclosed in this application, the thickness of the photonic integrated circuit wafer is greater than the thickness of the electronic integrated circuit wafer. In step S4, when thinning the top of the encapsulated interposer wafer, the encapsulation material is thinned down to the substrate of the photonic integrated circuit wafer to expose the optical connector, while retaining a portion of the encapsulation material on the top of the electronic integrated circuit wafer.

[0008] According to the optoelectronic co-packaging method of this application, by designing the PIC chip thickness to be greater than the EIC chip thickness and precisely controlling the thinning depth during the thinning process, the optical connector is fully exposed while the molding compound on top of the EIC chip provides mechanical protection and support. This differentiated thickness design and precise thinning process enable the packaging structure to simultaneously achieve both optical performance and mechanical stability, solving the technical dilemma of the difficulty in achieving both in traditional packaging.

[0009] In the optoelectronic co-packaging method disclosed in this application, step S4 further includes: preparing an anti-reflective film on top of the interposer wafer from which at least a portion of the molding compound has been removed.

[0010] According to the optoelectronic co-packaging method of this application, by preparing an anti-reflection film at the optical interface, the reflection loss of optical signals at the chip interface is effectively reduced and the optical coupling efficiency is improved.

[0011] In the optoelectronic co-packaging method disclosed in this application, the packaging substrate is a ball grid array (BGA) or a grid array (LGA) packaging substrate.

[0012] The optoelectronic co-packaging method according to this application can adapt to different application scenarios. BGA packaging substrates are suitable for CPO (co-packaged optics) scenarios, providing excellent electrical connectivity; LGA packaging substrates are suitable for NPO (near-packaged optics) scenarios, offering better thermal stability and maintainability. This flexible packaging substrate selection strategy expands the application scope of this invention and improves market adaptability.

[0013] In the optoelectronic co-packaging method disclosed in this application, step S7 further includes: attaching a lens on the optical connector of the bare photonic integrated circuit wafer, and then attaching an optical fiber array unit, aligning the lens with the optical connector.

[0014] According to the optoelectronic co-packaging method of this application, efficient optical coupling and precise optical path alignment are achieved by integrating a lens and fiber array unit above the optical connector. This integrated design significantly reduces optical path loss, improves signal transmission quality, and avoids complex external optical calibration systems, making the entire packaging structure more compact and suitable for high-density optoelectronic integration applications.

[0015] In the optoelectronic co-packaging method disclosed in this application, step S7 further includes: attaching a thermal interface material (TIM) onto the bare electronic integrated circuit wafer, then attaching a thermally conductive metal cover onto the thermal interface material; and attaching a packaging shell, wherein the thermally conductive metal cover abuts against the inner side of the packaging shell.

[0016] According to the optoelectronic co-packaging method of this application, a highly efficient heat conduction channel is constructed by designing a dedicated heat dissipation path above the EIC chip, including TIM material, a thermally conductive metal cap, and a package shell. This top-surface heat dissipation solution solves the problem of poor heat dissipation in traditional CPO packaging, and can significantly improve the reliability and lifespan of the device.

[0017] The second aspect of this application discloses an optoelectronic co-packaging structure, comprising: an interposer wafer; a photonic integrated circuit die bonded to the interposer wafer via microbumps using flip-chip bonding, the photonic integrated circuit wafer having an optical connector; an electronic integrated circuit die bonded to the interposer wafer via microbumps using flip-chip bonding; a molding compound for encapsulating the photonic integrated circuit wafer and the electronic integrated circuit wafer to provide mechanical support, the molding compound not covering the optical connector of the photonic integrated circuit wafer; and a packaging substrate, wherein the interposer wafer is connected to the packaging substrate via microbumps.

[0018] According to the optoelectronic co-packaging structure of this application, the signal transmission quality problem caused by wire bonding is eliminated through the optimized multi-chip integrated architecture. At the same time, the selective molding design ensures the smooth optical path while guaranteeing mechanical strength.

[0019] In the optoelectronic co-packaging structure disclosed in this application, the thickness of the photonic integrated circuit die is greater than the thickness of the electronic integrated circuit die, and the top of the electronic integrated circuit die is covered with a molding compound.

[0020] According to the optoelectronic co-packaging structure of this application, by differentiating the thickness of the PIC and EIC chips, the molding material covering the top of the EIC chip provides the necessary mechanical protection to prevent chip damage caused by external stress; while the thicker PIC chip ensures that the optical interface is completely exposed after the molding thinning process, avoiding optical path obstruction. This collaborative design significantly improves the overall reliability and optical performance of the packaged device.

[0021] The optoelectronic co-packaging structure disclosed in this application further includes an anti-reflective film, which is prepared on the optical connection port side of the bare photonic integrated circuit wafer.

[0022] According to the optoelectronic co-packaging structure of this application, by integrating an anti-reflection film on the optical connector side, the reflection of optical signals at the interface is effectively reduced, the light transmittance is improved, and the optical signal transmission loss can be significantly reduced.

[0023] In the optoelectronic co-packaging structure disclosed in this application, the packaging substrate is a ball grid array packaging substrate or a grid array packaging substrate.

[0024] According to the optoelectronic co-packaging structure of this application, by supporting different types of packaging substrates, the invention possesses broad application adaptability. BGA substrates offer excellent electrical performance and mechanical stability, suitable for CPO applications; LGA substrates are easy to maintain and upgrade, suitable for NPO applications. This flexibility enables the invention to meet the needs of different customers and application fields, enhancing its market competitiveness.

[0025] The optoelectronic co-packaging structure disclosed in this application further includes: a lens, which is mounted on the optical connector of the photonic integrated circuit wafer; and an optical fiber array unit, which is aligned with the optical connector through the lens.

[0026] According to the optoelectronic co-packaging structure of this application, by integrating lenses and fiber array units, efficient optical coupling and precise optical path alignment are achieved, which significantly improves the optical signal transmission efficiency.

[0027] The optoelectronic co-packaging structure disclosed in this application further includes: a thermally conductive metal cover, which is attached to the bare electronic integrated circuit die via a thermally conductive interface material; and a packaging shell, wherein the thermally conductive metal cover abuts against the inner side of the packaging shell.

[0028] Based on the optoelectronic co-packaging structure of this application, an efficient heat conduction path from the EIC chip to the external environment is constructed through optimized heat dissipation design.

[0029] Compared with existing technologies, this application successfully solves the technical problems in traditional optoelectronic co-packaging technology by adopting an innovative Chip on wafer on substrate architecture and combining precise control of molding and thinning processes: 1) The use of a full flip-chip design eliminates the negative impact of wire bonding on high-speed signals; 2) Selective molding and thinning processes ensure unobstructed optical paths while maintaining mechanical strength; 3) Optimized top surface heat dissipation design significantly improves the heat dissipation performance of the EIC chip. Attached Figure Description

[0030] Figure 1 This is a schematic cross-sectional view of the bare photonic integrated circuit wafer 10;

[0031] Figure 2 This is a schematic cross-sectional view of a bare electronic integrated circuit chip;

[0032] Figure 3 This is a schematic diagram of a cross-section of the interposer wafer;

[0033] Figure 4 A cross-sectional schematic diagram of bonding bare photonic integrated circuit wafers and bare electronic integrated circuit wafers onto an interposer wafer;

[0034] Figure 5 This is a schematic cross-sectional view of the bonding interposer wafer being encapsulated.

[0035] Figure 6 This is a schematic diagram of a cross-section showing the thinning of the top of the molded interposer wafer.

[0036] Figure 7 This is a schematic cross-sectional view of a temporary carrier bonded to the top of the interposer wafer.

[0037] Figure 8 A schematic cross-sectional view of fabricating microbumps on the back side of an interposer wafer;

[0038] Figure 9 This is a schematic diagram of the cross-section of the bare intermediate layer.

[0039] Figure 10 This is a cross-sectional schematic diagram of the bare interposer bonded to the packaging substrate;

[0040] Figure 11 A cross-sectional schematic diagram of mounting a thermal interface material and a thermally conductive metal cap on an electronic integrated circuit wafer.

[0041] Figure 12 A cross-sectional schematic diagram of mounting lenses and fiber optic array units on a bare photonic integrated circuit wafer;

[0042] Figure 13 This is a cross-sectional schematic diagram of an optoelectronic co-package structure with a mounting shell. Detailed Implementation

[0043] The present application will be further described below with reference to specific embodiments and accompanying drawings. It is to be understood that the illustrative embodiments of this disclosure are merely for explaining the present application and not for limiting it. Furthermore, for ease of description, the accompanying drawings show only the parts relevant to the present application, and not all of the structures or processes.

[0044] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Although the description of this application is presented in conjunction with preferred embodiments, this does not mean that the features of this invention are limited to this embodiment. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of this application. To provide a thorough understanding of this application, many specific details will be included in the following description. This application may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of this application, some specific details will be omitted in the description. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0045] Unless the context otherwise specifies, the terms “contains,” “has,” and “includes” are synonyms. The phrase “A / B” means “A or B.” The phrase “A and / or B” means “(A and B) or (A or B).”

[0046] It should be understood that although terms such as "first," "second," etc., may be used herein to describe various components, units, or data, these components, units, or data should not be limited by these terms. These terms are used merely to distinguish one feature from another. For example, without departing from the scope of the exemplary embodiments, a first feature may be referred to as a second feature, and similarly, a second feature may be referred to as a first feature.

[0047] It should be understood that although directional terms such as "up," "down," "left," and "right" may be used here to describe the positional relationship between the various components, these directional terms are only for the convenience of understanding and are not intended to limit the scope of protection of this application.

[0048] It should be noted that in this specification, similar reference numerals and letters in the accompanying drawings indicate similar items. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0050] This application provides an optoelectronic co-packaging method, including the following steps:

[0051] Step S1: Prepare a photonic integrated circuit wafer, an electronic integrated circuit wafer, and an interposer wafer, respectively. The photonic integrated circuit wafer has an optical connection port.

[0052] Step S2: Using flip-chip bonding, the photonic integrated circuit wafer and the electronic integrated circuit wafer are bonded to the interposer wafer via microbumps, respectively.

[0053] Step S3: The bonded interposer wafer is encapsulated to provide mechanical support;

[0054] Step S4: Thin the top of the molded interposer wafer to remove at least part of the molding compound, so as to expose the optical interconnect of the photonic integrated circuit wafer.

[0055] Step S5: Cut the thinned interposer wafer into an interposer bare wafer;

[0056] Step S6: Prepare the packaging substrate by bonding the interposer to the packaging substrate using flip chip bonding through microbumps.

[0057] The specific description of step S1 is as follows.

[0058] Figure 1 This is a schematic cross-sectional view of the bare photonic integrated circuit wafer 10. (See diagram below.) Figure 1As shown, the photonic integrated circuit bare wafer 10 includes a substrate 11, a photonic device layer 12, and microbumps 13 disposed on the top of the photonic device layer. Various photonic devices, including optical connectors 14, are fabricated within the photonic device layer 12. The fabrication process of the photonic integrated circuit bare wafer 10 is as follows: The substrate 11 (wafer level) is cleaned and processed. The material of the substrate 11 can be silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), etc. Subsequently, the photonic device layer 12 is constructed through epitaxial growth, photolithography, etching, deposition, and other processes. Depending on functional requirements, the photonic device layer 12 may include waveguides, modulators, detectors, and other devices, as well as optical connectors 14 for optical coupling with the outside of the photonic integrated circuit. Specifically, the optical connector 14 can be a grating coupler, and the optical connector 14 may also include a metal or dielectric reflective layer fabricated on the side of the grating coupler away from the substrate 11 (the side of the substrate 11 serves as the light incident surface for subsequent flip-chip bonding) to reflect incident light, thereby improving optical coupling efficiency. Next, metal wiring is performed on top of the photonic device layer, and microbumps 13 (e.g., copper pillar type) are fabricated on the top pads. These microbumps not only provide electrical connection points for flip-chip bonding with external interposers or packaging substrates, but also structurally serve as mechanical supports and partial heat dissipation. Optionally, chemical mechanical polishing (CMP) can be used to thin the photonic integrated circuit wafer to a specific thickness. Finally, the photonic integrated circuit wafer is diced to obtain the photonic integrated circuit bare wafer 10.

[0059] Figure 2 This is a schematic cross-sectional view of a bare electronic integrated circuit chip. (Example) Figure 2 As shown, the electronic integrated circuit die 20 includes a substrate 21, an electronic device layer 22, and microbumps 23 disposed on top of the electronic device layer. The fabrication process of the electronic integrated circuit die 20 is as follows: Using silicon semiconductor material as the substrate 21 (wafer level), after cleaning and surface treatment, source / drain regions, gate dielectric layers, and gate electrodes are sequentially formed through epitaxial growth, ion implantation, photolithography, etching, and thin film deposition processes to construct active devices such as transistors and complete device isolation and local interconnection. Subsequently, by alternately depositing dielectric and metal layers, and through photolithography, etching, electroplating, and chemical mechanical polishing processes, a multilayer interconnection structure including vias, metal lines, and pads is formed to realize electrical connections and signal routing between devices. Then, microbumps 23 are fabricated on the top pads. Optionally, chemical mechanical polishing can be used to thin the electronic integrated circuit wafer to a specific thickness. Finally, the electronic integrated circuit wafer is diced to obtain the electronic integrated circuit die 20.

[0060] Figure 3 This is a schematic cross-sectional view of the interposer wafer. (Example:) Figure 3As shown, the interposer wafer 30 includes a substrate 31, through-silicon vias (TSVs) 32, and microbumps 33 disposed on its top. The fabrication process of this interposer wafer is as follows: First, the substrate 31 (typically a silicon wafer) is cleaned and surface-treated. Then, through photolithography, etching, and other processes, through-silicon vias 32 penetrating the entire wafer thickness are formed in the substrate 31 to achieve vertical interconnection between upper and lower layers. Next, conductive material (e.g., copper or tungsten) is filled into the through-silicon vias 32 to form highly reliable vertical conductive channels. Then, a metal wiring layer is fabricated on the upper surface of the substrate 31, and multiple microbumps 33 are formed on the wiring layer according to design requirements, providing reliable electrical connection points for subsequent flip-chip bonding with photonic integrated circuit wafers and electronic integrated circuit wafers. Figure 3 In the illustrated embodiment, the interposer wafer is a silicon wafer, but this application is not limited to this; the interposer wafer may also be a glass wafer, a sapphire wafer, or the like.

[0061] Regarding step S2, Figure 4 This is a cross-sectional schematic diagram showing the bonding of bare photonic integrated circuit wafers and bare electronic integrated circuit wafers onto an interposer wafer. (See diagram below.) Figure 4 As shown, the photonic integrated circuit wafer 10 is flipped, and flip-chip bonding is performed between the microbumps 13 disposed on the top of the photonic device layer and the microbumps 33 on the interposer wafer 30. Then, underfill is performed on the bonding surface to form an underfill layer 34. Similarly, the electronic integrated circuit wafer 20 is flipped, and flip-chip bonding is performed between the microbumps 23 disposed on the top of the electronic device layer and the microbumps 33 on the interposer wafer 30. Then, underfill is performed on the bonding surface to form an underfill layer 34.

[0062] Regarding step S3, Figure 5 This is a schematic cross-sectional view of the bonding intermediate layer wafer being encapsulated. (See diagram below.) Figure 5 As shown, for the interposer wafer 30 bonded in step S2, a molding compound is used to encapsulate the surface of one side where the photonic integrated circuit wafer 10 and the electronic integrated circuit wafer 20 are bonded, covering the entire surface and filling the gap between the photonic integrated circuit wafer 10 and the electronic integrated circuit wafer 20, forming a molding compound layer 41. The molding compound can be epoxy resin, silicone resin, etc. Molding provides good mechanical support and excellent electrical insulation to the bonded interposer wafer, and it remains stable over a wide temperature range, which helps with heat dissipation and reduces stress problems caused by temperature changes.

[0063] Regarding step S4, Figure 6This is a schematic cross-sectional view showing the thinning of the top of the molded interposer wafer. (See diagram below.) Figure 6 As shown, for the molded interposer wafer, the top molding layer 41 is thinned to remove at least part of the molding material, exposing the optical connector 14 of the photonic integrated circuit wafer 10. Since the molding material has low light transmittance, the molding material covering the optical connector will severely affect the optical coupling efficiency between the photonic integrated circuit wafer and the outside. Therefore, it is necessary to thin the molding layer to at least expose the optical connector 14 of the photonic integrated circuit wafer 10. Exposing the optical connector 14 here means ensuring that the light incident surface corresponding to the optical connector 14 (as mentioned earlier, due to flip-chip bonding, the light incident surface is the surface on one side of the substrate 11) is free of optical obstruction. Specifically, as... Figure 6 In the illustrated embodiment, the thickness of the photonic integrated circuit wafer 10 is greater than the thickness of the electronic integrated circuit wafer. For example, the thickness of the photonic integrated circuit wafer 10 is 500µm, and the thickness of the electronic integrated circuit wafer is 450µm. Thus, when thinning the molding compound layer 41, only the molding compound layer above the photonic integrated circuit wafer 10 needs to be removed to expose the optical connector 14. A portion (e.g., 50µm) of the molding compound layer 41 above the electronic integrated circuit wafer 20 can be retained, providing better mechanical support for the interposer wafer. However, the invention is not limited to this. The thickness of the photonic integrated circuit wafer can also be equal to or less than the thickness of the electronic integrated circuit wafer. When thinning the molding compound layer, the top molding compound layer can be completely removed, thinning the photonic integrated circuit wafer and the electronic integrated circuit wafer to the same thickness. The molding compound layer can be thinned using chemical mechanical polishing.

[0064] In step 4, optionally, an anti-reflective film can also be prepared on top of the interposer wafer after at least a portion of the molding compound has been removed. After thinning the molding compound to expose the optical connector, an anti-reflective film can be prepared on top of the interposer wafer, i.e., on the light incident surface of the optical connector, thereby improving the optical coupling efficiency between the bare photonic integrated circuit wafer and the outside world.

[0065] Regarding step S5, further processing of the interposer wafer may be included before dicing the interposer wafer into an interposer bare wafer. Figure 7 This is a schematic cross-sectional view of a temporary substrate bonded to the top of the interposer wafer. Figure 7 As shown, a temporary carrier 42 is bonded to the top of the interposer wafer after the molding compound has been removed. The temporary carrier 42 can be a glass carrier, and it can be bonded to the top of the interposer wafer with bonding adhesive to provide temporary mechanical support for processing the interposer wafer. Figure 8 A schematic cross-sectional view of fabricating microbumps on the back side of an interposer wafer. (See diagram below.) Figure 8As shown, after the temporary carrier 42 is bonded, the interposer wafer is flipped so that its back side faces upward. The back side of the interposer wafer is thinned to expose the through-silicon vias (TSVs). Microbumps 43 corresponding to the TSVs are then prepared on the back side of the interposer wafer. The temporary carrier 42 is then debonded. Figure 9 This is a schematic cross-sectional view of the bare interposer wafer. The interposer wafer obtained from the above processing is then cut to obtain... Figure 9 The intermediate layer is shown as a naked sheet.

[0066] It should be pointed out that, Figure 7 and Figure 8 The processing procedure shown for the interposer wafer involves thinning the back side of the interposer wafer to expose the through-silicon vias (TSVs) and preparing microbumps corresponding to the TSVs. This process can also be performed during the preparation of the interposer wafer in step S1.

[0067] Regarding step S6, Figure 10 This is a cross-sectional schematic diagram of the bare interposer bonded to the packaging substrate. (Example) Figure 10 As shown, the packaging substrate 60 is a ball grid array (BGA) packaging substrate, including pads 61 disposed on the top and solder balls 62 disposed on the bottom. Figure 9 The bare interposer shown is soldered to pads 61 via microbumps 43 to achieve electrical connection between the bare interposer and the package substrate 60. An underfill layer 64 is formed between the bare interposer and the package substrate 60. The solder balls 62 on the bottom of the package substrate 60 can be connected to other motherboards via processes such as reflow soldering. Other peripheral chips 50 and / or electronic devices, such as microcontroller units (MCUs), surface mount resistors, and surface mount capacitors, can also be mounted onto the pads 61 on the package substrate 60 using surface mount technology (SMT). The ball grid array package substrate features high pin density, excellent heat dissipation, and good mechanical stability, making it suitable for high-power applications such as co-packaged optics (CPO) where thermal management is critical. The packaging substrate 60 can also be a Land Grid Array (LGA) packaging substrate. The bottom of the LGA packaging substrate uses a planar pad array, which is connected by sockets or pressure contacts. It has the advantages of being removable, easy to test and maintain, and the absence of solder balls reduces the overall height of the package. It is more suitable for applications such as Near-Packaged Optics (NPO) where replaceability is a high priority.

[0068] Figure 11This is a cross-sectional schematic diagram of mounting a thermally conductive interface material and a thermally conductive metal cap onto a bare electronic integrated circuit die. (See diagram below.) Figure 11 As shown, according to one embodiment of this application, step S7 may further include attaching a thermal interface material (TIM) 81 onto the bare electronic integrated circuit chip, and then attaching a thermally conductive metal cap 82 onto the TIM 81. The TIM 81 can fill the gap between the bare electronic integrated circuit chip and the thermally conductive metal cap, significantly reducing the interface thermal resistance, thereby efficiently dissipating the heat generated by the chip. The TIM 81 can be thermally conductive silicone grease, or a thermally conductive pad made of elastomers such as silicone rubber or polyurethane. Figure 11 As shown, the thermal interface material 81 and the thermal metal cover 82 can also extend above the photonic integrated circuit wafer, and are also used for heat dissipation of the photonic integrated circuit wafer, as long as they do not cover the optical connector and affect optical coupling.

[0069] Figure 12 This is a cross-sectional schematic diagram of mounting lenses and fiber optic array units on a bare photonic integrated circuit wafer. Figure 12 As shown, according to one embodiment of this application, step S7 may further include mounting a lens 91 on the optical connector of the photonic integrated circuit wafer and mounting a fiber array unit 92, wherein the fiber array unit 92 is aligned with the optical connector via the lens 91. Mounting the lens 91 on the optical connector specifically means mounting a lens on the light incident surface of the optical connector, i.e., the substrate-side surface of the photonic integrated circuit wafer. This lens may be a silicon lens, used to converge light and align it with the optical connector. The fiber array unit 92 is mounted on the packaging substrate or the photonic integrated circuit wafer via a support member. The fiber array unit 92 is used to introduce signal light into the photonic integrated circuit wafer from the outside or to extract signal light from the photonic integrated circuit wafer. Optionally, one end of the fiber array unit 92 aligned with the optical connector is prepared as a bevel 93 to convert the horizontally transmitted signal light into downward-transmitting light aligned with the optical connector of the photonic integrated circuit wafer. The bevel angle of the bevel 93 is preferably 45°, but it may also be other angles besides 45°. Alternatively, a metal reflective layer can be fabricated on the inclined surface 93 to improve light reflectivity. Furthermore, a lens 94 can also be provided on one side of the fiber array unit, working in conjunction with lens 91 for optical coupling between the fiber array unit 92 and the optical interface of the photonic integrated circuit wafer.

[0070] Figure 13 This is a cross-sectional schematic diagram of an optoelectronic co-package structure with a mounting shell. (See diagram below.) Figure 13As shown, according to one embodiment of this application, step S7 may further include mounting a package shell 100 on a package substrate, with a thermally conductive metal cover 82 abutting against the inner side of the package shell 100. The package shell 100 can provide mechanical protection, structural support, and environmental sealing. Furthermore, the abutment with the thermally conductive metal cover can also form a heat dissipation path, making the entire package shell act as a heat sink, effectively increasing the heat dissipation area. In addition, the package shell 100 can be made of metal material according to actual needs, thereby further achieving the purpose of electromagnetic interference shielding.

[0071] like Figure 9-13 As shown, this application also provides an optoelectronic co-packaging structure comprising: an interposer 30; a photonic integrated circuit die 10, bonded to the interposer 30 via microbumps 13 using flip-chip bonding, the photonic integrated circuit die having an optical connector 14; an electronic integrated circuit die 20, bonded to the interposer 30 via microbumps 23 using flip-chip bonding; a molding compound for encapsulating the photonic integrated circuit die 10 and the electronic integrated circuit die 20 to form a molding layer 41, thereby providing mechanical support, the molding compound not covering the optical connector of the photonic integrated circuit die; and a packaging substrate 60, the interposer 30 being connected to the packaging substrate 60 via microbumps 43.

[0072] According to one embodiment of this application, in the optoelectronic co-packaging structure, the thickness of the photonic integrated circuit die 10 is greater than the thickness of the electronic integrated circuit die 20, and the top of the electronic integrated circuit die 20 is covered with a molding compound, thereby providing stronger mechanical support and protection.

[0073] According to one embodiment of this application, the optoelectronic co-packaging structure further includes an anti-reflection film, which is fabricated on the optical interface side of the bare photonic integrated circuit wafer. Specifically, the anti-reflection film is fabricated on the light incident surface on the substrate side of the bare photonic integrated circuit wafer to reduce light reflectivity, thereby improving optical coupling efficiency.

[0074] According to one embodiment of this application, in the optoelectronic co-packaging structure, the packaging substrate 60 is a ball grid array packaging substrate or a grid array packaging substrate.

[0075] According to one embodiment of this application, the optoelectronic co-packaging structure further includes: a lens 91, which is mounted on the optical connector 14 of the photonic integrated circuit bare chip 10; and an optical fiber array unit 92, which is aligned with the optical connector 14 through the lens 91.

[0076] According to one embodiment of this application, the optoelectronic co-packaging structure further includes: a thermally conductive metal cover 82, which is attached to the bare electronic integrated circuit chip 20 via a thermally conductive interface material 81; and a package shell 100, wherein the thermally conductive metal cover 82 abuts against the inner side of the package shell 100.

[0077] The optoelectronic co-packaging method and structure provided in this application completely replace traditional wire bonding with full-process flip-chip bonding, significantly improving the transmission quality of high-speed electrical signals. It innovatively employs a process of overall plastic encapsulation followed by selective thinning, ensuring the overall mechanical strength and reliability of the package while precisely exposing the optical connectors of the photonic chip, resolving the core contradiction in traditional optoelectronic co-packaging where mechanical support and unobstructed optical paths cannot be simultaneously achieved. Through optimized chip thickness difference design and precise thinning control, it achieves integrated design where the optical path area is completely open and the circuit area is plastic-encapsulated for protection. A heat dissipation path specifically designed for the electronic chip (via thermally conductive interface material, metal cap to the outer shell) effectively solves the heat dissipation problem in co-packaging, improving the long-term reliability of the system. This technical solution achieves high-performance, high-reliability, and mass-producible optoelectronic heterogeneous integration, providing a complete packaging solution for advanced optical interconnect scenarios such as CPO / NPO.

[0078] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Where there is no conflict, the embodiments and features described in the embodiments of this application can be combined with each other. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for optoelectronic co-packaging, characterized in that, Includes the following steps: Step S1: Prepare a photonic integrated circuit wafer, an electronic integrated circuit wafer, and an interposer wafer, respectively. The photonic integrated circuit wafer has an optical connection port. Step S2: Using flip-chip bonding, the photonic integrated circuit wafer and the electronic integrated circuit wafer are respectively bonded to the interposer wafer via microbumps; Step S3: The bonded interposer wafer is encapsulated to provide mechanical support; Step S4: Thin the top of the encapsulated interposer wafer to remove at least part of the encapsulation material, so as to expose the optical connector of the photonic integrated circuit wafer. Step S5: Cut the thinned interposer wafer into an interposer bare wafer; Step S6: Prepare a packaging substrate by bonding the interposer to the packaging substrate using flip-chip bonding via microbumps.

2. The optoelectronic co-packaging method as described in claim 1, characterized in that, The thickness of the photonic integrated circuit wafer is greater than the thickness of the electronic integrated circuit wafer. In step S4, when thinning the top of the encapsulated interposer wafer, the encapsulation material is thinned down to the substrate of the photonic integrated circuit wafer to expose the optical connector, while retaining a portion of the encapsulation material on the top of the electronic integrated circuit wafer.

3. The optoelectronic co-packaging method as described in claim 1, characterized in that, Step S4 further includes: preparing an anti-reflective film on top of the interposer wafer from which at least a portion of the molding compound has been removed.

4. The optoelectronic co-packaging method as described in claim 1, characterized in that, The packaging substrate is a ball grid array packaging substrate or a grid array packaging substrate.

5. The optoelectronic co-packaging method as described in claim 1, characterized in that, Step S6 further includes: attaching a lens to the optical connector of the photonic integrated circuit wafer, and then attaching an optical fiber array unit, wherein the optical fiber array unit is aligned with the optical connector through the lens.

6. The optoelectronic co-packaging method as described in claim 1, characterized in that, Step S6 further includes: attaching a thermally conductive interface material onto the bare electronic integrated circuit chip, and then attaching a thermally conductive metal cover onto the thermally conductive interface material; attaching a package shell, wherein the thermally conductive metal cover abuts against the inner side of the package shell.

7. A photoelectric co-packaging structure, characterized in that, include: Intermediate layer nude film; A photonic integrated circuit die is bonded to the interposer die via microbumps using flip-chip bonding, and the photonic integrated circuit die has an optical interface. Electronic integrated circuit dies are bonded to the bare interposer layer using flip-chip bonding via microbumps. A molding compound is used to encapsulate the bare photonic integrated circuit wafer and the bare electronic integrated circuit wafer, thereby providing mechanical support. The molding compound does not cover the optical connector of the bare photonic integrated circuit wafer. The packaging substrate has an intermediate layer nub connected to it via microbumps.

8. The optoelectronic co-packaging structure as described in claim 7, characterized in that, The thickness of the photonic integrated circuit die is greater than the thickness of the electronic integrated circuit die, and the top of the electronic integrated circuit die is covered with a molding compound.

9. The optoelectronic co-packaging structure as described in claim 7, characterized in that, Also includes: An anti-reflective film is prepared on the optical interface side of the bare photonic integrated circuit wafer.

10. The optoelectronic co-packaging structure as described in claim 7, characterized in that, The packaging substrate is a ball grid array packaging substrate or a grid array packaging substrate.

11. The optoelectronic co-packaging structure as described in claim 7, characterized in that, Also includes: A lens, which is mounted on the optical connector of the photonic integrated circuit substrate; A fiber optic array unit, wherein the fiber optic array unit is aligned with the optical connector via the lens.

12. The optoelectronic co-packaging structure as described in claim 7, characterized in that, Also includes: A thermally conductive metal cover is attached to the bare electronic integrated circuit chip via a thermally conductive interface material. The thermally conductive metal cap abuts against the inner side of the encapsulation housing.

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