Fan-out packaging method and product thereof

Abstract

The invention discloses a fan-out type packaging structure and a packaging method. The packaging method comprises the following steps: 1) preprocessing a chip and a carrier plate; 2) preparing a temporary bonding layer on the carrier plate; 3) mounting the metal frame on the temporary bonding layer; 4) mounting the chip on the metal frame; 5) plastic packaging; 6) processing the product obtained in the step 5) to expose the terminal on the surface of the chip; 7) preparing an RDL (redistribution layer); 8) preparing a PA passivation layer on the RDL; (9) opening holes in the PA passivation layer; 10) completing preparation of an I / O export structure on a product obtained in the step 9); according to the packaging structure, the volume ratio of the metal frame in the packaging structure is greatly increased, the heat dissipation performance of a product can be remarkably improved, the strength of the finished product is higher, the reliability is better, and meanwhile the packaging structure is suitable for wafer-level fan-out and board-level fan-out type packaging.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a fan-out packaging method and its product. Background Technology

[0002] With the increase in transistor density, the power consumption and heat density of chip products have also increased significantly. Therefore, fan-out packaging places higher demands on the heat dissipation performance of these products. Based on the different sizes and shapes of the "reconstructed wafer," it can be divided into wafer-level fan-out packaging (FOWLP) and board-level fan-out packaging (FOPLP). Based on the different processes and materials used in the reconstruction, it can also be divided into plastic-encapsulated fan-out and embedded silicon-based fan-out, represented by Infineon's eWLB technology and Huatian Technology's eSiFO technology, respectively. In plastic-encapsulated fan-out packaging products, represented by eWLB, the customer's chip (the main heat source) is encapsulated by a large amount of low thermal conductivity epoxy molding compound (EMC), and its heat dissipation problem urgently needs to be solved. Summary of the Invention

[0003] To address the problems in the prior art, the present invention aims to provide a fan-out packaging method and its product.

[0004] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: A fan-out packaging method includes the following steps: 1) Pre-processing of chips and carrier boards; 2) Prepare a temporary bonding layer on the carrier substrate; 3) Mount the metal frame onto the temporary bonding layer; 4) Mount the chip onto the metal frame; 5) Seal the product obtained in step 4); 6) Process the product obtained in step 5) to expose the terminals on the chip surface; 7) Prepare the RDL redistribution layer according to product requirements; 8) Fabricate a PA passivation layer on the RDL redistribution layer; 9) Create openings in the PA passivation layer; 10) Complete the fabrication of the I / O export structure on the product obtained in step 9); 11) Debond the bond, removing the carrier board and temporary bond layer; 12) After completing the testing, marking, cutting, tape weaving, and inspection in sequence, the product is packaged and shipped.

[0005] Furthermore, in step 3), the metal frame is cut into individual pieces or a single patterned mesh structure before mounting.

[0006] Furthermore, in step 4), a highly thermally conductive die bond adhesive is first applied to the metal frame at the location where the chip will be mounted. Then, the chips are mounted one by one at the applied position with the functional side facing up, and the die bond adhesive is cured.

[0007] Furthermore, the curing temperature of the die bond adhesive does not exceed the temperature that the temporary bonding layer can withstand.

[0008] Furthermore, in step 5), it is recommended that the overmold thickness be set to be no less than twice the maximum size of the filler particles in the molding compound.

[0009] Furthermore, in step 10), the I / O output structure includes a UBM-Cu structure and a UBM-Sn structure disposed thereon.

[0010] Furthermore, in step 10), the I / O export structure includes a UBM-Cu structure.

[0011] Furthermore, in step 12), solder balls are placed on the I / O export structure.

[0012] This invention also discloses a fan-out package structure prepared by a fan-out packaging method, comprising a molding compound, a metal frame encapsulated within the molding compound, a chip mounted on the metal frame, an RDL redistribution layer disposed on the molding compound, a PA passivation layer prepared on the RDL passivation layer, and an I / O exit structure disposed on the PA passivation layer, the I / O exit structure comprising a UBM-Cu structure and a UBM-Sn structure disposed thereon.

[0013] This invention also discloses a fan-out package structure prepared by a fan-out packaging method, comprising a molding compound, a metal frame encapsulated within the molding compound, a chip mounted on the metal frame, an RDL redistribution layer disposed on the molding compound, a PA passivation layer prepared on the RDL redistribution layer, an I / O exit structure disposed on the PA passivation layer, the I / O exit structure comprising a UBM-Cu structure, and solder balls disposed on the UBM-Cu structure.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) Significantly increasing the volume ratio of high thermal conductivity material (metal frame) in the packaging structure can significantly improve the heat dissipation performance of the product, resulting in higher strength and better reliability of the finished product. It can effectively reduce the warpage of the wafer or board in the packaging process, which is conducive to improving process accuracy and production yield. The warpage of the finished product can also be significantly improved. (2) This invention is applicable to both wafer-level fan-out (FOWLP) and board-level fan-out packaging (FOPLP). Attached Figure Description

[0015] Figure 1 This is a structural schematic diagram of step 1) of the present invention; Figure 2 This is a structural schematic diagram of step 2) of the present invention; Figure 3 This is a structural schematic diagram of step 3) of the present invention; Figure 4-5 This is a structural schematic diagram of step 4) of the present invention; Figure 6 This is a structural schematic diagram of step 5) of the present invention; Figure 7 This is a structural schematic diagram of step 6) of the present invention; Figure 8 This is a schematic diagram of the structure of step 7) of the present invention; Figure 9 This is a structural schematic diagram of step 8) of the present invention; Figure 10 This is a schematic diagram of the structure of step 9) of the present invention; Figure 11 This is a schematic diagram of step 10) of Embodiment 1 of the present invention; Figure 12 This is a schematic diagram of step 11) of Embodiment 1 of the present invention; Figure 13 This is a schematic diagram of step 12) of Embodiment 1 of the present invention; Figure 14 This is a schematic diagram of step 10) of Embodiment 2 of the present invention; Figure 15 This is a schematic diagram of step 11) of Embodiment 2 of the present invention; Figure 16-17 This is a schematic diagram of step 12) of Embodiment 2 of the present invention. Detailed Implementation

[0016] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0017] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0018] Example 1 like Figure 1-13 As shown, a fan-out packaging method includes the following steps: 1) Pre-processing of incoming wafers and substrates Incoming material testing, grinding, and cutting of customer chip wafers are performed. Incoming material visual inspection and cleaning of carrier board 1 are conducted to ensure that carrier board 1 is free from abnormalities in thickness uniformity (TTV), surface roughness (Ra), dirt, scratches, etc. Figure 1 As shown; the material of the carrier plate 1 includes, but is not limited to, metal and glass, and its coefficient of thermal expansion (CTE) is close to that of the molding compound (EMC) used later; 2) such as Figure 2 As shown, a temporary bonding layer 2 is prepared on the carrier substrate 1. The function of the temporary bonding layer 2 is to fix the mounted integrated circuit devices during subsequent wafer reconstruction. Its structure can be a single layer or a multi-layer composite, and its material can be a liquid paste or a solid film. Its curing method can be thermosetting, UV curing, or a combination of both. The bonding structure can be disassembled by methods such as thermal foaming to reduce adhesion, UV debonding, or laser ablation of the interface layer. The surface of the temporary bonding layer 2 needs to have a certain degree of adhesion to ensure that the mounted chip components do not slip or detach during the transfer of the carrier substrate 1. If a bonding material using UV debonding or laser debonding methods is selected, the carrier substrate 1 must also be transparent in the UV band or laser working band; a glass carrier substrate is preferred. 3) Metal frame mounting like Figure 3 As shown, a custom-patterned metal frame 3 is mounted onto the temporary bonding layer 2. The metal frame 3 can be cut into individual pieces before mounting, or it can be a single patterned "mesh" structure. The patterning of the "mesh" should correspond to the specific product size, and sufficient overlap (i.e., the difference in size between one side of the frame and the chip) should be allowed according to the mounting accuracy. Preferably, the frame size is larger than the chip size. Simultaneously, the metal frame structure mounted here can be set with characteristic patterns as alignment marks for the next chip mounting step. 4) Sequentially complete the application of die bond adhesive, chip mounting (face up), and adhesive curing. like Figure 4-5 As shown, a highly thermally conductive die-bonding adhesive 5 is first applied to the metal frame 3 at the location where the chip 4 will be mounted. Application methods include, but are not limited to, screen printing, stencil printing, and inkjet printing. Then, the chips 4 are mounted one by one to the applied positions with their functional surfaces facing up, according to the required precision and speed, and the die-bonding adhesive is cured. The die-bonding adhesive is preferably thermosetting, and the curing temperature does not exceed the temperature that the temporary bonding layer material can withstand. When applying the die-bonding adhesive, the amount of adhesive applied must be controlled according to the specific dimensions of the product chip, ensuring that the chip 4 is adequately fixed while preventing significant adhesive overflow (i.e., adhesive overflowing outside the metal frame 3) and adhesive creep (i.e., adhesive creeping onto the front of the chip 4, causing short circuits, open circuits, or other defects). 5) Plastic sealing like Figure 6 As shown, the product with the metal frame 3 and chip 4 mounted is encapsulated using molding compound 6 to form a molded body. Molding compound 6 includes, but is not limited to, polymer molding materials in powder, liquid, or dry film form. The process can be compression molding or vacuum lamination (for dry films). It is recommended that the overmold thickness (d) be no less than twice the maximum size of the filler particles in molding compound 6. 6) Exposed chip terminals like Figure 7 As shown, methods including but not limited to laser drilling and dry etching are used to expose the terminals (pads) on the surface of chip 4 for subsequent routing. Laser drilling is preferred; if dry etching is used, a patterned resist layer needs to be prepared in conjunction with photolithography. 7) For example Figure 8 As shown, the RDL redistribution layer 7 is prepared according to product requirements; 8) For example Figure 9 As shown, a PA passivation layer 8 is prepared on the RDL redistribution layer 7. The PA passivation layer 8 can be made of polymer materials such as polyimide (PI), build-up film, poly(p-phenylenebenzodioxazole) fiber (PBO), or inorganic coating materials such as silicon oxide, silicon nitride, and aluminum oxide. Methods such as slot coating, screen printing, and vacuum lamination (dry film morphology) can be used to prepare the PA passivation layer 7 using polymer materials. Methods including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) can be used to prepare the PA passivation layer 7 using inorganic coating materials. 9) For example Figure 10 As shown, a hole 9 is made in the PA passivation layer 8; 10) such as Figure 11 As shown, the I / O export structure is prepared on the product obtained in step 9), and the I / O export structure includes UBM-Cu structure 10 and UBM-Sn structure 11; 11) For example Figure 12 As shown, the bond is debonded, and carrier 1 is removed. The corresponding debonding method is selected based on the type of the temporary bond layer 2 described above. 12) For example Figure 13 As shown, the process involves testing, marking, cutting, tape making, inspection, and packaging before shipment.

[0019] The present invention also discloses a fan-out package structure prepared by a fan-out packaging method, including a molding compound, a metal frame 3 encapsulated in the molding compound, a chip 4 mounted on the metal frame 3, an RDL redistribution layer 7 disposed on the molding compound, a PA passivation layer 8 prepared on the RDL redistribution layer 7, and an I / O exit structure disposed on the PA passivation layer 8. The I / O exit structure includes a UBM-Cu structure 10 and a UBM-Sn structure 11 disposed thereon.

[0020] Example 2 like Figure 1-10 , Figure 14-17 As shown, a fan-out packaging method includes the following steps: 1) Pre-processing of incoming wafers and substrates Incoming material testing, grinding, and cutting of customer chip wafers are performed. Incoming material visual inspection and cleaning of carrier board 1 are conducted to ensure that carrier board 1 is free from abnormalities in thickness uniformity (TTV), surface roughness (Ra), dirt, scratches, etc. Figure 1 As shown; the material of the carrier plate 1 includes, but is not limited to, metal and glass, and its coefficient of thermal expansion (CTE) is close to that of the molding compound (EMC) used later; 2) such as Figure 2 As shown, a temporary bonding layer 2 is prepared on the carrier substrate 1. The function of the temporary bonding layer 2 is to fix the mounted integrated circuit devices during subsequent wafer reconstruction. Its structure can be a single layer or a multi-layer composite, and its material can be a liquid paste or a solid film. Its curing method can be thermosetting, UV curing, or a combination of both. The bonding structure can be disassembled by methods such as thermal foaming to reduce adhesion, UV debonding, or laser ablation of the interface layer. The surface of the temporary bonding layer 2 needs to have a certain degree of adhesion to ensure that the mounted chip components do not slip or detach during the transfer of the carrier substrate 1. If a bonding material using UV debonding or laser debonding methods is selected, the carrier substrate 1 must also be transparent in the UV band or laser working band; a glass carrier substrate is preferred. 3) Metal frame mounting like Figure 3 As shown, a custom-patterned metal frame 3 is mounted onto the temporary bonding layer 2. The metal frame 3 can be cut into individual pieces before mounting, or it can be a single patterned "mesh" structure. The patterning of the "mesh" should correspond to the specific product size, and sufficient overlap (i.e., the difference in size between one side of the frame and the chip) should be allowed according to the mounting accuracy. Preferably, the frame size is larger than the chip size. Simultaneously, the metal frame structure mounted here can be set with characteristic patterns as alignment marks for the next chip mounting step. 4) Sequentially complete the application of die bond adhesive, chip mounting (face up), and adhesive curing. like Figure 4-5As shown, a highly thermally conductive die-bonding adhesive 5 is first applied to the metal frame 3 at the location where the chip 4 will be mounted. Application methods include, but are not limited to, screen printing, stencil printing, and inkjet printing. Then, the chips 4 are mounted one by one to the applied positions with their functional surfaces facing up, according to the required precision and speed, and the die-bonding adhesive is cured. The die-bonding adhesive is preferably thermosetting, and the curing temperature does not exceed the temperature that the temporary bonding layer material can withstand. When applying the die-bonding adhesive, the amount of adhesive applied must be controlled according to the specific dimensions of the product chip, ensuring that the chip 4 is adequately fixed while preventing significant adhesive overflow (i.e., adhesive overflowing outside the metal frame 3) and adhesive creep (i.e., adhesive creeping onto the front of the chip 4, causing short circuits, open circuits, or other defects). 5) Plastic sealing like Figure 6 As shown, the product with the metal frame 3 and chip 4 mounted is encapsulated using molding compound 6 to form a molded body. Molding compound 6 includes, but is not limited to, polymer molding materials in powder, liquid, or dry film form. The process can be compression molding or vacuum lamination (for dry films). It is recommended that the overmold thickness (d) be no less than twice the maximum size of the filler particles in molding compound 6. 6) Exposed chip terminals like Figure 7 As shown, methods including but not limited to laser drilling and dry etching are used to expose the terminals (pads) on the surface of chip 4 for subsequent routing. Laser drilling is preferred; if dry etching is used, a patterned resist layer needs to be prepared in conjunction with photolithography. 7) For example Figure 8 As shown, the RDL redistribution layer 7 is prepared according to product requirements; 8) For example Figure 9 As shown, a PA passivation layer 8 is prepared on the RDL redistribution layer 7. The PA passivation layer 8 can be made of polymer materials such as polyimide (PI), build-up film, poly(p-phenylenebenzodioxazole) fiber (PBO), or inorganic coating materials such as silicon oxide, silicon nitride, and aluminum oxide. Methods such as slot coating, screen printing, and vacuum lamination (dry film morphology) can be used to prepare the PA passivation layer 7 using polymer materials. Methods including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD) can be used to prepare the PA passivation layer 7 using inorganic coating materials. 9) For example Figure 10 As shown, a hole 9 is made in the PA passivation layer 8; 10) such as Figure 14As shown, the I / O export structure is prepared on the product obtained in step 9), and the I / O export structure includes the UBM-Cu structure 10; 11) For example Figure 15 As shown, the bond is debonded, and carrier 1 is removed. The corresponding debonding method is selected based on the type of the temporary bond layer 2 described above. 12) For example Figure 16-17 As shown, 12 solder balls are implanted, and then testing, marking, cutting, tape bonding, inspection, packaging and shipping are completed in sequence.

[0021] This embodiment also discloses a fan-out package structure prepared by a fan-out packaging method, including a molding compound, a metal frame 3 encapsulated in the molding compound, a chip 4 mounted on the metal frame 3, an RDL redistribution layer 7 disposed on the molding compound, a PA passivation layer 8 disposed on the RDL redistribution layer 7, an I / O exit structure disposed on the PA passivation layer 8, the I / O exit structure including a UBM-Cu structure 10, and solder balls 12 disposed on the UBM-Cu structure.

[0022] The rest is the same as in Example 1.

[0023] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0024] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A fan-out packaging method, characterized in that, Includes the following steps: 1) Pre-processing of chips and carrier boards; 2) Prepare a temporary bonding layer on the carrier substrate; 3) Mount the metal frame onto the temporary bonding layer; 4) Mount the chip onto the metal frame; 5) Seal the product obtained in step 4); 6) Process the product obtained in step 5) to expose the terminals on the chip surface; 7) Prepare the RDL redistribution layer according to product requirements; 8) Fabricate a PA passivation layer on the RDL redistribution layer; 9) Create openings in the PA passivation layer; 10) Complete the fabrication of the I / O export structure on the product obtained in step 9); 11) Debond the bond, removing the carrier board and temporary bond layer; 12) After completing the testing, marking, cutting, tape weaving, and inspection in sequence, the product is packaged and shipped.

2. The fan-out packaging method according to claim 1, characterized in that, In step 3), the metal frame is cut into individual pieces or a single patterned mesh structure before mounting.

3. The fan-out packaging method according to claim 1, characterized in that, In step 4), a highly thermally conductive die bonder is first applied to the metal frame at the location where the chip will be mounted. Then, the chips are mounted one by one at the applied position with the functional side facing up, and the die bonder is cured.

4. The fan-out packaging method according to claim 3, characterized in that, The curing temperature of the die bond adhesive does not exceed the temperature that the temporary bonding layer can withstand.

5. A fan-out packaging method according to claim 1, characterized in that, In step 5), it is recommended that the overmold thickness be set to be no less than twice the maximum size of the filler particles in the molding compound.

6. The fan-out packaging method according to claim 1, characterized in that, In step 10), the I / O output structure includes a UBM-Cu structure and a UBM-Sn structure disposed thereon.

7. A fan-out packaging method according to claim 1, characterized in that, In step 10), the I / O export structure includes a UBM-Cu structure.

8. A fan-out packaging method according to claim 7, characterized in that, In step 12), solder balls are placed on the I / O export structure.

9. The fan-out package structure prepared by the fan-out package method according to any one of claims 1-6, characterized in that, The device includes a molding compound containing a metal frame, on which a chip is mounted. An RDL redistribution layer is disposed on the molding compound, a PA passivation layer is fabricated on the RDL passivation layer, and an I / O exit structure is disposed on the PA passivation layer. The I / O exit structure includes a UBM-Cu structure and a UBM-Sn structure disposed thereon.

10. A fan-out package structure prepared by any one of the fan-out package methods according to claims 1-5, 7, and 8, characterized in that, The device includes a molding compound containing a metal frame, on which a chip is mounted. An RDL redistribution layer is disposed on the molding compound, a PA passivation layer is fabricated on the RDL redistribution layer, and an I / O exit structure is disposed on the PA passivation layer. The I / O exit structure includes a UBM-Cu structure, and solder balls are disposed on the UBM-Cu structure.

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