Integrated circuit with micro-repository memory

Abstract

Disclosed herein are integrated circuits that may include a plurality of micro-repositories, where each of the micro-repositories is disposed in a spaced relationship with respect to each other and adjacent a first surface. The plurality of micro-repositories includes a first micro-repository. Further, the integrated circuit may include a plurality of bonding regions, where each bonding region is disposed on the first surface and adjacent a respective one of the plurality of micro-memory banks. The plurality of bonding regions includes a first bonding region in operative communication with the first micro-repository.

Description

Cross-reference to related applications

[0001] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 518,988, filed August 11, 2023, entitled “INTEGRATED CIRCUIT HAVINGMEMORIES AND A SHARED WRITE PORT”, the entire contents of which are incorporated herein by reference.

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,733, filed November 27, 2023, entitled “METHOD AND SYSTEM FORKNOWN-GOOD-DIE TESTABILITY OF FACE-TO-FACE BONDED CHIPLETS”, the entire contents of which are incorporated herein by reference.

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,737, filed November 27, 2023, entitled “SYSTEM AND METHOD FORHAVING CORRECT-BY-CONSTRUCTION TIMING CLOSURE,” the entire contents of which are incorporated herein by reference.

[0004] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 567,649, filed March 20, 2024, entitled “ASSEMBLY HAVING A FACE-TO-FACE BONDED CHIPLET”, with case number P24-052-US-PSP, the entire contents of which are incorporated herein by reference.

[0005] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 637,742, filed April 23, 2024, entitled “INTEGRATED CIRCUIT HAVINGMICROVAULT MEMORIES”, identified by Case No. P24-081-US-PSP, the entire contents of which are incorporated herein by reference.

[0006] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 637,764, filed April 23, 2024, entitled “FEFET STRUCTURES ON INTEGRATED CIRCUITS”, identified by Case No. P24-082-US-PSP, the entire contents of which are incorporated herein by reference.

[0007] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 674,471, filed July 23, 2024, entitled “SYSTEM, METHOD, ANDAPPARATUS FOR WAFER-SCALE MEMORY”, the entire contents of which are incorporated herein by reference. Technical Field

[0008] This disclosure relates to integrated circuits. More specifically, this disclosure relates to integrated circuits having multiple modules including microvault memory. Background Technology

[0009] A chiplet is a tiny chip designed to function as a single entity when using advanced packaging techniques. These miniaturized chips are created by dividing a larger chip into several smaller chips, each with its own function or capability. The concept originated from the semiconductor industry's need to overcome the physical limitations of traditional monolithic chip designs and achieve higher levels of integration. The idea behind chiplets is to create modular systems composed of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality.

[0010] Chiplets can be based on different architectures, such as CPUs, GPUs, memory, or I / O, and can be assembled and stacked in various ways depending on specific application requirements. One advantage of the chiplet approach is its ability to mix and match different chiplets from different manufacturers to create custom solutions that meet specific computing needs. This approach also allows for faster time-to-market, reduced development costs, and increased flexibility, as chiplets can be upgraded or replaced without requiring a complete system redesign.

[0011] Chipsets can be used across a variety of industries, including consumer electronics, cloud computing, and data centers, where there is a high demand for high-performance computing and energy efficiency. Chipsets are expected to play a significant role in the future of computing and can unlock new possibilities for creating more powerful and / or more complex electronic devices. Summary of the Invention

[0013] This document discloses integrated circuits, which may be part of a semiconductor device. Methods of manufacturing these circuits, or methods of writing and reading data into and from the circuit, are disclosed herein and can be used utilizing all the examples, embodiments, and aspects described herein.

[0014] The integrated circuit may include a plurality of micro-repositories, wherein each of the plurality of micro-repositories is disposed relative to each other in a spaced-out relationship and adjacent to a first surface. The plurality of micro-repositories includes a first micro-repository. Furthermore, the integrated circuit may include a plurality of bonding regions, wherein each bonding region is disposed on the first surface and adjacent to a corresponding micro-repository among the plurality of micro-repositories. The plurality of bonding regions includes a first bonding region that operatively communicates with the first micro-repository.

[0015] In some embodiments, the integrated circuit may include a first bonding region disposed on a first surface and adjacent to a first microrepository. The first bonding region may optionally include a plurality of bonds, each of which operatively communicates with the first microrepository.

[0016] In some embodiments, the first bonding region may include a plurality of bonding members, each of which operatively communicates with a first micro-repository. Optionally, these plurality of bonding members may be bumpless bonding members.

[0017] In some embodiments, the integrated circuit may have a first micro-repository having a capacity between 4KB (kilobyte) and 1MB (megabyte).

[0018] In some embodiments, the first micro-repository has a capacity between 4KB and 128KB.

[0019] In some embodiments, the micro repository may have a storage capacity ranging from 4KB to 16KB.

[0020] In some embodiments, the first micro-repository may have a size of less than 256 micrometers by less than 256 micrometers and extend a predetermined distance in the vertical dimension.

[0021] In some embodiments, the first micro-repository has a size of 32 micrometers by 32 micrometers and extends vertically over a predetermined distance.

[0022] In some embodiments, the integrated circuit may involve a first micro-repository having a vertical dimension corresponding to at least eight memory layers. Specifically, in one embodiment, the first micro-repository has a size of 32 micrometers by 32 micrometers and extends a predetermined distance in the vertical dimension. In some embodiments, this vertical dimension corresponds to at least eight memory layers.

[0023] In some embodiments, the bit density of the first micro-repository can be greater than 0.2 gigabits per square millimeter for each layer of the micro-repository.

[0024] In some embodiments, a plurality of micro-repositories, including a first micro-repository, may be located on the back-end-of-the-line portion of the die.

[0025] Optionally, the integrated circuit embodiment may include an SRAM repository, which is configured to be adjacent to the first micro repository.

[0026] The integrated circuit may include an SRAM repository positioned adjacent to a first micro-repository, wherein a first bonding region operatively communicates with the SRAM repository. In some embodiments, the integrated circuit may include a second bonding region disposed on a first surface, the second bonding region operatively communicating with the SRAM repository.

[0027] In some embodiments, the integrated circuit may further include a second bonding region disposed on the first surface and operationally communicating with the SRAM repository. The second bonding region enables connections and data transfer between the SRAM repository component and other components in the system.

[0028] In some embodiments, the integrated circuit may involve a plurality of micro-repositories formed on a first die and an SRAM repository formed on a second die, wherein the first die and the second die are bonded together.

[0029] In some embodiments, the integrated circuit also includes a DRAM (Dynamic Random Access Memory) library configured adjacent to the micro-repository. The DRAM library provides additional memory storage area that can be utilized together with the micro-repository memory.

[0030] In some embodiments, the integrated circuit may involve a DRAM repository configured to be adjacent to a plurality of micro-repositories. A first bonding region may be operationally communicating with the DRAM repository to facilitate data transfer between the first micro-repository and the DRAM repository.

[0031] In some embodiments, the integrated circuit further includes a second bonding region disposed on the aforementioned first surface. This second bonding region operatively communicates with the previously mentioned DRAM repository. This operative communication allows for the exchange of data and signals between the second bonding region and the DRAM repository.

[0032] In some embodiments, the integrated circuit may include a plurality of micro-repositories formed on a first die and a DRAM repository formed on a third die. The first die and the third die may be rigidly fixed together.

[0033] In some embodiments, the integrated circuit further includes a read address register operatively coupled to the first bonding region. The read address register can be configured to hold a read address and transfer the read address to a first micro-repository.

[0034] In some embodiments, the integrated circuit also includes a read data register. The read data register may be operatively coupled to a first micro-repository to receive and retain read data from the first micro-repository.

[0035] In some embodiments, the integrated circuit further includes a read data register operatively coupled to a first micro-repository to receive and hold read data from and from the first micro-repository. The read data register may also be operatively coupled to a first bonding region to transfer the held read data to the first bonding region.

[0036] The integrated circuit may include a read data register operatively coupled to a second bonding region within a plurality of bonding regions to transfer read data to the second bonding region. In some embodiments, the read data register receives and holds read data from a first micro-repository and then transfers the read data to the second bonding region.

[0037] In some embodiments, the integrated circuit may further include a second read data register that operatively communicates with the first read data register. The second read data register may be configured to receive read data from and hold the read data.

[0038] The integrated circuit may involve a second read data register disposed on a die having a second surface, wherein the second surface includes a read data bonding region operatively coupled to a first bonding region on a first surface.

[0039] In some embodiments, the integrated circuit may further include a second read data register disposed on a die having a second side. This second read data register is configured to receive and hold read data from and hold read data from a first read data register. Optionally, the second side of the die includes a read data bonding region operatively coupled to a second bonding region on the first surface to facilitate data transfer between dies. This bonding allows data to be transferred from a first read data register on the first die to a second read data register on the second die.

[0040] In some embodiments, the integrated circuit may further include a second read data register, which is located on a different die than the die having a plurality of micro-repositories.

[0041] In some embodiments, the integrated circuit further includes a second read address register disposed on a different die than the die containing the multiple micro-repositories. This additional read address register, located on a separate die, can be used for various purposes, such as increasing storage capacity or providing bandwidth for reading data from the micro-repositories. By having multiple read address registers distributed across discrete dies, a flexible architecture can be implemented to meet performance requirements while minimizing device footprint and power consumption.

[0042] In some embodiments, the integrated circuit further includes a second read address register. The second read address register is configured to receive and hold a read address. Optionally, the second read address register transfers the read address to a first micro-repository.

[0043] In addition to the read address register and the second read address register, the integrated circuit may also include a second bonding region disposed on the second surface. The second bonding region provides an interface on the second surface to facilitate communication and data transfer related to read addressing functions. By having this second bonding region, the integrated circuit enables read addressing architectures to be interfacing across multiple surfaces and dies.

[0044] In some embodiments, the integrated circuit may further include a second read address register. The second read address register may be disposed on a second die having a second surface. The second read address register may be configured to receive and hold a read address. Furthermore, the second read address register may transmit the read address to the read address register of the first die via the second surface, wherein the second surface of the second die and the first surface of the first die may be bonded together.

[0045] In some embodiments, the integrated circuit further includes a second surface on which a second read address register is disposed. The second read address register is configured to receive and hold a read address, and to transfer the read address to a read address register on the first surface. Optionally, the second surface and the first surface may be bonded together to facilitate the transfer of the read address between the two surfaces.

[0046] In some embodiments, the integrated circuit further includes a through-silicon via (TSV), which is operatively coupled at a first end to a third surface, wherein the third surface is on the opposite side of the first surface.

[0047] In some embodiments, the integrated circuit further includes an interconnect coupled to a first surface having a plurality of microrepositories. The interconnect is also coupled to a second end of a through-silicon via (TSV), which facilitates transport between dies. The TSV has a first end coupled to a third surface on an opposite side of the first surface.

[0048] In some embodiments, the integrated circuit further includes a second micro-repository that operatively communicates with the first bonding region.

[0049] In some embodiments, the integrated circuit may further include a multiplexer operatively coupled to a first micro-repository to receive first read data from the first micro-repository. The multiplexer may also be operatively coupled to a second micro-repository to receive second read data from the second micro-repository. The multiplexer may be configured to select between the first read data from the first micro-repository and the second read data from the second micro-repository for output.

[0050] In some embodiments, the integrated circuit further includes a counter operatively coupled to the multiplexer. The counter is configured to control the multiplexer to serially read first read data from a first micro-repository and second read data from a second micro-repository.

[0051] In some embodiments, the integrated circuit further includes a read data register configured to receive first read data from a first microrepository or second read data from a second microrepository, selected by a multiplexer. The read data register holds the received first or second read data.

[0052] In some embodiments, the integrated circuit further includes a second bonding region on the first surface. A read data register is coupled to the second bonding region to transfer either first read data or second read data held from the multiplexer to the second bonding region.

[0053] In some embodiments, the integrated circuit further includes a component comprising a first die having a plurality of microrepositories.

[0054] In some embodiments, the integrated circuit further includes a component comprising a first die having a plurality of micro-repositories. The plurality of micro-repositories on the first die includes a first micro-repository and a second micro-repository.

[0055] In some embodiments, the integrated circuit further includes a component comprising a first die and a second die, the first die having a plurality of micro-repositories including a first micro-repository and a second micro-repository, and the second die including a read address register and a read data register. In this component, the first die can be bonded to the second die.

[0056] In some embodiments, the integrated circuit may relate to a component having a first die and a second die bonded together. The first die may have a plurality of micro-repositories, including a first micro-repository and a second micro-repository, while the second die may have a read address register and a read data register. In addition to the first bonding region described above, the first die may also include a second bonding region on a first surface. Furthermore, the second die may include a third bonding region and a fourth bonding region. The various bonding regions may be connected such that the first bonding region of the first die is coupled to the third bonding region of the second die, and the second bonding region of the first die is coupled to the fourth bonding region of the second die.

[0057] In some embodiments, the integrated circuit further includes a read address register operatively coupled to a third bonding region of the second die to transmit a read address at the third bonding region. The read address register is configured to hold the read address and transmit the read address to a first micro-repository on the first die via the third bonding region, which is coupled to the first bonding region of the first die.

[0058] In some embodiments, the integrated circuit further includes a read data register operatively coupled to a fourth bonding region of the second die to receive read data from the fourth bonding region. The read data register is configured to receive and retain read data transferred from the fourth bonding region of the second die, which is bonded to a first die having a plurality of micro-repositories.

[0059] In some embodiments, the integrated circuit may relate to a component including a first die having a plurality of micro-repositories, such as a first micro-repository and a second micro-repository. The first die may also include a second read address register configured to receive and hold a read address. The second read address register may be configured to transfer the read address to the first micro-repository and the second micro-repository.

[0060] In some embodiments, the component may include a first die having a plurality of micro-repositories, including a first micro-repository and a second micro-repository. The first die may also include a multiplexer configured to select between the output of the first micro-repository and the output of the second micro-repository.

[0061] In some embodiments, the integrated circuit may further include a second bonding region on a second surface of a first die, the first die having a plurality of micro-repositories. Interconnects may connect the second bonding region to an input of a multiplexer configured to select among the outputs of the first micro-repository, the outputs of the second micro-repository, and transmissions received from the second bonding region.

[0062] In some embodiments, the integrated circuit may further include a stage counter configured to control a multiplexer that selects between outputs from a first micro-repository and a second micro-repository. The stage counter facilitates the sequential reading of data from multiple micro-repositories using the multiplexer.

[0063] In some embodiments, the integrated circuit may further include a third address register configured to receive and hold the output of the multiplexer. The multiplexer may be configured to select from one of a plurality of micro-repositories, and a stage counter may be configured to control the selection of the multiplexer. The third address register may receive and hold the output selected by the multiplexer.

[0064] The integrated circuit may relate to a component including a first die and a second die. The first die has a plurality of micro-repositories, including a first micro-repository and a second micro-repository. The second die has a read address register and a read data register, wherein the first die is bonded to the second die. In some embodiments, the first die may further include a multiplexer and a third address register. The multiplexer is configured to select between the outputs of the first micro-repository and the outputs of the second micro-repository, and the third address register is configured to receive and hold the output of the multiplexer. Optionally, the third address register may be operatively coupled to a second bonding region of the first die.

[0065] The integrated circuit may also include a through-silicon via (TSV) coupled to a read address register and a second surface of the die on which the read address register is disposed. In some embodiments, the TSV facilitates the transfer of data, such as read addresses, between the read address register and components located on the opposite side of the die.

[0066] In some embodiments, the integrated circuit further includes a second through-silicon via (TSV), the second TSV being coupled to a second bonding region of a first die on a second surface and a second read data register. The second TSV facilitates data transfer between the second bonding region on the second surface of the first die and a second read data register on another die. This configuration enables efficient transfer of read data between multiple dies that are stacked and bonded together.

[0067] In some embodiments, the integrated circuit may include a multiplexer configured to select among a plurality of micro-repositories. The multiplexer enables selective access to data from different micro-repositories.

[0068] In some embodiments, the integrated circuit may further include a stage counter configured to control the selection operation of a multiplexer that selects from one of a plurality of micro-repositories. The stage counter provides control signals to the multiplexer to facilitate sequential access to data from the plurality of micro-repositories.

[0069] In some embodiments, the integrated circuit further includes a through-silicon via (TSV) operatively coupled to a first surface and a second surface of a die having a plurality of microrepositories. The TSV facilitates transport between the first surface having a plurality of microrepositories and bonding regions and the opposing second surface of the die.

[0070] In some embodiments, the integrated circuit further includes through-silicon vias (TSVs) configured to facilitate transfer between second dies coupled to a first die having a plurality of microrepositories. The TSVs enable inter-die transfer and integration between microrepository dies and additional dies in a multi-die assembly.

[0071] In some embodiments, the integrated circuit may relate to a first micro-repository comprising at least one column of 3D-NOR formed of a plurality of transistors. Each transistor in these 3D-NOR columns may include a gate coupled to a read-write enable line, a source coupled to a bit line, and a drain coupled to a select line.

[0072] In some embodiments, the integrated circuit may include a first micro-repository comprising a 3D-NAND column formed of a plurality of transistors. Each transistor in the column may have a gate terminal coupled to a read / write enable line, a source terminal coupled to a bit line, and a drain terminal coupled to the source terminal of an adjacent second transistor in the column. The 3D-NAND column configuration in the first micro-repository can facilitate high-density vertical stacking of transistors while allowing individual control of read and write operations via separate enable lines.

[0073] In some embodiments, the integrated circuit may include a first micro-repository comprising a 3D-NAND column having a transmission gate formed by a plurality of transistors. Each transistor in the 3D-NAND column may have a gate coupled to a read / write enable line, a source coupled to a bit line, and a drain coupled to the source of a second transistor. Furthermore, the transmission gate may be coupled to all the transistors in the plurality of transistors in the 3D-NAND column.

[0074] In some embodiments, the integrated circuit may include a first micro-repository comprising a 3D-NOR (three-dimensional NOR gate) column formed of a plurality of transistors, the 3D-NOR column having independent read and write enable functions. Each transistor within the 3D-NOR gate may have a source terminal coupled to a bit line, a drain terminal coupled to a read enable line, and a gate terminal coupled to a write enable line. The independent read and write enable lines allow for individual control of reading and writing to the micro-repository.

[0075] In some embodiments, the plurality of microrepositories may include a thermal management layer configured to dissipate heat generated by the microrepositories during operation. The thermal management layer may optionally involve a material with high thermal conductivity selected from the group consisting of copper, aluminum, diamond, and graphene to facilitate heat dissipation.

[0076] In some embodiments, the integrated circuit further includes a thermal management layer configured to dissipate heat generated by the microrepository during operation. The thermal management layer may optionally include a material with high thermal conductivity selected from the group consisting of copper, aluminum, diamond, and graphene.

[0077] In some embodiments, the integrated circuit further includes a hardware-based encryption module operatively coupled to at least one micro-repository. The encryption module is used to protect data written to or read from the micro-repository. By incorporating hardware-based encryption into the integrated circuit, data stored in the micro-repository can be protected.

[0078] In some embodiments, the integrated circuit further includes power management circuitry configured to adjust the voltage and current supplied to the multiple micro-repositories. The adjustment of voltage and current by the power management circuitry may be based on the operating state of the micro-repositories. For example, the power management circuitry may include a low-power mode that reduces the power supply to the micro-repositories during periods of inactivity.

[0079] The integrated circuit may include power management circuitry configured to adjust the voltage and current supplied to the multiple micro-repositories based on their operating states. In some embodiments, the power management circuitry includes a low-power mode that reduces the power supply to the micro-repositories during periods of inactivity.

[0080] In some embodiments, the integrated circuit may further include signal conditioning circuitry operatively coupled to a plurality of microrepositories. The signal conditioning circuitry may be configured to enhance the signal integrity of data transmissions to and from the microrepositories. Optional components of the signal conditioning circuitry may include filters, amplifiers, or error-correcting encoders.

[0081] In some embodiments, the integrated circuit also includes signal conditioning circuitry operatively coupled to multiple miniature repositories to enhance signal integrity of data transmission. The signal conditioning circuitry may involve filters, amplifiers, or error-correcting encoders to enhance signal integrity.

[0082] In some embodiments, the integrated circuit also includes a diagnostic module configured to monitor the health and performance of the micro-repository and report metrics to an external controller. The diagnostic module may be able to perform self-tests on the micro-repository and generate alerts if a fault is detected.

[0083] In some embodiments, the integrated circuit further includes a diagnostic module configured to monitor the health and performance of the micro-repository and report metrics to an external controller. Optionally, the diagnostic module is capable of performing self-tests on the micro-repository and generating alarms if a fault is detected.

[0084] In some embodiments, each micro-repository may include a built-in self-healing mechanism capable of isolating and bypassing faulty memory cells. The self-healing mechanism may optionally utilize redundancy in the form of spare memory cells, which can be dynamically allocated to replace faulty cells.

[0085] In some embodiments, each micro-repository may include a built-in self-healing mechanism capable of isolating and bypassing faulty memory cells. This self-healing mechanism may utilize redundancy in the form of spare memory cells, which can be dynamically allocated to replace any detected faulty cells.

[0086] In some embodiments, micro-repositories can be arranged in a matrix configuration to enable parallel processing and data retrieval.

[0087] In some embodiments, micro-repositories can be arranged in a matrix configuration to enable parallel processing and data retrieval. The matrix configuration may optionally include row decoders and column decoders to facilitate access to individual micro-repositories.

[0088] In some embodiments, the integrated circuit further includes a flexible substrate. The flexible substrate enables the integrated circuit to conform to a non-planar surface.

[0089] In some embodiments, the integrated circuit further includes a flexible substrate that allows the circuit to conform to a non-planar surface. The flexible substrate may include materials such as polyimide, PEEK (polyetheretherketone), liquid crystal polymers, flexible glass, or combinations thereof. By using a flexible substrate, embodiments can be applied to curved or irregular surfaces and operate normally.

[0090] In some embodiments, the integrated circuit may relate to a first micro-repository configured to operate as a cache memory for a processor. The cache memory may operate in one or more modes, such as write-through, write-back, write-around, or combinations thereof.

[0091] In some embodiments, the first micro-repository may be configured to operate as a cache memory for the processor. The cache memory may operate in one or more cache modes, such as write-through, write-back, write-around, or combinations thereof.

[0092] In some embodiments, multiple microrepositories can form a redundant array of independent memory elements. This redundant array of independent memory elements enables error correction and facilitates data recovery in the event of memory failure. Specifically, a first microrepository can be configured as an element in an array of redundant, independent memory blocks, allowing data errors or failures in one block to be reconstructed from other independent blocks. The redundant array architecture provides fault tolerance and reliability to help ensure operational continuity.

[0093] In some embodiments, the first micro-repository may include a crossbar switch architecture to facilitate data routing between memory cells. This crossbar switch architecture enables non-blocking data transfer within the integrated circuit.

[0094] The integrated circuit may involve a cross-switching architecture associated with the first micro-repository to facilitate data routing between memory cells. In some embodiments, the cross-switching architecture is configured to enable non-blocking data transfer within the integrated circuit.

[0095] In some embodiments, the integrated circuit may relate to a first micro-repository, which includes a dedicated read peripheral. Specifically, the first micro-repository may optionally have its own, separate read peripheral from other components, to facilitate data reading. This dedicated read peripheral for the first micro-repository achieves optimized readout performance.

[0096] In some embodiments, the integrated circuit may include a dedicated read port operatively coupled to a first micro-repository. This allows read operations to be performed on the first micro-repository independently of write operations, thereby enabling concurrent read and write access. The dedicated read port improves overall data throughput by eliminating contention between read and write data.

[0097] In some embodiments, the integrated circuit may include a dedicated write peripheral associated with the first micro-repository. This allows write operations to the first micro-repository to be handled by a dedicated write circuitry device specifically tailored for efficient writing. The dedicated write peripheral facilitates fast and reliable data storage within the micro-repository by optimizing the write path.

[0098] In some embodiments, the integrated circuit may include a dedicated write port operatively coupled to a first micro-repository. This dedicated write port facilitates writing data to the first micro-repository independently of read operations, thereby enabling concurrent read and write access. The dedicated write port can improve the overall data throughput to and from the micro-repository.

[0099] An integrated circuit may include a first transistor having a channel layer formed using a semiconductor material and a ferroelectric layer rigidly coupled to the channel layer. The first transistor may also include a source terminal fixed to the channel layer, a drain terminal fixed to the channel layer, and a gate terminal fixed to the ferroelectric layer.

[0100] In some embodiments, the channel layer of the first transistor may be formed of polysilicon. Using polysilicon for the channel layer provides known electrical properties that allow the transistor to operate normally.

[0101] In some embodiments, the channel layer of the transistor can be formed of an amorphous oxide semiconductor. This amorphous oxide semiconductor material can provide desirable properties when used as a channel layer, such as high carrier mobility and low off-state current, while also being compatible with deposition on top of standard CMOS materials during back-end processing. Examples of amorphous oxide semiconductors that can be utilized include indium oxide, indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), gallium zinc oxide (GZO), aluminum zinc oxide (AZO), cadmium oxide, hafnium indium zinc oxide (HIZO), tin oxide, and indium tin zinc oxide (ITZO). The amorphous oxide semiconductor channel layer can also be doped with elements such as gallium, indium, zinc, tin, hafnium, silicon, and aluminum to optimize carrier concentration and mobility.

[0102] In some embodiments, the amorphous oxide semiconductor forming the channel layer of the first transistor may include at least one of indium oxide, indium gallium zinc oxide, zinc tin oxide, indium zinc oxide, gallium zinc oxide, aluminum zinc oxide, cadmium oxide, hafnium indium zinc oxide, tin oxide, tin suboxide, high tin oxide, indium tin zinc oxide, indium tungsten oxide, indium gallium zinc tin oxide, indium gallium zinc oxynitride, aluminum indium gallium zinc oxide, and zinc indium oxide.

[0103] In some embodiments, the amorphous oxide semiconductor channel layer may be doped with a material selected from gallium (Ga), indium (In), zinc (Zn), tin (Sn), hafnium (Hf), silicon (Si), aluminum (Al), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), titanium (Ti), zirconium (Zr), molybdenum (Mo), tantalum (Ta), niobium (Nb), chromium (Cr), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), silver (Ag), gold (Au), and cerium. The dopant is at least one of the following groups: Ce, Lanthanum (La), Neodymium (Nd), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lutetium (Lu), Yttrium (Y), Scandium (Sc), Bismuth (Bi), Lead (Pb), Thallium (Tl), Antimony (Sb), Arsenic (As), Phosphorus (P), Boron (B), Nitrogen (N), Fluorine (F), Chlorine (Cl), Bromine (Br), and Iodine (I). Doping of the channel layer can enhance certain properties of the transistor, such as carrier mobility, threshold voltage, subthreshold swing, on-state current, and off-state current.

[0104] In some embodiments, the channel layer of the first transistor is formed of a two-dimensional material comprising a transition metal dichalcogenide. The transition metal dichalcogenide may be monovalent or divalent. In some embodiments, the chalcogenide element in the transition metal dichalcogenide is sulfur, selenium, or tellurium.

[0105] Transition metal dichalcogenides (TMDs) can be written as MX2, where M represents a transition metal atom, such as molybdenum (Mo), tungsten (W), platinum (Pt), and palladium (Pd), and X is a chalcogen atom, such as sulfur (S), selenium (Se), and tellurium (Te). TMDs exhibit a wide range of electrical properties, from semiconducting [molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), and tungsten diselenide (WSe2)], to half-metallic [molybdenum distelluride (MoTe2), tungsten distelluride (WTe2), and titanium diselenide (TiSe2)], to metallic [niobium disulfide (NbS2), titanium disulfide (TiS2), nickel disulfide (NiS2), and vanadium diselenide (VSe2)], and to superconducting [niobium diselenide (NbSe2) and tantalum sulfide (TaS2)] systems.

[0106] In some embodiments, the channel layer of the integrated circuit is formed of a two-dimensional material comprising a transition metal dichalcogenide. In these embodiments, the transition metal dichalcogenide may be monovalent.

[0107] In some embodiments, the channel layer of an integrated circuit embodiment may be formed of a two-dimensional transition metal dichalcogenide material. Specifically, these transition metal dichalcogenides may have a divalent transition metal composition. The use of divalent transition metal dichalcogenides for the channel layer achieves electrical properties that are beneficial to the operation of transistors formed from integrated circuit components.

[0108] In some embodiments, the transition metal dichalcogenide forming the channel layer may have a chalcogenide element as sulfur.

[0109] In some embodiments, the integrated circuit may include a transition metal dichalcogenide forming a channel layer. The transition metal dichalcogenide may be monovalent or divalent. Optionally, the sulfide element in the transition metal dichalcogenide may be selenium.

[0110] In some embodiments, the integrated circuit may involve a channel layer formed of a two-dimensional material comprising a transition metal dichalcogenide. The transition metal dichalcogenide may have a chalcogenide element such as tellurium.

[0111] In some embodiments, the channel layer of the transistor can be formed of indium tungsten oxide (IWO). This material can provide the channel layer with desirable properties, such as high mobility for charge carriers. The use of IWO allows for the fabrication of high-performance transistors suitable for a wide range of integrated circuit applications.

[0112] In some embodiments, the channel layer of the transistor can be formed of indium gallium zinc oxide (IGZO). IGZO material provides ideal properties for the channel layer, such as high electron mobility and stability when deposited as a thin film, thereby allowing efficient operation of the transistor within the integrated circuit.

[0113] In some embodiments, the channel layer may be a thin film.

[0114] Examples may involve a ferroelectric layer comprising a hafnium zirconium oxide (Hf0.5Zr0.5O2) having an equimolar ratio of hafnium and zirconium.

[0115] In some embodiments, the integrated circuit including the ferroelectric FET can be disposed on the back-end process (BEOL) portion of the semiconductor device manufacturing process. More specifically, this involves fabricating an integrated circuit comprising a ferroelectric layer and a FET channel layer on a higher layer above the transistor level, after the front-end process is completed. Disposing of the integrated circuit in the BEOL portion enables integration with the underlying transistor structure and metal interconnect layers already fabricated on the chip.

[0116] In some embodiments, the ferroelectric layer in the integrated circuit is made of transition metal oxide, perovskite, or two-dimensional material.

[0117] In some embodiments, the integrated circuit further includes a metal layer disposed between the channel layer and the ferroelectric layer.

[0118] In some embodiments, the integrated circuit further includes an insulating layer disposed between the metal layer and the channel layer. Specifically, the metal layer may be disposed between the channel layer and the ferroelectric layer. Furthermore, the insulating layer is disposed between the metal layer and the underlying channel layer.

[0119] In some embodiments, the integrated circuit further includes a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer.

[0120] In some embodiments, the integrated circuit further includes a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer. Furthermore, in some embodiments, an insulating layer is disposed on the channel layer, and the ferroelectric layer is also disposed on the insulating layer.

[0121] Embodiments may also include a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer. This additional metal layer on top of the ferroelectric material can serve various purposes, such as providing improved electrical contact or acting as a barrier layer. Its integration on top of the ferroelectric layer and the channel layer optimizes the electrical performance and reliability of the ferroelectric field-effect transistor.

[0122] In some embodiments, the channel layer of the integrated circuit can have a thickness of less than 30 nanometers. Constructing the channel layer so thin allows for size reduction and potentially improves the performance of transistors formed using the channel layer.

[0123] In some embodiments, the channel layer can have a thickness between 1 nm and 30 nm. Configuring the channel layer thickness to less than 30 nm allows for effective charge modulation of adjacent ferroelectric layers within this ultra-miniaturized dimension. Maintaining the size at the lower end of this range, such as between 1 nm and 10 nm, allows the integrated circuit to utilize improved channel controllability and reduced short-channel effects. The relatively thin channel layer size thus contributes to low-voltage operation and efficient switching.

[0124] In some embodiments, the channel layer of the transistor can be formed using physical vapor deposition or chemical vapor deposition. These deposition techniques can be used to deposit the required thin film for the channel layer. The channel layer formed in this manner can be less than 30 nm in thickness, or between 1 nm and 30 nm.

[0125] In some embodiments, the channel layer of the integrated circuit is formed using atomic layer deposition. This fabrication process enables precise thickness control and uniform coverage during the deposition of thin channel layers. By constructing one atomic layer at a time through continuous, self-limiting surface reactions, atomic layer deposition allows for sub-nanometer-level thickness control.

[0126] Examples may involve forming a channel layer by adding a dopant comprising at least one of tungsten, gallium (Ga), and zinc (Zn). In some embodiments, the channel layer is formed using physical vapor deposition or chemical vapor deposition, and the dopant facilitates the deposition of a thin channel layer.

[0127] Examples may involve ferroelectric layers formed using atomic layer deposition.

[0128] In some embodiments, the ferroelectric layer of the integrated circuit can be formed using vapor deposition.

[0129] In some embodiments, the ferroelectric layer in an integrated circuit is formed by adding a dopant including at least one of lanthanum, niobium, manganese, zirconium, tin, strontium, calcium, yttrium, or magnesium. The doped ferroelectric layer can be formed using atomic layer deposition or vapor deposition methods. Doping ferroelectric materials can potentially enhance properties such as crystallization temperature, remanent polarization, and leakage current.

[0130] In some embodiments, the channel layer may be configured to have a carrier concentration ranging from 10^17 to 10^20 per cubic centimeter.

[0131] In some embodiments, the channel layer comprises a two-dimensional material. When the thickness of the channel layer is less than 30 nm, the two-dimensional material can maintain an electron mobility of at least 0.1 cm² / V / s. In some embodiments, the channel layer comprises fewer than five monolayers of two-dimensional material.

[0132] In some embodiments, the channel layer comprises a two-dimensional material. When the thickness of the channel layer is less than 30 nm, the two-dimensional material can be configured to maintain an electron mobility of at least 0.1 cm² / Volts.

[0133] In some embodiments, the channel layer may comprise a two-dimensional material that maintains high electron mobility even when the channel layer thickness is less than 30 nm. Optionally, the channel layer may comprise fewer than five monolayers of this two-dimensional material. Using only a few monolayers can help minimize thickness while preserving the beneficial properties of the two-dimensional material.

[0134] In some embodiments, the ferroelectric layer used in the integrated circuit is hafnium zirconium oxide.

[0135] In some embodiments, the integrated circuit has a ferroelectric layer with a coercive voltage between -3 volts and 3 volts. This specifies the range of voltages at which the polarization of the ferroelectric material within the layer can be switched. By tuning the composition and thickness of the ferroelectric layer, it can exhibit a coercive voltage within this range, enabling switching at low voltages compatible with transistor operation. Keeping the coercive voltage relatively low can help reduce the operating voltage and power consumption of devices incorporating the ferroelectric layer.

[0136] In some embodiments, the integrated circuit may have a ferroelectric layer having an off-state current of less than 10^-7 amperes per cubic centimeter.

[0137] In some embodiments, the integrated circuit may involve a ferroelectric layer having an on-state current greater than 10^-7 amperes per cubic centimeter.

[0138] In some embodiments, the integrated circuit has a ferroelectric layer having a crystallization annealing temperature of less than or equal to 500 degrees Celsius.

[0139] In some embodiments, the integrated circuit may involve a ferroelectric layer having a residual polarization of greater than 10 microcoulombs per square centimeter.

[0140] In some embodiments, the integrated circuit may involve a channel layer that is annealed at a temperature below 450 degrees Celsius. Specifically, the channel layer that forms part of the transistor structure in the integrated circuit may undergo an annealing process at a temperature below 450 degrees Celsius. Maintaining a sufficiently low annealing temperature for the channel layer facilitates the integration of ferroelectric materials while preserving the integrity of the channel layer itself during device fabrication.

[0141] In some embodiments, the embodiment includes a channel layer having a channel mobility of less than 100 cm² / Vs. Specifically, the channel layer, as part of an integrated circuit having transistors including a channel layer, a ferroelectric layer, source terminals, drain terminals, and a gate terminal, has a channel mobility configured to be less than 100 cm² / Vs.

[0142] In some embodiments, the integrated circuit includes a channel layer having a subthreshold swing of less than 0.3 volts per decade. Subthreshold swing refers to the gate voltage change required to reduce the current in the transistor by a factor of ten, and a lower subthreshold swing enables faster switching speeds and lower power consumption. This ultra-low subthreshold swing can be achieved by using novel materials and optimized interfaces between the layers.

[0143] In some embodiments, the channel layer in an integrated circuit can be configured to have an off-state current of less than 10^-7 amperes per micrometer.

[0144] In some embodiments, the embodiment includes a channel layer configured to have a channel bandgap greater than 2.5 electron volts.

[0145] In some embodiments, the channel layer may be configured to have an annealed threshold voltage between -1.5 volts and 1.5 volts.

[0146] In some embodiments, the integrated circuit may involve a first transistor having a width of less than 200 nanometers and a length of 50 nanometers.

[0147] The first transistor can have a device area that is less than 30 times the square of the feature size.

[0148] In some embodiments, the integrated circuit may have a first transistor having a low voltage threshold (LVT) level greater than -2.5V.

[0149] In some embodiments, the integrated circuit may have a first transistor having a high voltage threshold (HVT) level greater than -2V.

[0150] In some embodiments, the memory cell incorporating the first transistor has a read voltage between 0V and 1V. Operating the memory cell with the first transistor at a read voltage within this range can facilitate low power consumption during read operations. Configuring transistor characteristics to achieve a low read voltage can also help minimize the overall power requirements of the integrated circuit.

[0151] In some embodiments, the memory cell incorporating the first transistor can have a low read power consumption of less than 10 picojoules. Specifically, the memory cell incorporating the ferroelectric field-effect transistor described above can optionally be designed and configured to achieve read operations dissipating less than 10 picojoules of energy. This extremely low read power consumption will allow for the fabrication of low-power non-volatile memories ideally suited for battery-powered and energy-constrained applications.

[0152] In some embodiments, the memory cell incorporating the first transistor may have a read pulse width of less than 20 nanoseconds.

[0153] In some embodiments, a memory cell having a first transistor can have a read endurance of greater than or equal to 10^9 cycles. This indicates that the memory cell can reliably withstand at least one billion read operations without failure, thereby contributing to high reliability and long operating life.

[0154] In some embodiments, a memory cell incorporating a first transistor can have a read interference tolerance of greater than 10^9 cycles. This indicates that the memory cell can withstand at least 10^9 read cycles without the stored data being disturbed or corrupted, thereby enabling reliable long-term data storage. The high read interference tolerance is achieved in part due to the nature and configuration of the ferroelectric layer, channel layer, and other components in the first transistor.

[0155] In some embodiments, a memory cell incorporating a first transistor can have a write-after-read latency of less than or equal to 10 microseconds. This indicates that the time delay between completing a write operation to the memory cell and being able to reliably read back the stored data is very short. Achieving such fast read access times allows for the construction of high-performance memory systems.

[0156] In some embodiments, the memory cell incorporating the first transistor described herein has a write voltage of less than or equal to 3.0 volts (V).

[0157] In some embodiments, the memory cell incorporating the first transistor may have a write speed of less than or equal to 10 microseconds.

[0158] In some embodiments, a memory cell having the first transistor herein has a write energy of less than 10 picojoules.

[0159] In some embodiments, the memory cell incorporating the first transistor can have write endurance greater than 10^8 cycles. This indicates that the memory cell can withstand at least 100 million write cycles without failure, thereby enabling reliable data storage and retrieval over an extended lifetime. By leveraging the performance characteristics of the underlying ferroelectric field-effect transistor, each memory cell can provide improved durability and lifetime compared to conventional alternatives. High write endurance further translates into enhanced data integrity and reduced requirements for error correction or redundancy.

[0160] In some embodiments, a memory cell having the first transistor described herein has an off-state resistance to on-state resistance ratio (Roff / Ron) of about 10^3 or greater than 10^2.

[0161] In some embodiments, a memory cell incorporating a first transistor can have an on-state current to off-state current ratio (Ion / Off) greater than 100 at Vread, measured from DC. Specifically, a memory cell with a ferroelectric field-effect transistor can achieve a high on-state to off-state current ratio during a read operation, indicating good discriminability between logic 0 and logic 1 states stored in the cell. A high Ion / Ioff ratio facilitates reliable read operations at low voltages.

[0162] In some embodiments, a memory cell may include a first transistor as described herein and a second transistor having the same configuration as the first transistor. The first and second transistors may form a bit state for storing binary values ​​in the memory cell.

[0163] In some embodiments, the integrated circuit may relate to a memory cell having a first transistor, wherein the first transistor is configured to have three or more states. Each of these states corresponds to a stored value in the memory cell. This allows for multi-level data storage within a single memory cell.

[0164] In some embodiments, the integrated circuit may involve a first transistor having an on-state current to off-state current ratio (Ion / Ioff) greater than 10^2 at Vread from a pulse measurement.

[0165] In some embodiments, the integrated circuit includes a first transistor as described herein. Optionally, the first transistor may include less than 10 per micrometer. -14 The off-state leakage current (Ioff) of the Ampere provides extremely low leakage when the transistor is in the off-state and not conducting. With an off-state leakage current below this threshold, the transistor exhibits minimal leakage through the channel and effectively maintains the off state, thus allowing low static power consumption.

[0166] In some embodiments, the memory cell having the first transistor can have a reliability durability of greater than or equal to 10^11 cycles. This high reliability durability allows the memory cell to withstand an extremely large number of read / write cycles without failure throughout its lifespan. Robust durability enables applications requiring frequent data access with minimal downtime for maintenance or replacement.

[0167] In some embodiments, a memory cell having the first transistor described herein has a retention time of at least 1 minute when measured at room temperature of 25 degrees Celsius.

[0168] In some embodiments, the channel layer of the first transistor may involve incorporating another two-dimensional material configured to enhance the on-state current (ION) through the transistor. The additional two-dimensional material provides increased conductivity to allow for a higher ION when the transistor is turned on.

[0169] In some embodiments, the channel layer in an integrated circuit is configured to maintain high mobility despite the presence of a ferroelectric layer. Specifically, the channel layer and the ferroelectric layer are designed such that the ferroelectric layer does not significantly impede electron mobility within the channel layer. This allows integrated circuit transistors to operate with high channel mobility to improve performance while still taking advantage of the benefits of the ferroelectric layer.

[0170] In some embodiments, the integrated circuit can be configured such that the ferroelectric layer does not significantly impede electron mobility within the channel layer. The ferroelectric layer and channel layer can be designed to maintain high mobility despite the presence of the ferroelectric layer on top of the channel layer. For example, the interface between the ferroelectric layer and the channel layer can be optimized to minimize scattering of electrons flowing through the channel.

[0171] In some embodiments, the channel layer is configured to be in direct contact with the ferroelectric layer, without an interface layer between the channel layer and the ferroelectric layer. This direct contact between the channel layer and the ferroelectric layer facilitates minimizing the voltage drop across the interface, thereby enabling low-voltage operation of the transistor. Furthermore, the absence of an interface layer between the channel layer and the ferroelectric layer allows for low-voltage operation and reduces power consumption.

[0172] In some embodiments, the integrated circuit may include a first transistor having a channel layer in direct contact with the ferroelectric layer, without an interface layer between the ferroelectric layer and the channel layer. This direct contact configuration can help minimize the voltage drop across the interface between the channel layer and the ferroelectric layer. By reducing such parasitic voltage drop, the first transistor can potentially operate at lower voltages, thereby achieving low-voltage operation and reduced power consumption. The absence of an interface layer can also contribute to faster switching times and improved transient characteristics.

[0173] Integrated circuits may involve a first transistor characterized by low-voltage operation and low power consumption. This is because, in some embodiments, there is no interface layer between the channel layer and the ferroelectric layer.

[0174] In some embodiments, the integrated circuit may relate to a first transistor characterized by low-voltage operation and low power consumption. This may be due to the absence of an interface layer between the ferroelectric layer and the gate layer of the first transistor. Reduced voltage operation can help reduce the overall power consumption of the integrated circuit.

[0175] In some embodiments, the integrated circuit is characterized by low-voltage operation and low power consumption due to the absence of an interface layer between the channel layer and the ferroelectric layer or between the ferroelectric layer and the gate layer. This reduced voltage operation can help reduce the overall power consumption of the integrated circuit.

[0176] In some embodiments, the integrated circuit may relate to a first transistor characterized by improved switching characteristics, such as faster turn-on and turn-off times. This may be due to the absence of an interface layer between the ferroelectric layer and the channel layer or between the ferroelectric layer and the gate layer. The absence of an interface layer can help reduce parasitic capacitance at these interfaces, thereby enabling faster charging and discharging of the ferroelectric layer during write and erase operations of the transistor.

[0177] In some embodiments, the integrated circuit is characterized by reduced parasitic capacitance at the interface between the channel layer and the ferroelectric layer due to the absence of an interface layer between them. The direct contact between the channel layer and the ferroelectric layer minimizes the voltage drop across the interface, thereby enabling low-voltage operation of the transistor. The reduced parasitic capacitance can also contribute to improved transistor switching characteristics, including faster turn-on and turn-off times.

[0178] In some embodiments, the ferroelectric layer can be configured to have a substantially uniform electric field distribution across the ferroelectric layer.

[0179] In some embodiments, the integrated circuit may involve a ferroelectric layer configured to have a gradient of electric field distribution across the ferroelectric layer.

[0180] In some embodiments, the integrated circuit further includes a micro-repository formed by a plurality of transistors including the first transistor as described herein. The micro-repository may be organized as a column comprising 3-terminal unit cells. Optionally, the micro-repository is formed via a column in one of a 3D-NOR, 3D-AND, 3D-NAND, or 3D-NAND-PG configuration.

[0181] In some embodiments, the micro-repository includes columns of three-terminal bit cells. Specifically, the plurality of transistors constituting each micro-repository can be arranged in vertical columns, wherein each column serves as a bit cell with three terminals (corresponding to the source, drain, and gate terminals of the transistors in that column). This three-terminal bit cell configuration in column form facilitates compact integration and wiring of the micro-repository memory structure.

[0182] In some embodiments, the integrated circuit may include a micro-repository formed of a plurality of transistors. The micro-repository may be organized into columns, the columns including three-terminal bit cells in one of several configurations, the configurations including 3D-NOR, 3D-AND, 3D-NAND, or 3D-NAND with additional transmission gates (3D-NAND-PG).

[0183] In some embodiments, the integrated circuit may include a channel material, including indium gallium zinc oxide (IGZO). Channel materials formed from IGZO may be incorporated into the transistors described herein.

[0184] Embodiments may include source terminals fixed to the channel layer. In some embodiments, the source terminals are formed of at least one of tungsten, titanium nitride, nickel, and molybdenum.

[0185] In some embodiments, the drain terminal of the first transistor comprises at least one of tungsten, titanium nitride, nickel, and molybdenum. These materials can be used to form the drain contact to enable efficient carrier transport and integration within the manufacturing process.

[0186] In some embodiments, the gate terminal of the first transistor comprises at least one of tungsten, titanium nitride, nickel, and molybdenum. These materials are utilized due to their conductivity and integration compatibility in semiconductor manufacturing processes. The selection of a suitable gate terminal material can affect the performance and reliability of the transistor.

[0187] In some embodiments, the integrated circuit further includes a memory formed by a plurality of first transistors. The memory can be configured as a 3D vertical device architecture selected from NAND and NOR configurations.

[0188] In some embodiments, the integrated circuit includes a micro-repository column, which includes a plurality of transistors. Each of the plurality of transistors in the micro-repository column can be configured to be identical to the first transistor previously described. The micro-repository column including a plurality of identical transistors can be organized into a 3D vertical architecture, such as 3D-NOR, 3D-AND, 3D-NAND, or 3D-NAND with transmission gates.

[0189] In some embodiments, the integrated circuit may include a micro-repository column comprising a plurality of transistors, each of which is configured identically to the first transistor. The micro-repository column may be organized in a 3D-NOR configuration.

[0190] In some embodiments, the integrated circuit includes a micro-repository column comprising a plurality of transistors, each of which is configured relative to a first transistor. The micro-repository column may be configured as a 3D-AND structure.

[0191] In some embodiments, the integrated circuit may include a micro-repository column comprising multiple transistors, each transistor configured similarly to a first transistor. The micro-repository column may be arranged in a 3D-NAND configuration.

[0192] In some embodiments, the integrated circuit may include a micro-repository array comprising a plurality of transistors, wherein each of the plurality of transistors is configured according to the first transistor design as described above. The micro-repository array may be organized as a 3D-NAND architecture with transmission gates coupled to all transistors of the plurality of transistors.

[0193] In some embodiments, the integrated circuit may relate to a micro-repository array comprising a plurality of transistors, wherein each transistor includes a source coupled to a bit line, a drain coupled to a read enable line, and a gate coupled to a write enable line. This micro-repository array configuration enables independent control of read and write operations via separate read and write enable lines.

[0194] In some embodiments, the integrated circuit may include a micro-repository array comprising a plurality of transistors, each transistor being formed similarly to a first transistor. The micro-repository array may be configured as a 3D-AND architecture having an independent read / write enable line coupled to each transistor. Specifically, each transistor in the 3D-AND micro-repository array may have a source terminal coupled to a bit line, a drain terminal coupled to a select line, and a gate terminal coupled to a read / write enable line independent of the other transistors.

[0195] In some embodiments, the ferroelectric layer utilized in the integrated circuit is formed of various ferroelectric materials, including but not limited to perovskite, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), and bismuth zinc niobate (Bi(Zn1 / Hafnium-based oxides (e.g., hafnium oxide (HfO2) and doped hafnium oxides (e.g., zirconium-doped lead zirconium oxide (HfZrO2)), lanthanum lead zirconium titanate (PLZT), neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium-based oxides (e.g., hafnium oxide (HfO2) and doped hafnium oxides (e.g., zirconium-doped hafnium oxide (HfZrO2)), and tungsten bronze structural materials (including barium strontium niobate (BSN), barium lead niobate (PBN), and potassium tantalate niobate (KTN)). Bismuth layered ferroelectrics (e.g., bismuth titanate (Bi4Ti3O12), bismuth strontium tantalate (SBT), and bismuth calcium niobate (CBN)), organic ferroelectrics (such as polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), and P(VDF-TrFE) copolymers), Aurivillius phase oxides, rare earth manganates (e.g., YMnO3 and lanthanum-modified lead lanthanum zirconate titanate (PLZT)), nickel manganese oxides (NiMnO3), and relaxor ferroelectrics (including lead magnesium niobate (PMN)). Lead scandium tantalate (PST), lead indium niobate (PIN), multiferroic materials (such as terbium manganate (TbMnO3) and europium titanium oxide (EuTiO3)), SbSI (antimony sulfide iodide), GeTe (germanium telluride), SnTe (tin telluride), thin-film ferroelectrics (such as PZT films, SBT films, and HfO2-based films), layered superlattices, and PbTiO3 / SrTiO3. The wide range of ferroelectric materials offers flexibility in designing integrated circuits, depending on the intended application and desired device characteristics.

[0196] In some embodiments, the integrated circuit includes a first vertical structure having a dielectric column, a channel column disposed around the dielectric column, and a ferroelectric column disposed around the channel column along the length of the channel column. The integrated circuit also includes a plurality of horizontal gate electrode layers, each horizontal gate electrode layer being disposed at a predetermined distance from each other. Each of the horizontal gate electrode layers is disposed adjacent to the ferroelectric column along the length of the ferroelectric column.

[0197] Integrated circuit embodiments may have dielectric columns that are substantially cylindrical in shape. Specifically, the dielectric columns, surrounded by channel columns, can be formed to have a circular or elliptical cross-section along their vertical length. Making the dielectric columns cylindrical can promote conformal deposition of the surrounding channel material.

[0198] In some embodiments, the dielectric column in the first vertical structure is substantially cylindrical. The dielectric column may have a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter and the second diameter may be the same, or the first diameter may be larger than the second diameter.

[0199] In some embodiments, the dielectric column in the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at an opposite second end. Optionally, the first and second diameters of the dielectric column can be configured to be the same.

[0200] In some embodiments, the dielectric column in the first vertical structure has a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

[0201] In some embodiments, the integrated circuit includes a first vertical structure having dielectric columns. The dielectric columns may be configured as solid columns rather than hollow columns. Forming the dielectric columns as solid structures can provide mechanical stability and robustness to the entire vertical stack.

[0202] In some embodiments, the integrated circuit may involve hollow dielectric columns. Specifically, the dielectric columns disposed around the channel columns in the first vertical structure may optionally be configured as hollow columns rather than solid columns. This hollow configuration of the dielectric columns may facilitate certain manufacturing processes or allow additional components to be integrated within the columns. However, in other embodiments, the dielectric columns may instead be implemented as solid columns.

[0203] In some embodiments, the channel array formed around the dielectric array in the first vertical structure may be substantially cylindrical in shape. For example, the channel array may have a circular or elliptical cross-section along its vertical length. A cylindrical channel array configuration may provide certain advantages related to current flow, capacitance, or ease of manufacture.

[0204] In some embodiments, as described in the summary section, the channel array formed around the dielectric array is substantially cylindrical. Optionally, the channel array has a first diameter at a first end and a second diameter at a second end. In some embodiments, the first diameter and the second diameter may be the same. In other embodiments, the first diameter may be larger than the second diameter.

[0205] In some embodiments, the channel column of the first vertical structure has a generally cylindrical shape and a uniform diameter from the first end to the second end.

[0206] In some embodiments, the integrated circuit includes a first vertical structure, wherein a dielectric column has a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

[0207] The ferroelectric array can be substantially cylindrical. In some embodiments, the integrated circuit further includes a first vertical structure in which the ferroelectric array is disposed around the channel array. Optionally, the ferroelectric array can be formed in a substantially cylindrical shape.

[0208] In some embodiments, the integrated circuit may have a generally cylindrical ferroelectric array as described for the first vertical structure. The ferroelectric array may have a first diameter at a first end and a second diameter at an opposite second end. The first diameter and the second diameter may be the same, or in some cases the first diameter may be larger than the second diameter.

[0209] In some embodiments, the integrated circuit has a generally cylindrical ferroelectric train having a first diameter at a first end and a second diameter at a second end, wherein the first diameter and the second diameter can be configured to be the same.

[0210] In some embodiments, the integrated circuit may involve a ferroelectric train that is substantially cylindrical. The ferroelectric train may have a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

[0211] In some embodiments, the integrated circuit further includes a dielectric terminal array disposed around the ends of the channel array. The dielectric terminal array is positioned adjacent to the ends of the channel array and also adjacent to the ferroelectric array.

[0212] In some embodiments, the integrated circuit further includes a drain selection layer disposed parallel to a plurality of horizontal gate electrode layers and adjacent to a dielectric terminal block. The drain selection layer is arranged adjacent to a dielectric terminal block surrounding one end of a channel array. By positioning the drain selection layer parallel to the horizontal gate electrode layers and adjacent to the dielectric terminal block, access to the drain side of the vertical structure can be achieved.

[0213] In some embodiments, the integrated circuit further includes a second dielectric terminal array disposed around the other end of the channel array. The second dielectric terminal array is adjacent to the other end of the length of the channel array and also adjacent to the ferroelectric array.

[0214] The integrated circuit may also include a source selection layer disposed parallel to a plurality of horizontal gate electrode layers. This source selection layer is adjacent to a second dielectric terminal column disposed around the other end of a channel column. In some embodiments, the second dielectric terminal column is adjacent to the other end of the length of the channel column and to a ferroelectric column.

[0215] In some embodiments, the integrated circuit further includes a second vertical structure. The second vertical structure may be formed substantially the same as the first vertical structure, but is configured to be adjacent to the first vertical column at a predetermined horizontal distance.

[0216] In some embodiments, the integrated circuit may include a second vertical structure. The second vertical structure may be formed substantially the same as the first vertical structure, but is configured to be adjacent to the first vertical column at a predetermined horizontal distance.

[0217] In some embodiments, the integrated circuit may include a first vertical structure and a second vertical structure, wherein the second vertical structure is formed substantially the same as the first vertical structure, but is configured to be adjacent to the first vertical column at a predetermined horizontal distance. The first and second vertical structures may be configured to form a single-port 3D NAND structure.

[0218] Optionally, in some embodiments, the plurality of horizontal gate electrode layers of the first vertical structure are formed of at least one of the following: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, TiSi2, CoSi2, NiSi, graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys, AlCu, TiW, and conductive polymers.

[0219] In some embodiments, the ferroelectric train of the first vertical structure is formed from at least one of the following materials: perovskite; lead zirconate titanate (PZT); barium titanate (BaTiO3); strontium titanate (SrTiO3); bismuth ferrite (BiFeO3); potassium niobate (KNbO3); lithium niobate (LiNbO3); lithium tantalate (LiTaO3); sodium bismuth titanate (Na0.5Bi0.5TiO3); bismuth titanate (Bi4Ti3O1). 2); Bismuth zinc niobate (Bi(Zn1 / 2Ti1 / 2)O3); Bismuth lanthanum titanate (BiLaTiO3); Bismuth nickel titanate (BiNiTiO3); Lead magnesium niobate-lead titanate (PMN-PT); Lead lanthanum zirconate titanate (PLZT); Neodymium-doped bismuth titanate (Bi4-xNdxTi3O12); Hafnium-based oxides (e.g., hafnium oxide (HfO2)) and doped hafnium oxides (including zirconium-doped hafnium oxide (HfZrO2)). ); tungsten bronze structural materials (such as barium strontium niobate (BSN), barium lead niobate (PBN), and potassium tantalate niobate (KTN)); bismuth layered ferroelectrics, including bismuth titanate (Bi4Ti3O12), bismuth strontium tantalate (SBT), and calcium bismuth niobate (CBN); organic ferroelectrics, such as polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), and P(VDF-TrFE) copolymers; Aurivillius phase oxides; rare earth manganates, such as YMnO3 and lanthanum-modified lanthanum lead zirconate titanate (PLZT); relaxor ferroelectrics, such as lead magnesium niobate (PMN), lead scandium tantalate (PST), and lead indium niobate (PIN); multiferroic materials, such as terbium manganate (TbMnO3) and europium titanium oxide (EuTiO3); and thin-film ferroelectrics, layered superlattices, etc. This comprehensive list provides flexibility in selecting suitable ferroelectric materials for the vertical structures in various embodiments.

[0220] In some embodiments, the channel array of the first vertical structure is formed from at least one of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), hafnium indium oxide (HIO), cadmium oxide (CdO), polycrystalline silicon, polycrystalline germanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-Silicon), crystalline germanium (c-Germanium), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polystyrene styrene (PPV), graphene, carbon nanotubes (CNTs), methylammonium lead halide (CH3NH3PbX3, X = Cl, Br, I), cesium lead halide (CsPbX3, X = Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), cobaltite, Ruddlesden-Popper phase, cage compound, perovskite oxide, or magnetic semiconductor.

[0221] In some embodiments, the dielectric column of the first vertical structure is formed from at least one of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), silicon nitride (Si3N4), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO3), and titanium. Barium strontium oxide (BST), lead zirconate titanate (PZT), bismuth ferrite (BiFeO3), magnesium oxide (MgO), cerium oxide (CeO2), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd2O3), dysprosium oxide (Dy2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), terbium oxide (Tb4O7), vanadium pentoxide (V2O5) Niobium pentoxide (Nb₂O₅), chromium trioxide (Cr₂O₃), ferric oxide (Fe₂O₃), molybdenum trioxide (MoO₃), tungsten trioxide (WO₃), ruthenium oxide (RuO₂), rhodium trioxide (Rh₂O₃), palladium oxide (PdO), silver oxide (Ag₂O), cadmium oxide (CdO), tin dioxide (SnO₂), antimony trioxide (Sb₂O₃), tellurium dioxide (TeO₂), iridium dioxide (IrO₂), and 2... Platinum oxide (PtO2), gold oxide (Au2O3), beryllium oxide (BeO), magnesium aluminate (MgAl2O4), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeOx), bismuth trioxide (Bi2O3), bismuth titanate (Bi4Ti3O12), perovskite oxides, layered oxides, or complex transition metal oxides.

[0222] In some embodiments, one of the plurality of horizontal gate electrode layers and the first vertical structure can be configured to form a plurality of transistors. These transistors may include a first transistor as described herein. The first vertical structure includes a dielectric column, a channel column disposed around the dielectric column, a ferroelectric column disposed around the channel column, and a plurality of horizontal gate electrode layers disposed adjacent to the ferroelectric column.

[0223] In some embodiments, the integrated circuit may include a first vertical structure. The first vertical structure may include a transmission gate electrode array. A dielectric array may be disposed around the transmission gate electrode array. Optionally, a channel array may be disposed around the dielectric array. Furthermore, a ferroelectric array may be disposed around the channel array along its length. The integrated circuit may also include a plurality of horizontal gate electrode layers, wherein each layer is disposed at a predetermined distance from each other. Each of the plurality of horizontal gate electrode layers may be disposed adjacent to the ferroelectric array along its length.

[0224] In some embodiments, the integrated circuit may involve a transmission gate electrode array that is substantially cylindrical in form. The cylindrical transmission gate electrode array may optionally have a first diameter at one end and a second diameter at the other end, wherein the diameters are the same, or the first diameter is larger than the second diameter. In various variations, the transmission gate electrode array may also be configured as a solid array or a hollow array.

[0225] According to one embodiment, the integrated circuit may have a generally cylindrical array of transmission gate electrodes. In some embodiments, the array of transmission gate electrodes has a first diameter at a first end and a second diameter at a second end. These first and second diameters may be the same or different in various embodiments, wherein in some cases, the first diameter may optionally be larger than the second diameter.

[0226] In some embodiments, the transmission gate electrode array of the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at an opposite second end. Optionally, the integrated circuit may be configured such that the first and second diameters of the transmission gate electrode array are the same.

[0227] In some embodiments, the transmission gate electrode array of the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter of the transmission gate electrode array may be larger than the second diameter.

[0228] In some embodiments, the integrated circuit may include a transmission gate electrode array as part of a first vertical structure. This transmission gate electrode array may be substantially cylindrical in form. Optionally, the transmission gate electrode array is solid rather than hollow.

[0229] In some embodiments, the integrated circuit may have a hollow array of transmission gate electrodes. Specifically, the transmission gate electrode array, which is part of a first vertical structure and is disposed around the dielectric array and located within the channel array, may be hollow rather than a solid array. Forming the transmission gate electrode array as a hollow configuration may provide certain advantages related to material cost or ease of handling.

[0230] In some embodiments, the integrated circuit may include a dielectric column that is substantially cylindrical in shape. This cylindrical dielectric column is disposed around a transmission gate electrode column as part of a first vertical structure. The diameter of the dielectric column may be uniform along its length, or it may vary from one end to the other.

[0231] In some embodiments, the dielectric column of the first vertical structure is substantially cylindrical. Optionally, the dielectric column may have a first diameter at a first end and a second diameter at a second end. In various embodiments, the first and second diameters of the dielectric column may be configured to be the same or different.

[0232] In some embodiments, the dielectric column in the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end. The first and second diameters of the dielectric column can be configured to be the same.

[0233] An integrated circuit may include a generally cylindrical dielectric column, wherein the dielectric column has a first diameter at a first end and a second diameter at a second end. In some embodiments, the first diameter of the dielectric column is larger than the second diameter.

[0234] In some embodiments, the integrated circuit may include a channel array that is substantially cylindrical in shape. The channel array is disposed around a dielectric array, which itself is disposed around a transmission gate electrode array. Ferroelectric arrays are disposed around the channel array along the length of the cylindrical channel array.

[0235] In some embodiments, the channel array formed around the dielectric array in the first vertical structure is substantially cylindrical in shape. The channel array may have a first diameter at a first end and a second diameter at an opposite second end. The first diameter and the second diameter of the channel array may be the same, or the first diameter may be larger than the second diameter.

[0236] In some embodiments, the channel array in the first vertical structure may have a substantially cylindrical shape with a uniform diameter along its entire length. Specifically, the channel array has a first diameter at a first end and a second diameter at an opposite second end, wherein the first diameter is the same as the second diameter. This uniform cylindrical channel array extends parallel to the ferroelectric array and the plurality of horizontal gate electrode layers in the vertical structure.

[0237] In some embodiments, the integrated circuit may involve a generally cylindrical channel array, wherein the channel array has a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter of the channel array is configured to be larger than the second diameter.

[0238] In some embodiments, the integrated circuit may have a ferroelectric train that is substantially cylindrical in shape. The ferroelectric train is disposed around the channel train along the length of the channel train. The cylindrical ferroelectric train may optionally have a first diameter at a first end and a second diameter at a second end, wherein the diameters may be the same, or the first diameter may be larger than the second diameter.

[0239] In some embodiments, the integrated circuit may include a ferroelectric train that is substantially cylindrical. The ferroelectric train may have a first diameter at a first end and a second diameter at a second end. Optionally, the first diameter and the second diameter may be the same, or the first diameter may be larger than the second diameter.

[0240] In some embodiments, the ferroelectric train of the first vertical structure is substantially cylindrical, having a first diameter at a first end and a second diameter at a second end. Optionally, the first and second diameters of the ferroelectric train are configured to be the same.

[0241] In some embodiments, the integrated circuit may have a substantially cylindrical ferroelectric train having a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

[0242] In some embodiments, the integrated circuit further includes a dielectric terminal array disposed around the ends of the channel array. The dielectric terminal array is adjacent to the ends of the length of the channel array and also adjacent to the ferroelectric array.

[0243] In some embodiments, the integrated circuit further includes a drain selection layer disposed parallel to a plurality of horizontal gate electrode layers. The drain selection layer is positioned adjacent to a dielectric terminal row surrounding the ends of a channel column. In a first vertical structure, the dielectric terminal row is adjacent to the ends of the channel column's length and adjacent to a ferroelectric column.

[0244] In some embodiments, the integrated circuit further includes a second dielectric terminal array disposed around the other end of the channel array. The second dielectric terminal array is adjacent to the other end of the length of the channel array and also adjacent to the ferroelectric array.

[0245] In some embodiments, the integrated circuit further includes a source selection layer configured to be parallel to a plurality of horizontal gate electrode layers and adjacent to a second dielectric terminal column surrounding another end of the channel column. The source selection layer is positioned adjacent to the end of the length of the channel column and the ferroelectric column.

[0246] In some embodiments, the integrated circuit further includes a dielectric horizontal layer disposed within the channel column and adjacent to the ends of the transmission gate electrode columns. Specifically, the dielectric layer may be horizontally incorporated within the cylindrical channel column structure and positioned immediately adjacent to the ends of the vertical transmission gate electrode columns. This dielectric isolation layer helps define the transmission gate regions within the 3D NAND string.

[0247] In addition to the first vertical structure, the integrated circuit may also include a second vertical structure. The first vertical structure includes a transmission gate electrode array, a dielectric array disposed around the transmission gate electrode array, a channel array disposed around the dielectric array, and a ferroelectric array disposed along the length of the channel array. Each of the plurality of horizontal gate electrode layers is disposed at a predetermined distance from each other and adjacent to the ferroelectric array. The second vertical structure may be formed substantially the same as the first vertical structure, but is configured to be horizontally adjacent to the first vertical structure at a predetermined distance.

[0248] In addition to the first vertical structure described above, the integrated circuit may also include a second vertical structure. In some embodiments, the second vertical structure is formed to have substantially the same composition and dimensions as the first vertical structure. However, the second structure is configured to be horizontally adjacent to the first vertical structure, with a predetermined distance between them. Configuring the two identical vertical structures in this parallel arrangement enables certain circuit configurations, such as forming a dual-port 3D NAND structure with paired vertical structures.

[0249] The integrated circuit may include a first vertical structure and a second vertical structure, wherein the second vertical structure is formed to be substantially the same as the first vertical structure, but is configured to be adjacent to the first vertical column at a predetermined horizontal distance. In some embodiments, these first and second vertical structures are configured to form a dual-port 3D NAND structure.

[0250] In some embodiments, the plurality of horizontal gate electrode layers of the first vertical structure may be formed of at least one conductive material selected from the group consisting of: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides (such as TiSi2, CoSi2 and NiSi), graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys (such as AlCu and TiW), and conductive polymers.

[0251] In some embodiments, the first vertical transmission gate electrode array is formed of at least one of the following materials: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides (such as TiSi2, CoSi2, and NiSi), graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys (such as AlCu and TiW), and conductive polymers. The transmission gate electrode array can be constructed using one or more of these conductive materials.

[0252] In some embodiments, the first vertical ferroelectric column is formed from at least one of the following ferroelectric materials: perovskite; lead zirconate titanate (PZT); barium titanate (BaTiO3); strontium titanate (SrTiO3); bismuth ferrite (BiFeO3); potassium niobate (KNbO3); lithium niobate (LiNbO3); lithium tantalate (LiTaO3); sodium bismuth titanate (Na0.5Bi0.5TiO3); bismuth titanate (Bi4Ti3O12). Bismuth zinc niobate (Bi(Zn1 / 2Ti1 / 2)O3); Bismuth lanthanum titanate (BiLaTiO3); Bismuth nickel titanate (BiNiTiO3); Lead magnesium niobate-lead titanate (PMN-PT); Lead zirconate titanate (PLZT); Neodymium-doped bismuth titanate (Bi4-xNdxTi3O12); Hafnium-based oxides; Hafnium oxide (HfO2); Doped hafnium oxide; Zirconium-doped hafnium oxide (HfZrO2); Tungsten bronze structural materials; Strontium barium niobate (BS) N); lead barium niobate (PBN); potassium tantalate niobate (KTN); bismuth layered ferroelectrics; bismuth titanate (Bi4Ti3O12); strontium bismuth tantalate (SBT); calcium bismuth niobate (CBN); organic ferroelectrics; polyvinylidene fluoride (PVDF); TrFE (trifluoroethylene); P(VDF-TrFE) copolymer; Aurivillius phase oxides; rare earth manganates; YMnO3; lanthanum-modified lanthanum lead zirconate titanate (PLZT); nickel manganese oxide Ferroelectric materials (NiMnO3); relaxor ferroelectrics; lead magnesium niobate (PMN); lead scandium tantalate (PST); lead indium niobate (PIN); multiferroic materials; terbium manganate (TbMnO3); europium titanium oxide (EuTiO3); SbSI (antimony sulfide iodide); GeTe (germanium telluride); SnTe (tin telluride); thin film ferroelectrics; PZT thin films; SBT thin films; HfO2-based thin films; layered superlattices; or PbTiO3 / SrTiO3.

[0253] In some embodiments, the channel array of the first vertical structure is formed of at least one of the following materials: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), hafnium indium oxide (HIO), cadmium oxide (CdO), polycrystalline silicon, polycrystalline germanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-Silicon), crystalline germanium (c-Germanium), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polystyrene styrene (PPV), graphene, carbon nanotubes (CNTs), methylammonium lead halide (CH3NH3PbX3, X = Cl, Br, I), cesium lead halide (CsPbX3, X = Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), cobaltite, Ruddlesden-Popper phase, cage compounds, perovskite oxides, and magnetic semiconductors. The choice of channel array material can affect characteristics such as electron mobility, switching speed, and power consumption.

[0254] In some embodiments, the dielectric array described herein is formed from at least one of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), silicon nitride (Si3N4), aluminum nitride (AlN), silicon carbide (SiC), strontium titanate (SrTiO3), and barium strontium titanate. (BST), Lead zirconate titanate (PZT), Bismuth ferrite (BiFeO3), Magnesium oxide (MgO), Cerium oxide (CeO2), Nickel oxide (NiO), Cobalt oxide (CoO), Copper oxide (CuO), Manganese oxide (MnO), Zinc oxide (ZnO), Gadolinium oxide (Gd2O3), Dysprosium oxide (Dy2O3), Samarium oxide (Sm2O3), Europium oxide (Eu2O3), Terbium oxide (Tb4O7), Vanadium pentoxide (V2O5) Niobium pentoxide (Nb₂O₅), chromium trioxide (Cr₂O₃), ferric oxide (Fe₂O₃), molybdenum trioxide (MoO₃), tungsten trioxide (WO₃), ruthenium oxide (RuO₂), rhodium trioxide (Rh₂O₃), palladium oxide (PdO), silver oxide (Ag₂O), cadmium oxide (CdO), tin dioxide (SnO₂), antimony trioxide (Sb₂O₃), tellurium dioxide (TeO₂), iridium dioxide (IrO₂), and oxa dioxide. Platinum oxide (PtO2), gold oxide (Au2O3), beryllium oxide (BeO), magnesium aluminate (MgAl2O4), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeOx), bismuth trioxide (Bi2O3), bismuth titanate (Bi4Ti3O12), perovskite oxides, layered oxides, or complex transition metal oxides.

[0255] In some embodiments, one of the plurality of horizontal gate electrode layers and a first vertical structure may be configured to form a plurality of transistors. These transistors may include a first transistor as described herein. Specifically, the first vertical structure includes a transmission gate electrode array, a dielectric array disposed around the transmission gate electrode array, a channel array disposed around the dielectric array, and a ferroelectric array disposed around the channel array along the length of the channel array. The plurality of horizontal gate electrode layers are each configured to have a predetermined distance between them and to be adjacent to the ferroelectric array along the length of the ferroelectric array. One of these horizontal gate electrode layers and the first vertical structure together form a plurality of transistors, which may include the first transistor having the configuration described herein.

[0256] In some embodiments, the integrated circuit includes a first vertical structure. This vertical structure may involve a vertical plug array. Adjacent to the vertical plug array, a source electrode array and a drain electrode array may be disposed. A channel array may be disposed around the vertical plug array, the source electrode array, and the drain electrode array. Furthermore, a ferroelectric array may be disposed around the channel array. The integrated circuit may also involve a plurality of horizontal gate electrode layers, each configured to be spaced apart from each other at a predetermined distance. These horizontal gate electrode layers may each be configured to be adjacent to the ferroelectric array along the length of the ferroelectric array.

[0257] In some embodiments, the integrated circuit further includes an oxide / nitride / oxide stack configured to be adjacent to each of a plurality of horizontal gate electrode layers. The oxide / nitride / oxide stack can provide electrical isolation between the gate electrode layers while enabling the layers to control channel formation in a vertical channel array structure.

[0258] In some embodiments, the vertical plug array of the integrated circuit has a first diameter at a first end and a second diameter at a second end. The first diameter and the second diameter may be the same or different.

[0259] In some embodiments, the vertical plug array of the first vertical structure has a first diameter at a first end and a second diameter at a second end. The first diameter and the second diameter may be configured to be the same.

[0260] In some embodiments, the vertical plug array in the first vertical structure has a first diameter at a first end and a second diameter at a second end, wherein the first diameter is larger than the second diameter.

[0261] In some embodiments, the vertical plug array of the first vertical structure is configured as solid rather than hollow. Specifically, the vertical plug array has continuous material filling rather than empty conduits. Forming the vertical plug array as a solid configuration can provide specific advantages related to manufacturing simplicity or the integrity of adjacent components in the overall integrated circuit structure. However, other embodiments may use a hollow configuration for the vertical plug array, depending on specific design considerations.

[0262] In some embodiments, the integrated circuit may have a hollow vertical plug array. Specifically, the vertical plug array disposed adjacent to the source and drain electrode arrays in the first vertical structure may be hollow, rather than solid. Forming a hollow vertical plug array structure allows for additional design flexibility.

[0263] In some embodiments, the integrated circuit further includes a second vertical structure. The second vertical structure may be formed substantially the same as the first vertical structure, but is configured to be adjacent to the first vertical structure at a predetermined horizontal distance. In some embodiments, the first and second vertical structures may be configured to form a 3D AND structure or a 3D NOR structure.

[0264] In some embodiments, the integrated circuit further includes a second vertical structure. The second vertical structure may be formed substantially the same as the first vertical structure, but is configured to be adjacent to the first vertical structure at a predetermined horizontal distance.

[0265] In some embodiments, the integrated circuit may include a first vertical structure and a second vertical structure, wherein the second vertical structure is formed to be substantially identical to the first vertical structure, but is configured to be adjacent to the first vertical structure at a predetermined horizontal distance. The first and second vertical structures may be configured to form a 3D AND structure.

[0266] In some embodiments, the integrated circuit may include a first vertical structure and a second vertical structure, wherein the second vertical structure is formed to be substantially identical to the first vertical structure, but is configured to be adjacent to the first vertical structure at a predetermined horizontal distance. The first and second vertical structures may be configured to form a 3D NOR structure.

[0267] In some embodiments, the plurality of horizontal gate electrode layers of the first vertical structure may be formed of at least one material selected from the group consisting of: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides (such as TiSi2, CoSi2, NiSi), graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys (such as AlCu and TiW), and conductive polymers.

[0268] In some embodiments, the source electrode array of the first vertical structure is formed from at least one of the following: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicide, TiSi2, CoSi2, NiSi, graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys (such as AlCu and TiW), and conductive polymers.

[0269] In some embodiments, the integrated circuit further includes a gate electrode array formed of at least one of the following: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium oxide, ruthenium oxide, silicides (such as TiSi2, CoSi2, NiSi), graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys (such as AlCu and TiW), and conductive polymers.

[0270] In some embodiments, the ferroelectric train of the first vertical structure is formed from at least one of the following: perovskite, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), zinc bismuth niobate (B Hafnium-based oxides, hafnium oxide (HfO2), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium oxides, hafnium oxide (HfO2), doped hafnium oxide, zirconium-doped hafnium oxide (HfZrO2), tungsten bronze structural materials, barium strontium niobate (BSN). Lead barium niobate (PBN), potassium tantalate niobate (KTN), bismuth layered ferroelectrics, bismuth titanate (Bi4Ti3O12), strontium bismuth tantalate (SBT), calcium bismuth niobate (CBN), organic ferroelectrics, polyvinylidene fluoride (PVDF), TrFE (trifluoroethylene), P(VDF-TrFE) copolymer, Aurivillius phase oxides, rare earth manganates, YMnO3, lanthanum-modified lanthanum lead zirconate titanate (PLZT), nickel manganese oxide NiMnO3, relaxor ferroelectrics, lead magnesium niobate (PMN), lead scandium tantalate (PST), lead indium niobate (PIN), multiferroic materials, terbium manganate (TbMnO3), europium titanium oxide (EuTiO3), SbSI (antimony sulfide), GeTe (germanium telluride), SnTe (tin telluride), thin film ferroelectrics, PZT thin films, SBT thin films, HfO2-based thin films, layered superlattices, and PbTiO3 / SrTiO3.

[0271] In some embodiments, the channel array of the first vertical structure is formed from at least one of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), hafnium indium oxide (HIO), cadmium oxide (CdO), polycrystalline silicon, polycrystalline germanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon (c-Silicon), crystalline germanium (c-Germanium), gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT (poly(3-hexylthiophene)), polythiophene, polystyrene styrene (PPV), graphene, carbon nanotubes (CNTs), methylammonium lead halide (CH3NH3PbX3, X = Cl, Br, I), cesium lead halide (CsPbX3, X = Cl, Br, I), lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), cobaltite, Ruddlesden-Popper phase, cage compounds, perovskite oxides, and magnetic semiconductors.

[0272] In some embodiments, the vertical plug array of the first vertical structure is formed from at least one of the following: hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), silicon nitride (Si3N4), aluminum nitride (AlN), silicon carbide (SiC), and strontium titanate (SrTiO3). Barium strontium titanate (BST), lead zirconate titanate (PZT), bismuth ferrite (BiFeO3), magnesium oxide (MgO), cerium oxide (CeO2), nickel oxide (NiO), cobalt oxide (CoO), copper oxide (CuO), manganese oxide (MnO), zinc oxide (ZnO), gadolinium oxide (Gd2O3), dysprosium oxide (Dy2O3), samarium oxide (Sm2O3), europium oxide (Eu2O3), terbium oxide (Tb4O7), vanadium pentoxide (V2O) 5) Niobium pentoxide (Nb₂O₅), Chromium trioxide (Cr₂O₃), Ferric trioxide (Fe₂O₃), Molybdenum trioxide (MoO₃), Tungsten trioxide (WO₃), Ruthenium oxide (RuO₂), Rhodium trioxide (Rh₂O₃), Palladium oxide (PdO), Silver oxide (Ag₂O), Cadmium oxide (CdO), Tin dioxide (SnO₂), Antimony trioxide (Sb₂O₃), Tellurium dioxide (TeO₂), Iridium dioxide (IrO₂) Platinum dioxide (PtO2), gold oxide (Au2O3), beryllium oxide (BeO), magnesium aluminate (MgAl2O4), zinc selenide (ZnSe), zinc telluride (ZnTe), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), silicon germanium oxide (SiGeOx), bismuth trioxide (Bi2O3), bismuth titanate (Bi4Ti3O12), perovskite oxides, layered oxides, or complex transition metal oxides.

[0273] In some embodiments, an integrated circuit may include a plurality of transistors, any transistors as described herein, formed from one of the horizontal gate electrode layers and a first vertical structure. The first vertical structure may include components such as vertical plug arrays, source and drain arrays, channel arrays, and ferroelectric arrays. The horizontal gate electrode layers may be disposed at a predetermined distance from each other and adjacent to the ferroelectric array. Configuring the horizontal gate electrode layers and the first vertical structure in this manner allows the formation of transistors having characteristics such as those described herein. Attached Figure Description

[0275] These and other aspects will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0276] Figure 1This is a block diagram of an integrated circuit that may be a part of a semiconductor device such as a chiplet, according to embodiments of this disclosure;

[0277] Figure 2 A perspective view of a component according to an embodiment of the present disclosure is shown, the component having Figure 1 An integrated circuit is implemented on a semiconductor device, which is electrically connected to another device to form the component;

[0278] Figure 3 Illustrations of embodiments according to this disclosure are shown. Figure 1 A block diagram of the memory address space of an integrated circuit;

[0279] Figure 4 Illustrations of embodiments according to this disclosure are shown. Figure 1 A block diagram of the memory address space of an integrated circuit with a signal interface;

[0280] Figure 5 An illustration shows an integrated circuit that may be a part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure;

[0281] Figure 6 A perspective view of a component according to an embodiment of the present disclosure is shown, the component having Figure 1 Integrated circuits are implemented on semiconductor devices, which are electrically connected to the system-on-a-chip.

[0282] Figure 7 A perspective view of the component is shown, the component having a semiconductor device and a second semiconductor device, the semiconductor device having an array of processing elements, and the second semiconductor device having an array of micro-repositories;

[0283] Figure 8 Components of a semiconductor device including several memory types according to embodiments of the present disclosure are shown;

[0284] Figure 9 An embodiment of the present disclosure is shown comprising a semiconductor device and another semiconductor device, the semiconductor device having a system-on-a-chip and the other semiconductor device having a micro-repository disposed on top;

[0285] Figure 10 A semiconductor component according to an embodiment of the present disclosure is shown, which is incorporated into a daisy-chain configuration of a microrepository that is operatively connected to a multiplexer and managed by a counter for coordinating data selection and retrieval.

[0286] Figure 11A semiconductor component according to an embodiment of the present disclosure is shown, wherein the semiconductor component incorporates a daisy-chain configuration of micro-repositories in a plurality of semiconductor devices, the micro-repositories being operatively connected to a multiplexer and managed by a counter for coordinating data selection and retrieval;

[0287] Figure 12 The illustration depicts a three-dimensional (3D) memory array configured as a 3D-NOR or 3D-AND structure according to an embodiment of the present disclosure, characterized by a series of ferroelectric field-effect transistors (FeFETs) having interconnected drain terminals and individual gate terminals, the drain terminals being linked to a common select line and the gate terminals being connected to corresponding read / write enable lines, both of which are coupled to a common bit line.

[0288] Figure 13 A three-dimensional (3D) memory column according to an embodiment of the present disclosure is depicted, the 3D memory column being configured as a 3D-NAND structure including a vertically stacked ferroelectric field-effect transistor (FeFET);

[0289] Figure 14 A three-dimensional (3D) memory column according to an embodiment of the present disclosure is depicted, the three-dimensional (3D) memory column being configured as a 3D-NAND with integrated transmission gates;

[0290] Figure 15 The illustration shows a 3D memory column 1500 according to an embodiment of the present disclosure, which can be configured to have an independent read / write enable capability in a three-dimensional (3D)-NOR or 3D-AND structure;

[0291] Figure 16 A cross-sectional view of a 3D memory structure configured as a single-port 3D NAND according to an embodiment of the present disclosure is shown;

[0292] Figure 17 A cross-sectional view of a 3D memory structure arranged as a dual-port 3D NAND according to an embodiment of the present disclosure is shown.

[0293] Figure 18 The illustration shows a 3D memory structure that can be configured as a 3D NOR vertical transistor memory array according to an embodiment of the present disclosure;

[0294] Figure 19 A planar FeFET according to an embodiment of the present disclosure is shown; and

[0295] Figure 20 The electrical characteristics of an embodiment of a FeFET according to an embodiment of the present disclosure are shown. Detailed Implementation

[0297] Figure 1 A block diagram of an integrated circuit 100 according to one embodiment of the present disclosure is shown. The integrated circuit 100 can be packaged as a bondable chiplet (e.g., face-to-face chiplet bonding). The integrated circuit (IC) 100 includes a module group 106 comprising modules 108, 110, 112, and 114. The IC 100 also has a shared write port 102 configured to write to the module group 106 using a write peripheral 104. Furthermore, it includes read peripherals 116, 118, 120, and 122 and read ports 124, 126, 128, and 130 configured to read from modules 108, 110, 112, and 114.

[0298] Write port 102 can be configured to provide a single write address space to all module groups 106, where each of modules 108, 110, 112, and 114 has dedicated read ports 124, 126, 128, and 130, respectively. Integrated circuit 100 can be packaged as a portion of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet, or an IC package, with or without electrical contacts, electrical bumps, etc.). The chiplet can be electrically connected to the other device, including, for example, by bonding, soldering, wafer-to-wafer bonding, face-to-face chiplet bonding, chiplet-to-wafer bonding, chiplet-to-interposer bonding, and / or the chiplets can be connected together using an interposer or other interface technologies. When electrically connecting the chiplet to another device, an interposer may not be used, one interposer may be used, or multiple interposers may be used, or other interface technologies common in heterogeneous 3D system-in-package solutions may be utilized.

[0299] Each read port (124, 126, 128, 130) in the chiplet may have electrical contacts on one or more sides of the chiplet. Read ports 124, 126, 128, 130 may use multi-loop pipeline circuitry. When bonded to another device (e.g., wafer, chiplet, SoC, package, FPGA, etc.), the electrical contacts may be queued in a manner that provides dedicated access to a specific module among modules 108, 110, 112, 114. For example, a processing / computing element may exclusively access module 108 via read port 124, and module 108 may contain neural network weights in a register file. Similarly, different processing / computing elements may exclusively access module 110 via read port 126, and module 110 includes different register files. In this particular embodiment, the arrangement of the electrical contacts ensures that each computing / processing element has dedicated access required to efficiently perform its specific computations, thereby providing a compact, modular, and scalable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, and 114. Without dedicated access, different processing elements might have to queue to use the same resources, which would slow down overall processing speed. By providing dedicated access, the proposed chiplet ensures that each processing element can operate at its maximum capacity without interference from other computing elements in this particular embodiment.

[0300] The write peripheral 104 is a peripheral circuit device responsible for processing data and writing data to memory cells located within modules 108, 110, 112, and 114. The write peripheral 104 may include dedicated contacts that allow the chip to be electrically connected (e.g., bonded) to a chiplet of the integrated circuit, enabling the write port 102 to be accessed via a shared write logic system. This shared write logic system involves utilizing a shift register-based design with different voltage levels, preferably a high-voltage design, having shared write address and data components. This shared write logic system is designed to be accessed via a bonded chiplet, another bonded chiplet, and / or via other circuit devices within the same package as the integrated circuit 100. The shift register allows the system to move data through a series of stages, where each subsequent stage receives data from the previous stage. By utilizing shift registers, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location within the chiplet where data is written.

[0301] In another embodiment, interlock 132 can disable read ports 124, 126, 128, and 130 while data is being written to module group 106 via write port 102. Similarly, interlock 132 can disable write port 102 while read operations are being performed on read ports 124, 126, 128, and 130. The written data can then be accessed concurrently by all processing elements that need to read data via the corresponding read port among read ports 124, 126, 128, and 130. This ensures that all processing elements have their most frequently used data available, regardless of other reads performed concurrently by other processing elements.

[0302] The write peripheral 104 circuitry includes a write driver. This unit receives data to be written and converts that data into appropriate signals that can change the state of the memory cell. Depending on the type of memory technology used, these signals may involve voltage levels, current pulses, or other types of energy. Due to the specific voltage requirements of the chiplet, shared write logic systems may be high-voltage. The write driver must provide sufficient power to reliably change the state of the memory cell, but it must also operate within appropriate parameters to avoid damage or unnecessary wear.

[0303] The write peripheral 104 circuit can also have a data buffer or a write buffer. This component temporarily stores the data to be written, allowing write operations to be performed at an optimal pace. By balancing the rate at which data enters the memory with the rate at which memory cells can be written, the write buffer helps prevent data loss and optimize system performance.

[0304] In some embodiments, the write peripheral 104 may further include a write control unit that orchestrates the sequence of operations during the write process. It generates control signals to activate the write driver at appropriate times, controls the data flow from the write buffer, and coordinates the timing of the write operations. By synchronizing these various activities, the write control unit ensures efficient and reliable write operations.

[0305] The write peripheral 104 may also include data encoding mechanisms to improve reliability and data integrity. For example, these mechanisms encode the data in a way that allows potential errors to be detected and, in some cases, corrected when the data is read later, before it is written to the memory cell. This can be helpful in systems where data integrity is a higher priority, such as in servers or scientific research equipment.

[0306] The write peripheral 104 may also include a timing unit that acts as the system heartbeat, supplying clock signals to synchronize the operation of various components of the system. In some systems, it may include components such as an oscillator, clock generator, or phase-locked loop. The timing unit ensures that all operations occur at appropriate times relative to each other.

[0307] IC 100 can be implemented as a face-to-face bonded chiplet, wherein modules 108, 110, 112, and 114 are formed from non-volatile memory. In some specific embodiments, IC 100 may also have dynamic allocation circuitry to allocate memory blocks to module group 106 based on the usage of module group 106 (e.g., each module 108 may include dynamic allocation circuitry for dynamically allocating a series of read locations for a corresponding processing element).

[0308] IC 100 has multiple clocks, each of which feeds into a corresponding module among the multiple modules, thereby providing decoupled timing for each corresponding module relative to the other modules among the multiple modules. Module group 106 can be arranged in any topology known to those skilled in the art. The bit cell density in module group 106 can be up to 10 times higher than that of embedded SRAM cells.

[0309] IC 100 can be formed on a chiplet, which includes a first side and a second side, wherein the second side is configured for bonding to a second semiconductor device. IC 100 may include high-voltage write logic adjacent to the first side of the chiplet. Decoder circuitry, driver circuitry, and register circuitry can be formed on a silicon substrate portion of the chiplet, while module group 106 is formed on a second layer portion of the chiplet. The second semiconductor device may include a plurality of processing elements. Each processing element includes a corresponding interface for communicating with a corresponding module among the plurality of modules on module group 106 when the second semiconductor device is bonded to the chiplet.

[0310] Silicon substrates have traditionally served as the initial stage in IC manufacturing, focusing on creating active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are employed to shape complex transistor structures. These processes operate on a very small scale. The application of photolithography, etching, and implantation techniques enables precise definition of transistor structures. The importance of silicon substrates lies in their ability to establish the fundamental building blocks required for signal processing, amplification, and control within ICs. This layer is sometimes referred to as the "front-end process" ("FEOL").

[0311] Next, a second layer can be added in the manufacturing process. This second layer traditionally serves the role of interconnect fabrication, facilitating electrical connections between various IC components. This level traditionally focuses on the creation of passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The second-layer process typically differs from the process used on the silicon substrate in terms of precision and scale. Interconnects are formed by depositing and patterning metal layers (typically aluminum or copper) to build a wiring network. Dielectric layers, such as silicon dioxide or low-k dielectrics, are introduced to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to establish the necessary interconnects, enabling the routing and distribution of electrical signals throughout the IC. However, as described herein, circuitry can be used within this second layer (sometimes referred to as the “back-end process” or “BEOL”).

[0312] Alternative embodiments of IC 100 can be implemented as stacked dies, a monolithic design, a TSV, or a through-silicon via (TSV). In a stacked die design, several dies can be stacked on top of each other, with each die performing different functions, such as memory and processing. Stacked dies can communicate via wire bonding, microbumps, or bumpless bonding. In a monolithic design, various functions and modules of IC 100 can be integrated onto a single die, resulting in a more compact and power-efficient design.

[0313] In addition, IC 100 may include one or more interlocks 132 to prevent collisions during data reading and writing. Module group 106 may be formed from various non-volatile or semi-volatile (e.g., extremely long refresh periods) memory technologies, such as static random access memory (SRAM), ferroelectric field-effect transistor (FeFET), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin-transfer torque (STT) memory, charge traps, floating gate memory, and / or Schottky diodes.

[0314] Module group 106 may utilize a static random access memory (SRAM) topology. The SRAM topology may employ a cross-coupled flip-flop structure (e.g., latch flip-flops) to ensure that the stored data remains intact as long as power is supplied. Therefore, in some specific embodiments, module group 106 may utilize heterogeneous types of memory, including volatile and non-volatile memory types.

[0315] Module group 106 can utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. The flash memory topology disclosed herein has a matrix of memory cells, each memory cell including a floating-gate transistor or a charge trapping device. Module group 106 can also use wear leveling techniques to extend the lifetime of the memory cells.

[0316] Module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. FeRAM topology utilizes ferroelectric materials capable of maintaining polarization states. In a particular embodiment, such a memory topology may utilize FeFETs to retain state information and program the ferroelectric material. These ferroelectric materials can be used to retain state information and act as memory bit cells.

[0317] Module group 106 can utilize phase change memory (PCM) topology, which is a non-volatile memory technology that uses reversible phase changes in materials to store data. PCM topology can include any phase change material, such as chalcogenide alloys or chalcogenide glasses housed in memory cells.

[0318] Module 106 can utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the resistance switching phenomenon. The ReRAM topology can utilize thin film materials that exhibit reversible resistance changes when an electrical excitation is applied.

[0319] Module group 106 can utilize a spin-orbit torque (SOT) magnetic random access memory topology. SOT-MRAM is a non-volatile memory that uses spin-orbit torque to switch the magnetic state of storage elements. The SOT-MRAM topology can incorporate a magnetic tunnel junction (MTJ) structure and utilize spin-orbit coupling effects for writing and reading data. The MTJ can have a dielectric layer between the magnetically fixed layer and the magnetically free layer. Writing can be accomplished by switching the magnetization of the free magnetic layer by injecting an in-plane current into an adjacent SOT layer. Reading can be accomplished by injecting current into the MTJ. In some specific embodiments, SOT-MRAM can optimize the spin-orbit material by using a current-driven switching scheme while minimizing write power consumption.

[0320] Module group 106 can utilize a spin-transfer torque (STT) magnetic random access memory topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of the storage elements. The STT-MRAM topology can use a magnetic tunnel junction (MTJ) structure, where the magnetization orientation determines the stored data. Furthermore, for example, the orientation of the magnetic layers in the magnetic tunnel junction or spin valve can be changed using spin-polarized current.

[0321] IC 100 may include a single write peripheral 104 with a dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock. Figure 1 (Not shown in the image). In addition, module group 106 can be organized into separate partitions, each partition including dedicated read peripherals 116, 118, 120, and 122 with independent clocks.

[0322] Another possible embodiment of IC 100 includes an interface (e.g., the same, different, higher, or lower voltage) to enable data transfer outside the IC 100 package. In other specific embodiments, IC 100 may also include an integrated microcontroller unit (MCU) or digital signal processor (DSP) for processing data within the IC.

[0323] Figure 2 An embodiment according to this disclosure is shown. Figure 1 The diagram shows a perspective view of component 200 implemented on chiplet 230, where integrated circuit 212 is bonded to second device 226. Integrated circuit 212 is a circuit arrangement within chiplet 230. Second device 226 may be a chiplet, semiconductor wafer, semiconductor package, encapsulated circuit arrangement, etc. For example, second device 226 may be an AI accelerator, such that each processing unit has read access to a module (or a predetermined set) of module group 236. In another embodiment, second device 226 may be a network controller, in which offloading circuitry is present to read data from each module to process incoming / outgoing packets, etc. Component 200 includes module group 236, which has multiple modules, including first module 232 and second module 234. Figure 2 Several modules are shown; however, for clarity, only modules 232 and 234 are indicated by reference numerals. Integrated circuit 212 also includes a shared write port 222. Shared write port 222 is connected to write peripheral 202.

[0324] While the second device 226 can write data to any module within the module group 236 via the address and data buses, using clock and enable signals and the shared write port 222, other methods of writing data can also be considered. For example, serial connections, parallel connections, and various buses or ports can be used, such as DDR (Double Data Rate) interfaces, SRAM (Static Random Access Memory) interfaces, NAND flash memory interfaces, NOR flash memory interfaces, HBM (High Bandwidth Memory) interfaces, GDDR (Gradient Double Data Rate) interfaces, NVMe (Non-Volatile Memory Fast Display) interfaces, SPI, I2C, etc. Each module in the group has a read port with a read address 218 (for sending an address to module 234) and read data 214 (which is data read from chip 232).

[0325] Module group 236 is formed on a chiplet 230 having two sides. Chiplet 230 includes a surface 228, which can be bonded to and complement the second device 226. Chiplet 230 can be formed by forming circuitry on a silicon substrate 204 and then by adding a second layer 206. In other embodiments, these layers can be reversed and / or other layers can be added, removed, etc. Read address 218 and read data 220 are used to read module 232.

[0326] While the second device 226 can read data from module 232 using the clock and enable signals via the address and data buses, other methods of reading data can also be considered. For example, serial connections, parallel connections, and various buses or ports can be used, such as DDR (Double Data Rate) interfaces, SRAM (Static Random Access Memory) interfaces, NAND flash memory interfaces, NOR flash memory interfaces, HBM (High Bandwidth Memory) interfaces, GDDR (Gradient Double Data Rate) interfaces, NVMe (Non-Volatile Memory for Graphics) interfaces, SPI, I2C, etc.

[0327] All read ports (e.g., 218 and 222) are configured to be inactive when a write operation is applied to shared write port 222. Read ports can also be configured to process reads concurrently with each other. Shared write port 222 is configured to write to the address space, wherein shared write port 222 is configured to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion of the address space. Each of the plurality of modules 236 includes an independent read port for concurrent reading via the respective independent read port of any of the plurality of modules.

[0328] Each read port for a given module may include a contact for mating with circuitry found within the second device 226 via metal contacts. Therefore, metal contacts may be present on the top layer 208, configured to mate with metal contacts on the surface 228 of the chiplet 230, allowing the metal contacts to share a read space with the read space of the modules in module 236. The read spaces of module group 236 may all share a common space with each other (as referenced). Figure 3 and Figure 4 (as described).

[0329] In one embodiment, the read peripheral for the first module 232 is implemented on the silicon substrate 204 (sometimes referred to as the front-end process). A second layer 206 (sometimes referred to as the back-end process) may then be built on top of the silicon substrate 204 (and any circuitry) during the manufacturing process and may contain corresponding memory bit cells. In another embodiment, the read peripheral for the first module 232 is implemented in the second layer 206 and is disposed between the module group 236 and the surface 228 of the chiplet 230.

[0330] Module group 236 can be configured to process write commands only during reset. The write command can be a "slow write" command. That is, module group 236 can have a very low write speed relative to its read speed. When module group 236 is used to read data, the write logic can be frozen (or disabled). In some specific embodiments, integrated circuit 212 provides the functionality to allocate memory blocks to module group 236 based on its usage. In other embodiments, the memory addresses, along with the allocation, are fixed. Integrated circuit 212 can be implemented as a face-to-face bonded chiplet 230. Face-to-face bonding can be bumpless wafer bonding.

[0331] Module group 236 may have a single write peripheral 202. In other embodiments, each module of module group 236 may have a dedicated write peripheral utilizing a shared clock. In other embodiments, module group 236 may also be organized into separate partitions, each partition having a dedicated read peripheral, wherein each dedicated read peripheral has an independent clock. A partition may be one, two, or more modules of module group 236.

[0332] The overall architecture of the write peripheral 202 circuitry may include a series of different components, including write drivers, address decoders, sense amplifiers, data input latches, data buses, and / or some combination thereof. Write drivers or write buffers are responsible for transferring data to memory cells. They amplify input signals to achieve a level suitable for the memory cell. Address decoders are used to interpret the memory address fed as input, the address to which data needs to be written. They can be used to select the target memory cell by activating specific rows and columns of the memory array linked to that address. Sense amplifiers are used to identify and amplify signals from memory cells during read operations and also participate in flushing memory cells after data is written during write operations. Write operations are triggered by a write enable signal. When a write command is initiated, this signal drives the write driver and decoder into the write process. Data input latches can be used as temporary storage units, holding the dataset to be written to memory until the write operation is performed. A data bus with a transmission path can be used to facilitate the movement of data from the data input latches to the memory cells.

[0333] Write operations to the module group can be performed via a priority arbitration circuit that facilitates access to modules in a predetermined order, and the shared write port 222 can be configured to write to a virtual address space mapped onto the physical memory space. The integrated circuit 212 may include high-voltage write logic used within the write peripheral 202, and the second semiconductor device 226 may include multiple processing elements, each including a corresponding interface for communicating with a corresponding module of the module group 236. Furthermore, the chiplet 230 may include an interface on the second side to the shared write port 222, thereby interfacing with a supplementary interface on the second semiconductor device 226.

[0334] Integrated circuit 212 may also include a power gating circuit that selectively shuts off the power of modules in the plurality of modules 236 when not in use. Furthermore, integrated circuit 212 may have a write peripheral 202 for the module group 236 connected to dedicated I / O pads to enable external data transfer from the integrated circuit package.

[0335] Integrated circuit 212 may utilize multiple modules of module group 234 that are grouped together. In certain embodiments, these modules may be synchronized with each other. In some cases, all modules are synchronized, while in other instances, only specific modules will be synchronized. For example, when reading data from one module in module group 236, the circuitry on second device 226 may need to be synchronized with that specific module.

[0336] To synchronize the modules, integrated circuit 212 can use various timing techniques. In some cases, multiple clocks can feed each corresponding module of module group 236, thereby allowing each module to have decoupled timing relative to other modules in the group. This decoupling ensures that any delay in one module will not affect the functionality of other modules. It is worth noting that the clocks used may or may not need to be synchronized. In some cases, a common clock can be used to synchronize the modules. In other embodiments, one or more clock signals may be provided by second device 226.

[0337] In alternative embodiments, other synchronization techniques can be used, such as phase comparison of the clock signal or phase-locked loop (PLL) synchronization methods. Another embodiment of the synchronization module in the IC can use delay-locked loop (DLL) synchronization. In this method, a delay element is added to the clock signal path, and the output is compared with the input clock signal. The feedback loop adjusts the delay element until the output of the DLL matches the input, thereby resulting in synchronization of the clock signals.

[0338] In another embodiment, integrated circuit 212 can use a combination of different synchronization techniques to achieve synchronization between modules. For example, depending on the specific requirements of the modules, some modules may use PLL synchronization, while other modules may use clock delay lines or DLL synchronization. Furthermore, integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in the event of a failure of one method. For example, integrated circuit 212 may use both phase-locked loop (PLL) synchronization and DLL synchronization simultaneously, so that if one method fails, the other method can still maintain synchronization.

[0339] Figure 3 An embodiment according to the present disclosure is illustrated. Figure 1 A block diagram 300 of the memory address space of the integrated circuit is shown. The memory address space includes a write address space 316 and read data address spaces 310, 312, and 314.

[0340] The write address space 316 includes various units that can store data (e.g., weights) and / or instructions. These units are referred to as memory addresses. Module group 302 includes multiple memory modules 304, 306, and 308. The write address space 316 can be distributed among memory modules 304, 306, and 308, such that the write address space 316 spans from 0 to N. M-1. For example... Figure 3 As shown, module group 302 has N memory modules 304, 306, and 308, where N is a positive integer, and each module has a memory size of M. The total number of unique write memory addresses in the write address space will be N. M, N M can range from 0 to N. Integer references of M-1.

[0341] Starting from address 0, the memory addresses written into address space 316 are arranged sequentially up to N. M-1. In other words, the first address is 0, and the last address is N. M-1, covering a total of N There are M addresses. The sorting can be linear (increasing by 1 for each address) or dependent on some other specified pattern.

[0342] Write-to-memory addressing can be implemented in various ways based on the system architecture. One approach used in a particular embodiment is to use a base register and a limit register. The base register holds the minimum legal physical write-to-memory address, and the limit register specifies the size of the range. Therefore, to generate a logical address, you need to add the base address to the relative address. In other embodiments, a memory addressing scheme can be used where the base address is set to 0. Other write-to-memory addressing techniques will be understood by those skilled in the art.

[0343] For any device writing to module group 302, each memory module can have a unique set of write memory addresses, making all memory addresses within module group 302 unique in terms of the data being written. For example, the first module starts at address 0, and the last module starts at address N. The allocation ends at M-1. In some embodiments, the allocation may depend on the memory management system of the device writing data to modules 304, 306, 308, and the allocation ranges from simple fixed partitioning schemes to more complex dynamic partitioning models.

[0344] For example, in a simple linear model where each module (304, 306, or 308) has M addresses of equal size, the first module 304 will have write addresses 0 to M-1, the second module will have write addresses M to 2M-1, the third module will have write addresses 2M to 3M-1, and so on. The Nth module 308 will therefore have addresses from (N-1) M to N The write address of M-1.

[0345] It is expected that ordinary technical personnel in related fields can use it from 0 to N Other implementations of the write memory address of M-1 depend on various factors, such as hardware architecture, operating system, memory management scheme, and the nature of the programs running on the system.

[0346] Module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 can have overlapping address spaces, can have contiguous address spaces, or can have a common extension address space. Read address spaces 310, 312, and 314 can be independent of each other. The system includes three independent read address spaces, labeled as read address spaces 310, 312, and 314. Each of these read address spaces is different from the others, meaning that reads can be performed in each space without affecting the others.

[0347] The read address spaces 310, 312, and 314 can be defined as contiguous blocks of memory addresses, each with its own start and end addresses. Within module group 302, each read address space 310, 312, and 314 can have an address range corresponding to values ​​from 0 to M-1, where M is the maximum value determined by the size of the modules 304, 306, and 308 used.

[0348] In one embodiment, a processing unit is allowed to interface with each of the read address spaces 310, 312, 314, and concurrent reads can be implemented as described herein. The independence of the read address spaces 310, 312, 314 ensures that each processing unit can access the data it needs without causing any interference or conflict with other processing units.

[0349] Figure 4 The illustration shows an embodiment according to the present disclosure. Figure 1 A block diagram of the memory address space with signal interfaces in an integrated circuit. Figure 4 The signals used can be used in conjunction with any of the embodiments described herein. However, those skilled in the art will understand that different signaling schemes can be used.

[0350] Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. The write peripheral 411 includes a write address bus with the address of the data to be written, a write data bus with the data, and a write clock that causes a write to occur (e.g., on the rising or falling edge of a clock signal). A write occurs only when a write enable signal indicates that a write should occur. Any logic can be used; for example, a high voltage can correspond to 1 and a low voltage can correspond to 0, or vice versa. In some embodiments, the write peripheral 411 may be on chiplet 230, and in other embodiments, the write peripheral 411 may be on a second device 226.

[0351] Module group 402 includes modules 404, 406, and 408, each module having a corresponding read peripheral 410, 412, and 414. Each of the read peripherals 410, 412, and 414 has a read address bus for sending read addresses, a read data bus for receiving data, a read clock for timing the output of digital data, and an output enable as a prerequisite for outputting data. Any logic can be used; for example, a high voltage can correspond to 1 and a low voltage can correspond to 0, and vice versa. In other embodiments, multi-bit or analog data storage can be used. In some embodiments, one or more of the read peripherals 410, 412, and 414 can be on chip 230, and in other embodiments, one or more of the read peripherals 410, 412, and 414 are on a second device 226.

[0352] Figure 5 An illustration is shown of an integrated circuit 500 that can serve as part of a semiconductor device such as a chiplet, according to one embodiment of the present disclosure. The integrated circuit 500 may be disposed on a semiconductor device (such as a chiplet) having a silicon substrate 506 and a second layer portion 508. Within the integrated circuit 500, an array cross-section forming a module 502 may be present, wherein a three-dimensional column array of memory bit cells 522 has components required for storing memory in a non-voltage, semi-volatile memory or a memory format as described herein.

[0353] Even if only a single module 502 is shown, the integrated circuit 500 may also include a group of modules having multiple modules including a first module and a second module, etc. Memory bit cells 522 are written to via shared write ports 512, 516, which include both a write address bus line 512 and a write data bus 516. These buses pass through the second layer 508 and can be connected to a second semiconductor device via an intermediary. The second device has electrical contacts on a supplementary surface 518, allowing it to be electrically coupled to the write address and data buses. Memory bit cells 522 can be read via read ports 524, 526, which include a read address bus line 524 and a read data bus 526. Both of these buses can also pass through the second layer 508 to reach a second semiconductor device coupled to surface 518, which also has supplementary electrical contacts to allow it to be electrically coupled to the read address and data buses.

[0354] Various memory technologies can be used for memory bit cells 522, such as a vertically connected fabric structure formed by non-volatile memory unit cells arranged in a three-dimensional column array 522. Memory bit cells 522 can utilize one or more of cross-point, 3D NAND, 3D NOR, 3D AND, and / or stacked planar layers.

[0355] In some embodiments, the integrated circuit 500 is electrically connected to a second semiconductor device ( Figure 5 (Not shown in the image), the second semiconductor device includes another integrated circuit, which may be a system-on-a-chip or a field-programmable gate array (FPGA). In some embodiments, the memory bit cell 522 may be formed of various non-volatile memory types such as FeFET, FeRAM, ReRAM, SOT, or STT. Additionally, alternatively, or optionally, the memory bit cell may be formed of a non-volatile memory unit cell having a 2-terminal device, a 3-terminal device, or a 4-terminal device.

[0356] For example, the memory unit bit cell 522 can be formed of a ferroelectric material, such as a ferroelectric tunnel junction, diode, capacitor, single-gate transistor, or dual-gate transistor. Alternatively, the memory unit bit cell 522 can be formed of a memristor material, such as at least one ReRAM, or of a magnetic material, such as at least one spin-orbit torque device or at least one spin-transfer torque device. Furthermore, the non-volatile memory unit cell 522 can also be formed of a phase-change material or an antiferroelectric material.

[0357] In some alternative embodiments, the nonvolatile memory unit 522 may be formed of other types of materials, such as phase change materials, antiferroelectric materials, or multi-bit PCM materials. The nonvolatile unit may be formed using different structures, such as resistive random access memory (RRAM) technology, magnetic random access memory (MRAM) technology, or ferroelectric random access memory (FRAM) technology.

[0358] Furthermore, in some implementations, 3D NAND technology can be used to form the memory unit bit cell 522. For example, the memory unit bit cell 522 can be formed from stacked memory layers, where each layer includes multiple memory cells that can be accessed using shared bit lines. In such a case, read ports 524, 526 can be coupled to bit lines, and write ports 512, 516 can be coupled to word lines that control access to each layer.

[0359] In another embodiment, the 3D interconnect architecture can be constructed using stacked layers of NAND gates, NOR gates, or AND gates, and in some cases, different types of logic gates can be combined to optimize the functionality of the structure. Furthermore, the 3D interconnect architecture can be formed using through-silicon via (TSV) technology, which allows for vertical interconnection between different layers of the structure.

[0360] Furthermore, the non-volatile memory unit may include 2-terminal devices, such as capacitors or memristor devices connected in series with or not connected in series with additional selector devices (such as diodes); 3-terminal devices, such as floating-gate transistors or transistors with access gates; or 4-terminal devices, such as transistors with two access gates. The type and configuration of the non-volatile memory unit 522 may depend on specific application requirements, including circuit speed, power consumption, and reliability. The memory unit may include either a single ferroelectric transistor or a 6T SRAM cell. The memory unit may be a combination of many different devices, including but not limited to one or more of transistors, memristors, capacitors, etc.

[0361] In some embodiments of this disclosure, ferroelectric materials can be used to form non-volatile memory unit cells 522. Ferroelectric materials can be implemented as any type of device, including but not limited to thin-film devices such as ferroelectric tunnel junctions, capacitors, single-gate transistors, or dual-gate transistors.

[0362] In another embodiment, the non-volatile memory unit 522 may be formed of a memristor material, such as a metal oxide memristor (MOM), a conductive bridged RAM (CBRAM), or a valence-variable memory (VCM), each of which offers different benefits in terms of power consumption, speed, durability, etc.

[0363] Furthermore, in some embodiments, the non-volatile memory unit 522 may be formed of a magnetic material, such as a spin-orbit torque (SOT) device, a spin-transfer torque (STT) device, or a vertical magnetic tunnel junction (p-MTJ).

[0364] In one embodiment, a module group may include a plurality of modules, each of which can be accessed via dedicated read ports 524, 526 having a dedicated read peripheral 520, while sharing the same write ports 512, 516 and a shared write peripheral 510. The shared write ports 512, 516 may be configured to selectively write to one or more modules (including memory bit cells 522) within the module group. Each module may have the same or different sizes, and different module sizes may be configured to optimize the utilization of the memory array under different operating scenarios, etc.

[0365] Furthermore, the integrated circuit 500 can be formed using different manufacturing processes and technologies, including but not limited to CMOS or bipolar-CMOS-DMOS (BCD) processes, silicon-on-insulator (SOI) processes, FinFET processes, silicon-germanium (SiGe) processes, gallium arsenide (GaAs) processes, etc.

[0366] In some embodiments, a three-dimensional column array in the form of memory bit cells 522 is configured as a microvault. Additionally or alternatively, each microvault in the microvault will have a dedicated read peripheral 520 and a write peripheral 510, the write peripheral being a dedicated write peripheral rather than a shared write peripheral. That is, in some embodiments, each microvault includes a dedicated write connection and a dedicated read connection, and a predetermined number of microvaults (e.g., two or four) may have dedicated write connections and dedicated read connections with or without corresponding dedicated peripherals, etc.

[0367] Figure 6 A perspective view of a component 600 according to an embodiment of the present disclosure is shown. The component 600 has features implemented on a semiconductor device (such as chiplet 230). Figure 1 In the integrated circuit, the semiconductor device is electrically connected to the system-on-chip (“SOC”) 610. In this embodiment, the semiconductor device is a small chip 230 electrically connected to the system-on-chip (“SOC”) 610.

[0368] refer to Figure 6 The SOC 610 includes a silicon substrate 602 on which multiple processing elements are formed, including processing element 606. The processing elements can communicate with each other via an on-chip network (“NOC”) 604, which is a communication architecture that guides data transfer between the processing elements. The communication architecture can take various forms, including buses, switches, NOCs, etc. The NOC 604 in the SOC 610 guides data traffic between various nodes (e.g., the processing elements 606) and links, which provide communication paths between the nodes.

[0369] The plurality of processing elements, including processing element 606, can be any suitable type of processor capable of executing instructions, including microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), or application-specific integrated circuits (ASICs).

[0370] Furthermore, the SOC 610 may include various modules, such as module 232, which are grouped together to provide memory functionality to component 600 as described herein. Modules in module group 236 may be coupled to corresponding processing elements to provide them with readable memory. In some embodiments, the coupling between a module (e.g., module 232) and a processing element (e.g., 606) may be achieved via interconnects on silicon substrate 602.

[0371] After the circuitry is formed on the silicon substrate 602, a second layer 608 can be disposed on top of the substrate. The second layer 608 can be any suitable material, such as an insulating material, metal, dielectric, or interconnect layer, and it can be bonded to the chiplet 230. Bonding can be performed using any suitable technique, including but not limited to adhesives, soldering, or forging.

[0372] Overall, component 600 provides for chiplet 230 (which may include Figure 1 The chiplet 230 is integrated with the SOC 610 in various ways. Integrating the chiplet 230 offers various advantages, such as enhanced functionality, higher performance, and lower power consumption. Furthermore, depending on the specific application and design goals of the system, the integration of the chiplet 230 with the SOC 610 can be accomplished in a variety of ways.

[0373] Component 600 may include various variations and modifications depending on the specific requirements of the system. For example, the number, type, and arrangement of processing elements formed on silicon substrate 602 may differ. Similarly, the number, type, and function of modules in module group 236 may differ.

[0374] Furthermore, the second layer 608 can be modified to include additional functionality. For example, the second layer 608 may include passive components such as resistors, capacitors, and inductors, or it may include active components such as transistors or diodes. Incorporating these components into the second layer 608 can further enhance the functionality and performance of the system.

[0375] In another variation, component 600 can be incorporated into a heterogeneous integration approach, where chiplet 230 is manufactured using a different technology than that used in SOC 610. This approach allows for the optimization of different manufacturing technologies for different parts of the system, resulting in improved performance and reduced power consumption.

[0376] Figure 7A perspective view of component 700 is shown, comprising a semiconductor device 707 and a second semiconductor device 709. Semiconductor device 707 has an array of processing elements 706 (on a grid of processing elements 706a,a to 706n,n, where the first subscript is a column and the second subscript is a row), and second semiconductor device 709 has an array of micro-repositories 708. The array of micro-repositories 708 is on a grid of micro-repositories 708a,a to 708n,n, where the first subscript is a column and the second subscript is a row. These subscripts can be aligned such that a corresponding subscript of a processing element 706 corresponds to a corresponding subscript of a micro-repository 708. Micro-repositories 708 are of the module type described herein, wherein they are positioned vertically, for example, above the corresponding processing element 706. Semiconductor device 707 may be a chiplet. Furthermore, semiconductor device 709 may also be a chiplet. Chipslets 707 and 709 may be bonded together. Different layers 710 (e.g., corresponding to 710a to 710d) can be assigned to individual AI models (e.g., parameters in a neural network, such as a CNN or a transformer model).

[0377] Component 700 is a accommodator Figure 7 The diagram illustrates the overall structure of the various components. It provides mechanical support and integration for other elements, allowing them to operate as a unified system.

[0378] Component 700 includes two semiconductor devices, namely semiconductor device 707 and semiconductor device 709. Semiconductor device 707 contains an array of processing elements labeled 706a,a to 706n,n. Similarly, semiconductor device 709 contains an array of micro-repositories labeled 708a,a to 708n,n.

[0379] Subscripts a,a to n,n indicate that processing elements 706 and micro-repositories 708 are arranged in a grid pattern, where the first subscript indicates a column and the second subscript indicates a row. This grid arrangement allows each processing element 706 to have a corresponding micro-repository 708 vertically positioned above each processing element 706. For example, processing element 706a,a has a micro-repository 708a,a above processing element 706a,a, processing element 706b,b has a micro-repository 708b,b above processing element 706b,b, and so on. Grid alignment allows for tight integration between the processing and storage components.

[0380] In some embodiments, semiconductor devices 707 and 709 may be individual chiplets integrated into a unified component 700 using packaging technology. The form factor of the chiplets allows for greater flexibility and customization when assembling the system. This arrangement allows each processing element 706 to access a corresponding micro-repository 708 located on top of each processing element 706 to retrieve data, such as weights for a neural network or AI model. This provides high-bandwidth and low-latency access to data that requires efficient processing.

[0381] Input data enters the system via input DRAM memory 702. This data flows into processing element 706, where it is processed locally using weights or parameters from a vertically integrated micro-repository 708. Processing results are output via output DRAM memory 704. Input DRAM memory 702 includes multiple individual DRAM modules labeled 702a, 702b, and 702c. DRAM memory 702 can be any type of dynamic random access memory, including but not limited to DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, and HBM. The DRAM memory provides high-bandwidth data input capabilities to feed data (such as inference input or training data) into the processing pipeline.

[0382] In some embodiments, each individual DRAM module 702a, 702b, and 702c has a dedicated interface and data path to each processing element 706. For example, DRAM module 702a may feed data only to processing elements 706a,a, while DRAM module 702b may feed data only to processing elements 706b,b. This provides modular scalability, as additional DRAM modules can be added to feed data to more processing elements.

[0383] The number of input DRAM memory modules 702 and the number of individual modules 702a-702c can vary depending on application requirements. For example, there can be four, eight, sixteen, or more input DRAM modules. Depending on factors such as access speed, power consumption, and cost budget, the capacity of each module can range from gigabytes to terabytes.

[0384] For example, high-speed interfaces such as DDR5, GDDR6, or HBM3 can be used to maximize the data transfer bandwidth between the input DRAM memory 702 and the processing element 706 across the semiconductor device 707. Shared data buses, crossbar switches, or on-chip networks can interconnect groups of DRAM modules 702 and processing elements 706.

[0385] In some implementations, the input DRAM modules 702 can be stacked or arranged in a multidimensional configuration to increase overall memory capacity and bandwidth while reducing latency and power consumption. A dedicated memory controller and scheduler can manage parallel data access across multiple input DRAM modules 702.

[0386] The input DRAM memory 702 supplies the high-bandwidth data requirements of the parallel processing element 706, enabling fast and efficient data-intensive computations such as neural network inference. Each processing element 706 can directly access the required input data from its dedicated DRAM module 702 without competing for data access with other processors.

[0387] In alternative embodiments, adjacent accelerator chiplets may communicate with semiconductor device 707, in addition to or as an alternative to DRAM memories 702 and 706. That is, a grid-like arrangement of components 700 communicating with each other may exist to perform AI inference and / or AI training (e.g., transformer inference, CNN inference, ANN inference, etc.). In some embodiments, a cluster of semiconductor devices 707 sharing libraries or portions of DRAM memories 702 and / or 706 may exist. In some embodiments, input DRAM memory 702 and output DRAM memory 704 may be combined into the same DRAM memory.

[0388] Component 700 includes a semiconductor device 707, which comprises an array of processing elements labeled 706a,a to 706n,n. Each processing element in the array can be configured to perform specialized computational and data processing operations. For example, in some embodiments, the processing elements may be optimized for artificial intelligence workloads, such as neural network inference. In other cases, the processing elements may focus more on general-purpose capabilities. Ultimately, the capabilities of each processing element depend on its specific microarchitecture, which can be customized for specific applications as needed.

[0389] Processing element 706 can access nearby memory storage to retrieve data fed into its computation. This memory can be physically separated from the array of processing element 706, as if it were... Figure 7 The same applies to the micro-repository 708 shown. The processing element 706 is aligned with the micro-repository 708, such that each micro-repository is positioned directly above its corresponding processing element in a vertical configuration. This tight coupling provides fast data transfer speeds between each repository-element pair.

[0390] In terms of physical implementation, the array of processing elements 706 resides within a semiconductor device 707. The semiconductor device 707 can potentially be fabricated as a standalone chiplet using advanced packaging techniques. This modular chiplet can then be integrated with other components, such as the microrepository chiplet 709, via high-density interconnects. Options include bumpless hybrid bonding, interposers, or even monolithic 3D integration. Ultimately, combining chiplets allows for the creation of robust heterogeneous systems using optimized dies.

[0391] The specific number, design, and interconnection scheme of processing elements 706 may vary in the implementation of component 700. For example, a simpler system may require only a 2×2 element grid, while a complex AI accelerator may have a 32×32 array. Processing elements 706 themselves may also have different memory access paths across components. Point-to-point links, crossbar switches, or shared buses are possible connection structures. Such architectural decisions depend on the performance and area constraints that are being met.

[0392] The second semiconductor device 709 is a device separate from the first semiconductor device 707. Similar to the first semiconductor device 707, the second semiconductor device 709 can also be implemented as a chiplet. The second semiconductor device 709 includes an array of micro-repositories 708 arranged on a grid from micro-repositories 708a,a to 708n,n.

[0393] As previously described, the micro-repositories 708 on the second semiconductor device 709 are vertically positioned above the processing elements 706 on the first semiconductor device 707. Based on subscripts identifying the position of each micro-repository 708 in the grid, each micro-repository 708 is aligned with and corresponds to the processing element 706 below it. For example, micro-repositories 708a,a are vertically aligned with and correspond to processing elements 706a,a. This allows each processing element 706 to access the micro-repositories 708 above it.

[0394] The micro-repository 708 acts as a memory structure, storing contents such as AI model weights, which can be accessed by the processing element 706 below it during operations such as neural network inference. The micro-repository 708 can be optimized for extremely fast read times but slower write times. This allows the processing element 706 to quickly access the weights and data required for its computation, while data that is updated less frequently can still be written at a slower rate.

[0395] In some embodiments, a second semiconductor device 709 comprising an array of microrepositories 708 is directly bonded to a first semiconductor device 707 having a processing element 706. This bonding aligns each microrepository 708 with its corresponding processing element 706 below it. Conductive interconnects between the devices allow each processing element 706 to communicate directly upwards with its corresponding upper-level microrepository 708. This provides a compact, modular, and efficient system architecture.

[0396] The micro repository 708 can contain multiple storage layers, labeled 710a to 710d, each storing weights or data for a different AI model. For example, layer 710a contains weights for model A, layer 710b contains weights for model B, and so on. Vertically stacking these layers contributes to the high density and fast access times of the micro repository design.

[0397] The micro-repository 708 can be implemented using various memory technologies, including but not limited to SRAM, FeFET, ReRAM, SOT, and STT, all optimized for fast read times to supply data to the processing element 706 with minimal latency. Certain embodiments may configure the micro-repository 708 to have read speeds significantly faster than its write speed. The micro-repository 708 can be implemented using any FeFET or memory structure described herein.

[0398] In some embodiments, each micro-repository 708 may have a capacity between 4 kilobytes and 128 kilobytes for storing parameters or other data for machine learning models. The bit density per layer may exceed 0.4 gigabits per square millimeter. The compact size of the micro-repository 708 (less than 100 micrometers per side in one embodiment, or 12 micrometers by 12 micrometers in another embodiment) allows for high-density integration of memory modules.

[0399] The array-based arrangement of the micro-repository 708 enables the processing element 706 to perform concurrent parallel data access, supporting high-throughput data processing of the component 700. The one-to-one alignment between the micro-repository 708 and the processing element 706 also ensures that each processing element 706 has dedicated access to the data it needs without contention.

[0400] The micro-repository 708 shares a semiconductor device interface provided by the second semiconductor device 709, which facilitates writing data from the input DRAM memory 702 to the micro-repository 708. Data read from the micro-repository 708 to the processing element 706 and the output DRAM memory 704 is processed through a dedicated path between each vertically aligned micro-repository 708 and the processing element pair.

[0401] The micro-repository memory layer 710 refers to multiple micro-repository memory layers stacked vertically within the second semiconductor device 709. For example... Figure 7 As shown, there are four separate micro-repository storage layers, labeled 710a, 710b, 710c, and 710d. Each layer contains an array of micro-repositories, such as the array of micro-repositories 708 shown in the figure.

[0402] In one embodiment, the micro-repository 708 may utilize a stacked 3D NAND architecture built from multiple NAND memory array layers using charge-trap flash technology. Each micro-repository 708 may include a dedicated set of word line drivers on the bottom layer to facilitate access to the upper array of 3D NAND cells spaced apart by alternating dielectric layers. This 3D NAND implementation can be used to maximize density and throughput by leveraging vertical scaling.

[0403] In an alternative embodiment, the micro-repository 708 employs a 3D NOR architecture constructed from a multi-level NOR flash memory array. Each plane has a NOR string, which has source lines and bit line architectures stacked on top of each other using vias. This 3D NOR arrangement optimizes random read access time to the stored data.

[0404] The micro-repository 708 can also employ a hybrid configuration with different types of volatile and / or non-volatile memories organized as vertical subarrays, such as a combination of FeRAM and ReRAM cells. This heterogeneous 3D integration allows for optimization for speed, durability, and persistence within the same repository structure.

[0405] In some embodiments, the micro-repository 708 integrates, for example, analog computing processing logic directly into the memory array stack itself. This in-memory computing approach places basic computational operators within memory peripherals or bit cells, enabling highly parallel and efficient in-situ data processing.

[0406] Some implementations can utilize 2.5D or 3D stacking to integrate the micro-repository 708 with other components such as logic, CPU, GPU, or dedicated accelerators. This compact packaging integration via techniques such as high-bandwidth memory cube architecture reduces data transfer latency and power consumption.

[0407] The micro-repository 708 can also employ a virtualization architecture, where an external memory controller handles the translation between physical array organization and dynamically allocated virtual memory domains. These virtual domains, mapped onto the physical array, effectively create individual virtual repositories with flexible capacities tailored to application needs.

[0408] In some embodiments, the micro-repository 708 is designed as computational RAM (CRAM), which integrates processing capabilities within bit cell peripherals to enable a highly parallel in-memory computing architecture. The gateless transistor structure integrated into the computational RAM (CRAM) array facilitates the efficient execution of large numbers of bit operations.

[0409] Some implementations arrange the micro-repository 708 as a modular memory processing unit (MPU) architecture, which contains dedicated processing logic tailored for workloads such as AI inference. The MPU architecture couples the repository array to a vector processor via a high-speed interface such as HBM2, thereby enabling low-latency data transfer.

[0410] The micro-repository 708 also enables content addressability by integrating comparison logic into the memory peripheral. This facilitates searching for or accessing data based on content rather than explicit addresses, thereby enabling powerful pattern matching capabilities.

[0411] Some implementations can stack multiple micro-repository dies on top of an underlying logic die containing content such as GPUs or AI accelerators. This creates dense, high-bandwidth heterogeneous systems optimized for data-centric workloads while minimizing data movement.

[0412] The micro-repository memory layer 710 can be fabricated using three-dimensional integrated circuit manufacturing processes to stack multiple dies or wafers containing an array of micro-repositories 708 on top of each other. Through-silicon vias (TSVs) or other vertical interconnect technologies can be used to enable communication between layers.

[0413] In some embodiments, each micro-repository storage layer 710 corresponds to a different artificial intelligence (AI) model or application. For example, layer 710a may store weights and parameters for AI model A, layer 710b may store weights and parameters for AI model B, and so on. This allows multiple AI models to be efficiently stored within the same micro-repository structure 708.

[0414] In some embodiments, the microrepository 708 can have a capacity ranging from 4 kilobytes to 128 kilobytes. In other cases, the capacity can be between 4 kilobytes and 16 kilobytes. Each microrepository can have a lateral dimension of less than 100 micrometers by less than 100 micrometers, while in some implementations, it extends vertically to incorporate potentially more than 200 memory cell layers.

[0415] In some embodiments, the bit density per square millimeter per layer within the micro-repository memory layer 710 can facilitate high-capacity storage with a small footprint. The layer can utilize non-volatile memory technologies, such as FeFET, STT-MRAM, or ReRAM, to retain data when power is removed.

[0416] In operation, the processing element 706 can access weights or parameters from the micro-repository memory layer 710 to perform neural network inference or other machine learning calculations.

[0417] The inference results of various AIs can be sent to an output DRAM memory 704, which includes individual DRAM memory modules labeled 704a, 704b, and 704c. The output DRAM memory 704 is positioned adjacent to an array of micro-repositories 708 and a second semiconductor device 709. The output DRAM memory 704 can act as a temporary data storage device, buffering output data retrieved from the micro-repository 708 before it is transferred externally.

[0418] Each DRAM memory module 704a, 704b, and 704c may have similar or different storage capacities depending on design requirements. For example, in one embodiment, each module contains 16 megabits of storage. DRAM memory cells utilize capacitors to retain data bits in the form of charge. Due to charge leakage, DRAM memories require periodic refresh cycles to maintain the integrity of the stored data. To enable concurrent reads and writes across multiple modules, each DRAM module 704a, 704b, and 704c may have dedicated internal control circuitry and I / O ports.

[0419] Data output from a separate micro-repository 708 can be aggregated and buffered in the output DRAM memory 704 before being transmitted to external components via peripheral circuitry. Buffering the data allows the transfer rate to be adjusted to match the requirements of the external interface. It also enables the second semiconductor device 709 to perform data processing operations such as formatting, encoding, or encryption before output.

[0420] In some embodiments, output DRAM modules 704a, 704b, and 704c are designed to provide high-density, low-cost temporary data storage to support high-bandwidth parallel reads from an array of micro-repositories 708. Optimizing these performance parameters allows for efficient data retrieval from the micro-repository to feed computational workflows hosted on external chips or devices. Specific implementations can utilize various types of DRAM, including application-specific asynchronous DRAM, synchronous DRAM, graphics DRAM, and low-power DRAM. Overall, the output DRAM memory 704 facilitates seamless data movement from the integrated micro-repository to external execution pipelines.

[0421] Figure 8 A component 800 comprising several memory types of semiconductor devices 802, 804, 806, 808, 810, 812, 814 is shown according to one embodiment of the present disclosure. Specifically, Figure 8 Exemplary component 800 is shown, which is configured to provide a layered memory structure of semiconductor devices 802, 804, 806, 808, 810, 812, 814. Component 800 is modular and scalable, allowing various combinations and numbers of semiconductor devices (which may be implemented as chiplets in some embodiments) to be stacked to meet specific performance and density requirements.

[0422] Component 800 includes application semiconductor 802, which may be one of multiple processing elements as described herein. On top of semiconductor device 802 is semiconductor device 814, which includes an array of micro-repository cells. On top of semiconductor device 814 is semiconductor device 812, which may also include an array of micro-repository cells. On top of semiconductor device 812 are semiconductor devices 810 and 808, which may be SRAM repository dies. On top of semiconductor device 808 are semiconductor devices 806 and 804, which may be DRAM repository dies. These repositories 816 may be arranged in a grid, such that 816a,a to 816n,n are labeled with subscripts. Each of these repositories may include a corresponding micro-repository from semiconductor devices 804 and 812, a corresponding SRAM repository from semiconductor devices 810 and 808, and a corresponding DRAM repository from semiconductor devices 806 and 804.

[0423] At the bottom of component 800 is semiconductor device 802, which includes multiple processing elements. These processing elements perform computational tasks and facilitate data flow within the system.

[0424] Directly above semiconductor device 802 is semiconductor device 814, which includes an array of micro-repositories. These micro-repositories utilize ferroelectric field-effect transistors (FeFETs), known for their non-volatile characteristics and suitability for high-density memory applications. FeFET-based micro-repositories can be designed to enable high-speed read operations essential for rapid data retrieval during processing tasks such as AI inference, while supporting slower write operations that are more tolerant of latency. Stacked on top of semiconductor device 814 is semiconductor device 812, which similarly includes an array of micro-repositories. The presence of multiple micro-repository layers in semiconductor devices 814 and 812 illustrates the scalability of the components, where additional memory capacity and functionality can be integrated through additional layers.

[0425] To further refine the memory hierarchy, semiconductor devices 810 and 808, positioned on top of semiconductor device 812, are depicted as SRAM repository dies. SRAM provides fast-access memory, which can act as a cache or buffer for the slower but denser FeFET micro-repository memory layer below.

[0426] At the top of component 800, and therefore at the top of the memory structure, are semiconductor devices 806 and 804, which are illustrated as DRAM storage dies. DRAM is typically used for main memory due to its higher speed and lower cost per bit compared to SRAM, offering a balance between performance and cost-effectiveness.

[0427] The grid arrangement of repositories 816, with subscripts 816a,a to 816n,n, indicates that each processing element at a given location (a,b) in semiconductor device 802 has dedicated access to corresponding vertically aligned repositories of micro-repositories and memory cells in the upper layers. This vertical stacking and alignment ensures that data and control signals can be directly routed between processing elements and their corresponding memory stacks, and is facilitated by interconnect technologies such as through-silicon vias (TSVs) and microbumps used in the 3D integrated circuit architecture of component 800.

[0428] The modular and scalable design of Component 800 allows for the integration of various combinations of semiconductor devices or chiplets into a wider range of systems. The number of stacks and the flexibility of combination provide adaptability for tailoring components to the requirements and performance needs of different applications. Each repository in Repository 816 within Component 800 represents a multi-die structure, which contributes to the overall capacity and performance of the system.

[0429] Figure 9An assembly of a semiconductor device according to an embodiment of the present disclosure is shown. The semiconductor device includes a semiconductor device having a system-on-a-chip (SoC) 914 and another semiconductor device 906 having a micro-repository disposed on top. Component 900 integrates semiconductor device 906 and semiconductor device 914, which can be implemented as separate chiplets bonded together. Semiconductor device 914 includes various components to facilitate reading data from the micro-repository on semiconductor device 906, such as a read address register input interconnect 924, a read data register 922, and a read data register output interconnect 950. These components pass a read address to the micro-repository on semiconductor device 906 and return read data to semiconductor device 914.

[0430] Specifically, the read address enters the read address register 926 via interconnect 924. The output 962 of this register is connected via interconnects and bump-free bonding to another read address register 938 on semiconductor device 906, which then addresses the target micro-repository 936. Micro-repository 936 outputs read data to read data register 942 via interconnect 940, and read data register 942 passes the data back to read data register 922 on semiconductor device 914 via bump-free bonding 910, 918. This data can then be accessed externally via read data register output interconnect 950. Furthermore, semiconductor devices 914 and 906 have interconnected through-silicon vias 916 and 944 to allow communication with devices that may be stacked on top of semiconductor device 906.

[0431] Semiconductor device 906 incorporates various memory structures to provide data storage capabilities. This includes a micro-repository 936 providing high-density, low-latency data storage, along with other peripheral memory components, such as a read data register 942 and a read address register 938, to facilitate data retrieval. The micro-repository 936 resides on the BEOL portion of the chiplet, allowing for high-density 3D integration of the memory layer. In some implementations, the micro-repository utilizes non-volatile memory technologies such as FeFET or STT-MRAM to retain data without power.

[0432] Semiconductor device 914 includes processing elements and data routing circuitry for retrieving and manipulating data stored in semiconductor device 906. For example, components of read address register 926 and read data register 922 handle sending read addresses and receiving data from micro-repository 936, respectively. Device 914 also includes interconnects 924 and 950 and through-silicon vias 916 for external communication.

[0433] The two devices 906 and 914 are integrated via fine-pitch interconnects, such as bumpless hybrid bonding elements 908, 910, 918, 920, 930, and 932. This allows a direct data transfer path to be established between the processing components in device 914 and the memory structure in device 906. Alignment during bonding ensures dedicated access; for example, the read data register output interconnect 950 on 914 is directly linked to the read data register 922 to receive requested data.

[0434] The data flow path during reading can be summarized as follows: The read address enters the read address register 926 on device 914 via interconnect 924. This is transferred via interconnect and bumpless bonding to read address register 938 on device 906, which then addresses the micro-repository 936. The requested data is passed to read data register 942 via interconnect 940 and then transferred back to read data register 922 on 914 via bonding, where the requested data can be obtained externally via interconnect 950.

[0435] Component 900 illustrates a modular, high-density architecture optimized for data-centric applications such as AI inference. Tight integration of processing and memory dies via advanced packaging technology allows for localized data access with minimal latency and power consumption. Scalability is also achieved through the incorporation of multiple chiplets (in this case, devices 906 and 914). Component 900 illustrates potential configurations suitable for space-constrained, high-performance computing systems.

[0436] A through-silicon via (TSV) 916 is an electrical connection that passes vertically through a semiconductor device 914. Its purpose is to provide a path for signals to travel between the top and processing elements within the semiconductor device 914. This allows the device to be stacked and interconnected with other components in a vertical configuration. The TSV 916, along with other TSVs on the device, facilitates high-density 3D integration and heterogeneous stacking of multiple devices, such as chiplets.

[0437] TSV 916 interacts with several other components within the system. On the top side of semiconductor device 914, it connects to interconnect 912, which couples semiconductor device 914 to bump-free bonding member 918. When two devices are stacked, these bonding members mat with supplemental bump-free bonding member 910 on the bottom side of semiconductor device 906. This allows signals to travel from device 914 to device 906 via TSV 916. The path continues as the signal passes through interconnect 902 to TSV 944 on device 906. TSV 944 provides a vertical signal path to the top surface of device 906, on which additional devices can be stacked. In the reverse direction, signals can travel down from TSV 944 through device 906, back to TSV 916, and down into device 914. Thus, TSV 916 provides bidirectional vertical communication across device boundaries.

[0438] Several possible variations exist for the implementation of TSV 916. First, multiple TSVs arranged in an array can be used instead of a single via to increase throughput and redundancy. Second, the size and material of the TSVs can be optimized; for example, using a higher-density material such as tungsten to reduce the TSV diameter may be advantageous. Furthermore, the interface circuitry (e.g., interconnects 912 and 902) driving signals to the TSVs can employ variable line drivers to support different voltage levels or signal integrity enhancements. Other embodiments may include integrated monitoring circuitry within the TSV 916 to track metrics such as temperature and link utilization. And in future implementations, alternative signaling schemes may be employed in addition to electrical signals. For example, integrated silicon photonics technology utilizing modulated light to transmit data through TSVs can achieve extremely high bandwidth and low latency connections. Within these complex 3D integrated architectures, multiple pathways exist for further development of TSV-based vertical links (e.g., TSV 916).

[0439] Several variations and alternatives exist for the implementation of interconnect 912. For example, different conductive materials such as copper or aluminum can be used to create the pathways forming interconnect 912, and optimizations can be made for conductivity or heat dissipation. Furthermore, interconnect 912 can also have redundant signal paths, or use spare interconnects to achieve self-healing capabilities, thereby improving reliability and resilience. The bumpless bonding elements 918 and 910 connecting devices 906 and 914 can also be replaced by other high-density bonding methods such as hybrid bonding or through-silicon vias. In addition to simple digital logic, alternative signaling schemes, such as analog signaling or multi-level digital waveforms, can be employed on interconnect 912 to enhance data transmission capabilities. The wiring and dimensions of interconnect 912 can also be adapted to bandwidth requirements or circuit layout considerations. In summary, many structural and functional alternatives exist for designing interconnect 912 to meet application requirements.

[0440] Bump-free bonding member 918 is an electrical connection located on semiconductor device 914 between interconnect 912 and bump-free bonding member 910 of semiconductor device 906. Bump-free bonding member 918 provides an electrical path for signals to travel between semiconductor device 914 and any additional semiconductor devices (such as semiconductor device 906) stacked on top of component 900. Signals transmitted through bump-free bonding member 918 may include data signals, control signals, address signals, or any other signals required to coordinate operation between multiple semiconductor devices.

[0441] Several possible variations exist for the bumpless bonding element 918. Depending on signal bandwidth requirements, the number of individual bonding sites can range from several to hundreds. Bonding methods can utilize techniques such as direct bonding, plasma-activated bonding, adhesive bonding, or pressure bonding. Hybrid bonding methods are also possible, combining direct wafer bonding with intermediate metal bonding. The size and pitch of each bonding site can vary, and pitches of less than 10 micrometers can be used to achieve high-density connections. Redundant bonding elements can provide backup paths. For noise immunity, shielding structures can surround the bonding elements. In summary, many embodiments of the bumpless bonding element 918 can meet the requirements of cost, reliability, and performance.

[0442] Bump-free bonding element 910 provides an interface for signal transmission between semiconductor device 906 and semiconductor device 914. Specifically, the bump-free bonding element 910 of semiconductor device 906 is electrically coupled to a supplementary bump-free bonding element 918 of semiconductor device 914. This allows signals such as read / write data and address signals to be transmitted between the two devices. The bump-free nature of the bonding element allows for thin, high-density interconnects.

[0443] The bumpless bonding member 910 interacts with other components in the system to facilitate data transfer operations. For writes, data enters semiconductor device 914 via through-silicon via 916, passing through interconnects 912 and 918 before reaching bumpless bonding member 910 in device 906. For reads, the address flows from read address register 926 in device 914 through interconnects 928, 930, and bumpless bonding member 932 into read address register 938 on device 906. Read data is then returned to device 914 via bumpless bonding members 908 and 920. Therefore, bumpless bonding member 910 provides critical data and address routing between devices.

[0444] Possible variations of the bumpless bond 910 include using different bonding densities, materials, or electrical contact configurations to optimize performance. Alloying or doping techniques can be used on the bond to improve conductivity. Furthermore, signal routing can be altered, for example, by using separate input and output ports instead of shared ports. More bumpless bonds can be added to increase bandwidth between devices. Shielding can be added around the bonds to reduce interference. In summary, numerous modifications to the bumpless bond 910 are possible within the scope of electrically interconnecting multiple devices.

[0445] A through-silicon via (TSV) 944 is an electrical connection that runs vertically from the top surface to the bottom surface through a semiconductor device 906. Its purpose is to facilitate signal and data transmission between the semiconductor device 906 and any additional semiconductor devices that may be stacked on top of it in a 3D integrated circuit configuration. The TSV 944 enables high-density interconnects between multiple stacked semiconductor layers, providing an efficient way for data routing and signaling.

[0446] The TSV 944 interfaces with surrounding circuitry within the semiconductor device 906, allowing signals to be transmitted up or down depending on the system configuration. At one end, the TSV 944 is coupled to a read data register 942 via interconnect 946. The read data register 942 can use the TSV 944 path to transfer read data from the micro-repository 936 to an external semiconductor device. This enables efficient data offloading from on-chip memory. At the other end, the TSV 944 continues through to the top surface of the semiconductor device 906, where it can interface with supplementary contacts or interconnects on the semiconductors bonded thereon. This facilitates vertical signal and data transmission along component 900.

[0447] Numerous variations are possible in the specific implementation of the TSV 944. Its size can range from several micrometers to tens of micrometers to match pitch requirements. The TSV 944 can be tapered, straight, or have a non-uniform cross-section. Different conductive materials can be used as pads and fillers, including metals such as copper, tungsten, or alloys. Insulating pads made of materials such as silicon dioxide can separate the conductive filler from the substrate. The contacts and interconnects coupled to the TSV 944 can also have various layouts. If desired, multiple TSVs can be placed adjacent to each other in a high-density array configuration. In summary, many architectural optimizations in the design and fabrication of the TSV 944 are within the scope of this disclosure.

[0448] Figure 10 A semiconductor component 1000 according to one embodiment of the present disclosure is illustrated. The semiconductor component 1000 is incorporated into a daisy-chain configuration of micro-repositories 1036, 1058, which are operatively connected to a multiplexer 1060 and managed by a counter 1062 for coordinating data selection and retrieval. The component 1000 is designed to perform data processing tasks and can be used in applications such as artificial intelligence (AI) and machine learning, where high-speed data access and processing are utilized.

[0449] Component 1000 includes two primary semiconductor devices: semiconductor device 1006 and semiconductor device 1014. Semiconductor device 1014 is depicted as including several interfaces and registers for data communication, including a read address register input interconnect 1024. This interconnect 1024 facilitates the delivery of read addresses to a read address register 1026, which temporarily holds these addresses before they are transferred to corresponding micro-repositories 1036, 1058 in semiconductor device 1006 for data retrieval operations.

[0450] In semiconductor device 1014, interconnect 1028 serves as a pathway for the read address to transition from read address register 1026 to bumpless bonding member 1030. Bumpless bonding members 1030 and 1032 represent a high-density, thin electrical connection between semiconductor device 1014 and semiconductor device 1006, ensuring the transmission of the read address with minimal signal loss and physical space requirements.

[0451] The received address reaches the read address register 1038 in the semiconductor device 1006 via interconnect 1034, and the read address register 1033 then instructs the micro-repository 1036 to output the requested read data. The micro-repository 1036, as a memory storage unit, can encompass various memory technologies, such as FeFET and / or 3D-NAND structures as described herein, to facilitate data storage and rapid retrieval.

[0452] Multiplexer 1060 selects the appropriate data stream from the outputs of multiple micro-repositories 1036, 1058. Controlled by counter 1062 (which can operate according to a predefined sequence or be driven by an external control signal), multiplexer 1060 arbitrates between the output of micro-repository 1036 and the output of another micro-repository, referred to as micro-repository 1058. Micro-repository 1058 is similar to micro-repository 1036 in function and potential memory technology, providing multiplexer 1060 with an additional data source to choose from.

[0453] Once the desired data is selected by multiplexer 1060, it is temporarily stored in read data register 1042, also located within semiconductor device 1006. Register 1042 acts as a buffer, holding the data for subsequent processing or transmission. The read data is then routed via interconnect 1004 to bumpless bonding member 1008, which facilitates the transfer of data to semiconductor device 1014.

[0454] Bump-free bonding elements 1010 and 1018 facilitate the continued journey of data through component 1000, ensuring data transfer from semiconductor device 1006 to semiconductor device 1014. Once the read data arrives at semiconductor device 1014, it is directed to the read data register (specifically read data register 1022) via interconnect 1048, where it can be accessed by external systems such as application-specific integrated circuits (ASICs) or systems-on-chips (SoCs) via read data register output interconnect 1050.

[0455] Furthermore, component 1000 includes through-silicon vias (TSVs) 1016 and 1044, providing vertical electrical connections via semiconductor devices 1014 and 1006, respectively. These TSVs enable the stacking of additional semiconductor devices or chiplets on top of component 1000, thus allowing for vertical expansion of system capabilities. Interconnects 1012 and 1046 act as horizontal paths for signals to travel to and from TSVs 1016 and 1044, respectively.

[0456] Although the description presents a specific configuration, component 1000 can be subject to various modifications and alternative embodiments. For example, the number and arrangement of micro-repositories, the specific type of memory technology used within the micro-repositories, and the configuration of interconnects and bonding areas can be customized to meet the requirements of different applications.

[0457] In some embodiments, semiconductor devices 1006 and 1014 may be designed to accommodate additional functions, such as a thermal management layer for heat dissipation, a hardware-based encryption module for data security, or a power management circuit for optimizing energy consumption. Figure 10 Its detailed structure thus serves as the basis for building a variety of complex semiconductor systems, each of which is customized for the specific needs of its intended application.

[0458] exist Figure 10 In the configuration of component 1000 depicted, the micro-repositories 1036 and 1058 present a daisy-chain configuration, which allows for a scalable and flexible memory architecture within semiconductor device 1006. This daisy-chain is facilitated by a series of interconnect paths and is controlled by multiplexer 1060 in coordination with counter 1062.

[0459] Each micro-repository (such as 1036 and 1058) is designed to retain and provide fast access to data, which may be in the form of stored charges, magnetic states, ferroelectric material states, or other physical embodiments of binary information. The micro-repositories are interconnected such that the output of one micro-repository can be routed to the input of another, thereby creating a chain of memory elements. This is achieved through a series of interconnects, such as interconnect 1034 for micro-repository 1036 and interconnect 1056 for micro-repository 1058, which act as conduits for read data signals from the micro-repositories.

[0460] Multiplexer 1060 manages the data flow from the daisy chain of the microrepository. It is designed to have multiple inputs, each connected to the output of the microrepository via a corresponding interconnect. In the provided example, interconnect 1040 carries read data from microrepository 1036, and interconnect 1056 carries read data from microrepository 1058 to multiplexer 1060. Multiplexer 1060 is able to select which input is connected to its output at any given time, thus controlling which microrepository's data is forwarded to read data register 1042.

[0461] Counter 1062 orchestrates the operation of multiplexer 1060. It can be a binary counter or any form of sequential logic circuit that generates a series of output states in response to a clock signal. Counter 1062 advances its state with each tick of the clock, which can be provided by an external clock source or generated internally in semiconductor device 1006. As counter 1062 advances, it outputs a control signal that instructs multiplexer 1060 which input to select.

[0462] For example, at the first clock pulse, counter 1062 can instruct multiplexer 1060 to connect the output from micro-repository 1036 to read data register 1042. At the next clock pulse, the counter can switch the connection to the output of micro-repository 1058, and so on, cycling through the available micro-repositories in a predefined order. The sequence and timing of the counters can be configured based on the desired data access pattern and the specific requirements of the task at hand.

[0463] This clock-driven coordination allows for efficient and organized retrieval of data from a potentially large array of micro-repositories. It ensures that each micro-repository has an equal opportunity to present its data for processing, and it simplifies the control scheme by reducing it to a predictable, rhythmic progression of states. This is particularly advantageous in systems requiring parallel processing of large amounts of data, as it provides a systematic approach to accessing and utilizing the stored information.

[0464] It should be noted that, although Figure 10 Only two micro-repositories are illustrated, but the described daisy-chain mechanism can be extended to accommodate any number of micro-repositories. Additional micro-repositories can be added to the chain, with each new micro-repository connected to a multiplexer via additional input lines. Multiplexer 1060 and counter 1062 will be extended accordingly to manage the increased number of inputs, maintaining the same clock-driven, sequential data retrieval process across the extended memory architecture.

[0465] This daisy-chain of micro-repositories, combined with a multiplexing and counter-driven control system, exemplifies a modular and scalable approach to memory design in semiconductor devices. It allows for customized memory arrays to match the capacity and performance requirements of a wide range of applications, from embedded systems to large-scale data centers, providing a versatile solution to modern computing challenges.

[0466] Figure 11 A semiconductor component 1100 according to one embodiment of the present disclosure is shown. The semiconductor component 1100 incorporates a daisy-chain configuration of micro-repositories in a plurality of semiconductor devices 1106, 1116. The micro-repositories in the plurality of semiconductor devices 1106, 1116 are operatively connected to a multiplexer and managed by a counter for coordinating data selection and retrieval.

[0467] This detailed description refers to the figures shown in the accompanying drawings. Figure 11 , Figure 11An embodiment of component 1100, which is part of an integrated circuit, is illustrated. Component 1100 can be viewed as a hierarchical structure comprising a bottom semiconductor device 1122, a middle semiconductor device 1116, and a top semiconductor device 1106 (each of these semiconductor devices may be a chiplet). Each semiconductor device is configured to interface with other semiconductor devices via a series of bump-free bonding elements (such as bump-free bonding elements 1128, 1129, 1158, 1159, 1160, 1161, 1162, and 1163), which facilitates electrical interconnection without increasing the profile of conventional bonding methods, thus achieving a compact and high-density stacking of semiconductor layers.

[0468] Bottom semiconductor device 1122 includes a read address register 1126, which can be configured to store read addresses and transmit read addresses to a miniature repository located across component 1100. Read address register 1126 communicates via interconnects 1174, which act as conduits for guiding signals to bump-free bonding members 1128. These bonding members then engage with bump-free bonding members 1129 of middle semiconductor device 1116, thus transmitting read addresses to the middle semiconductor device. Bottom semiconductor device 1122 also includes a read data register 1124, which can act as a repository for received read data. Read data is received via interconnects 1176, which are connected to bump-free bonding members 1158, which communicate with bump-free bonding members 1159 of middle semiconductor device 1116.

[0469] The intermediate semiconductor device 1116 acts as an intermediate layer within component 1100, housing micro-repositories such as micro-repositories 1132 and 1118, each designed to store and provide fast data access. These micro-repositories are linked to other components within the device via interconnects such as interconnects 1130 and 1134, which respectively guide the flow of read addresses and read data. The intermediate semiconductor device 1116 also includes a read address register 1146 that receives read addresses from interconnect 1130, and a read data register 1154 that collects read data from TSV 1152.

[0470] Multiplexer 1114 within the middle semiconductor device 1116 selects between various data streams. This multiplexer is controlled by stage counter 1110, which determines the sequence of data selections based on input received from the top semiconductor device 1106 via TSV 1152. Read data register 1112 serves as a holding area for the data stream selected from multiplexer 1114.

[0471] The top semiconductor device 1106 has a stage counter 1102 and a read data register 1104, which are used to coordinate the data flow within component 1100. The stage counter 1102, in conjunction with multiplexer 1150, determines the output of read data from micro-repositories 1138 and 1164 based on the selected stage. The read data register 1104 captures the output from multiplexer 1150, which is then relayed via interconnect 1108 to bump-free bonding member 1162, thereby facilitating communication with the middle semiconductor device 1116.

[0472] Component 1100 illustrates the integration of multiple micro-repositories across different semiconductor devices. For example, micro-repository 1132 on the middle semiconductor device 1116 can receive a read address from read address register 1146 via interconnect 1134 (path "1"). Similarly, micro-repository 1118 can receive a read address from the same register via interconnect 1156 (path "2"). Micro-repositories 1138 and 1164 on the top semiconductor device 1106 receive read addresses from read address register 1142 via interconnect 1140 and paths "3" and "4", respectively, and read address register 1142 communicates with the middle semiconductor device 1116 via TSV 1136 and bumpless bonding members 1160 and 1161.

[0473] Each micro-repository (such as 1132, 1118, 1138, and 1164) can potentially output read data to multiplexer 1114 or 1150, where the data is then selected based on the configuration of the corresponding stage counter 1110 or 1102. The selected data is temporarily stored in read data register 1112 or 1104 before being transmitted down through component 1100 via the corresponding bumpless bonding and interconnects, ultimately reaching read data register 1124 of the bottom semiconductor device 1122. This arrangement allows for synchronous readout of data from all micro-repositories, which can be essential in applications requiring parallel processing and high-speed data access.

[0474] TSVs (such as 1136 and 1152) provide vertical connections across semiconductor devices, enabling the integration of additional layers or functions on top of existing components 1100. These TSVs are coupled to various interconnects and bumpless bonds, which establish pathways for both signal transmission within and between semiconductor devices.

[0475] In some embodiments, the micro-repositories within component 1100 may include various memory technologies, such as 3D-NAND or 3D-NOR structures, and are arranged to facilitate parallel processing and efficient data retrieval. Each micro-repository may include additional features such as a thermal management layer for heat dissipation, a hardware-based encryption module for data security, or power management circuitry for optimizing energy consumption.

[0476] Data path 1 within component 1100 illustrates the route in which read address and corresponding read data are transferred across components, specifically guiding the operation from read address register 1126 located on bottom semiconductor device 1122 to read data register 1124 within the same device.

[0477] The process begins with the read address register 1126 holding a specific read address. This address is sent via interconnect 1174, which acts as a channel for the signal. The read address is then transmitted to bump-free bonding elements 1128, which are carefully designed to create reliable electrical connections without the physical protrusions associated with conventional bonding methods. These bonding elements ensure a thin interface that preserves the compactness of the semiconductor stack.

[0478] The signal continues from bumpless bonding member 1128 to engage with bumpless bonding member 1129 of the central semiconductor device 1116. The read address is carried forward by interconnect 1130, which delivers the address to the read address register 1146 of the central semiconductor device. Read address register 1146 then propagates the read address through interconnect 1134, designated as path "1," directing the signal to the micro-repository 1132.

[0479] Upon receiving a read address, micro-repository 1132 accesses the requested data. This data is then output via interconnect 1170 and directed to multiplexer 1114. In some embodiments, multiplexer 1114 acts as a selective switch, choosing between data streams based on a configuration determined by stage counter 1110. This stage counter can be designed to cycle through a sequence of timing and selection of data streams, ensuring that each micro-repository is read in a coordinated manner.

[0480] Data selected from multiplexer 1114 is then captured by read data register 1112, which temporarily holds the data. The data is subsequently transmitted via interconnect 1120, which carries the signal to bump-free bonding elements 1159. These bonding elements, together with the bump-free bonding elements 1158 on the bottom semiconductor device 1122, enable vertical and horizontal integration within the semiconductor stack.

[0481] At this point, a signal in the form of read data travels from bumpless bond 1159 to bumpless bond 1158 and is ultimately introduced into interconnect 1176. This interconnect completes the connection to read data register 1124, which is configured to receive and hold read data. Read data register 1124 can be configured to retain data for subsequent processing or external communication.

[0482] Data path 2 within component 1100 depicts a route specifically designed to transfer the read address from the read address register 1126 on the bottom semiconductor device 1122 to the micro repository 1118 located on the middle semiconductor device 1116 and subsequently transfer the read data back to the read data register 1124 on the bottom device.

[0483] The journey begins at read address register 1126, where the read address is held in preparation for dispatch. This register is part of the semiconductor device's control mechanism, orchestrating data retrieval by issuing specific addresses to memory cells. From read address register 1126, the read address is sent via interconnect 1174, which provides a secure and reliable path for electrical signals within the integrated circuit.

[0484] The read address continues from interconnect 1174 to bumpless bond 1128, which provides a seamless and thin connection to the central semiconductor device 1116 via corresponding bumpless bond 1129. These bonds maintain signal integrity during interlayer communication and are designed to meet the requirements of modern semiconductor architectures.

[0485] The signal is then routed via interconnect 1130 to read address register 1146 within central semiconductor device 1116. Read address register 1146 acts as a secondary storage and holding register, and the read address is routed down from read address register 1146 to interconnect 1156, which is labeled path "2" and terminates at micro storage 1118.

[0486] Upon receiving a read address, the micro-repository 1118 accesses the corresponding data. This data retrieval process is facilitated by the internal architecture of the micro-repository, which may include an array of memory cells optimized for fast access and data stability. The read data is output from the micro-repository 1118 and travels via interconnect 1172 to the multiplexer 1114.

[0487] Multiplexer 1114 determines which data stream to forward based on input from stage counter 1110. Stage counter 1110 operates synchronously with the system clock or an external control signal, cycling through various states to control the selection process of multiplexer 1114 in a precise and predictable manner.

[0488] The output of the multiplexer 1114, now carrying the selected read data, is transferred to the read data register 1112. This register temporarily stores the read data, acting as a buffer. The read data is then distributed to the bumpless bonding member 1159 via interconnect 1120.

[0489] Bump-free bonding element 1159 forms an interface with bump-free bonding element 1158 on the underlying semiconductor device 1122, through which signals are transmitted downwards via the component. The read data then passes through interconnect 1176 to reach its final destination, the read data register 1124. The read data register 1124 captures the read data, holding it ready for further processing or transmission to external circuitry.

[0490] Data path 3 within component 1100 is another communication route, illustrating a data transfer sequence that begins with the read address register 1126 on the bottom semiconductor device 1122, passes through various components, finally reaches the micro-repository 1138 on the top semiconductor device 1106, and then returns to the read data register 1124 on the bottom device.

[0491] The sequence begins with read address register 1126, which acts as the source for the read address. Register 1126 securely holds the address before it is distributed via interconnect 1174. Interconnect 1174 acts as a dedicated channel, ensuring the read address is accurately transmitted to bump-free bonding members 1128. These bump-free bonding members 1128 facilitate a streamlined connection to bump-free bonding members 1129 of the central semiconductor device 1116, maintaining the integrity and compactness of the signal path.

[0492] Upon reaching the middle semiconductor device 1116, the read address is relayed to the read address register 1146 via interconnect 1130. The read address register 1146 acts as a node for further propagating the address signal through the through-silicon via (TSV) 1136. The TSV 1136 is a vertical interconnect that penetrates the semiconductor substrate, providing a direct link from the middle semiconductor device 1116 to the top semiconductor device 1106, thus illustrating the 3D integration capability of semiconductor design.

[0493] The read address rises from TSV 1136 and appears on bumpless bonding pad 1160 on middle semiconductor device 1116. Bumpless bonding pad 1160 is connected to bumpless bonding pad 1161 on top semiconductor device 1106. The address signal is transmitted to read address register 1142 on top device 1106 via interconnect 1140.

[0494] Upon receiving a read address, read address register 1142 directs a signal along interconnect 1144. This path, marked "3," directs the address to miniature repository 1138. Miniature repository 1138, designed for data storage, retrieves the requested information in response to the read address. The read data is output via interconnect 1166, which feeds the data into multiplexer 1150.

[0495] The multiplexer 1150 in the top semiconductor device 1106 is managed by a stage counter 1102, which determines the selection of the data stream to be directed to the read data register 1104. The selected data stream is temporarily held in the read data register 1104, where it awaits downstream transmission.

[0496] Read data originates from read data register 1104 via interconnect 1108, which connects to bumpless bonding members 1162. These bonding members 1162 engage with corresponding bumpless bonding members 1163 on the central semiconductor device 1116 to transmit the read data to TSV 1152.

[0497] TSV 1152 operates as a vertical conduit, allowing read data to travel down to the intermediate semiconductor device 1116, where it is received by the read data register 1154. The read data register 1154 temporarily holds the read data, which is then guided to the multiplexer 1114 via interconnect 1156.

[0498] In the central semiconductor device 1116, the multiplexer 1114, coordinated by the stage counter 1110, selects appropriate data for output. The read data is then directed to the read data register 1112, where it is briefly stored. Immediately afterwards, the read data travels via interconnect 1120 to bumpless bonding member 1159.

[0499] Bump-free bonding member 1159 forms an interface with bump-free bonding member 1158 on the bottom semiconductor device 1122. The read data signal is then carried through interconnect 1176, completing its journey at read data register 1124 on the bottom device.

[0500] The data path 4 within component 1100 is as follows: establishing a flow of read address from read address register 1126 on bottom semiconductor device 1122 to micro storage 1164 on top semiconductor device 1106, and subsequently facilitating the movement of read data back down to read data register 1124 on bottom device.

[0501] The data path begins at read address register 1126, which is responsible for maintaining and issuing the read address required for data retrieval from the micro-repository. The read address is sent from register 1126 via interconnect 1174, which is a pathway for maintaining signal integrity and facilitating electrical transmission.

[0502] The read address is directed from interconnect 1174 to bumpless bonding 1128. These bonding regions create an interconnect between the bottom semiconductor device 1122 and the middle semiconductor device 1116 via bumpless bonding 1129. The design of these bumpless bonding components facilitates data transfer.

[0503] Once the read address reaches the central semiconductor device 1116, it is carried forward by interconnect 1130 to the read address register 1146. This register acts as an intermediate mechanism, preparing the address for vertical ascent through the device stack. The address is then transmitted via through-silicon via (TSV) 1136, which facilitates vertical integration by providing a direct electrical link through the semiconductor substrate.

[0504] After rising through TSV 1136, the read address appears on bumpless bonding member 1160, which is aligned to connect with bumpless bonding member 1161 on top semiconductor device 1106. The read address then travels along interconnect 1140 to read address register 1142 located on top device.

[0505] The read address register 1142 is used to forward the read address to its final destination, the micro-repository 1164, via interconnect 1148, which is marked as path "4". Upon receiving the read address, the micro-repository 1164 retrieves the requested data, which is then output via interconnect 1168. This data is then routed to multiplexer 1150, which is under the control of stage counter 1102.

[0506] Stage counter 1102 determines which data stream is selected by multiplexer 1150, which then sends the read data to read data register 1104. Read data register 1104 acts as a temporary repository, holding data until it can be sent down through the device stack.

[0507] Data leaves the read data register 1104 and travels via interconnect 1108 to bumpless bonding members 1162. These bonding members maintain connection with bumpless bonding members 1163 on the central semiconductor device 1116. The read data is then transmitted to TSV 1152, which carries the data vertically downward to the read data register 1154 on the central semiconductor device 1116.

[0508] The read data register 1154 temporarily holds the read data before it is fed to the multiplexer 1114 via interconnect 1156. The multiplexer 1114, coordinated by stage counter 1110, directs the appropriate data stream to the read data register 1112. This register acts as a temporary storage area for the read data, which is then sent to the bumpless bonding member 1159 via interconnect 1120.

[0509] Bump-free bonding member 1159 interfaces with bump-free bonding member 1158 on the bottom semiconductor device 1122 to provide downlink transmission of read data. Finally, the signal is routed through interconnect 1176 and arrives at read data register 1124, where data is available for subsequent processing or external communication.

[0510] Figure 12 The illustration shows a three-dimensional (3D) memory column 1200 according to an embodiment of the present disclosure. The 3D memory column 1200 is configured as a 3D-NOR or 3D-AND structure, characterized by a series of ferroelectric field-effect transistors (FeFETs) 1202, each FeFET 1202 having interconnected drain terminals 1204 and individual gate terminals 1206. The drain terminals 1204 are linked to a common select line 1212, and the gate terminals 1206 are connected to corresponding read / write enable lines 1214 (e.g., 1214a for FeFET 1202a). The read / write enable lines 1214 are all coupled to a common bit line.

[0511] therefore, Figure 12 A three-dimensional (3D) memory array designated as element 1200 is depicted. Element 1200 can be configured as a 3D-NOR or 3D-AND structure in various embodiments, providing flexibility in the application and use of integrated circuits. This memory array is an assembly of multiple ferroelectric field-effect transistors (FeFETs), collectively referred to as fefet1202, wherein each FeFET is indicated by elements such as 1202a, 1202b, 1202c, and 1202d, in addition to other elements that may be present in the array.

[0512] Within each FeFET (such as 1202a), there is a drain terminal 1204a. This drain terminal is part of the output path of the memory cell and is connected to a common select line 1212. In some embodiments, the common select line 1212 acts as a control mechanism, enabling the selection of a specific FeFET for data read or write operations.

[0513] The gate terminal of each FeFET (illustrated as 1206a for FeFET 1202a) is individually connected to a corresponding read / write enable line (such as 1214a). This allows control over the state of the FeFET, enabling it to be in an on state for reading or writing data, or in an off state that blocks data flow. The existence of individual read / write lines for each FeFET allows for precise control and operation of each memory cell.

[0514] In addition, each FeFET (such as 1202a) includes a source terminal (such as 1208a) coupled to a common bit line 1210. Bit line 1210 provides a conduit for data being written to or read from the FeFET. In some embodiments, this bit line can be shared across multiple memory columns, which can facilitate parallel processing and increase data throughput.

[0515] According to various embodiments of this disclosure, the 3D memory column 1200 can incorporate additional elements and configurations to enhance performance and functionality. For example, the 3D memory column 1200 may include insulating material, conductive pathways, and... Figure 12 Other structural components not explicitly shown but inherent to the implementation of such a 3D memory structure. The FeFET 1202 can also exhibit variations in material composition, structural dimensions, and electrical properties, thereby providing a range of performance characteristics suitable for different applications.

[0516] Furthermore, memory columns 1200 can be incorporated into larger memory arrays to form memory modules or parts of a system. These arrays can be arranged in various configurations (such as rows and columns) to create matrices that efficiently meet the needs of high-density data storage. Memory columns 1200 can also interface with other circuit elements and control logic that manage the operation of the memory array, including data management protocols, error correction algorithms, and power optimization strategies.

[0517] In some embodiments, the memory column 1200 can be fabricated using advanced semiconductor manufacturing techniques such as photolithography, etching, deposition, and planarization processes. The selection of materials for the FeFET (including ferroelectric materials, semiconductor channels, and conductive elements) can be based on desired electrical characteristics such as charge retention, switching speed, and energy efficiency.

[0518] like Figure 12 As shown, the 3D memory array 1200 may include FeFETs (such as 1202) made of various materials that provide the electrical and physical properties necessary to achieve the desired functionality. For example, in some embodiments, the channel layer of each FeFET in FeFET 1202 may be constructed using materials such as indium gallium zinc oxide (IGZO) or other amorphous oxide semiconductors (AOS) (e.g., zinc tin oxide or indium tungsten oxide (IWO)). These materials are chosen because of their electronic properties, such as carrier mobility and stability.

[0519] The ferroelectric material rigidly coupled to the channel layer in each FeFET can include hafnium zirconium oxide (HfZrO2) or other transition metal oxides, perovskites, etc. These ferroelectric materials are chosen for their ability to maintain a polarized state when an electric field is applied, a capability used for the non-volatile memory characteristics of FeFETs. The thickness, crystal structure, and stoichiometry of the ferroelectric layer can be controlled to achieve the desired coercivity, remanent polarization, and other electrical parameters for reliable data storage and retrieval.

[0520] The drain 1204 and source 1208 terminals of the FeFET 1202 are connected to a common select line 1212 and a common bit line 1210, respectively. These common lines can be formed of a conductive material (such as tungsten, titanium nitride, or other metals and metal alloys) that provides a low-resistance path for electrical signals. The configuration of these terminals and their corresponding common lines ensures that the FeFET can be effectively accessed and controlled during operation.

[0521] Each gate terminal (such as gate 1206 of FeFET 1202a) is connected to its corresponding read / write enable line (such as 1214a). The gate terminals help control the state of the FeFET, and the materials chosen for these terminals can include conductive materials that can provide a reliable electrical interface with the ferroelectric material. Read / write enable line 1214 is designed to deliver an appropriate voltage level to gate 1206 of FeFET 1202 to switch between states.

[0522] The memory column 1200 as a whole is designed to support a range of operating parameters. In some embodiments, these parameters may include, but are not limited to: off-state current less than 10^-8 amperes per cubic centimeter, on-state current greater than 10^-7 amperes per cubic centimeter, and channel mobility maintained despite the presence of a ferroelectric layer. The thickness of the channel layer may be less than 30 nanometers to ensure high device density, while the properties of the ferroelectric layer (such as coercivity and remanent polarization) are optimized to provide the necessary memory functionality.

[0523] In some embodiments, the FeFET 1202 may include additional materials or dopants to enhance its electrical properties. For example, dopants such as gallium (Ga), indium (In), or zinc (Zn) may be introduced into the channel layer to modulate carrier concentration or adjust the threshold voltage of the FeFET. Similarly, the ferroelectric layer may include dopants such as lanthanum (La) or niobium (Nb) to adjust its ferroelectric properties.

[0524] In other embodiments, the 3D memory array 1200 can be integrated with additional semiconductor devices and structures to form complex memory systems. These systems can provide storage capacity and support a variety of memory architectures.

[0525] Figure 13 A three-dimensional (3D) memory column 1300 is depicted, configured as a 3D-NAND structure comprising a vertically stacked ferroelectric field-effect transistor (FeFET) 1302, each having a source 1304 and a drain 1308 terminal. The source 1304 of each FeFET (such as 1304a for FeFET 1302a) is coupled to the start of bit line 1310 or connected to the drain of the preceding FeFET; for example, the source 1304b of FeFET 1302b is coupled to the drain 1308a of FeFET 1302a. According to one embodiment of this disclosure, each FeFET includes a gate 1306 (such as 1306a for FeFET 1302a), which is connected to a corresponding read / write enable line (illustrated by 1314a for FeFET 1302a).

[0526] The 3D memory array 1300 includes a series of vertically stacked field-effect transistors (FeFETs), collectively referred to as FeFET 1302. These transistors include FeFET 1302a, FeFET 1302b, FeFET 1302c, FeFET 1302d, etc., characterized by the incorporation of ferroelectric material within their gate structures. Each FeFET in the series of the memory array contributes to the memory storage capacity of the device.

[0527] In the depicted embodiment, each FeFET (such as FeFET 1302a) includes a source terminal 1304 (e.g., source 1304a) coupled to a bit line 1310. The bit line 1310 acts as a conduit for electrical signals used to read from and write to memory cells associated with FeFET 1302a. In scenarios where FeFET 1302a is not the bottom transistor in the column, its source 1304b may be connected to the drain 1308a of the immediately preceding FeFET (such as FeFET 1302a), thereby facilitating a series connection that defines a vertical NAND architecture.

[0528] Each FeFET within FeFET 1302 is also equipped with a gate terminal 1306, exemplified by gate 1306a for FeFET 1302a. This gate terminal 1306 is coupled to a corresponding read / write enable line, exemplified by 1314a for FeFET 1302a. Read / write enable line 1314a controls the state of the FeFET, allowing current to flow through the device or preventing current flow, thereby enabling data writing or reading.

[0529] In addition, each FeFET of FeFET 1302 also includes a drain terminal 1308 (such as drain 1308a for FeFET 1302a), which is typically connected to the source of a subsequent FeFET in a vertical stack. This arrangement ensures that the charge stored in the ferroelectric material of the gate can modulate the current flowing from the source to the drain, thereby allowing data storage and retrieval.

[0530] Figure 13 The memory column 1300 indicates the memory architecture, which can be used in a variety of applications, from portable electronics to enterprise-level data storage systems. In some embodiments, the ferroelectric material used in the FeFET may include various components, such as hafnium oxide, zirconium oxide, or any combination thereof, and the ferroelectric material may be doped with elements such as lanthanum or yttrium to adjust the ferroelectric properties as needed.

[0531] In some variations, the 3D memory column 1300 can incorporate additional features that enhance performance, reliability, or manufacturability. For example, the FeFET 1302 may include a protective layer to shield the ferroelectric material from environmental factors or process-induced damage. Column 1300 may also be integrated with other circuit elements, such as capacitors or diodes, to facilitate, for example, the operation of a charge pump or to provide additional functionality within the memory array.

[0532] The 3D memory array 1300 can be fabricated from various materials that impart specific electrical properties to enhance device performance. In some embodiments, the channel layer of each FeFET can be formed from a material such as indium gallium zinc oxide (IGZO). Other materials for the channel layer can include amorphous oxide semiconductors (AOS), such as zinc tin oxide or aluminum zinc oxide.

[0533] The ferroelectric layer within the FeFET 1302 can comprise materials such as hafnium zirconium oxide (HfZrO2). The thickness and material composition of the ferroelectric layer can be controlled, for example, by atomic layer deposition (ALD), to achieve desired coercivity, remanent polarization, and robustness characteristics. In some implementations, the coercivity of the ferroelectric layer can be tuned between -3 volts and +3 volts, facilitating low-voltage operation of the memory device.

[0534] The source and drain terminals of the FeFET 1302 can include conductive materials such as tungsten or titanium nitride. These materials can also be selected to optimize the contact resistance with the channel layer, reduce overall power consumption, and improve the device's on / off current (Ion / Ioff) ratio.

[0535] Furthermore, the FeFET 1302 can be designed to exhibit specific electrical parameters. For example, in some embodiments, the thickness of the channel layer can be less than 30 nanometers. In some embodiments, the channel layer can exhibit a carrier concentration of 10^17 to 10^20 per cubic centimeter, which can be tuned by doping with elements such as gallium, indium, or zinc to modulate the electrical properties.

[0536] The memory cells formed by FeFET 1302 within the 3D memory column 1300 can also be optimized for operational parameters such as read / write latency, robustness, and power consumption. For example, read and write operations can be performed with less than 10 picojoules of energy and within timeframes of less than 20 nanoseconds, thus contributing to the low-power and high-speed properties of the memory column.

[0537] Furthermore, the 3D-NAND configuration of memory column 1300 can be designed to achieve a high off-state resistance to on-state resistance ratio (Roff / Ron), which is crucial for distinguishing different data states and ensuring reliable data retention. This ratio can be approximately 10^3 or greater, which helps maintain a high signal-to-noise ratio during memory operation.

[0538] The FeFET 1302 in memory row 1300 can also be designed to maintain high reliability, with a durability rating of 10^11 cycles or greater, thereby ensuring the longevity and durability of the memory device. This durability is complementary to the ability of the ferroelectric layer to retain data for at least 1 minute at room temperature (25°C).

[0539] Figure 14 A three-dimensional (3D) memory column according to one embodiment of the present disclosure is depicted, the 3D memory column being configured as a 3D-NAND with integrated transmission gates. The figure illustrates a series of ferroelectric field-effect transistors (FeFETs) 1402, each including source 1404 and drain 1408 terminals, selected by a corresponding gate terminal 1406 and coupled to a read / write enable line 1414. The FeFETs are interconnected to form a vertical memory structure having transmission gates 1418 linked to transmission gate lines 1416.

[0540] therefore, Figure 14 The illustration shows a three-dimensional (3D) memory column designated as element 1400, which can be configured as a 3D-NAND structure with integrated transmission gates. This configuration enables enhanced control over individual memory cells within the 3D structure, potentially improving read / write operations and facilitating efficient memory management.

[0541] In detail, the 3D memory column 1400 includes multiple ferroelectric field-effect transistors (FeFETs), collectively referred to as FeFETs 1402. Each FeFET within the 1402 series (such as 1402a, 1402b, 1402c, 1402d, etc.) is a constituent memory cell of the 3D memory column 1400. These FeFETs are used because of their ability to retain data in a non-volatile manner due to the ferroelectric properties of their gate material, which allows data to be retained even when there is no continuous power supply for a period of time.

[0542] Each FeFET in the series 1402 includes a source, exemplified by source 1404a for FeFET 1402a. The source 1404 for each FeFET is coupled to a bit line (illustrated by bit line 1410 for FeFET 1402a) or connected to the drain of the preceding FeFET in the series. For example, source 1404b of FeFET 1402b is electrically coupled to drain 1408a of FeFET 1402a. This cascading connection forms the basis for a daisy-chain configuration, used in NAND architectures to allow sequential access to an array of FeFETs.

[0543] Furthermore, each FeFET within FeFET 1402 is equipped with a gate terminal, such as gate 1406a for FeFET 1402a. The gates of the FeFETs are connected to their respective read / write enable lines, which are depicted as element 1414 in the figure. For example, gate 1406a of FeFET 1402a is affected by read / write enable line 1414a. These enable lines control the application of appropriate voltages for reading and writing data.

[0544] Furthermore, each FeFET in the FeFET 1402 series includes a drain, such as drain 1408a for FeFET 1402a. This drain is connected to the source of subsequent FeFETs in the series, thus establishing continuity in the columnar structure for 3D memory stacks.

[0545] In some embodiments, each FeFET of FeFET 1402 incorporates a transmission gate, such as transmission gate 1418a, which is connected to a transmission gate line, indicated by 1416 in the figure. Transmission gate line 1416 is a conductive path that provides an electrical signal to control the transmission gate 1418 of the FeFET. Including transmission gates in the FeFET can improve isolation between memory cells during operation, thereby reducing interference and potentially enhancing the reliability of data storage and retrieval.

[0546] like Figure 14 As depicted, the 3D memory column 1400 also encompasses a wide range of materials and parameters that can be utilized to optimize its performance in various embodiments. Each FeFET 1402 within the column can be fabricated using a variety of semiconductor materials. For example, the channel layer of the FeFET can be formed from a material such as indium gallium zinc oxide (IGZO).

[0547] The ferroelectric layer is a defining characteristic of FeFETs and can include materials such as hafnium zirconium oxide (HfZrO2) or other perovskite materials known for their remanent polarization. This property determines the data retention capability of the FeFET. The coercive voltage of this layer affects the energy required to switch polarization states and is a key parameter that can be adjusted according to the requirements of the specific application, wherein the coercive voltage in one embodiment ranges from -3 volts to 3 volts.

[0548] The source and drain terminals of the FeFET, which includes elements 1404 and 1408 respectively, can be made of conductive materials such as tungsten or titanium nitride. These materials provide a path for current flow, which is used for switching. The read / write enable line 1414 that controls the gate 1406 of the FeFET can also be made of a similar material to ensure consistent electrical characteristics throughout the device.

[0549] In terms of physical parameters, the thickness of the channel layer can be less than 30 nanometers. The electron mobility within these channel layers can be maintained at a predetermined level even when the layer thickness is less than 30 nanometers.

[0550] The transmission gate 1418 can be made of a low-resistance material to enable fast switching times, which is beneficial when memory columns are frequently accessed during operation.

[0551] Figure 15 The illustration shows a three-dimensional (3D) memory column 1500 according to one embodiment of the present disclosure. The three-dimensional (3D) memory column 1500 can be configured as a 3D-NOR or 3D-AND structure with independent read / write enable capabilities. The memory column encompasses a series of vertically aligned FeFETs 1502, such as FeFET 1502a, FeFET 1502b, FeFET 1502c, FeFET 1502d, etc. Each FeFET is integrated with a source 1504 (e.g., source 1504a for FeFET 1502a) linked to a corresponding read enable line 1520 (e.g., read enable line 1520a for FeFET 1502a) and a gate 1506 (e.g., gate 1506a for FeFET 1502a) connected to a corresponding write enable line 1522 (e.g., write enable line 1522a for FeFET 1502a). All FeFETs within the column are shared and connected to a common bit line 1510 on their drains 1508, enabling the column to perform coordinated memory operations.

[0552] Figure 15 A detailed description of a three-dimensional (3D) memory column 1500 is presented. The 3D memory column 1500 can be configured as a 3D-NOR or 3D-AND structure with independent read / write enable functions. This memory column is a component of field-effect transistors with ferroelectric gate layers. The field-effect transistors are collectively referred to as FeFET 1502, and are individually identified as, for example, 1502a, 1502b, 1502c, 1502d, etc. Each field-effect transistor represents a memory cell within the column.

[0553] In the illustrated embodiment, each FeFET 1502 includes a source 1504, such as source 1504a corresponding to FeFET 1502a. The source 1504 is designed to be electrically coupled to a corresponding read enable line 1520, such as read enable line 1520a dedicated to FeFET 1502a. The read enable line 1520 is used to selectively activate FeFET 1502 for read operations, thereby allowing stored data to be read from the memory cell.

[0554] Furthermore, each FeFET 1502 is equipped with a gate 1506, exemplified by gate 1506a for FeFET 1502a. Gate 1506 is connected to a corresponding write enable line 1522, such as write enable line 1522a specific to FeFET 1502a. Write enable line 1522 is used to selectively activate FeFET 1502 for write operations, thereby enabling data to be stored within a memory cell.

[0555] Furthermore, each FeFET 1502 includes a drain 1508, such as drain 1508a associated with FeFET 1502a. The drain 1508 is connected to a common bit line 1510. Bit line 1510 acts as a conduit for transferring data to and from memory cells during read and write operations. The commonality of bit line 1510 across multiple FeFETs 1502 means that data from any activated memory cell can be routed through this shared path.

[0556] In some embodiments of the memory column 1500, the configuration of the FeFET 1502 enables high density of memory cells stacked vertically within a compact footprint.

[0557] The ferroelectric material used in the gate 1506 of the FeFET 1502 can include various compositions, such as hafnium oxide-based materials, which can be deposited using atomic layer deposition techniques. The ferroelectric properties of the material allow for data retention, enabling memory cells to maintain stored information even when power is not supplied.

[0558] The source 1504, gate 1506, and drain 1508 of each FeFET 1502 can be made of materials that provide predetermined electrical properties. These materials may include metals such as tungsten or copper, or metal nitrides such as titanium nitride.

[0559] In some embodiments, the read enable line 1520 and write enable line 1522 may be designed to minimize crosstalk and interference between adjacent lines. In some specific embodiments, a shielding layer or insulating material may be included to further isolate the signal path.

[0560] Furthermore, the described memory array 1500 can be integrated into larger semiconductor devices, such as processors or memory modules. It can form part of a system-on-a-chip (SoC) or be included in a multi-chip module (MCM), contributing to data storage and retrieval systems.

[0561] The materials used to construct the FeFETs 1502 within the memory array 1500 are selected to provide specific electrical and physical properties that optimize the performance of the integrated circuit. For example, the channel layer in each FeFET can be formed from advanced semiconductor materials such as indium gallium zinc oxide (IGZO) or other amorphous oxide semiconductors (AOS) (e.g., zinc tin oxide or cadmium oxide). These materials are chosen because of their superior electron mobility and stability.

[0562] The ferroelectric layer, essential for FeFET 1502, can be fabricated from various ferroelectric materials exhibiting suitable polarization properties. Materials such as hafnium zirconium oxide (HfZrO2) or lead zirconate titanate (PZT) can be utilized. These materials can be doped with elements such as lanthanum, yttrium, or other suitable dopants to modify their ferroelectric properties, such as coercivity, remanent polarization, and crystallization temperature. The thickness and material composition of the ferroelectric layer can be tuned to achieve desired memory characteristics (such as write durability and retention time) while ensuring the layer remains compatible with the overall semiconductor manufacturing process and other considerations.

[0563] The source 1504, gate 1506, and drain 1508 terminals of the FeFET 1502 may include conductive materials such as tungsten, titanium nitride, nickel, or molybdenum. Connections to the read enable line 1520 and write enable line 1522 may be facilitated via conductive vias or contacts.

[0564] The read enable line 1520 and write enable line 1522, together with the common bit line 1510, can be patterned using photolithography to achieve predetermined precision and alignment for normal function. These lines can be insulated from each other using dielectric materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), or low-k dielectrics to reduce parasitic capacitance and crosstalk.

[0565] Each element within memory column 1500 can take into account factors such as linewidth, spacing, and aspect ratio to ensure manufacturability, functionality, and / or other objectives or characteristics. The materials and processes used in the construction of memory column 1500 are selected to ensure compatibility with standard semiconductor manufacturing techniques such as photolithography, etching, deposition, and annealing, while also enabling the integration of materials and structures.

[0566] The fabrication of the FeFET 1502 within the memory column 1500 may involve deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) to create uniform and / or non-uniform layers.

[0567] Figure 16A cross-sectional view of a 3D memory structure, designated 1600, according to an embodiment of the present disclosure, is presented. The 3D memory structure is configured as a single-port 3D NAND. The structure includes a first vertical structure 1608a and an identical second vertical structure 1608b. Each vertical structure includes: dielectric columns 1610a, 1610b; channel columns 1612a, 1612b disposed around the dielectric columns; and ferroelectric columns 1614a, 1614b disposed around the channel columns. A series of horizontal gate electrode layers 1606a-160c are disposed at predetermined distances from each other, adjacent to the ferroelectric columns along the length of the vertical structure. The assembly also includes a drain selection layer 1602 and a source selection layer 1604, wherein corresponding end dielectric columns 1618a, 1618b and 1616a, 1616b are positioned at the interface with the vertical structure, illustrating a detailed and complex design for high-density data storage.

[0568] therefore, Figure 16 A cross-sectional view of a three-dimensional (3D) memory structure labeled 1600 is provided, configured as a single-port 3D NAND architecture. This structure incorporates a pair of vertical structures 1608a and 1608b, which can be manufactured substantially identical (as indicated by their respective subscripts a and b), suggesting potential for modular and scalable memory array designs.

[0569] Each vertical structure, exemplified by the first vertical structure 1608a, includes a dielectric column 1610a. The dielectric column can take various geometric forms; it can be cylindrical, substantially cylindrical, or curved. Furthermore, it can be tapered, with a different diameter at each end, implying a design that narrows towards the top. Both solid and hollow configurations of the dielectric column are considered within the scope of this disclosure, providing design flexibility for different electrical and structural requirements.

[0570] Surrounding the dielectric column 1610a is the channel column 1612a, which is the trajectory of charge carriers during device operation. The channel column is also described as possibly cylindrical, substantially cylindrical, or curved, and / or may exhibit a diameter variation along its length similar to that of the dielectric column.

[0571] Enclosing the channel train 1612a is the ferroelectric train 1614a, which extends along the length of the channel train but can be recessed at the ends, thus meaning that the ferroelectric train 1614a does not extend the entire length of the channel train 1612a.

[0572] Intersecting the vertical structure are a series of horizontal grid electrode layers 1606a-1606c positioned at predetermined distances from each other. These layers function in controlling the operating state of the device by influencing the electric field within the ferroelectric array.

[0573] At the top of the 3D memory structure 1600 is a drain selection layer 1602, which is parallel to the horizontal gate electrode layer 1606. At the intersection of the drain selection layer 1602 and the vertical structures 1608a and 1608b, end dielectric columns 1618a and 1618b are identifiable. These end dielectric columns 1618 interface with the channel column 1612 and the drain selection layer 1602, facilitating the isolation and control of charge carriers within the channel column. They can contact the ferroelectric layer 1614 because they encapsulate the channel column 1612 at different locations along its length.

[0574] Similarly, the source selection layer 1604 is located at the bottom of the structure 1600, again parallel to the horizontal gate electrode layer 1606. The corresponding end dielectric columns 1616a and 1616b exist at the position where the source selection layer 1604 docks with the vertical structure, serving a similar function to the end dielectric column 1618 near the drain selection layer 1602.

[0575] The horizontal gate electrode layer 1606 can be constructed from a range of conductive materials, including metals and metal compounds, which can provide different work functions, conductivity, and compatibility with other materials in the structure. Similarly, the ferroelectric array 1614 can incorporate various ferroelectric materials, each with its unique polarization characteristics, coercive field, and dielectric constant, affecting the memory retention and switching behavior of the device.

[0576] The channel column 1612 material can be selected based on its electronic properties, such as carrier mobility and band gap, to achieve the desired on-state and off-state current levels. The dielectric column 1610 provides the necessary electrical insulation to prevent leakage current and ensure proper operation of the device.

[0577] The dielectric array (such as 1610a for the first vertical structure) can be constructed of a material that provides insulating properties to mitigate any potential leakage current. The dielectric material can be hafnium oxide (HfO2) or silicon dioxide (SiO2).

[0578] Surrounding the dielectric column, the channel column (1612a) has a channel material selected from a wide range of semiconductor materials that provide a predetermined carrier mobility. For example, indium gallium zinc oxide (IGZO) can be used due to its electrical properties. The thickness of the channel layer can vary, with some embodiments considering a thickness of less than 30 nanometers. This thickness is chosen to achieve the predetermined electrical performance. Ferroelectric columns (e.g., 1614a) can include perovskite structures, such as lead zirconate titanate (PZT).

[0579] The horizontal gate electrode layers, denoted as 1606a-1606c, include a conductive material that facilitates the application of an electric field to the ferroelectric train. The conductive material can be selected based on its electrical behavior. The selection of the gate electrode material also considers factors such as work function, thermal stability, and ease of integration with existing semiconductor manufacturing processes.

[0580] Drain select and source select layers (1602 and 1604, respectively) are incorporated to enable addressing of individual memory cells within the array. The materials used for these layers are selected based on their conductivity and compatibility with channel and ferroelectric materials. The design of these layers also incorporates considerations for reducing parasitic capacitance and ensuring fast data access.

[0581] The end dielectric columns (e.g., 1618a and 1616a) provide electrical insulation at the ends of the channel columns, and the ferroelectric material does not extend at the ends of the channel columns.

[0582] The disclosed embodiments outline components capable of providing data storage within a 3D memory structure 1600. The design allows for variations in structural dimensions (such as the diameter of the cylindrical columns), which can be uniform or gradually decreasing. Furthermore, options for solid or hollow configurations can be used.

[0583] Figure 17 A 3D memory structure arranged as a dual-port 3D NAND according to one embodiment of the present disclosure is shown. Figure 17 The three-dimensional (3D) memory structure illustrated in the figure (referred to as 3D memory structure 1700) illustrates a dual-port 3D NAND arrangement for providing memory functionality. This structure is characterized by the vertical formation of two primary components, designated as a first vertical structure 1708a and a second vertical structure 1708b, which may be identical or nearly identical, as confirmed by the designated subscripts 'a' and 'b'.

[0584] The first vertical structure 1708a includes a hollow or solid, conical transmission gate electrode array 1718a, which is substantially cylindrical in shape. The transmission gate electrode array 1718a may be made of titanium nitride and may have a larger diameter at the bottom end than at the top end.

[0585] Surrounding the transmission gate electrode array 1718a is a dielectric array 1710a, which can be made of hafnium oxide. The dielectric array 1710a is also basically cylindrical with a slightly tapered shape and a slightly larger diameter at the top. The dielectric array 1710a provides electrical isolation between the transmission gate electrodes and subsequent layers.

[0586] Surrounding the dielectric array 1710a is a cylindrical channel array 1712a, which can be made of IGZO semiconductor material. The channel array 1712a has a curved feature along its length and a uniform diameter overall. The thickness of the channel array can be less than 30 nanometers.

[0587] Surrounding the channel array 1712a is the PZT ferroelectric array 1714a, which covers most of the length of the channel array 1712a, but tapers back at the ends, leaving a portion of the channel array 1712a uncovered. The ferroelectric array 1714a is basically cylindrical and contains lead, zirconium, and titanium as key elemental components.

[0588] Vertical structures 1708a and 1708b extend through several horizontal gate electrode layers 1706a, 1706b, and 1706c, which may be made of tungsten. These horizontal gate electrode layers are positioned at fixed intervals to form an interconnected grid layout. These layers affect the electric field within the ferroelectric array 1714a during memory operation.

[0589] At the top of the memory structure 1700, a drain selection layer 1702 (e.g., titanium nitride) extends parallel to the horizontal gate electrode layer 1706. At the intersection of the drain selection layer 1702 and the vertical structures 1708a and 1708b, end dielectric columns 1718a and 1718b are visible. These end columns (e.g., made of HfO2) contact the ferroelectric column 1714a at one end and surround the uncovered portion of the channel column 1712a, thereby providing insulation.

[0590] Similarly, at the bottom of structure 1700, source selection layer 1704 (e.g., made of tungsten) is parallel to electrode layer 1706 and docks with the vertical structure. End dielectric columns 1716a and 1716b can be observed at these intersections, enclosing the open ends of channel columns 1712a and 1712b.

[0591] In the hollow region at the ends of the transmission gate electrode arrays 1718a and 1718b, thin horizontal dielectric layers 1720a and 1720b can be placed near the bottom terminals (e.g., HfO2). These layers seal the bottom open ends of the vertical hollow voids.

[0592] Figure 18 The illustration shows a 3D memory structure 1800 that can be configured as a 3D NOR vertical transistor memory array. The 3D memory structure 1800 includes a first vertical structure 1808a arranged adjacent to each other and a second vertical structure 1808b that is the same (or substantially the same).

[0593] The first vertical structure 1808a includes a vertical plug array 1802a that provides electrical connections to the lower portion of the 3D memory structure. The vertical plug array 1802a may have a uniform diameter along its entire length, or it may have a larger diameter at its lower end than at its upper end. In various embodiments, the plug array 1802a may be manufactured as a solid array or a hollow array.

[0594] Adjacent to the vertical plug array 1802a are the source electrode array 1804a and the drain electrode array 1816a. The source electrode array 1804a and the drain electrode array 1816a provide electrical connections to the source and drain nodes of the vertical transistor formed along the vertical structure 1808a. The source electrode array 1804a and the drain electrode array 1816a may include various conductive materials, including but not limited to: tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides, graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys (such as AlCu and TiW), and conductive polymers.

[0595] Surrounding the vertical plug array 1802a, the source electrode array 1804a, and the drain electrode array 1816a is the channel array 1812a, which provides a semiconductor channel region for the vertical transistors along the first vertical structure 1808a. The channel array 1812a can be formed from materials including but not limited to: indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), hafnium indium oxide (HIO), cadmium oxide (CdO), polycrystalline silicon, polycrystalline germanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon, crystalline germanium, gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (ZnO), pentacene, P3HT, polythiophene, PPV, graphene, carbon nanotubes (CNT), methylammonium lead halide, cesium lead halide, lead sulfide (PbS), lead selenide (PbSe), cadmium selenide (CdSe), indium arsenide (InAs), and other semiconductor materials.

[0596] Surrounding the channel array 1812a is the ferroelectric array 1814a, which provides the gate dielectric for the vertical transistors along the first vertical structure 1808a. Ferroelectric series 1814a can be composed of ferroelectric materials, including but not limited to: perovskite oxides, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), bismuth zinc niobate (Bi(Zn1 / 2Ti1 / 2)O3), lanthanum bismuth titanate (BiLaTiO3), nickel bismuth titanate (BiNiTiO3), PMN-PT, PLZT, neodymium-doped bismuth titanate (Bi4-xNdxTi3O12), hafnium-based oxides (e.g., hafnium oxide (HfO2) and doped hafnium oxide), tungsten. Bronze structural materials, barium strontium niobate (BSN), barium lead niobate (PBN), potassium tantalum niobate (KTN), bismuth titanate (Bi4Ti3O12), bismuth strontium tantalate (SBT), calcium bismuth niobate (CBN), organic ferroelectrics (e.g., PVDF, TrFE, and P(VDF-TrFE) copolymers), Aurivillius phase oxides, rare earth manganese oxides (e.g., YMnO3), lanthanum-modified PLZT, nickel manganese oxides (NiMnO3), relaxor ferroelectrics (e.g., PMN, PST, and PIN), multiferroic materials (e.g., TbMnO3, EuTiO3, SbSI, GeTe, SnTe), PZT thin films, SBT thin films, HfO2-based thin films, layered superlattices, and PbTiO3 / SrTiO3.

[0597] The 3D memory structure 1800 also includes multiple horizontal gate electrode layers 1806, including layers 1806a, 1806b, 1806c, etc. The horizontal gate electrode layers 1806 are arranged at regular intervals along the vertical structure 1808 and provide gate electrodes for the vertical transistors. The gate electrode layers 1806 can be formed from materials such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides, graphene, carbon nanotubes, doped polycrystalline silicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys (such as AlCu and TiW), and conductive polymers.

[0598] Each horizontal gate electrode layer in the horizontal gate electrode layer 1806 may be surrounded by an oxide / nitride / oxide (ONO) stack 1810, such as 1810a surrounding the gate electrode layer 1806a, to provide insulation between the gate electrodes.

[0599] The second vertical structure 1808b in the 3D memory structure 1800 is configured identically to the first vertical structure 1808a. The two vertical structures 1808a and 1808b are arranged adjacent to each other in the horizontal direction with a spacing that allows for the integration of the gate electrode layer 1806 and the ONO stack 1810. The first vertical structure 1808a and the second vertical structure 1808b, together with the horizontal gate electrode layer 1806, can be configured as a 3D NOR memory architecture.

[0600] Figure 19 An embodiment of a planar FeFET 1900 is illustrated. The FeFET 1900 includes a substrate 1910 on which various layers and components are formed. The substrate 1910 may include silicon or other suitable semiconductor materials. A TiN layer 1912 is disposed on top of the substrate 1910. The TiN layer 1912 may serve as an electrode and may be deposited by sputtering or other suitable deposition techniques.

[0601] A layer of HZO 1908 is formed on top of substrate 1910 and TiN layer 1912. HZO 1908 comprises hafnium, zirconium, and oxygen and can exhibit ferroelectric properties. HZO 1908 can be deposited by ALD, CVD, PVD, or other suitable deposition methods and can have a thickness in the range of 5 nm to 50 nm. As a ferroelectric layer, HZO 1908 enables non-volatile data storage in FeFET 1900.

[0602] A layer of IWO 1906 is conformally deposited on top of the HZO 1908. IWO 1906 comprises indium, tungsten, and oxygen. It can be deposited by sputtering or other suitable techniques and can have a wide range of thicknesses. The IWO 1906 layer acts as the control oxide layer in the FeFET 1900.

[0603] On top of the IWO 1906 layer, drain contacts 1904 and source contacts 1914 are formed. Drain contacts 1904 and source contacts 1914 can comprise metals such as copper, aluminum, or alloys thereof, and can be deposited by PVD, CVD, or other suitable methods. Drain contacts 1904 and source contacts 1914 allow electrical connections to the FeFET 1900. They can have a thickness in the range of 50 nm to 500 nm.

[0604] In operation, the voltage applied to the drain 1904, source 1914, and TiN gate contact 1912 controls the ferroelectric polarization of the HZO 1908 layer. This polarization state can be used to store information in a non-volatile manner, enabling memory storage capabilities. The IWO 1906 layer helps improve the switching speed and robustness of the FeFET 1900. Overall, Figure 19 The layered structure shown implements the FeFET 1900, which is suitable for non-volatile memory applications.

[0605] Figure 20 The transfer characteristics of the ferroelectric FET (FeFET) device are presented, and the relationship between the gate voltage (V_GS) on the x-axis and the resulting drain current (I_D) on the y-axis is illustrated. Figure 20 The characteristics of the FeFET as disclosed herein can be shown. The x-axis spans from -1V to 1V, while the y-axis displays current values ​​from 10^-12 A / μm to 10^-4 A / μm on a logarithmic scale.

[0606] Two distinct curves represent the drain current behavior of the FeFET under clockwise (CW) and counterclockwise (MW) polarization. The blue curve (CW) starts at approximately 10^-11 A / μm at -1V and exhibits a steep increase around -1V, reaching slightly above 10^-5 A / μm at 1V. This demonstrates the rapid increase in drain current exhibited by the FeFET when forward biased in the clockwise polarization state.

[0607] Conversely, the red curve (MW) starts at approximately 10^-11 A / μm at -1V and increases more gradually as it approaches 0V. At around 1V, it then closely follows the blue curve across 1V. This demonstrates comparable drain current behavior under reverse bias conditions, regardless of polarization state.

[0608] Notably, the interval between the red and blue curves spans several orders of magnitude across a negative voltage range approaching -1V. This significant difference in off-state current highlights the non-volatile memory effect achievable with FeFETs, which depends on their polarization direction. This large memory window is clearly indicated in a green box labeled "Large Memory Window" in the upper left corner.

[0609] Additional key details provided include the FeFET device dimensions, with a width / length ratio of 1μm / 50nm specified. The drain voltage is also fixed at 0.05V. Specific points along the curves are marked, with "MW @5e-7A / μm=1V" on the red MW curve indicating a 1V memory window at a drain current of 5x10^-7A / μm. Another marked point is "CW @-0.5V =1x10^6" on the blue CW curve, highlighting a clockwise current value of 1x10-6A / μm at a gate voltage of -0.5V.

[0610] In short, Figure 20 This paper comprehensively depicts the bidirectional transfer characteristics of FeFET devices, highlighting the large memory window achievable through polarization switching and providing detailed voltage, current, and size specifications to fully convey measurement conditions and transistor performance. Paired curves effectively compare clockwise and counterclockwise operating modes across the entire gate voltage range.

[0611] Various alternatives and modifications can be devised by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to cover all such alternatives, modifications, and variations. Furthermore, while several embodiments of this disclosure have been shown in the figures and / or discussed herein, this is not intended to limit the disclosure thereto, as this disclosure is intended to cover as broadly as possible the scope permitted by the prior art, and the specification should be interpreted accordingly. Therefore, the foregoing description should not be construed as restrictive, but merely as illustrative of particular embodiments. Other modifications will be foreseen by those skilled in the art within the scope and spirit of the appended claims. Other elements, steps, methods, and techniques that are substantially different from those described in the foregoing description and / or the appended claims are also intended to be within the scope of this disclosure.

[0612] The embodiments shown in the figures are merely illustrative of certain examples of this disclosure. Furthermore, the figures described are illustrative only and not restrictive. In the figures, the dimensions of some elements may be exaggerated for illustrative purposes and are not drawn to scale. Additionally, depending on the context, elements shown in the figures with the same reference numerals may be the same element or may be similar elements.

[0613] When the term "comprising" is used in this specification and claims, it does not exclude other elements or steps. When referring to a singular noun (e.g., "a," "an," or "the"), the use of an indefinite or definite article includes the plural form of that noun unless otherwise specified. Therefore, the term "comprising" should not be construed as limited to the items listed thereafter; it does not exclude other elements or steps, and thus the scope of "device comprising items A and B" should not be limited to a device that includes only components A and B. This expression means that, with respect to this disclosure, the only relevant components of the device are A and B.

[0614] Furthermore, the terms “first,” “second,” “third,” etc., used in the specification or claims are provided to distinguish similar elements and are not necessarily used to describe order or chronological sequence. It should be understood that such terms are interchangeable where appropriate (unless otherwise explicitly disclosed), and the embodiments of this disclosure described herein can operate in other sequences and / or arrangements different from those described or illustrated herein.

[0615] Each feature and example, and combination thereof, described herein can be considered to be covered by this disclosure. This disclosure therefore relates to the following non-limiting numbered aspects:

[0616] 1. An integrated circuit comprising: a plurality of micro-repositories, each of the plurality of micro-repositories being disposed at a distance from each other and adjacent to a first surface, the plurality of micro-repositories including a first micro-repository; and a plurality of bonding regions, each of the plurality of bonding regions being disposed on the first surface and adjacent to a corresponding micro-repository of the plurality of micro-repositories, the plurality of bonding regions including a first bonding region operatively communicating with the first micro-repository.

[0617] 2. The integrated circuit according to aspect 1, wherein the first bonding region includes a plurality of bonding elements, each of the plurality of bonding elements being operationally in communication with the first micro-repository.

[0618] 3. The integrated circuit according to aspect 2, wherein the plurality of bonding members are bumpless bonding members.

[0619] 4. The integrated circuit according to any one of the foregoing aspects, wherein the first micro-repository has a capacity between 4 kilobytes and 1 megabyte.

[0620] 5. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository has a capacity between 4 kilobytes and 128 kilobytes.

[0621] 6. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository has a capacity between 4 kilobytes and 16 kilobytes.

[0622] 7. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository has a size of less than 256 micrometers by less than 256 micrometers and extends a predetermined distance in the vertical dimension.

[0623] 8. The integrated circuit according to any one of the foregoing aspects, wherein the first micro-repository has a size of 32 micrometers by 32 micrometers and extends a predetermined distance in the vertical dimension.

[0624] 9. The integrated circuit according to aspect 8, wherein the vertical dimension corresponds to at least eight memory layers.

[0625] 10. The integrated circuit according to any one of the foregoing aspects, wherein for each layer of the micro-repository, the bit density of the first micro-repository is greater than 0.2 gigabits per square millimeter.

[0626] 11. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository is disposed on the back-end processing portion of the die.

[0627] 12. The integrated circuit according to aspect 1 further includes an SRAM repository disposed adjacent to the first micro repository.

[0628] 13. The integrated circuit according to aspect 12, wherein the first bonding region is in operative communication with the SRAM repository.

[0629] 14. The integrated circuit according to aspect 12 further includes a second bonding region disposed on the first surface and in operative communication with the SRAM repository.

[0630] 15. The integrated circuit according to aspect 12, wherein the plurality of micro-repositories are formed on the first die and the SRAM repository is formed on the second die, wherein the first die and the second die are bonded together.

[0631] 16. The integrated circuit according to any one of the foregoing aspects further includes a DRAM repository adjacent to the micro-repository.

[0632] 17. The integrated circuit according to aspect 16, wherein the first bonding region is in operative communication with the DRAM repository.

[0633] 18. The integrated circuit according to aspect 16 further includes a second bonding region disposed on the first surface and in operative communication with the DRAM repository.

[0634] 19. The integrated circuit according to aspect 16, wherein the plurality of micro-repositories are formed on a first die and the DRAM repository is formed on a third die, wherein the first die and the second die are rigidly fixed together.

[0635] 20. The integrated circuit according to aspect 1 further includes a read address register operatively coupled to the first bonding region, the read address being configured to hold a read address and transmit the read address to the first micro-repository.

[0636] 21. The integrated circuit according to aspect 1 or 20 further includes a read data register operatively coupled to the first micro-repository, the read data register being configured to receive read data from the first micro-repository and to hold the read data.

[0637] 22. The integrated circuit according to aspect 21, wherein the read data register is operatively coupled to the first bonding region to transfer read data to the first bonding region.

[0638] 23. The integrated circuit according to aspect 21, wherein the read data register is operatively coupled to a second bonding region of the plurality of bonding regions to transfer read data to the second bonding region.

[0639] 24. The integrated circuit according to any one of aspects 21 to 23 further includes a second read data register, the second read data register being operatively in communication with the read data register, and the second read data register being configured to receive read data from the read data register and to hold the read data.

[0640] 25. The integrated circuit according to aspect 24 when subordinate to aspect 22, wherein the second read data register is disposed on a die having a second surface, wherein the second surface includes a read data bonding region operatively coupled to the first bonding region of the first surface.

[0641] 26. The integrated circuit according to aspect 24 when subordinate to aspect 23, wherein the second read data register is disposed on a die having a second surface, wherein the second surface includes a read data bonding region operatively coupled to a second bonding region of the first surface.

[0642] 27. The integrated circuit according to any one of the foregoing aspects further includes a second read data register disposed on a die different from the die having the plurality of micro-repositories.

[0643] 28. The integrated circuit according to any one of the foregoing aspects further includes a second read address register, the second read address register being disposed on a die different from the die having the plurality of micro-repositories.

[0644] 29. The integrated circuit according to any one of aspect 1 or 20 further includes a second read address register.

[0645] 30. The integrated circuit according to aspect 29 further includes a second bonding region on the second surface.

[0646] 31. The integrated circuit according to aspect 30, wherein a second read address register is configured to receive and hold the read address, and to transmit the read address to the read address register via the second surface.

[0647] 32. The integrated circuit according to aspect 31, wherein the second surface is bonded to the first surface.

[0648] 33. The integrated circuit according to any one of the foregoing aspects further includes a through-silicon via (TSV), said TSV being operatively coupled at a first end of said TSV to a third surface on the opposite side of said third surface.

[0649] 34. The integrated circuit according to aspect 33 further includes an interconnect coupled to the first surface and a second end of the through-silicon via.

[0650] 35. The integrated circuit according to aspect 1 further includes a second micro-repository, the second micro-repository being in operative communication with the first bonding region.

[0651] 36. The integrated circuit according to aspect 35 further includes a multiplexer operatively coupled to the first micro-repository to receive first read data from the first micro-repository, the multiplexer being operatively coupled to a second micro-repository to receive second read data from the second micro-repository, wherein the multiplexer is configured to select between the first read data and the second read data for output.

[0652] 37. The integrated circuit according to aspect 36 further includes a counter that is operatively in communication with the multiplexer, and the counter is configured to serially read the first read data and the second read data.

[0653] 38. The integrated circuit according to any one of aspects 36 or 37 further includes a read data register configured to receive the first read data or the second read data to hold the first read data or the second read data in the read data register.

[0654] 39. The integrated circuit according to aspect 38 further includes a second bonding region on the first surface, wherein the read data register is coupled to the second bonding region to transmit the held first read data or the second read data from the multiplexer to the second bonding region.

[0655] 40. The integrated circuit according to any one of the foregoing aspects further includes a component comprising a first die having the plurality of micro-repositories.

[0656] 41. The integrated circuit according to any one of the foregoing aspects further includes a component comprising a first die having the plurality of micro-repositories, the plurality of micro-repositories including a first micro-repository and a second micro-repository.

[0657] 42. The integrated circuit according to any one of aspects 40 or 41 further includes a second die having a read address register and a read data register, wherein the first die is bonded to the second die.

[0658] 43. The integrated circuit according to aspect 42, wherein the first die includes a second bonding region on the first surface, wherein the second die includes a third bonding region and a fourth bonding region, wherein the first bonding region of the first die is coupled to the third bonding region of the second die, and the second bonding region of the first die is coupled to the fourth bonding region of the second die.

[0659] 44. The integrated circuit according to aspect 43, wherein the read address register is operatively coupled to the third bonding region to transfer read data to the third bonding region.

[0660] 45. The integrated circuit according to any one of aspects 43 or 42, wherein the read data register is operatively coupled to the fourth bonding region of the second die to receive read data from the fourth bonding region.

[0661] 46. ​​The integrated circuit according to any one of aspects 41 to 45, wherein the first die includes a second read address register configured to receive and hold a read address, the second read address register being configured to transmit the read address to the first micro-repository and the second micro-repository.

[0662] 47. The integrated circuit according to aspect 45, wherein the first die further includes a multiplexer configured to select between the output of the first micro-repository and the output of the second micro-repository.

[0663] 48. The integrated circuit according to aspect 47 further includes a second bonding region on a second surface of the first die, wherein interconnects connect the second bonding region to an input of the multiplexer, wherein the multiplexer is configured to select among the output of the first micro-repository, the output of the second micro-repository, and a transmission from the bonding region.

[0664] 49. The integrated circuit according to any one of aspects 47 or 48 further includes a stage counter configured to control the multiplexer.

[0665] 50. The integrated circuit according to any one of aspects 47 or 48 further includes a third address register configured to receive and hold the output of the multiplexer.

[0666] 51. The integrated circuit according to aspect 49, wherein the third address register is operatively coupled to a second bonding region of the first die.

[0667] 52. The integrated circuit according to any one of aspects 42 to 50 further includes a TSV, the TSV being coupled to the read address register and the second surface of the die.

[0668] 53. The integrated circuit according to any one of aspects 42 to 51 further includes a second TSV, the second TSV being coupled to the second bonding region of the first die on the second surface and the second read data register.

[0669] 54. The integrated circuit according to aspect 1, wherein the multiplexer is configured to select among one of the plurality of micro-repositories.

[0670] 55. The integrated circuit according to aspect 54, wherein a stage counter is configured to control the selection of the multiplexer.

[0671] 56. The integrated circuit according to aspect 1 further includes a through-silicon via (TSV) operatively coupled to the first surface and a second surface of the die having the plurality of microrepositories.

[0672] 57. The integrated circuit according to aspect 1, wherein a through-silicon via is configured to facilitate communication between a coupled second die and a first die having the plurality of micro-repositories.

[0673] 58. The integrated circuit according to aspect 1, wherein the first micro-repository comprises at least one column of 3D-NOR formed of a plurality of transistors, wherein each transistor includes a gate coupled to a read / write enable line, a source coupled to a bit line, and a drain coupled to a select line.

[0674] 59. The integrated circuit according to aspect 1, wherein the first micro-repository comprises a column of 3D-NAND formed of a plurality of transistors, each transistor having a gate coupled to a read / write enable line, a source coupled to a bit line, and a drain coupled to a source-to-drain junction of a second transistor.

[0675] 60. The integrated circuit according to aspect 1, wherein the first micro-repository comprises a column of 3D-NAND with transmission gates formed of a plurality of transistors, each transistor having a gate coupled to a read / write enable line, a source coupled to a bit line, a drain coupled to the source of a second transistor, and a transmission gate coupled to all of the plurality of transistors.

[0676] 61. The integrated circuit according to aspect 1, wherein the first micro-repository comprises a column of 3D-NORs formed of a plurality of transistors having independent read and write enable, wherein each transistor includes a source coupled to a bit line, a drain coupled to a read enable line, and a gate coupled to a write enable line.

[0677] 62. The integrated circuit according to any one of the preceding aspects, wherein the plurality of micro-repositories includes a thermal management layer configured to dissipate heat generated by the micro-repositories during operation.

[0678] 63. The integrated circuit according to aspect 62, wherein the thermal management layer comprises a material having high thermal conductivity selected from the group consisting of copper, aluminum, diamond and graphene.

[0679] 64. The integrated circuit according to any one of the preceding aspects further includes a hardware-based encryption module, the hardware-based encryption module being operatively coupled to at least one micro-repository for protecting data written to or read from the micro-repository.

[0680] 65. The integrated circuit according to any one of the foregoing aspects further includes a power management circuit configured to adjust the voltage and current supplied to the plurality of micro-repositories based on the operating state of the plurality of micro-repositories.

[0681] 66. The integrated circuit according to aspect 65, wherein the power management circuitry includes a low-power mode that reduces the power supply to the micro-repository during periods of inactivity.

[0682] 67. The integrated circuit according to any one of the preceding aspects further includes a signal conditioning circuit operatively coupled to the plurality of micro-repositories to enhance signal integrity of data transmission.

[0683] 68. The integrated circuit according to aspect 67, wherein the signal conditioning circuit includes a filter, an amplifier, or an error correction encoder.

[0684] 69. The integrated circuit according to any one of the foregoing aspects further includes a diagnostic module configured to monitor the health and performance of the micro-repository and report metrics to an external controller.

[0685] 70. The integrated circuit according to aspect 69, wherein the diagnostic module is capable of performing a self-test on the micro-repository and generating an alarm if a fault is detected.

[0686] 71. The integrated circuit according to any one of the foregoing aspects, wherein each micro-repository includes a built-in self-healing mechanism capable of isolating and bypassing faulty memory cells.

[0687] 72. The integrated circuit according to aspect 71, wherein the self-healing mechanism utilizes redundancy in the form of spare memory cells that can be dynamically allocated to replace faulty cells.

[0688] 73. The integrated circuit according to any one of the preceding aspects, wherein the micro-repository is arranged in a matrix configuration to enable parallel processing and data retrieval.

[0689] 74. The integrated circuit according to aspect 73, wherein the matrix configuration includes row decoders and column decoders to facilitate access to individual micro-repositories.

[0690] 75. The integrated circuit according to any one of the preceding aspects further includes a flexible substrate, enabling the integrated circuit to conform to a non-planar surface.

[0691] 76. The integrated circuit according to aspect 75, wherein the flexible substrate comprises a material selected from the group consisting of polyimide, PEEK, liquid crystal polymer and flexible glass.

[0692] 77. The integrated circuit according to any one of the foregoing aspects, wherein the first micro-repository is configured to operate as a cache memory for a processor.

[0693] 78. The integrated circuit according to aspect 77, wherein the cache memory operates in one of the following modes: write-through, write-back, write-around, or a combination thereof.

[0694] 79. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository is part of a redundant array of independent memory elements for error correction and data recovery.

[0695] 80. The integrated circuit according to any one of the foregoing aspects, wherein the first micro-repository includes a cross-switch architecture to facilitate data routing between memory cells.

[0696] 81. The integrated circuit according to aspect 80, wherein the cross-switch architecture enables non-blocking data transmission within the integrated circuit.

[0697] 82. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository includes a dedicated read peripheral.

[0698] 83. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository includes a dedicated read port.

[0699] 84. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository includes a dedicated write peripheral.

[0700] 85. The integrated circuit according to any one of the preceding aspects, wherein the first micro-repository includes a dedicated write port.

[0701] 86. A method comprising: forming an integrated circuit according to any one of aspects 1-85.

[0702] 87. A method of using an integrated circuit, the method comprising: using an integrated circuit according to any one of aspects 1-85.

Claims

1. An integrated circuit, comprising: A plurality of micro-repositories, each of the plurality of micro-repositories being arranged at intervals relative to each other and adjacent to a first surface, the plurality of micro-repositories including a first micro-repository; as well as Multiple bonding regions, each of the multiple bonding regions being disposed on the first surface and adjacent to a corresponding microrepository among the multiple microrepositories, the multiple bonding regions including a first bonding region that operatively communicates with the first microrepository.

2. The integrated circuit of claim 1, wherein the first bonding region comprises a plurality of bonding members, each of the plurality of bonding members being operationally in communication with the first micro-repository.

3. The integrated circuit according to claim 2, wherein the plurality of bonding members are bumpless bonding members.

4. The integrated circuit of claim 1 further includes an SRAM repository, the SRAM repository being configured adjacent to the first micro repository.

5. The integrated circuit of claim 4, wherein the first bonding region is in operative communication with the SRAM repository.

6. The integrated circuit of claim 4, further comprising a second bonding region disposed on the first surface and in operative communication with the SRAM repository.

7. The integrated circuit of claim 4, wherein the plurality of micro-repositories are formed on a first die and the SRAM repository is formed on a second die, wherein the first die and the second die are bonded together.

8. The integrated circuit of claim 1, further comprising a read address register operatively coupled to the first bonding region, the read address being configured to hold a read address and transmit the read address to the first micro-repository.

9. The integrated circuit of claim 1, further comprising a read data register operatively coupled to the first micro-repository, the read data register being configured to receive read data from the first micro-repository and to hold the read data.

10. The integrated circuit of claim 9, wherein the read data register is operatively coupled to the first bonding region to transfer read data to the first bonding region.

11. The integrated circuit of claim 9, wherein the read data register is operatively coupled to a second bonding region of the plurality of bonding regions to transfer read data to the second bonding region.

12. The integrated circuit according to claim 1, further comprising a second read address register.

13. The integrated circuit of claim 12, further comprising a second bonding region on the second surface.

14. The integrated circuit of claim 13, wherein the second read address register is configured to receive and hold the read address, and to transmit the read address to the read address register via the second surface.

15. The integrated circuit of claim 14, wherein the second surface is bonded to the first surface.

16. The integrated circuit of claim 1, further comprising a second micro-repository, the second micro-repository being in operative communication with the first bonding region.

17. The integrated circuit of claim 16, further comprising a multiplexer operatively coupled to the first micro-repository to receive first read data from the first micro-repository, the multiplexer operatively coupled to the second micro-repository to receive second read data from the second micro-repository, wherein the multiplexer is configured to select between the first read data and the second read data for output.

18. The integrated circuit of claim 17, further comprising a counter, the counter being operatively in communication with the multiplexer, and the counter being configured to serially read the first read data and the second read data.

19. The integrated circuit of claim 17, further comprising a read data register configured to receive the first read data or the second read data to hold the first read data or the second read data in the read data register.

20. The integrated circuit of claim 19, further comprising a second bonding region on the first surface, wherein the read data register is coupled to the second bonding region to transmit the held first read data or the second read data from the multiplexer to the second bonding region.

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