Package with isolated die

Abstract

A wafer chip scale package (WCSP) (104) includes: a first die (200) and a second die (202) in different voltage domains; and an isolation material (204) between the first die and the second die and contacting a plurality of surfaces of each of the first die and the second die. The package also includes a first resin material (206) contacting a plurality of surfaces of the isolation material, wherein the isolation material is between the resin material and the first die and the second die. The package also includes a glass fiber material (208) contacting a surface of the resin material and a second resin material (210) contacting a surface of the glass fiber material. The package also includes a first conductive structure (230) and a second conductive structure (226) coupled to the first die and the second die, respectively. The package also includes a passivation material (224) contacting the first die and the second die and the first conductive structure and the second conductive structure.

Description

Background Technology

[0001] A semiconductor wafer is a circular piece made of a semiconductor material such as silicon, used to manufacture semiconductor chips. Typically, many integrated circuits are formed on a single wafer using complex manufacturing processes. Forming such circuits on a wafer is called fabrication. After wafer fabrication, the wafer is diced into multiple pieces called semiconductor dies, each containing one of the circuits. Dicing or sawing the wafer into individual dies is called dicing. Diced dies can be coupled to conductive terminals and covered with molding compound to form a package. Summary of the Invention

[0002] In one example, a wafer-level package (WCSP) includes: a first die and a second die located in different voltage domains; and an insulating material located between the first die and the second die and contacting a plurality of surfaces of each of the first die and the second die. The package also includes a first resin material contacting the plurality of surfaces of the insulating material, wherein the insulating material is located between the resin material and the first die and the second die. The package further includes a glass fiber material contacting the surfaces of the resin material and a second resin material contacting the surfaces of the glass fiber material. The package also includes a first conductive structure and a second conductive structure respectively coupled to the first die and the second die. The package further includes a passivation material contacting the first die and the second die, as well as the first conductive structure and the second conductive structure.

[0003] In one example, a method for manufacturing a wafer-scale package (WCSP) includes: back-grinding a semiconductor wafer; coupling the wafer to an expandable dicing tape; patterning photoresist on the non-device side of the wafer; using the photoresist to etch the wafer to produce a first die and a second die separated by a gap; filling the gap with an insulating material; covering a plurality of surfaces of the first die and the second die with the insulating material; and performing a sawing process to produce a WCSP comprising the first die and the second die. Attached Figure Description

[0004] Figure 1 A block diagram of an electronic device containing a package with isolated semiconductor dies according to various examples.

[0005] Figure 2A This is a cross-sectional view of a package with isolated semiconductor dies according to various examples.

[0006] Figure 2B This is a top cross-sectional view of a package with isolated semiconductor dies according to various examples.

[0007] Figure 2C This is a perspective cross-sectional view of a package with isolated semiconductor dies according to various examples.

[0008] Figure 3A This is a cross-sectional view of a package with isolated semiconductor dies according to various examples.

[0009] Figure 3B This is a top cross-sectional view of a package with isolated semiconductor dies according to various examples.

[0010] Figure 3C This is a perspective cross-sectional view of a package with isolated semiconductor dies according to various examples.

[0011] Figure 4 This is a flowchart of a method for manufacturing packages with isolated semiconductor dies according to various examples.

[0012] Figure 5A1 to 5O3 This describes the process flow for manufacturing packages with isolated semiconductor dies according to various examples.

[0013] Figure 6A1 to 6O3 This describes the process flow for manufacturing packages with isolated semiconductor dies according to various examples. Detailed Implementation

[0014] Many packages contain semiconductor dies with high and low voltage domains. Trenches are sometimes positioned between these different voltage domains to prevent current leakage between them, but trenches are often ineffective. For example, current can leak from the high voltage domain to the low voltage domain through the die, such as after the package has been subjected to an electric shock. This current leakage can be particularly problematic in certain types of packages, such as wafer-scale packages deployed in high-voltage applications. Current leakage can compromise the functional and mechanical integrity of the package.

[0015] This disclosure describes various examples of packages that alleviate the technical challenges described above. Specifically, the package includes a plurality of semiconductor dies (e.g., two or more dies) located in separate voltage domains and an insulating material, such as parylene, positioned between the dies. The insulating material encapsulates each of the plurality of dies by contacting each such die on a plurality of lateral surfaces and on the bottom surface of the die (i.e., the non-device side). The package further includes support structures that provide rigidity and mechanical strength to the package, such as a first asymmetric prepreg (APP) resin material contacting the insulating material, an APP glass fiber material contacting the first APP resin material, and a second APP resin material contacting the APP glass fiber material. The insulating material encapsulating the plurality of semiconductor dies eliminates any path that leakage current can flow along between the dies, thus mitigating the challenges described above. Various examples of the package are now described with reference to the figures.

[0016] Figure 1This is a block diagram of an electronic device 100 containing a package with isolated semiconductor dies according to various examples. The electronic device 100 can be any suitable type of device, such as a computer (e.g., a laptop computer, desktop computer, notebook computer), a smartphone, a home appliance, an entertainment device (e.g., music entertainment, video entertainment), an automobile, an aircraft, a spacecraft, etc. The electronic device 100 includes a printed circuit board (PCB) 102. A package 104 is coupled to the PCB 102. Various examples of the package 104 are described below.

[0017] Figure 2A This is a cross-sectional view of a package 104 with isolated semiconductor dies according to various examples. In this example, package 104 is a wafer-scale package (WCSP). Example package 104 includes semiconductor dies 200 and 202. In this example, die 200 is considered to be in a low-voltage domain, and die 202 is considered to be in a high-voltage domain. For example, die 200 may be coupled to a ground node, and die 202 may be coupled to a voltage supply (also called a voltage rail). However, in some examples, die 200 is considered to be in a high-voltage domain, and die 202 is considered to be in a low-voltage domain.

[0018] Each of wafers 200 and 202 is encapsulated by a release material 204, such as parylene. The release material 204 encapsulates wafer 200 by contacting it on all four lateral surfaces 218 and the bottom surface 222. The release material 204 may cover all of each of the four lateral surfaces 218 and the entire bottom surface 222. Similarly, the release material 204 encapsulates wafer 202 by contacting it on all (e.g., four) lateral surfaces 216 and the bottom surface 220. The release material 204 may cover all of each of the four lateral surfaces 216 and the entire bottom surface 220. A portion 212 of the insulating material 204 lies between the dies 200 and 202 and has a thickness 214 ranging from 2 micrometers to 50 micrometers. Thicknesses below this range are disadvantageous because they would prevent adequate isolation, while thicknesses above this range are also disadvantageous because they would result in unacceptably large package sizes and high costs. The top surfaces of dies 200 and 202, respectively, opposite the bottom surfaces 222 and 220, are not covered by the insulating material 204, or are covered only minimally by it. By encapsulating the dies 200 and 202 with the insulating material 204 in this manner, leakage current that would otherwise flow between the dies 200 and 202, which are in different voltage domains, is eliminated.

[0019] Still referencing Figure 2AAs shown, an asymmetric prepreg (APP) material 206 (such as a resin material) covers the lateral and bottom surfaces of the insulating material 204. The APP material 206 is used to support the substrate processing system through subsequent processes such as wafer bumping and wafer probing. The APP material 206 has a thickness ranging from 1 micrometer to 200 micrometers, where thicknesses below this range are disadvantageous due to incompatibility with process tolerances, and thicknesses above this range are also disadvantageous due to unacceptably high cost and large footprint.

[0020] Furthermore, APP material 208 (such as glass fiber) contacts APP material 206 and serves to provide mechanical support and stiffness to package 104. Therefore, the glass fiber APP material 208 has a tensile modulus (i.e., a measure of stiffness) in the range of 1 gigapascal (GPa) to 30 GPa, where tensile modulus below this range is undesirable because it causes substrate shagging and warping, and tensile modulus above this range is also undesirable because it causes substrate warping. APP material 208 has a thickness in the range of 10 micrometers to 100 micrometers, where thickness below this range is undesirable because it causes substrate weakening and shagging, and thickness above this range is also undesirable because it causes substrate warping and unacceptably increases cost.

[0021] Furthermore, APP material 210 (such as a resin material) contacts APP material 208 and serves to provide additional mechanical support and a surface for marking (e.g., specific trademarks, model numbers, batch numbers, etc.). APP material 210 has a thickness ranging from 10 micrometers to 150 micrometers, where thicknesses below this range are disadvantageous because they lead to improper marking, and thicknesses above this range are also disadvantageous because they unacceptably increase costs.

[0022] Still referencing Figure 2A Metal contact pads 226 and 230 contact the top surfaces of bare dies 202 and 200, respectively. Metal contact pad 226 is coupled to under-bump metallization (UBM) 228, and metal contact pad 230 is coupled to UBM 232. UBM 228 is coupled to solder bump 234, and UBM 232 is coupled to solder bump 236. Metal contact pads 226 and UBM 228 are collectively referred to herein as conductive structures. Metal contact pads 230 and UBM 232 are collectively referred to herein as conductive structures. Passivation layer 224 covers metal contact pads 226 and 230.

[0023] Figure 2B This is a top cross-sectional view of a package 104 with isolated semiconductor dies according to various examples. Figure 2CA perspective cross-sectional view of package 104 with isolated semiconductor dies according to various examples.

[0024] Figure 3A This is a cross-sectional view of a package 104 with isolated semiconductor dies according to various examples. Figure 3A The 104 package is different Figure 2A The package is 104, but Figure 2A and 3A The 104 package is Figure 1 The example shown is of package 104. Figure 3A Package 104 includes dies 200 and 202, isolation material 204, and APP materials 206, 208, and 210, each of which has been described above and therefore will not be described again here. The device side of die 200 includes a metal trace 302, and the device side of die 202 includes a metal trace 304. The thicknesses of metal traces 302 and 304 are enlarged in the figures for improved visibility. Via 306 couples metal trace 302 to metal contact pad 308. Via 310 couples metal trace 304 to metal contact pad 312. Oxide layer 300 covers metal traces 302 and 304 and vias 306 and 310. Oxide layer 300 also includes a metal layer 316 coupled to metal contact pad 314 via via 317. Passivation layer 320 covers metal contact pads 308, 312, and 314. A polyimide layer 322 covers UBMs 324, 326, and 328, which are coupled to metal contact pads 308, 314, and 312, respectively. Solder bumps 330, 332, and 334 are coupled to UBMs 324, 326, and 328, respectively.

[0025] In this example, package 104 can operate in multiple domains. For instance, die 200 can operate in a first voltage domain, and die 202 can operate in a second voltage domain. Metal contact pad 308 can be a first terminal, and metal contact pad 312 can be a second terminal. Metal contact pad 314 can be a third terminal. Metal layer 316 can be located near metal trace 304 but not directly coupled to metal trace 304. Therefore, metal layer 316 and metal trace 304 can be capacitively coupled at the area indicated by digit 318.

[0026] Figure 3B For various examples Figure 3A Top sectional view of package 104. Figure 3C For various examples Figure 3A A perspective cross-sectional view of the package 104.

[0027] Figure 4 For use in manufacturing packages with isolated semiconductor dies according to various examples (e.g., Figures 2A to 2CThe flowchart of the method 400 for 3A to 3C packaging 104). Figure 5A1 to 5O3 For use in manufacturing packages with isolated semiconductor dies according to various examples (e.g., Figures 2A to 2C The process flow of packaging 104). Figure 6A1 to 6O3 For use in manufacturing packages with isolated semiconductor dies according to various examples (e.g., Figures 3A to 3C The process flow for the 104 package is described below. Therefore, it will now be described in parallel. Figure 4 , 5A1 To 5O3 and 6Al to 6O3.

[0028] Method 400 includes back-grinding a semiconductor wafer (402). The wafer may include circuitry suitable for operation in different voltage domains, and as described below, portions of the wafer containing circuitry suitable for operation in a low voltage domain may be spaced apart from portions of the wafer containing circuitry suitable for operation in a high voltage domain. The wafer may include multiple portions of circuitry suitable for operation in a low voltage domain and multiple portions of circuitry suitable for operation in a high voltage domain. Method 400 also includes coupling the wafer to an expandable dicing tape (404). Figure 5A1 This is a cross-sectional view of wafer 500, and Figure 5B1 This is a cross-sectional view of a wafer 500 that has been back-ground and coupled to an expandable dicing tape 504 coupled to a carrier 502. Figure 5A2 For various examples Figure 5A1 A top view of the structure. Figure 5A3 For various examples Figure 5A1 A perspective view of the structure. Figure 5B2 For various examples Figure 5B1 A top view of the structure. Figure 5B3 For various examples Figure 5B1 A perspective view of the structure.

[0029] Method 400 includes applying photoresist to the non-device side of the wafer (406). Figure 5C1 exhibit Figure 5B1 The cross-sectional view of the structure differs in that the photoresist 506 is coupled to the non-device side of the wafer 500. Figure 5C2 For various examples Figure 5C1 A top view of the structure. Figure 5C3 For various examples Figure 5C1 A perspective view of the structure.

[0030] Method 400 includes patterning the photoresist (408). Figure 5D1 exhibit Figure 5C1The cross-sectional view of the structure differs in that the photoresist 506 is patterned (e.g., using photolithography), so that the structure of the photoresist 506 is suitable for etching the wafer 500 as needed. Figure 5D2 For various examples Figure 5D1 A top view of the structure. Figure 5D3 For various examples Figure 5D1 A perspective view of the structure.

[0031] Method 400 involves using photoresist to etch a wafer to produce a plurality of dies (410) spaced apart by gaps. Figure 5E1 for Figure 5D1 The cross-sectional view of the structure differs in that the wafer 500 is etched (and thus cut) to produce multiple dies 200 and multiple dies 202. The photoresist 506 is also removed. Figure 5E2 For various examples Figure 5E1 A top view of the structure. Figure 5E3 For various examples Figure 5E1 A perspective view of the structure.

[0032] Method 400 includes expanding the cut tape to widen the gap between the first set of bare sheets and the second set of bare sheets (412). Figure 5F1 for Figure 5E1 The cross-sectional view of the structure differs in that the cutting tape 504 has been stretched to widen the gap between the various bare sheets 200, 202, as indicated by arrow 508. Figure 5F2 For various examples Figure 5F1 A top view of the structure. Figure 5F3 For various examples Figure 5F1 A perspective view of the structure.

[0033] Method 400 involves covering multiple surfaces of the bare die with an insulating material (414). Figure 5G1 for Figure 5F1 The cross-sectional view of the structure differs in that an insulating material 204 is added to cover the exposed areas of the various bare sheets 200, 202 and the cutting tape 504. As shown, the insulating material 204 fills the gaps between the bare sheets 200, 202, thus covering the lateral surfaces (e.g., all four lateral surfaces) of each of the bare sheets 200, 202. Additionally, the insulating material 204 covers the surfaces of the bare sheets 200, 202 furthest from the cutting tape 504. Figure 5G2 For various examples Figure 5G1 A top view of the structure. Figure 5G3 For various examples Figure 5G1 A perspective view of the structure.

[0034] Method 400 includes covering the insulating material (416) with the first APP material. Figure 5H1 for Figure 5G1 The cross-sectional view of the structure differs in that the APP material 206 is applied directly onto the insulating material 204. The APP material 206 can be, for example, a resin material or a polymer. The APP material 206 can be applied by any suitable technique, such as vacuum lamination, pressure lamination, spin coating, etc. Figure 5H2 For various examples Figure 5H1 A top view of the structure. Figure 5H3 For various examples Figure 5H1 A perspective view of the structure.

[0035] Method 400 includes covering the first APP material with the second APP material (418). Figure 5I1 for Figure 5H1 The cross-sectional view of the structure differs in that APP material 208 is added to APP material 206. APP material 208 can be, for example, glass fiber material or epoxy resin. APP material 208 can be applied by any suitable technique, such as vacuum lamination, pressure lamination, stencil printing, etc. Figure 5I2 For various examples Figure 5I1 A top view of the structure. Figure 5I3 For various examples Figure 5I1 A perspective view of the structure.

[0036] Method 400 includes covering the second APP material with the third APP material (420). Figure 5J1 for Figure 5I1 The cross-sectional view of the structure differs in that APP material 210 is added to APP material 208. APP material 210 can be, for example, a resin material or a polymer. APP material 210 can be applied by any suitable technique, such as vacuum lamination, pressure lamination, spin coating, etc. Figure 5J2 For various examples Figure 5J1 A top view of the structure. Figure 5J3 For various examples Figure 5J1 A perspective view of the structure.

[0037] Method 400 includes performing a sawing process in the gap between the first set of dies and the second set of dies to produce individual packages (422), and removing the individual packages from the cutting tape (424). Figure 5K1 for Figure 5J1 The cross-sectional view of the structure differs in that a sawing operation has been performed in the gap between the innermost bare dies 200, 202 to produce individual (but incomplete) packages 104, and the cutting tape 504 and carrier 502 have been removed from the packages 104. Figure 5K2 For various examples Figure 5K1 A top view of the structure. Figure 5K3For various examples Figure 5K1 A perspective view of the structure.

[0038] Method 400 includes applying a passivation layer, a polyimide layer, an insulating layer, and / or a metal layer to the device side of the package (426). Figure 5L1 for Figure 5K1 The cross-sectional view of the structure differs in that metal contact pads 226 and 230 are added. For example, the metal contact pads 226 and 230 can be applied using any suitable technique, such as electroplating. Figure 5L2 For various examples Figure 5L1 A top view of the structure. Figure 5L3 For various examples Figure 5L1 A perspective view of the structure. Figure 5M1 for Figure 5L1 The cross-sectional view of the structure differs in that a passivation layer 224 is applied to the metal contact pads 226, 230 and the remainder of the top surface of the package 104, as shown. Figure 5M2 For various examples Figure 5M1 A top view of the structure. Figure 5M3 For various examples Figure 5M2 A perspective view of the structure.

[0039] Figure 5N1 for Figure 5M1 The cross-sectional view of the structure differs in that apertures perpendicularly aligned with metal contact pads 226 and 230 have been formed in the passivation layer 224 using photolithography and etching techniques, and these apertures are lined with a seed layer 510 (e.g., a copper seed layer). Figure 5N2 For various examples Figure 5N1 A top view of the structure. Figure 5N3 For various examples Figure 5N1 A perspective view of the structure. Figure 5O1 for Figure 5N1 The cross-sectional view of the structure differs in that UBM228 and 232 are electroplated and solder bumps 234 and 236 are deposited on UBM 228 and 232 respectively. Figure 5O2 For various examples Figure 5O1 A top view of the structure. Figure 5O3 For various examples Figure 5O1 A perspective view of the structure. Therefore, Figures 2A to 2C The encapsulation of 104 is complete.

[0040] Steps 402 to 424 of method 400 can also be applied to manufacturing. Figures 3A to 3C The package is 104. Figures 6A1 to 6K3 The process flow describes the manufacturing according to steps 402 to 424 of method 400. Figures 3A to 3C The package is 104. Figures 6A1 to 6K3 The process flow is respectively with Figures 5A1 to 5K3 The process flow is the same, and therefore will not be described here. Figures 6A1 to 6K3 However, the execution of step 426 of method 400 in manufacturing... Figures 3A to 3C The packaging 104 is relative to the manufacturing process. Figures 2A to 2C The encapsulation 104 is different. Step 426 includes applying a passivation layer, a polyimide layer, an insulating layer, and / or a metal layer to the device side of the encapsulation, and Figure 6L1 to 6O3 Describe the execution of step 426. Figure 6L1 for Figure 6K1 The cross-sectional view of the structure differs in that through-holes 306, 310, and 317 are electroplated, as well as a metal layer 316 and an oxide layer 300 is applied. The oxide layer 300 can be applied using any suitable technique, such as thermal oxidation growth, chemical vapor deposition (CVD) oxidation, etc. Figure 6L2 For various examples Figure 6L1 A top view of the structure. Figure 6L3 For various examples Figure 6L1 A perspective view of the structure. Figure 6M1 for Figure 6L1 The cross-sectional view of the structure differs in that it has electroplated metal contact pads 308, 312, and 314 and a passivation layer 320 applied. The passivation layer 320 can be applied using any suitable technique, such as thermal oxidation growth, CVD oxidation, etc. Figure 6M2 For various examples Figure 6M1 A top view of the structure. Figure 6M3 For various examples Figure 6M1 A perspective view of the structure.

[0041] Figure 6N1 for Figure 6M1 The cross-sectional view of the structure differs in that a polyimide layer 322 is applied, and the polyimide layer 322 is etched over metal contact pads 308, 312 and 314 to form orifices over metal contact pads 308, 312 and 314, and the orifices are lined with a seed layer 600 (e.g., a copper seed layer). Figure 6N2 For various examples Figure 6N1 A top view of the structure. Figure 6N3 For various examples Figure 6N1 A perspective view of the structure. Figure 6O1 for Figure 6N1 The cross-sectional view of the structure differs in that UBM 324, 326 and 328 are electroplated, and solder bumps 330, 332 and 334 are deposited on UBM 324, 326 and 328 respectively. Figure 6O2 For various examples Figure 6O1 A top view of the structure. Figure 6O3For various examples Figure 6O1 A perspective view of the structure. Therefore, Figures 3A to 3C The encapsulation of 104 is complete.

[0042] In this description, the term "coupling" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0043] Devices “configured” to perform tasks or functions may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform functions and / or may be configured (or reconfigurable) by the user after manufacturing to perform functions and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and through the interconnection of the device or a combination thereof.

[0044] The use of the phrase "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this description. In this description, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of said parameter. Modifications to the described examples are possible within the scope of the claims, and other examples are also possible.

[0045] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless otherwise specified, these terms are generally used to refer to interconnects or terminals between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

Claims

1. A wafer-level chip-scale package (WCSP), comprising: The first and second bare wafers are located in different voltage domains; A separating material is located between the first bare sheet and the second bare sheet and contacts a plurality of surfaces of each of the first bare sheet and the second bare sheet; A first resin material has multiple surfaces in contact with the insulating material, the insulating material being located between the resin material and the first and second bare sheets; A glass fiber material, on the surface of which it contacts the resin material; A second resin material, which contacts the surface of the glass fiber material; A first conductive structure and a second conductive structure are respectively coupled to the first die and the second die; and A passivating material that contacts the first and second bare wafers, as well as the first and second conductive structures.

2. The WCSP of claim 1, wherein the portion of the insulating material between the first die and the second die has a thickness in the range of 2 micrometers to 50 micrometers.

3. The WCSP according to claim 1, wherein at least one of the first resin material, the second resin material, and the glass fiber material is an asymmetric prepreg (APP) material.

4. The WCSP according to claim 1, wherein the first resin material has a thickness in the range of 10 micrometers to 200 micrometers, the second resin material has a thickness in the range of 10 micrometers to 150 micrometers, and the glass fiber material has a thickness in the range of 10 micrometers to 100 micrometers.

5. The WCSP according to claim 1, wherein the insulating material comprises parylene.

6. A wafer-level chip-scale package (WCSP), comprising: The first bare die has a first top surface, a first bottom surface opposite to the first top surface, and a plurality of first transverse surfaces; The second die has a second top surface, a second bottom surface opposite to the second top surface, and a plurality of second lateral surfaces, and the first die and the second die are in different voltage domains; An insulating material that contacts the first bottom surface and the second bottom surface, the plurality of first lateral surfaces and the plurality of second lateral surfaces, wherein the portion of the insulating material between the first bare sheet and the second bare sheet has a width in the range of 2 micrometers to 50 micrometers; and An asymmetric prepreg (APP) material that is in contact with the insulating material and has a tensile modulus in the range of 1 gigapascal (GPa) to 30 GPa.

7. The WCSP according to claim 6, wherein the insulating material comprises parylene.

8. The WCSP of claim 6, wherein the APP material comprises a glass fiber-based asymmetric prepreg (APP) material and has a thickness in the range of 10 micrometers to 100 micrometers.

9. The WCSP according to claim 6, further comprising: A first resin-based APP material, which is in contact with the APP material and has a thickness in the range of 10 micrometers to 200 micrometers; and The second resin-based APP material is in contact with the APP material and has a thickness in the range of 10 micrometers to 150 micrometers.

10. A method for manufacturing a wafer-scale package (WCSP), comprising: Backside grinding of semiconductor wafers; Couple the wafer to an expandable dicing tape; Photoresist is patterned on the non-device side of the wafer; The photoresist is used to etch the wafer to produce a first and a second die separated by a gap; The gap is filled with insulating material; The insulating material is used to cover multiple surfaces of the first and second bare wafers; and A sawing process is performed to produce a WCSP containing the first blank and the second blank.

11. The method of claim 10, wherein the insulating material has a width in the range of 2 micrometers to 50 micrometers.

12. The method of claim 10, further comprising: The cutting tape is expanded to form a second gap between the first set of bare sheets and the second set of bare sheets, the first set of bare sheets comprising the first bare sheet and the second bare sheet. The sawing process is performed in the second gap between the first set of bare sheets and the second set of bare sheets.

13. The method of claim 10, further comprising covering the insulating material with a first resin material.

14. The method of claim 13, wherein the first resin material has a thickness in the range of 10 micrometers to 200 micrometers.

15. The method of claim 13, further comprising covering the first resin material with a glass fiber material.

16. The method of claim 15, wherein the glass fiber material has a thickness in the range of 10 micrometers to 100 micrometers.

17. The method of claim 15, further comprising covering the glass fiber material with a second resin material.

18. The method of claim 17, wherein the second resin material has a thickness in the range of 10 micrometers to 150 micrometers.

19. The method of claim 10, further comprising electroplating metal contact pads on the first die.

20. The method of claim 19, further comprising covering the metal contact pads at least partially with a polyimide layer, applying a seed layer on the polyimide layer, electroplating the seed layer to form an under-bump metallization, and depositing solder bumps on the under-bump metallization.

21. The method of claim 10, wherein the first die and the second die are in different voltage domains.

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