Impedance measurement device and method

Abstract

The application discloses an impedance measurement device and method, comprising a signal source module, a range resistance module, an unbalance detection module and a measurement module; the signal source module comprises a first signal generation unit, a second signal generation unit, a first clock synchronization unit, a plurality of first digital-to-analog conversion units, a plurality of second digital-to-analog conversion units, a first signal output unit and a second signal output unit; the first clock synchronization unit is used for outputting a plurality of equally-spaced synchronous clock signals; the plurality of first digital-to-analog conversion units are used for converting digital signals output by the first signal generation unit into a plurality of first analog signals based on the synchronous clock signals; the first signal output unit is used for synthesizing the plurality of first analog signals into a first signal source; and the measurement module is used for detecting a voltage signal of the range resistance module and an impedance to be measured, two-way synchronous and consistent signal sources are generated through the signal source module with the first clock synchronization unit, and the excitation precision of a balanced bridge is improved.

Description

Technical Field

[0001] This application relates to the field of impedance measurement technology, and in particular to an impedance measurement device and method. Background Technology

[0002] In the field of weak signal detection and precision impedance measurement, the balanced bridge system is one of the core architectures for achieving high-precision measurement of the complex impedance of the device under test. It relies on a high-precision excitation signal source to complete the bridge driving and signal modulation. Direct Digital Synthesis (DDS) technology has become the mainstream solution for generating excitation signals for balanced bridges due to its ability to finely control frequency, phase and amplitude.

[0003] Currently, the DDS system used in balanced bridge circuits is typically paired with a digital-to-analog converter (DAC) to convert digital signals into analog excitations. To alleviate the inherent contradiction between the sampling rate and accuracy of DACs, parallel interleaved output DAC structures are widely used. However, this architecture has significant drawbacks in balanced bridge scenarios: Firstly, the parallel DAC channels of the DDS are susceptible to clock jitter in each channel, leading to a decrease in the phase and amplitude consistency of the multi-channel output signals. Balanced bridges have stringent requirements for the synchronization and consistency of excitation signals, and clock jitter directly introduces non-test imbalance errors into the bridge circuit, reducing impedance measurement accuracy. Secondly, in high-frequency, wide dynamic range scenarios, the phase noise and amplitude distortion of the signal in the traditional DDS combined with parallel DAC signal output link are difficult to control, further weakening the sensitivity of the balanced bridge to detecting weak impedance changes and failing to meet the requirements of modern precision measurement for "low noise, high synchronization, and high fidelity" excitation signals. Summary of the Invention

[0004] To address the existing technical problems, this invention provides an impedance measurement device and method. The device generates two synchronization signals through a signal source module with a first clock synchronization unit to drive the impedance under test and the range resistance module. The measurement module then detects the voltage signal to achieve impedance measurement. Clock synchronization ensures the consistency of the two signal sources and improves the excitation accuracy of the balanced bridge.

[0005] In a first aspect, embodiments of this application provide an impedance measurement device, including a signal source module, a range resistance module, an imbalance detection module, and a measurement module;

[0006] The signal source module includes a first signal generating unit, a second signal generating unit, a first clock synchronization unit, multiple first digital-to-analog converters (DACs), multiple second DACs, a first signal output unit, and a second signal output unit. The first clock synchronization unit is connected to the multiple DACs and the multiple second DACs, and is used to output multiple equally spaced synchronous clock signals respectively. The multiple first DACs are used to convert the digital signals output by the first signal generating unit into multiple first analog signals based on the synchronous clock signals. The first signal output unit is used to synthesize the multiple first analog signals into a first signal source. The multiple second DACs are used to convert the digital signals output by the second signal generating unit into multiple second analog signals based on the synchronous clock signals. The second signal output unit is used to synthesize the multiple second analog signals into a second signal source.

[0007] The first end of the impedance to be measured is connected to the first signal source, and the second end is also connected to the first end of the range resistor module. The second end of the range resistor module is connected to the second signal source.

[0008] The imbalance detection module is used to adjust the second signal source based on the imbalance current between the impedance to be measured and the range resistance module;

[0009] The measurement module is used to detect the voltage signal of the impedance to be measured and the range resistance module.

[0010] In one optional embodiment, the first signal output unit includes a first signal synthesizer and a first signal amplification structure; the input terminal of the first signal synthesizer is connected to a plurality of first digital-to-analog conversion units, and the output terminal is connected to the input terminal of the first signal amplification structure;

[0011] The second signal output unit includes a second signal synthesizer and a second signal amplification structure; the input terminal of the second signal synthesizer is connected to multiple second digital-to-analog conversion units, and the output terminal is connected to the input terminal of the second signal amplification structure.

[0012] In one optional embodiment, the first signal amplification structure includes a first-stage amplification link and a second-stage amplification link;

[0013] The first-stage amplification link includes a first relay, a first amplification element, and a first external resistor; the first relay is used to receive and, based on a first amplification control signal, connect different first external resistors to the first amplification element, so that the first amplification element amplifies the signal by different factors.

[0014] The second-stage amplification link includes a second relay, a second amplifying element, and a second external resistor. The second relay is used to receive and connect different second external resistors to the second amplifying element based on the second amplification control signal, so that the second amplifying element amplifies the signal by different factors.

[0015] In one optional embodiment, the plurality of first digital-to-analog conversion units are configured as four first digital-to-analog converters; the plurality of second digital-to-analog conversion units are configured as four second digital-to-analog converters;

[0016] The first signal output unit is used to synthesize the analog signals output by the four first digital-to-analog converters into a first signal source; the second signal output unit is used to synthesize the analog signals output by the four second digital-to-analog converters into a second signal source.

[0017] In one optional embodiment, the first signal output unit further includes a first signal buffer structure; the input terminal of the first signal buffer structure is connected to the output terminal of the first signal amplification structure, and the output terminal is connected to the first terminal of the impedance to be measured.

[0018] The first signal output unit also includes a second signal buffer structure; the input end of the second signal buffer structure is connected to the output end of the second signal amplification structure, and the output end is connected to the second end of the range resistor module.

[0019] In one optional embodiment, the first clock synchronization unit includes a clock input structure and a clock tree structure;

[0020] The clock tree structure includes a clock tree root and multiple fan-out buffers; each fan-out buffer includes deterministic time error and uncertain time error; the clock tree root receives the original clock signal from the clock input structure, inputs it into the multiple fan-out buffers, and forms multiple synchronous clock signals, which are respectively connected to multiple first digital-to-analog conversion units and multiple second digital-to-analog conversion units.

[0021] In one optional embodiment, the range resistor module includes multiple reference resistors with different resistance values ​​and multiple switching switches, with each reference resistor connected in series with a switching switch; the multiple sets of series-connected reference resistors are connected in parallel with the switching switches.

[0022] In one alternative embodiment, the measurement module includes a switching element and a voltage measurement unit;

[0023] The first input terminal of the switching element is connected between the impedance to be measured and the first signal source, the second input terminal is connected between the range resistor module and the second signal source, and the output terminal is connected to the voltage measurement unit. It is used to acquire the first voltage signal of the impedance to be measured or the second voltage signal of the range resistor module based on the switching control signal.

[0024] In one optional embodiment, the voltage measurement unit includes a first range adjustment structure, a first buffer structure, and a first analog-to-digital conversion structure; the input terminal of the first range adjustment structure is connected to the output terminal of the switching element, and the output terminal is connected to the input terminal of the first buffer structure; the output terminal of the first buffer structure is connected to the first analog-to-digital conversion structure.

[0025] In one optional embodiment, the measurement module further includes a signal processing unit, which includes a third signal amplification structure and a second clock synchronization unit; the first analog-to-digital conversion structure includes a plurality of first analog-to-digital converters;

[0026] The third signal amplification structure is used to amplify the first voltage signal or the second voltage signal by different factors; the second clock synchronization unit is connected to multiple first analog-to-digital converters and is used to output multiple equally spaced synchronization clock signals to the multiple first analog-to-digital converters respectively; the multiple first analog-to-digital converters are used to convert the amplified first voltage signal or the second voltage signal into multiple digital signals and output them based on the multiple equally spaced synchronization clock signals.

[0027] Secondly, embodiments of this application provide an impedance measurement method, the method comprising:

[0028] The reference resistance value of the range resistance module is determined based on the impedance to be measured;

[0029] The unbalanced current between the impedance to be measured and the range resistance module is obtained using the unbalanced detection module.

[0030] If the unbalanced current is not zero, an adjustment signal is generated based on the unbalanced current, and the second signal source is adjusted based on the adjustment signal to obtain the adjusted unbalanced current; or; if the unbalanced current is zero, the first voltage value of the impedance to be measured and the second voltage value of the range resistor module are obtained.

[0031] The impedance value of the impedance to be measured is determined based on the first voltage value and the second voltage value.

[0032] Thirdly, embodiments of this application provide an impedance measuring device, the device comprising:

[0033] The first determining module is used to determine the reference resistance value of the range resistance module based on the impedance to be measured.

[0034] The first acquisition module is used to acquire the unbalanced current between the impedance to be measured and the range resistance module using the unbalance detection module.

[0035] The second acquisition module is used to generate an adjustment signal based on the unbalanced current if the unbalanced current is not zero, adjust the second signal source based on the adjustment signal, and acquire the adjusted unbalanced current; or; if the unbalanced current is zero, acquire the first voltage value of the impedance to be measured and the second voltage value of the range resistor module.

[0036] The second determining module is used to determine the impedance value of the impedance to be measured based on the first voltage value and the second voltage value.

[0037] Fourthly, embodiments of this application provide an electronic device, which includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The processor loads and executes the at least one instruction, at least one program, code set, or instruction set to implement the impedance measurement method of the first aspect.

[0038] Fifthly, embodiments of this application provide a computer-readable storage medium storing at least one instruction or at least one program, wherein the at least one instruction or at least one program is loaded and executed by a processor to implement the impedance measurement method of the first aspect.

[0039] Sixthly, embodiments of this application provide a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the impedance measurement method of the first aspect.

[0040] The balanced bridge and impedance measurement method provided in this application have the following technical effects:

[0041] The balanced bridge includes a signal source module, a range resistor module, an imbalance detection module, and a measurement module. The signal source module includes a first signal generation unit, a second signal generation unit, a first clock synchronization unit, multiple first digital-to-analog converters (DACs), multiple second DACs, a first signal output unit, and a second signal output unit. The first clock synchronization unit is connected to the multiple DACs and the multiple second DACs, and is used to output multiple equally spaced synchronous clock signals. The multiple DACs convert the digital signals output by the first signal generation unit into multiple first analog signals based on the synchronous clock signals. The first signal output unit... The system is used to synthesize multiple first analog signals into a first signal source; multiple second digital-to-analog conversion units are used to convert the digital signals output by the second signal generation unit into multiple second analog signals based on a synchronous clock signal; a second signal output unit is used to synthesize multiple second analog signals into a second signal source; the first end of the impedance to be measured is connected to the first signal source, and the second end is also connected to the first end of the range resistor module, and the second end of the range resistor module is connected to the second signal source; an unbalance detection module is used to adjust the second signal source based on the unbalanced current between the impedance to be measured and the range resistor module; a measurement module is used to detect the voltage signals of the impedance to be measured and the range resistor module. In this embodiment, the signal source module with a first clock synchronization unit generates two synchronous signals to drive the impedance to be measured and the range resistor module, and then the measurement module detects the voltage signals to achieve impedance measurement. The clock synchronization ensures the consistency of the two signal sources and improves the excitation accuracy of the balanced bridge. Attached Figure Description

[0042] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of a module of an impedance measuring device provided in an embodiment of this application. Figure 1 ;

[0044] Figure 2 This is a schematic diagram of an impedance measuring device provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of a range resistor module provided in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of a module of an impedance measuring device provided in an embodiment of this application. Figure 2 ;

[0047] Figure 5 This is a schematic diagram of a signal source module provided in an embodiment of this application. Figure 1 ;

[0048] Figure 6 This is a schematic diagram of a first clock synchronization unit provided in an embodiment of this application;

[0049] Figure 7 This is a schematic diagram of a first signal amplification structure provided in an embodiment of this application;

[0050] Figure 8 This is a circuit diagram of a first-stage amplification link provided in an embodiment of this application;

[0051] Figure 9 This is a schematic diagram illustrating the effect of a first-stage amplification link provided in an embodiment of this application. Figure 1 ;

[0052] Figure 10 This is a schematic diagram illustrating the effect of a first-stage amplification link provided in an embodiment of this application. Figure 2 ;

[0053] Figure 11 This is a circuit diagram of a second-stage amplification link provided in an embodiment of this application;

[0054] Figure 12 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 1 ;

[0055] Figure 13 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 2 ;

[0056] Figure 14 This is a schematic diagram of a signal source module provided in an embodiment of this application. Figure 2 ;

[0057] Figure 15 This is a schematic diagram of a multi-stage signal amplification structure provided in an embodiment of this application;

[0058] Figure 16 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 1 ;

[0059] Figure 17 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 2 ;

[0060] Figure 18 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 3 ;

[0061] Figure 19 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 1 ;

[0062] Figure 20 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 2 ;

[0063] Figure 21 This is a circuit diagram of a third-stage amplification link provided in an embodiment of this application;

[0064] Figure 22 This application provides a circuit effect of a third-stage amplification link according to an embodiment. Figure 1 ;

[0065] Figure 23 This application provides a circuit effect of a third-stage amplification link according to an embodiment. Figure 2 ;

[0066] Figure 24 This is a circuit diagram of a fourth-stage amplification link provided in an embodiment of this application;

[0067] Figure 25 This is a schematic diagram illustrating the effect of a fourth-level amplification link provided in an embodiment of this application. Figure 1 ;

[0068] Figure 26 This is a schematic diagram illustrating the effect of a fourth-level amplification link provided in an embodiment of this application. Figure 2 ;

[0069] Figure 27 This is a circuit diagram of a fifth-stage amplification link provided in an embodiment of this application;

[0070] Figure 28 This is a schematic diagram illustrating the effect of a fifth-level amplification link provided in an embodiment of this application. Figure 1 ;

[0071] Figure 29 This is a schematic diagram illustrating the effect of a fifth-level amplification link provided in an embodiment of this application. Figure 2 ;

[0072] Figure 30 This is a schematic diagram of a multi-stage signal amplification structure, a second clock synchronization unit, and a first analog-to-digital conversion structure provided in an embodiment of this application.

[0073] Figure 31 This is a schematic flowchart of an impedance measurement method provided in an embodiment of this application;

[0074] Figure 32 This is a schematic diagram of the structure of an impedance measuring device provided in an embodiment of this application;

[0075] Figure 33 This is a hardware structure block diagram of a server for an impedance measurement method provided in an embodiment of this application.

[0076] Figure label:

[0077] 1. Signal source module; 11. First signal generation unit; 12. Second signal generation unit; 13. First clock synchronization unit; 14. First digital-to-analog conversion unit; 15. Second digital-to-analog conversion unit; 16. First signal output unit; 17. Second signal output unit;

[0078] 2. Impedance to be measured;

[0079] 3. Range resistor module;

[0080] 4. Measurement module;

[0081] 5. Imbalance detection module. Detailed Implementation

[0082] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0083] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0084] Figure 1 This is a schematic diagram of a module of an impedance measuring device provided in an embodiment of this application. Figure 1 The impedance measurement device includes a signal source module 1, a range resistance module 3, a measurement module 4, and an unbalance detection module 5, which together form a balanced bridge for measuring the impedance to be measured 2.

[0085] In one optional embodiment, the signal source module 1 includes a first signal generating unit 11, a second signal generating unit 12, a first clock synchronization unit 13, a plurality of first digital-to-analog conversion units 14, a plurality of second digital-to-analog conversion units 15, a first signal output unit 16, and a second signal output unit 17.

[0086] The first signal generating unit 11 is connected to multiple first digital-to-analog converter units 14 and outputs a first digital signal to each of the multiple first digital-to-analog converter units; the second signal generating unit 12 is connected to multiple second digital-to-analog converter units 15 and outputs a second digital signal to each of the multiple second digital-to-analog converter units.

[0087] The first clock synchronization unit 13 is connected to multiple first digital-to-analog converter units 14 and multiple second digital-to-analog converter units 15, and is used to output two sets of multiple synchronization clock signals with different phases and equal intervals to the multiple first digital-to-analog converter units 14 and multiple second digital-to-analog converter units 15 respectively.

[0088] Multiple first digital-to-analog conversion units 14 are used to convert the first digital signal output by the first signal generation unit 11 into multiple first analog signals based on a first set of synchronous clock signals. The first signal output unit 16 is used to synthesize the multiple first analog signals into a first signal source.

[0089] Multiple second digital-to-analog conversion units 15 are used to convert the second digital signal output by the second signal generation unit 12 into multiple second analog signals based on the second set of synchronous clock signals; the second signal output unit 17 is used to synthesize the multiple second analog signals into a second signal source.

[0090] Signal source module 1 generates two high-precision signals, a first signal source and a second signal source. The first signal generation unit 11 and the second signal generation unit 12 output digital signals, respectively. The first clock synchronization unit 13 provides a multi-phase equally spaced synchronization clock to drive multiple DACs to convert the digital signals into analog signals. The two signals are then synthesized by the first and second signal output units, ensuring the synchronization and stability of the two signals and adapting to the bridge drive requirements. The multiple DACs synchronized by the clock can finally be synthesized into high-resolution first and second signals. Through the parallel interleaved output architecture, the inherent contradiction between the sampling rate and accuracy of a single DAC is overcome. Relying on the low jitter synchronization characteristics of the clock tree, the synthesized two signals are highly coordinated in frequency and phase. The amplitude dynamic range can also adapt to the devices under test with different impedance levels. At the same time, the timing misalignment problem when multiple DACs work independently is avoided. This provides a high-bandwidth, high-fidelity, and low-noise dual-channel drive signal for the balanced bridge, supporting subsequent bridge balance adjustment and precise impedance measurement.

[0091] like Figure 1 As shown, the first terminal of the impedance to be measured 2 is connected to the first signal source output by the signal source module 1, and the second terminal is also connected to the first terminal of the range resistor module 3. The second terminal of the range resistor module 3 is connected to the second signal source output by the signal source module 1. The impedance to be measured 2 is the object of detection, receives the driving signal from the first signal source, and forms a path with the range resistor. The range resistor module 3 contains a reference resistor with a known resistance value, receives the second signal source, and together with the impedance to be measured 2, forms the core path of the bridge circuit, serving as the reference for impedance measurement.

[0092] Finally, the measurement module 4 is connected to the impedance to be measured 2 to detect the unbalanced current between the impedance to be measured 2 and the range resistor module 3, providing data for impedance calculation.

[0093] Specifically, the two synchronous signal sources output by the signal source module 1 drive the impedance under test 2 and the range resistor to form a path, respectively. Since the resistance value of the impedance under test 2 is unknown, the currents in the two paths are not equal, which will generate an unbalanced current. The unbalanced detection module 5 adjusts the second signal source based on the unbalanced current between the impedance under test and the range resistor module until the unbalanced current is zero and the balance bridge is balanced. At this time, the value of the impedance under test 2 can be accurately calculated by measurement. The lock-in amplifier characteristics can also suppress noise and improve the measurement accuracy.

[0094] With the above settings, the signal source module 1 with the first clock synchronization unit 13 generates two synchronous signals to drive the impedance under test 2 and the range resistor module 3. Then, the unbalance detection module 5 adjusts the second signal source based on the unbalanced current between the impedance under test and the range resistor module. The consistency of the signal source is ensured by clock synchronization, which improves the excitation accuracy of the balanced bridge.

[0095] Figure 2 This is a schematic diagram of an impedance measuring device provided in an embodiment of this application. Figure 1 ,like Figure 2 As shown, the core principle of the balanced bridge impedance measurement is that the electrical parameters of the impedance to be measured 2 and the range resistor module 3 with known parameters are equivalently matched in the bridge's balanced state. The signal source module 1 provides two stable excitation signals, such as sinusoidal signals, which are applied to the branch of the impedance to be measured 2 and the branch of the range resistor module 3, respectively, forming the two core branches of the bridge. Since the parameters of the impedance to be measured 2 are unknown, the impedances of the two branches are initially mismatched, resulting in an unbalanced current.

[0096] The unbalance detection module 5 captures this unbalanced current and generates a compensation signal through vector modulation or other methods. This compensation signal acts on the second signal source of the range resistor module 3 branch, thereby adjusting the equivalent parameters of the range resistor module 3 in reverse until the unbalanced current of the balanced bridge approaches zero, at which point the bridge reaches a balanced state. Since the parameters of the range resistor module 3 are known, the specific value of the impedance 2 under test can be deduced by reading the current value flowing through it or the voltage value across it in the balanced state, thus achieving impedance measurement.

[0097] Specifically, a vector meter is connected to the impedance under test (DUT) terminal to measure the vector voltage value Vx across the DUT in real time. It also needs to measure the current Ix flowing through the DUT. A vector meter is connected to the range resistor Rr terminal to measure the vector current value Ir flowing through the range resistor in real time.

[0098] like Figure 2As shown in the diagram, Hc is the current sensing terminal used to detect the current value of the impedance under test. Hp and Lp are a pair of voltage sensing terminals, with the voltage between Hp and Lp representing the impedance under test. If the current of the range resistor and the current of the device under test are not balanced, an unbalanced current will occur, equal to Ix - Ir, flowing into the zero-position detector at the low potential point Lp. The unbalanced current vector reflects the degree of difference between the range resistor current and the current of the device under test in terms of amplitude and phase angle. After detecting the unbalanced current, the zero-position detector controls the amplitude and phase angle of the output signal of the second signal source to make the detected current approach zero.

[0099] When the current of the range resistor is unbalanced with the current of the impedance to be measured, Lp is not equal to zero. At this time, the second signal source is controlled to output a voltage signal proportional to the unbalanced current so that the current of the range resistor Ir and the current of the impedance to be measured Ix are balanced until the leakage current is zero.

[0100] According to Kirchhoff's current theorem (KCL), Ip = Ix + Ir.

[0101] Since the current at the node is 0, the currents Ix and Ir flow in opposite directions. When the current Ix flowing through the impedance to be measured 2 is equal to the current Ir flowing through the range resistor, the leakage current Ip is zero, and the circuit remains balanced.

[0102] In equilibrium, Ix = Ir, and Ir can be measured by a vector table. Since the device under test is a capacitor, it will be affected by its imaginary part, especially when the capacitance is smaller, the imaginary part of the impedance is larger. In this case, the phase of the current Ix is not simply 0 degrees or 180 degrees, but will be affected by the imaginary part of the capacitance. If the angle of the current Ix is θ, then the angle of Ir is 180 - θ.

[0103] If the signal source has an internal resistance R0, then the following can be obtained: .in The sum of the impedance values ​​of the impedance to be measured (DUT) and R0 allows us to determine the real and imaginary parts of the impedance to be measured (DUT). , .

[0104] The actual impedance value can be obtained. In actual measurement, Ix is the current flowing through the impedance to be measured 2 and the internal resistance R0 of the first signal source, and the output resistance should also be taken into account. Therefore, when obtaining the impedance to be measured Zx using the above formula, the real part of the impedance should be subtracted from the value of the output impedance.

[0105] Figure 3 This is a schematic diagram of a range resistor module 3 provided in an embodiment of this application, as shown below. Figure 3 As shown, in one optional embodiment, the range resistor module 3 includes multiple reference resistors with different resistance values ​​and multiple range switches.

[0106] Each reference resistor is connected in series with the range switch, and multiple sets of series-connected reference resistors are connected in parallel with the range switch. Multiple reference resistors with different resistance values ​​cover a wide range and can match various test objects from low impedance to high impedance, avoiding the problem that a single reference resistor cannot meet the measurement requirements of different impedances.

[0107] Based on the impedance value of the connected device under test (DUT), the resistance value of the range resistor can be manually selected to match the magnitude of the DUT. Then, adjust the output voltage of the second signal source to balance the current of the range resistor with the current of the DUT. The range resistor can be selected with five resistance values: 10Ω, 100Ω, 1kΩ, 10kΩ, and 100kΩ.

[0108] For the second signal source, the maximum resistance of the range resistor is 100kΩ. When the impedance to be measured 2 is in the megaohm range, in order to balance the current Ix of the range resistor module with the current Ir of the impedance to be measured 2, the second signal source needs to output a voltage signal proportional to the unbalanced current. Since the impedance to be measured 2 differs significantly in magnitude from the range resistor, the second signal source needs to output a smaller voltage signal. Therefore, a high-precision voltage source should be selected for the second signal source to ensure bridge balance and meet the requirements for accurate measurement of large resistances.

[0109] The obtained signal is fed back through the range resistor to cancel the current flowing through the impedance under test (2DUT). Even if there is a phase error in the balance control loop, the unbalanced current component caused by the phase error can be canceled by adjusting the phase of the output signal of the second signal source to cancel the error in the current of the range resistor module. Therefore, the unbalanced current will eventually converge to zero, ensuring that Ix=Ir in the high frequency range.

[0110] Figure 4 This is a schematic diagram of a module of an impedance measuring device provided in an embodiment of this application. Figure 2 ,like Figure 4 As shown, in an optional embodiment, the first signal output unit 16 includes a first signal synthesizer and a first signal amplification structure; the input terminal of the first signal synthesizer is connected to a plurality of first digital-to-analog conversion units 14, and the output terminal is connected to the input terminal of the first signal amplification structure.

[0111] The second signal output unit 17 includes a second signal synthesizer and a second signal amplification structure. The input terminal of the second signal synthesizer is connected to a plurality of second digital-to-analog conversion units 15, and the output terminal is connected to the input terminal of the second signal amplification structure.

[0112] In the embodiments of this application, such as Figure 4 As shown, the plurality of first digital-to-analog conversion units 14 are configured as four first digital-to-analog converters, and the plurality of second digital-to-analog conversion units 15 are configured as four second digital-to-analog converters.

[0113] The first signal output unit 16 is used to synthesize the analog signals output by the four first digital-to-analog converters into a first signal source; the second signal output unit 17 is used to synthesize the analog signals output by the four second digital-to-analog converters into a second signal source.

[0114] In an optional embodiment, the first signal output unit 16 further includes a first signal buffer structure, the input terminal of which is connected to the output terminal of the first signal amplification structure, and the output terminal is connected to the first end of the impedance to be measured.

[0115] The second signal output unit 17 further includes a second signal buffer structure. The input end of the second signal buffer structure is connected to the output end of the second signal amplification structure, and the output end is connected to the second end of the range resistor module.

[0116] The first and second signal buffer structures are two independently configured signal isolation and adaptation units. Their core function is to ensure the stable driving of the balanced bridge by the dual signal sources. The first signal, after being synthesized and amplified in two stages, is first input to the first signal buffer structure, and then the output of the buffer structure is connected to the first terminal of the impedance under test 2. The second signal, after being synthesized and amplified in two stages, is first input to the second signal buffer structure, and then the output of the buffer structure is connected to the second terminal of the range resistor module 3. The buffer structure achieves impedance isolation and matching, preventing the load characteristics of the impedance under test 2 and the range resistor from having a reverse effect on the pre-amplification link, preventing signal distortion, enhancing signal driving capability, improving the load capacity of the output signal, ensuring that the two signals are stably delivered to the corresponding branches of the balanced bridge, ensuring the stability of the bridge drive, and finally optimizing signal quality, suppressing link interference, maintaining the synchronization and accuracy of the two signals, laying the foundation for accurate impedance measurement.

[0117] This application improves the output rate by using four AD9117 chips in parallel and alternating output. The AD9117 is a high-performance DAC chip with a resolution of 14 bits and a sampling rate of 125 MSPS.

[0118] Figure 5 This is a schematic diagram of a signal source module provided in an embodiment of this application. Figure 1 ,like Figure 5As shown, four direct digital synthesizers (DDS) are used to read data from the waveform memory in a phase-delayed manner and output it to four synchronously clocked DACs. The four DDSs simultaneously read data from the waveform memory with a fixed phase difference, maintaining a consistent clock frequency for each DDS. The phases of each DDS differ by 90 degrees, meaning the read data are staggered in phase. The data is then transmitted to the corresponding four DAC chips. Finally, the DAC chips combine the data acquired at the same time using adders, and output the data in an alternating manner. A clock tree structure is used to generate multiple clock signals to provide the output clock for the DACs. This method increases the overall system output rate to four times that of a single-chip DAC while retaining the high output accuracy of the original single-chip DAC, theoretically resolving the contradiction between high sampling rate and high resolution.

[0119] In parallel DAC interleaved output architectures, designing a multi-channel low-jitter sampling clock system is crucial for ensuring system performance. In conventional implementations, the clock signal coordinating the collaborative operation of multiple DACs is typically generated using a clock distribution chip. From a hardware implementation perspective, this method is relatively simple. However, in actual circuit board design, factors such as PCB layout and manufacturing errors in electronic components inevitably cause a certain degree of jitter in the output clock signal, significantly increasing its uncertainty. Furthermore, these electronic components are highly susceptible to interference from external environmental factors, such as power supply voltage fluctuations, operating temperature changes, and manufacturing process deviations in specific components. These factors further exacerbate clock signal uncertainty, ultimately leading to timing deviations in the DAC. For parallel DAC structures with extremely stringent clock signal accuracy requirements, such timing deviations are intolerable and severely impact the performance and stability of the entire system.

[0120] Figure 6 This is a schematic diagram of a first clock synchronization unit provided in an embodiment of this application. In an optional embodiment, in order to meet the requirements of a multi-channel parallel DAC system for low jitter and high-precision clock signals, the first clock synchronization unit 13 includes a clock input structure and a clock tree structure.

[0121] The clock tree topology is as follows: Figure 6 As shown, the clock tree structure includes a clock tree root and multi-level fan-out buffers, exhibiting high flexibility and scalability, and can flexibly configure the number of clock signal output channels according to the needs of actual application scenarios.

[0122] Each fan-out buffer stage includes deterministic time error and uncertain time error. The deterministic time error is represented by t1 and t2 in the figure, and the uncertain time error is represented by Δt1 and Δt2 in the figure.

[0123] The deterministic timing error originates from the inherent timing characteristics of each component in the clock tree and can be accurately corrected through subsequent data processing algorithms. The uncertain timing error, however, is caused by a combination of factors, including PCB routing parasitic parameters, component performance fluctuations, and environmental interference. Therefore, the high-performance dual-loop integer N-division jitter attenuator HMC7044 serves as the root node of the clock tree. This chip supports sending Serial Peripheral Interface (SPI) commands or SYNC (synchronization request) pulses via host computer software to achieve precise phase alignment of the output clock signal. During this process, the chip's built-in general-purpose reference signal timer is synchronously reset, ensuring high-precision synchronization of all clock output dividers. Furthermore, the HMC7044 also supports generating a specific number of output pulses via host computer software as internal reference signal pulses, providing a reliable reference for the synchronization of multi-channel clock signals. The proposed solution effectively compensates for skew errors between output stages and errors caused by inconsistent line lengths at each output stage during subsequent PCB fabrication. The proposed clock tree structure significantly reduces the uncertainty error of the clock signal, providing a high-precision, low-jitter clock signal guarantee for parallel ADC systems.

[0124] The clock tree root receives the original clock signal from the clock input structure, inputs it into a multi-stage fan-out buffer, and forms multiple synchronous clock signals. These multiple synchronous clock signals are then connected to multiple digital-to-analog converters.

[0125] After receiving the original clock signal through the clock input structure and clock tree structure, the signal is processed by the clock tree root HMC7044 chip and multi-level fan-out buffers to generate multiple synchronous clock signals, which are then distributed to multiple digital-to-analog converters to meet the clock requirements of multi-channel parallel sampling.

[0126] For the two types of time errors in the clock tree, precise control is achieved through hardware selection and algorithm cooperation. Deterministic time errors caused by the inherent timing characteristics of components can be corrected by subsequent data processing algorithms; while uncertain time errors caused by PCB routing, environmental interference, etc. are significantly suppressed by the jitter attenuation function of the HMC7044 chip, while compensating for errors such as inconsistent line length and output skew.

[0127] Meanwhile, by using the SPI command or SYNC signal control of the HMC7044 chip, the phase alignment of multiple output clocks is achieved. The built-in timer synchronous reset ensures high-precision synchronization of all clock dividers, providing a unified reference for multi-channel analog-to-digital conversion, avoiding phase signal distortion caused by sampling time misalignment, and ensuring that weak voltage signals of different phases still maintain their original phase relationship after conversion.

[0128] Furthermore, the clock tree structure offers high flexibility and scalability, allowing for flexible configuration of the number of clock signal output channels based on actual application needs, adapting to different numbers of digital-to-analog converters, and enhancing the versatility of the solution.

[0129] The first signal source and the second signal source in this application have the same structure, so only the first signal amplification structure in the first signal output unit of the first signal source will be used as an example for explanation.

[0130] Figure 7 This is a schematic diagram of a first signal amplification structure provided in an embodiment of this application, as shown below. Figure 7 As shown, in order to precisely control the output signal source, in one optional embodiment, the first signal amplification structure includes a first-stage amplification link and a second-stage amplification link.

[0131] The first-stage amplification link includes a first relay, a first amplification element, and a first peripheral resistor; the first relay is used to receive and connect different first peripheral resistors to the first amplification element based on the first amplification control signal, so that the first amplification element amplifies the signal by different factors.

[0132] Figure 8 This is a circuit diagram of a first-stage amplification link provided in an embodiment of this application, wherein the first amplification element is THS4151, the signal input is pins 1 and 8 of THS4151, the signal output is pins 4 and 5 of THS4151, and the gain is 0dB or 20dB.

[0133] like Figure 8 As shown, the eight pins of the THS4151 are VIN+ (non-inverting input), VIN- (inverting input), VOCM (common-mode voltage), NC (not connected), VCC+ (positive power supply), VCC- (negative power supply), VOUT+ (positive output), and VOUT- (negative output). The same pins of different chips will not be described again.

[0134] Relay K12 is used to switch the gain between 0dB and 20dB. When the common pins 3 and 6 of relay K12 are connected to pins 2 and 7 respectively, the feedback resistors of the first-stage amplification link are R529, R530, and R531 in the diagram, and the input resistor is R532. Therefore, the gain is R532 / (R529+R530+R531) = 2KΩ / (68Ω+100Ω+1.5KΩ) = 0dB.

[0135] When the common pins 3 and 6 of relay K12 are connected to pins 4 and 5 respectively, the feedback resistors of the first-stage amplification link are R529 and R530 in the figure, and the input resistor is R532. Therefore, the gain is R532 / (R529+R530) = 2KΩ / (68Ω+100Ω) = 20dB.

[0136] Figure 9 This is a schematic diagram illustrating the effect of a first-stage amplification link provided in an embodiment of this application. Figure 1 , Figure 9 It is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the first-stage amplifier link gain is 0dB. Figure 10 This is a schematic diagram illustrating the effect of a first-stage amplification link provided in an embodiment of this application. Figure 2 , Figure 10 This is the output waveform after amplifying a 100kHz, 10mVpp sine wave by 20dB when the first-stage amplifier link gain is 20dB.

[0137] The second-stage amplification link includes a second relay, a second amplifying element, and a second external resistor. The second relay is used to receive and connect different second external resistors to the second amplifying element based on the second amplification control signal, so that the second amplifying element amplifies the signal by different factors.

[0138] Figure 11 This is a circuit diagram of a second-stage amplification link provided in an embodiment of this application. The second amplification element of the second-stage amplification link is a THS3001. The signal input is pins 2 and 3 of the THS3001, and the signal output is pin 6 of the THS3001. The gain is 0dB or -40dB.

[0139] Relay K14 is used to switch the gain between 0dB and -40dB. When the common pins 3 and 6 of relay K14 are connected to pins 2 and 7 respectively, the gain is 0.5 (R552 / R551) = 0.5 (2KΩ / 1KΩ) = 0dB.

[0140] When the common pins 3 and 6 of relay K14 are connected to pins 4 and 5 respectively, the gain is 0.006(R552 / R551) = 0.006(2KΩ / 1KΩ) = -40dB.

[0141] Figure 12 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 1 , Figure 12 It is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the first-stage amplifier link gain is 0dB. Figure 13 This is a schematic diagram illustrating the effect of a second-stage amplification link provided in an embodiment of this application. Figure 2 , Figure 13 This is the output waveform after amplifying a 100kHz, 1Vpp sine wave by -40dB when the second-stage amplification link gain is -40dB.

[0142] By combining two stages of amplification links, four different gain levels can be achieved, specifically including the following:

[0143] 10V level: The gain of the first stage amplification link is 20dB; the gain of the second stage amplification link is 0dB, and the total gain is 20dB + 0dB = 20dB.

[0144] 1V level: The gain of the first-stage amplification link is 0dB; the gain of the second-stage amplification link is 0dB, and the total gain is 0dB + 0dB = 0dB.

[0145] 100mV range: The gain of the first-stage amplification link is 20dB; the gain of the second-stage amplification link is -40dB, and the total gain is 20dB-40dB=-20dB.

[0146] 10mV range: The gain of the first-stage amplification link is 0dB; the gain of the second-stage amplification link is -40dB, and the total gain is 0dB-40dB=-40dB.

[0147] Figure 14 This is a schematic diagram of a signal source module provided in an embodiment of this application. Figure 2 The first signal generation unit 11 or the second signal generation unit 12 outputs multiple digital signals with different phases. The clock tree provides a multi-phase synchronous clock to drive four DACs to convert digital signals into analog signals. After two stages of amplification, the signals are synthesized and output.

[0148] In another possible embodiment, the signals output from the first and second DACs can be combined and then amplified in two stages to serve as the first signal source, and the signals output from the third and fourth DACs can be combined and then amplified in two stages to serve as the second signal source.

[0149] like Figure 2 As shown, in an optional embodiment, the unbalance detection module 5 includes a zero-position detector for detecting the unbalanced current between the impedance to be measured 2 and the range resistor module 3.

[0150] Since the impedance measurement method described above is difficult to implement in practice, the vector ratio measurement method described below is used to calculate the impedance.

[0151] First, a virtual ground needs to be established, which means using the unbalanced detection module to adjust the balance bridge to balance. At this time, the feedback current Ir flowing through the range resistor module Rr is equal to the test current Ix flowing through the DUT, Ir=Ix, so the voltage Vr of the range resistor module is Vr=Ir×Rr=Ix×Rr.

[0152] The test current Ix is determined by the impedance Zx of the DUT and the voltage Vx across the DUT, that is, Ix = Vx / Zx.

[0153] Therefore, the formula for calculating the impedance Zx of the DUT is Zx=(Vx / Ix)×Rr=Vx / Vr. That is, by simply measuring the ratio of Vx to Vr, the impedance Zx of the DUT can be obtained, thus realizing the measurement of the impedance to be measured.

[0154] In an optional embodiment, the measurement module 4 is used to detect the voltage signals of the impedance to be measured 2 and the range resistance module, which can be measured separately using two voltmeters.

[0155] like Figure 4 As shown in the embodiment of this application, in order to avoid tracking errors between the two voltmeters, Vx and Vr can be measured by alternating the use of a single vector voltmeter. Therefore, the measurement module includes a switching element and a voltage measurement unit.

[0156] The first input terminal of the switching element is connected between the impedance to be measured and the first signal source, the second input terminal is connected between the range resistor module and the second signal source, and the output terminal is connected to the voltage measurement unit. It is used to acquire the first voltage signal of the impedance to be measured or the second voltage signal of the range resistor module based on the switching control signal.

[0157] In one optional embodiment, the voltage measurement unit includes a first range adjustment structure, a first buffer structure, and a first analog-to-digital conversion structure; the input terminal of the first range adjustment structure is connected to the output terminal of the switching element, and the output terminal is connected to the input terminal of the first buffer structure; the output terminal of the first buffer structure is connected to the first analog-to-digital conversion structure.

[0158] In one alternative embodiment, the zero-point detector for measuring unbalanced current includes a second range adjustment structure, a second buffer structure, and a second analog-to-digital conversion structure.

[0159] In this embodiment of the application, the measurement module further includes a signal processing unit, which is used to amplify the first voltage signal or the second voltage signal by different factors to facilitate the calculation of the impedance value of the impedance to be measured.

[0160] Specifically, the signal processing unit includes a third signal amplification structure and a second clock synchronization unit.

[0161] The third signal amplification structure is used to amplify the first voltage signal or the second voltage signal by different factors based on the third amplification control signal.

[0162] In this embodiment, the third signal amplification structure has a two-branch selective amplification link and a multi-stage amplification link that allows for flexible selection of amplification factor.

[0163] Figure 15This is a schematic diagram of a multi-stage signal amplification structure provided in an embodiment of this application, such as... Figure 15 As shown, the selected amplification link includes a first switching switch, a first amplification link, a second amplification link, and a second switching switch. The first switching switch and the second switching switch connect the first amplification link or the second amplification link to the multi-stage amplification link based on the selection control signal.

[0164] The selection control signal is determined based on the amplitudes of the first voltage signal and the second voltage signal.

[0165] If the voltage signal is a large signal, the selection control signal controls the first and second switching switches to connect the first amplification link with the multi-stage amplification link.

[0166] If the voltage signal is a small signal, the selection control signal controls the first and second switching switches to connect the second amplification link to the multi-stage amplification link.

[0167] Figure 16 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 1 , Figure 16 This is the schematic diagram of the first amplification link. The amplifying element in the first amplification link is an OPA656. The large signal input that needs to be amplified is pins 3 and 4 of the OPA656, and the signal output is pin 1 of the OPA656. The gain is 0dB.

[0168] Figure 17 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 2 , Figure 17 This is the schematic diagram of the second amplification link. The amplifying element in the second amplification link is LSK389-ADA4897. The small signal input that needs to be amplified is pins 4 and 8 of LSK389, and the signal output is pins 1 and 9 of ADA4897. The gain is 20dB.

[0169] Figure 18 This is a circuit diagram of a selective amplification link provided in an embodiment of this application. Figure 3 , Figure 18 This is a schematic diagram of the first switching switch. The third-stage amplification link switching switch is specifically configured as a relay, which is used to control whether the amplification link uses a large signal input or a small signal input.

[0170] When the common pins 3 and 6 of relay K24 are connected to pins 4 and 5 respectively, the selected amplification link branch is LSK389-ADA4897, which is the small signal amplification link; when the common pins 3 and 6 of relay K24 are connected to pins 2 and 7 respectively, the selected amplification link branch is OPA656, which is the large signal amplification link.

[0171] The two selective amplification links have different base gains, which can avoid the inability of a single link to cover the range of extremely weak to relatively weak signals, effectively increasing the signal processing range.

[0172] Figure 19 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 1 , Figure 19 This is the output waveform after amplification of 0dB for a 100kHz, 1Vpp sine wave input when the second amplification link is OPA656 (large signal). Figure 20 This is a schematic diagram illustrating the effect of selecting an amplified link according to an embodiment of this application. Figure 2 , Figure 20 The output waveform is when the second amplification link is LSK389-ADA4897 (small signal), the input is a 100KHz, 10mVpp sine wave, and the amplification is 20dB.

[0173] In one alternative embodiment, the multi-stage amplification link includes a third-stage amplification link, a fourth-stage amplification link, and a fifth-stage amplification link.

[0174] Figure 21 This is a circuit diagram of a third-stage amplification link provided in an embodiment of this application. The third-stage amplification link includes a third relay, a third amplifying element, and a third peripheral resistor structure. The third relay is used to receive and, based on a third amplification control signal, connect different third peripheral resistor structures to the third amplifying element, so that the third amplifying element amplifies the signal by different factors.

[0175] The third amplifying element in this application is configured as a high-speed differential operational amplifier ADA4932. The signal input is pins 2 and 3 of ADA4932, and the signal output is pins 10 and 11 of ADA4932. The amplification factor is different, that is, the gain is 0dB or 20dB.

[0176] Pins 1-4 of the ADA4932 are the -FB negative feedback terminal, +IN non-inverting input terminal, -IN inverting input terminal, and +FB positive feedback terminal, respectively. Pins 10-12 are the +OUT positive output terminal, -OUT negative output terminal, and n_PD low-power mode enable terminal, respectively.

[0177] The third relay K27 is used to switch the gain between 0dB and 20dB. When the common pins 3 and 6 of relay K27 are connected to pins 2 and 7 respectively, the feedback resistors of the third-stage amplifier link are R691 and R662 in the figure, and the input resistors are R683, R687, R688 and R689. Therefore, the gain is (R683 / / R687+R688+R689) / (R691+R662) = (1M / / 1K+1.5K+130Ω) / (100Ω+100Ω) = 20dB.

[0178] When the common pins 3 and 6 of relay K27 are connected to pins 4 and 5 respectively, the feedback resistors of the third-stage amplification link are R691, R662, R683 and R687 in the figure, and the input resistors are R688 and R689. Therefore, the gain is (R688+R689) / (R691+R662+R683 / / R687) = (1.5K+130Ω) / (100Ω+100Ω+1M / / 1K) = 0dB.

[0179] Figure 22 This is a schematic diagram illustrating the effect of a third-level amplification link provided in an embodiment of this application. Figure 1 , Figure 22 It is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the third-level link gain is 0dB. Figure 23 This is a schematic diagram illustrating the effect of a third-level amplification link provided in an embodiment of this application. Figure 2 , Figure 23 This is the output waveform after amplifying a 100kHz, 10mVpp sine wave by 20dB when the third-level link gain is 20dB.

[0180] Figure 24 This is a circuit diagram of a fourth-stage amplification link provided in an embodiment of this application. The fourth-stage amplification link includes a fourth relay, a fourth amplifying element, and a fourth peripheral resistor structure. The fourth relay is used to receive and, based on the fourth amplification control signal, connect different fourth peripheral resistor structures to the fourth amplifying element, so that the fourth amplifying element amplifies the signal by different factors.

[0181] The fourth amplifying element in this application is configured as a high-speed differential operational amplifier ADA4932, with signal inputs at pins 10 and 11 of ADA4932, signal outputs at pins 3 and 6 of relay K26, and a gain of 0dB or -10dB.

[0182] When the common pins 3 and 6 of relay K26 are connected to pins 4 and 5 respectively, the feedback resistor of the fourth-stage amplifier link is R690 in the figure, the input resistor is R710 in the figure, and the gain is R710 / R690=100Ω / 100Ω=0dB.

[0183] When the common pins 3 and 6 of relay K26 are connected to pins 2 and 7 respectively, the feedback resistor of the fourth-stage amplifier link is R694 in the figure, the input resistor is R710 in the figure, and the gain is R710 / R694=100Ω / 267Ω=-10dB.

[0184] Figure 25 This is a schematic diagram illustrating the effect of a fourth-level amplification link provided in an embodiment of this application. Figure 1 , Figure 25This is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the fourth-level link gain is 0dB. Figure 26 This is a schematic diagram illustrating the effect of a fourth-level amplification link provided in an embodiment of this application. Figure 2 , Figure 26 This is the output waveform after amplifying a 100kHz, 1Vpp sine wave by -10dB when the fourth-level link gain is -10dB.

[0185] Figure 27 This is a circuit diagram of a fifth-stage amplification link provided in an embodiment of this application. The fifth-stage amplification link includes a fifth relay, a fifth amplifying element, and a fifth peripheral resistor structure. The fifth relay is used to receive and, based on the fifth amplification control signal, connect different fifth peripheral resistor structures to the fifth amplifying element, so that the fifth amplifying element amplifies the signal by different factors.

[0186] The fifth amplifying element in this application is configured as the input amplification link schematic of the high-speed differential operational amplifier ADA4932. The signal input is pins 2 and 3 of the ADA4932, and the signal output is pins 10 and 11 of the ADA4932. The gain is 0dB or 20dB.

[0187] The fifth relay K28 is used to switch the gain between 0dB and 20dB. When the common pins 3 and 6 of relay K28 are connected to pins 2 and 7 respectively, the feedback resistors of the fifth stage amplifier link are R710 and R690 in the figure, the input resistors are R711 and R712 in the figure, and the gain is (R711+R712) / (R710+R690) = (909Ω+909Ω) / (100Ω+100Ω) = 20dB.

[0188] When the common pins 3 and 6 of relay K28 are connected to pins 4 and 5 respectively, the feedback resistors of the fifth-stage amplifier link are R711, R710 and R690 in the figure, the input resistor is R712 in the figure, and the gain is R712 / (R711+R710+R690)=909Ω / (909Ω+100Ω+100Ω)=0dB.

[0189] Figure 28 This is a schematic diagram illustrating the effect of a fifth-level amplification link provided in an embodiment of this application. Figure 1 , Figure 28 This is the output waveform after amplifying a 100kHz, 1Vpp sine wave by 0dB when the fifth-level link gain is 0dB. Figure 29 This is a schematic diagram illustrating the effect of a fifth-level amplification link provided in an embodiment of this application. Figure 2 , Figure 29 This is the output waveform after amplifying a 100kHz, 10mVpp sine wave by 20dB when the fifth-level link gain is 20dB.

[0190] By selecting the combination of the amplification link and the three-stage amplification link, eight different gain levels can be achieved, including the following:

[0191] 3V setting: Select the gain of the first amplification link as 0dB, the gain of the third amplification link as 0dB, the gain of the fourth amplification link as -10dB, the gain of the fifth amplification link as 0dB, and the total gain as 0dB + 0dB - 10dB + 0dB = -10dB.

[0192] 1V setting: Select the gain of the amplification link as 0dB, the gain of the third amplification link as 0dB, the gain of the fourth amplification link as 0dB, the gain of the fifth amplification link as 0dB, and the total gain as 0dB+0dB+0dB+0dB=0dB.

[0193] 300mV range: Select the gain of the first amplification link as 0dB, the gain of the third amplification link as 20dB, the gain of the fourth amplification link as -10dB, and the gain of the fifth amplification link as 0dB. The total gain is 0dB + 20dB - 10dB + 0dB = 10dB.

[0194] 100mV range: Select the gain of the first amplification link as 0dB, the gain of the third amplification link as 20dB, the gain of the fourth amplification link as 0dB, the gain of the fifth amplification link as 0dB, and the total gain as 0dB + 20dB + 0dB + 0dB = 20dB.

[0195] 30mV range: Select a gain of 20dB for the first amplification stage, a gain of 20dB for the third amplification stage, a gain of -10dB for the fourth amplification stage, and a gain of 0dB for the fifth amplification stage. The total gain is 20dB + 20dB - 10dB + 0dB = 30dB.

[0196] 10mV range: Select a gain of 20dB for the first amplification stage, a gain of 20dB for the third amplification stage, a gain of 0dB for the fourth amplification stage, a gain of 0dB for the fifth amplification stage, and a total gain of 20dB + 20dB + 0dB + 0dB = 40dB.

[0197] 3mV range: Select a gain of 20dB for the first amplification stage, a gain of 20dB for the third amplification stage, a gain of -10dB for the fourth amplification stage, and a gain of 0dB for the fifth amplification stage. The total gain is 20dB + 20dB - 10dB + 20dB = 50dB.

[0198] 1mV range: Select a gain of 20dB for the first amplification stage, a gain of 20dB for the third amplification stage, a gain of 0dB for the fourth amplification stage, and a gain of 20dB for the fifth amplification stage. The total gain is 20dB + 20dB + 0dB + 20dB = 60dB.

[0199] Figure 30 This is a schematic diagram of a signal processing unit, a second clock synchronization unit, and a first analog-to-digital converter structure provided in an embodiment of this application.

[0200] like Figure 30 As shown in the embodiments of this application, the first analog-to-digital conversion structure includes multiple parallel first analog-to-digital converters, specifically four parallel first analog-to-digital converters.

[0201] Similar to the first clock synchronization unit, the second clock synchronization unit is connected to multiple first analog-to-digital converters and is used to output multiple equally spaced synchronization clock signals to the multiple first analog-to-digital converters respectively. The multiple first analog-to-digital converters are used to convert the amplified first voltage signal or second voltage signal into multiple digital signals based on the multiple equally spaced synchronization clock signals and output them, and finally output them to the signal processing module for subsequent signal processing.

[0202] The four parallel analog-to-digital converters are synchronized by the second clock synchronization unit, allowing the four ADCs to sample the same voltage signal in a fixed sequence. The final sampling rate is four times that of a single ADC, while retaining the resolution of a single ADC. This improves the ability to acquire high-frequency voltage signals and ensures the accuracy of identifying weak voltage changes, thus meeting the wide-band, weak signal detection requirements of balanced bridge circuits.

[0203] In one possible embodiment, the first clock synchronization unit of the synchronous DAC and the first clock synchronization unit of the synchronous ADC of this application use different clock sources. In this case, the signal generation part and the signal acquisition and processing part use independent clock sources to flexibly adapt to the different performance requirements of the two parts.

[0204] Specifically, designing the clock sources for the DAC and ADC separately allows for the selection of the optimal clock scheme to meet the high bandwidth and low jitter requirements of the DAC, as well as the high sampling rate and high resolution requirements of the ADC, thus adapting to the differentiated performance requirements in complex scenarios.

[0205] Furthermore, if one clock source fails, only the corresponding module is affected, while the other module can continue to operate, resulting in higher system fault tolerance and making it suitable for industrial-grade measurement equipment with stringent reliability requirements. If a DAC or ADC module needs to be upgraded later, the parameters of the corresponding clock source can be adjusted independently without modifying the entire clock link, adapting to the iterative upgrade needs of the equipment.

[0206] In another possible embodiment, the first clock synchronization unit of the synchronous DAC and the first clock synchronization unit of the synchronous ADC of this application use the same clock source.

[0207] In another possible embodiment, the first analog-to-digital converter structure is connected to the first clock synchronization unit 13, and the second analog-to-digital converter structure is also connected to the first clock synchronization unit 13 to receive the synchronization clock signal.

[0208] By using the clock tree structure of the first clock synchronization unit 13, the multiple first digital-to-analog conversion units 14, multiple second digital-to-analog conversion units 15, the first analog-to-digital conversion structure and the second analog-to-digital conversion structure in this application are synchronized in a unified clock manner, thereby eliminating the impact of timing deviation on impedance measurement accuracy from the root and ensuring the consistency and accuracy of the entire link of dual signal source driving, imbalance detection and impedance calculation.

[0209] First, the multiple first digital-to-analog conversion units 14 and multiple second digital-to-analog conversion units 15 after clock synchronization ensure high-precision synchronization of the two signal sources, which is the basis for bridge balance. The sampling clock frequencies of the two sets of conversion modules are completely consistent and the phases are aligned at equal intervals to avoid frequency offset or phase difference drift of the two signal sources and avoid false imbalance caused by signal asynchrony.

[0210] Secondly, with the first analog-to-digital converter structure for acquiring the impedance voltage under test and the second analog-to-digital converter structure for the zero-position detector sharing a synchronous clock with the digital-to-analog converter unit, a time difference between "signal generation" and "signal acquisition" is avoided, which would cause the acquired voltage / current signal to mismatch with the actual signal. During multiple measurements, the timing relationship of all modules remains consistent, avoiding the dispersion of measurement results due to clock drift, improving the measurement repeatability of the system, and meeting the consistency requirements of precision impedance measurement.

[0211] In this scenario, the DAC responsible for signal generation and the ADC responsible for signal acquisition have clocks from the same source, and their sampling and conversion times are strictly aligned. This can completely eliminate the time difference between signal generation and signal acquisition, avoid signal mismatch errors caused by timing misalignment, and adapt to the application's scenario where extremely high measurement accuracy is required for weak impedance.

[0212] Moreover, the system has low complexity, no need to design an additional clock synchronization calibration mechanism, simpler hardware links, and only needs to ensure the stability of a single clock source during later debugging. The phase and frequency drift trends of the clocks from the same source are consistent. When the environment (such as temperature and power fluctuations) changes, the timing relationship between the DAC and ADC can still remain stable, reducing the impact of environmental interference on the measurement results, with stronger anti-interference ability, lower operation and maintenance costs, and is suitable for standardized equipment for mass production.

[0213] The following describes a specific embodiment of an impedance measurement method according to this application. Figure 31 This is a flowchart illustrating an impedance measurement method provided in an embodiment of this application. This specification provides the method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive methods, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual system or server product execution, the method can be executed sequentially according to the embodiments or drawings, or in parallel (e.g., in a parallel processor or multi-threaded processing environment). Specifically, as shown... Figure 31 As shown, this method, applied to an impedance measurement device, may include:

[0214] S201: Determine the reference resistance value of the range resistance module based on the impedance to be measured.

[0215] In one possible embodiment, based on the estimated range of the impedance to be measured, a resistor with a magnitude close to that of the impedance to be measured is selected as the reference resistor Rr from among a plurality of reference resistors with different resistance values ​​in the range resistor module.

[0216] By performing the above operations, the current flowing through the impedance to be measured and the reference resistor are on the same order of magnitude, resulting in higher detection accuracy of subsequent unbalanced current and voltage signals and avoiding signal distortion caused by range mismatch.

[0217] S202: Use the unbalance detection module to obtain the unbalanced current between the impedance to be measured and the range resistance module.

[0218] After the dual signal sources drive the impedance under test and the reference resistor to form a path, since the resistance value of the impedance under test is unknown, the current in the two paths will inevitably be different, that is, unbalanced current.

[0219] S203: If the unbalanced current is not zero, generate an adjustment signal based on the unbalanced current, adjust the second signal source based on the adjustment signal, and obtain the adjusted unbalanced current; or; if the unbalanced current is zero, obtain the first voltage value of the impedance to be measured and the second voltage value of the range resistor module.

[0220] If the unbalanced current is not zero, an adjustment signal is generated to fine-tune the amplitude or phase of the second signal source. The unbalanced current after adjustment is repeatedly detected until the current approaches zero, that is, the bridge reaches balance.

[0221] If the unbalanced current is zero, the bridge is balanced. The accurate voltage value Vx across the impedance to be measured and the voltage value Vr across the range resistor are directly acquired through the voltage measurement unit of the measurement module. At this time, the noise and error of the voltage signal are minimized.

[0222] S204: Determine the impedance value of the impedance to be measured based on the first voltage value and the second voltage value.

[0223] When the bridge circuit is balanced, the current Ix flowing through the impedance to be measured is equal to the current Ir flowing through the reference resistor. The impedance value Zx of the impedance to be measured can be calculated using the first voltage value Vx and the second voltage value Vr.

[0224] This application also provides an impedance measuring device. Figure 32 This is a schematic diagram of the structure of an impedance measuring device provided in an embodiment of this application, as shown below. Figure 32 As shown, the device 300 includes:

[0225] The first determining module 301 is used to determine the reference resistance value of the range resistance module based on the impedance to be measured.

[0226] The first acquisition module 302 is used to acquire the unbalanced current between the impedance to be measured and the range resistance module using the unbalance detection module.

[0227] The second acquisition module 303 is used to generate an adjustment signal based on the unbalanced current if the unbalanced current is not zero, adjust the second signal source based on the adjustment signal, and acquire the adjusted unbalanced current; or; if the unbalanced current is zero, acquire the first voltage value of the impedance to be measured and the second voltage value of the range resistor module.

[0228] The second determining module 304 is used to determine the impedance value of the impedance to be measured based on the first voltage value and the second voltage value.

[0229] The apparatus and method embodiments in this application are based on the same application concept.

[0230] The methods and embodiments provided in this application can be executed on a computer terminal, server, or similar computing device. Taking running on a server as an example, Figure 33 This is a hardware structure block diagram of a server for an impedance measurement method provided in an embodiment of this application. Figure 33As shown, the server 400 can vary significantly due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 410 (CPUs 410 may include, but are not limited to, microprocessors such as MCUs or programmable logic devices such as FPGAs), a memory 430 for storing data, and one or more storage media 420 (e.g., one or more mass storage devices) for storing application programs 423 or data 422. The memory 430 and storage media 420 may be temporary or persistent storage. The program stored in the storage media 420 may include one or more modules, each module may include a series of instruction operations on the server. Furthermore, the CPU 410 may be configured to communicate with the storage media 420 and execute the series of instruction operations stored in the storage media 420 on the server 400. Server 400 may also include one or more power supplies 460, one or more wired or wireless network interfaces 450, one or more input / output interfaces 440, and / or one or more operating systems 421, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0231] The input / output interface 440 can be used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of server 400. In one example, the input / output interface 440 includes a network interface controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the input / output interface 440 may be a radio frequency (RF) module used for wireless communication with the Internet.

[0232] Those skilled in the art will understand that Figure 33 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, server 400 may also include... Figure 33 The more or fewer components shown, or having the same Figure 33 The different configurations shown.

[0233] This application provides an electronic device, which includes a processor and a memory. The memory stores at least one instruction, at least one program, code set, or instruction set. The processor loads and executes the at least one instruction, at least one program, code set, or instruction set to implement the above-described data processing method.

[0234] Embodiments of this application also provide a computer-readable storage medium, which can be disposed in a server to store at least one instruction, at least one program, code set, or instruction set related to implementing an impedance measurement method in the method embodiment. The at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the processor to implement the impedance measurement method described above.

[0235] Optionally, in this embodiment, the storage medium may be located at at least one of the multiple network servers in a computer network. Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0236] As can be seen from the embodiments of the impedance measurement method, apparatus, electronic device or storage medium provided in this application, the signal source module 1 with the first clock synchronization unit 13 generates two synchronization signals to drive the impedance under test and the range resistance module, thereby improving the excitation accuracy of the balanced bridge.

[0237] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0238] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0239] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0240] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An impedance measuring device, characterized by, It includes a signal source module, a range resistor module, an imbalance detection module, and a measurement module; The signal source module includes a first signal generating unit, a second signal generating unit, a first clock synchronization unit, multiple first digital-to-analog conversion units, multiple second digital-to-analog conversion units, a first signal output unit, and a second signal output unit; The first clock synchronization unit is connected to the plurality of first digital-to-analog converters and the plurality of second digital-to-analog converters, and is used to output a plurality of equally spaced synchronization clock signals respectively; the plurality of first digital-to-analog converters are used to convert the digital signals output by the first signal generating unit into a plurality of first analog signals based on the synchronization clock signals; the first signal output unit is used to synthesize the plurality of first analog signals into a first signal source; the plurality of second digital-to-analog converters are used to convert the digital signals output by the second signal generating unit into a plurality of second analog signals based on the synchronization clock signals; the second signal output unit is used to synthesize the plurality of second analog signals into a second signal source; The first signal source is connected to the first end of the impedance to be measured, the first end of the range resistor module is connected to the second end of the impedance to be measured, and the second end of the range resistor module is connected to the second signal source. The imbalance detection module is used to adjust the second signal source based on the imbalance current between the impedance to be measured and the range resistor module; The measurement module is used to detect the voltage signal of the impedance to be measured and the range resistor module; The measurement module includes a voltage measurement unit for acquiring a first voltage signal of the impedance to be measured or a second voltage signal of the range resistor module; the voltage measurement unit includes a first analog-to-digital converter structure. The measurement module further includes a signal processing unit, which includes a third signal amplification structure and a second clock synchronization unit; the first analog-to-digital conversion structure includes a plurality of first analog-to-digital converters. The third signal amplification structure is used to amplify the first voltage signal or the second voltage signal by different factors; The second clock synchronization unit is connected to the plurality of first analog-to-digital converters and is used to output a plurality of equally spaced synchronization clock signals to the plurality of first analog-to-digital converters respectively; the plurality of first analog-to-digital converters are used to convert the amplified first voltage signal or the second voltage signal into a plurality of digital signals and output them based on the plurality of equally spaced synchronization clock signals; The first clock synchronization unit and the second clock synchronization unit use the same clock source.

2. An impedance measuring device according to claim 1, characterised in that, The first signal output unit includes a first signal synthesizer and a first signal amplification structure; the input terminal of the first signal synthesizer is connected to the plurality of first digital-to-analog conversion units, and the output terminal is connected to the input terminal of the first signal amplification structure; The second signal output unit includes a second signal synthesizer and a second signal amplification structure; the input terminal of the second signal synthesizer is connected to the plurality of second digital-to-analog conversion units, and the output terminal is connected to the input terminal of the second signal amplification structure.

3. An impedance measuring device according to claim 2, wherein, The first signal amplification structure includes a first-stage amplification link and a second-stage amplification link; The first-stage amplification link includes a first relay, a first amplification element, and a first peripheral resistor; the first relay is used to receive and connect different first peripheral resistors to the first amplification element based on a first amplification control signal, so that the first amplification element amplifies the signal by different factors. The second-stage amplification link includes a second relay, a second amplification element, and a second external resistor; the second relay is used to receive and connect different second external resistors to the second amplification element based on the second amplification control signal, so that the second amplification element amplifies the signal by different factors.

4. An impedance measuring device according to claim 3, characterized in that, The plurality of first digital-to-analog conversion units are configured as four first digital-to-analog converters; the plurality of second digital-to-analog conversion units are configured as four second digital-to-analog converters; The first signal output unit is used to synthesize the analog signals output by the four first digital-to-analog converters into the first signal source; the second signal output unit is used to synthesize the analog signals output by the four second digital-to-analog converters into the second signal source.

5. An impedance measuring device according to claim 2, characterized in that, The first signal output unit further includes a first signal buffer structure; the input terminal of the first signal buffer structure is connected to the output terminal of the first signal amplification structure, and the output terminal is connected to the first terminal of the impedance to be measured. The second signal output unit further includes a second signal buffer structure; the input end of the second signal buffer structure is connected to the output end of the second signal amplification structure, and the output end is connected to the second end of the range resistor module.

6. An impedance measuring device according to claim 1, characterized in that, The first clock synchronization unit includes a clock input structure and a clock tree structure; The clock tree structure includes a clock tree root and a multi-level fan-out buffer; each level of the fan-out buffer includes deterministic time error and uncertain time error; the clock tree root receives the original clock signal input from the clock input structure, inputs it into the multi-level fan-out buffer, and forms multiple synchronous clock signals, which are respectively connected to the multiple first digital-to-analog converters and the multiple second digital-to-analog converters.

7. An impedance measuring device according to claim 1, characterized in that, The range resistor module includes multiple reference resistors with different resistance values ​​and multiple switching switches. Each reference resistor is connected in series with the switching switch. Multiple sets of series-connected reference resistors are connected in parallel with the switching switches.

8. An impedance measuring device according to claim 1, characterized in that, The measurement module includes a switching element; The first input terminal of the switching element is connected between the impedance to be measured and the first signal source, the second input terminal is connected between the range resistor module and the second signal source, and the output terminal is connected to the voltage measurement unit, for acquiring the first voltage signal of the impedance to be measured or the second voltage signal of the range resistor module based on the switching control signal.

9. An impedance measuring device according to claim 8, characterized in that, The voltage measurement unit includes a first range adjustment structure and a first buffer structure; the input terminal of the first range adjustment structure is connected to the output terminal of the switching element, and the output terminal is connected to the input terminal of the first buffer structure; the output terminal of the first buffer structure is connected to the first analog-to-digital conversion structure.

10. An impedance measurement method, characterized in that, An impedance measuring device according to any one of claims 1-9, comprising: The reference resistance value of the range resistance module is determined based on the impedance to be measured; The unbalanced current between the impedance to be measured and the range resistance module is obtained using the unbalanced detection module. If the unbalanced current is not zero, an adjustment signal is generated based on the unbalanced current, and the second signal source is adjusted based on the adjustment signal to obtain the adjusted unbalanced current; or; if the unbalanced current is zero, the first voltage value of the impedance to be measured and the second voltage value of the range resistor module are obtained. The impedance value of the impedance to be measured is determined based on the first voltage value and the second voltage value.

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