Closed-loop fluxgate current sensor system based on sampling and holding

Abstract

The invention relates to the technical field of magnetic variable measurement, and discloses a closed-loop fluxgate current sensor system based on sampling and holding, which is characterized in that a duty ratio sampling and holding unit is connected with a self-excited oscillation unit, receives CLK and SW signals of the self-excited oscillation unit, converts a duty ratio into voltage through a sampling and holding circuit, outputs duty ratio deviation voltage, and transmits the duty ratio deviation voltage to the self-excited oscillation unit; the duty ratio sampling and holding unit comprises an analog switch, and a high-level time acquisition access and a low-level time acquisition access which are symmetrically designed and controlled by the analog switch; the self-excited oscillation unit is connected with the excitation winding of the magnetic core to generate symmetrical excitation driving signals; the integration unit is connected with the duty ratio sampling and holding unit and the feedback compensation unit, carries out integration on the deviation voltage and outputs an integration signal; and the feedback compensation unit is connected with the compensation winding, outputs the integrated signal and feeds back the integrated signal to the compensation winding to form closed-loop feedback control. The problems of limited bandwidth and large output ripple in the prior art are solved, and the purposes of reducing the cost, improving the signal-to-noise ratio and increasing the bandwidth are achieved.

Description

Technical Field

[0001] This invention relates to the field of magnetic variable measurement technology, and in particular to a closed-loop fluxgate current sensor system based on sample-and-hold. Background Technology

[0002] The PAC integrated chip approach has drawbacks. PAC integrated chips are not widely available, resulting in high procurement costs. While the duty cycle measurement range of a PAC chip is 100%, the duty cycle variation within the measurement range of a fluxgate sensor is typically within 3%. This leads to a very small error signal amplitude and low signal-to-noise ratio at the PAC output, which is detrimental to subsequent feedback regulation. In practical applications, increasing the integrating capacitor is necessary to maintain stability, which reduces the overall bandwidth. The digital approach using a microcontroller and DAC is also problematic. Both the microcontroller and DAC are expensive, and the microcontroller requires programming during production, further increasing manufacturing costs.

[0003] For example, Chinese patent CN115112937A discloses a fluxgate current sensor circuit, providing the following technical solution: an excitation circuit, an excitation winding L1, a compensation winding L2, an error amplifier circuit, a low-pass filter circuit, and a sampling circuit. The excitation winding L1 is connected between the two arms of the excitation circuit to detect the excitation current. The excitation current is fed back to the compensation winding L2 after passing through the error amplifier circuit, the low-pass filter circuit, and the sampling circuit. By measuring the current flowing through the compensation winding L2, the value of the measured current can be determined. This invention uses a superior excitation self-excited oscillation scheme for detecting small currents, resulting in higher detection accuracy. However, while the above-mentioned fluxgate current sensor circuit improves zero-point deviation by uniformly controlling the excitation peak value with a reference voltage, it still relies on traditional error amplification and filtering, leading to limited bandwidth, large output ripple, and the need for a dedicated chip, resulting in higher cost. Summary of the Invention

[0004] This invention solves the problems of high cost, low signal-to-noise ratio, limited bandwidth, and large output ripple in the prior art. It proposes a closed-loop fluxgate current sensor system based on sample-and-hold, which achieves the goals of reducing cost, improving signal-to-noise ratio, increasing bandwidth, and reducing output ripple.

[0005] Furthermore, this invention achieves high signal-to-noise ratio, direct extraction, and stable holding of error signals through a pure analog duty cycle sampling and holding circuit, using common operational amplifiers and analog switches as the core. This not only significantly improves the bandwidth accuracy and output stability of the sensor, but also reduces the dependence on dedicated chips or digital solutions. While ensuring excellent dynamic performance, it greatly reduces material and production costs, and has greater practicality and industrialization advantages.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A sample-and-hold based closed-loop fluxgate current sensor system includes: The duty cycle sampling and holding unit is connected to the self-excited oscillation unit and receives its CLK and SW signals. It converts the duty cycle into voltage through the sampling and holding circuit and outputs the duty cycle deviation voltage. The duty cycle sampling and holding unit includes an analog switch and its symmetrically designed high-level time acquisition path and low-level time acquisition path. The self-excited oscillation unit is connected to the excitation winding of the magnetic core to generate a symmetrical excitation drive signal. The integration unit is connected to the duty cycle sampling and holding unit and the feedback compensation unit to integrate the deviation voltage and output the integrated signal. The feedback compensation unit is connected to the compensation winding, outputs the integrated signal, and feeds it back to the compensation winding to form a closed-loop feedback control.

[0007] By employing a duty cycle sampling and holding unit to directly convert the duty cycle into voltage deviation, combined with integral and feedback control, the system bandwidth and output accuracy are improved. At the same time, a pure analog scheme is used to reduce costs and isolate drive spike interference, ensuring ultra-low ripple output.

[0008] Preferably, the duty cycle sampling and holding unit includes: pin 10 of analog switch U25B receiving the SW signal, pin 7 connected to the high-level time acquisition path, pin 9 connected to the low-level time acquisition path; and pin 8 connected to VCC via R33.

[0009] The duty cycle sampling and holding unit uses analog switches and resistors to achieve symmetrical high-level and low-level time acquisition, ensuring the accuracy and reliability of duty cycle conversion and providing a stable voltage signal for subsequent processing.

[0010] Preferably, the high-level time acquisition path includes AND gates U33 and U34 for receiving signals from the self-excited oscillation unit CLK and SW, and the low-level time acquisition path includes AND gates U24 and U25 for receiving signals from the self-excited oscillation unit CLK and SW; the SW signal is input to pin 1 of U24 and U25, and the SW signal is input to pin 1 of U33 and U34 after passing through voltage inverter U32; the CLK signal is input to pin 2 of U25 and U34, and the CLK signal is input to pin 2 of U33 and U24 after passing through voltage inverter U35.

[0011] By processing the CLK and SW signals using logic gates and voltage inverters, timing control of the high-level and low-level acquisition paths is achieved, ensuring that the sample-and-hold circuit can accurately capture duty cycle information, thereby improving measurement accuracy and system stability.

[0012] Preferably, in the high-level time acquisition path, the output terminal of U33 is connected to the gate of NMOS transistor Q5, and the drain of Q5 is connected to the input terminal of operational amplifier U29, pin 7 of U28B, and C15 through current-limiting resistor R34; the output terminal of U34 is connected to pin 10 of analog switch U30B, pin 7 of U30B is connected to C16 and the input terminal of operational amplifier U31 through resistor R35, and pin 8 is connected to the output terminal of U29.

[0013] The high-level time acquisition path uses NMOS transistors, operational amplifiers, capacitors, and analog switches to achieve charging and holding functions, converting the high-level time into a stable voltage, avoiding noise interference, and improving the signal-to-noise ratio.

[0014] Preferably, in the low-level time acquisition path, the output terminal of U24 is connected to the gate of NMOS transistor Q4, and the drain of Q5 is connected to the input terminal of operational amplifier U21, pin 9 of U28B, and C11 through current-limiting resistor R26; the output terminal of U25 is connected to pin 10 of analog switch U22B, pin 7 of U22B is connected to C12 and the input terminal of operational amplifier U23 through resistor R27, and pin 8 is connected to the output terminal of U21.

[0015] The low-level time acquisition path and the high-level path are symmetrically designed to ensure accurate acquisition and retention of the low-level time, thereby fully realizing duty cycle sampling and improving the symmetry and overall accuracy of the sensor.

[0016] Preferably, the output terminals of U31 and U23 are connected to the input terminal of operational amplifier U27 in the integration unit via resistors R29 and R28, respectively.

[0017] The output voltage deviation of the duty cycle sampling and holding unit is sent to the integrator unit, and a control signal is generated through integration processing to achieve closed-loop feedback regulation, which helps to stabilize the system output and respond quickly to current changes.

[0018] Preferably, the output terminals of U31 and U23 are connected to the input terminal of operational amplifier U26 in the signal amplification unit through resistors R37 and R31, respectively. The output terminal of U26 is connected to the input terminal of operational amplifier U27 in the integration unit through R28. The input terminal of U27 is also connected to VREF through R29.

[0019] A signal amplification unit was added to amplify the deviation voltage before integration, which improved the signal-to-noise ratio and integration speed, thereby enhancing the system bandwidth and response performance. At the same time, the output stability was ensured by using the reference voltage VREF.

[0020] Preferably, in the high-level time acquisition path, the self-excited oscillation unit triggers SW to flip once at the positive edge of CLK. When a positive pulse arrives at CLK, SW changes from low level to high level, the outputs of U33 and U34 remain low level, Q5 is turned off, pin 8 of U28B is connected to pin 7, and the power supply charges C15 through R33 to accumulate the high-level time of SW; pin 8 of U30B is connected to pin 9, pin 7 is disconnected from pin 8, C16 keeps its voltage unchanged, and operational amplifier U31 maintains the voltage of C16 to drive the output, thus achieving the previous voltage holding.

[0021] High-level time acquisition converts time into voltage through a charging and holding mechanism, isolates drive spikes, and outputs a stable voltage, thereby improving system accuracy and anti-interference capability.

[0022] Preferably, in the high-level time acquisition path, when the CLK of the self-excited oscillation unit receives another positive pulse, SW changes from high level to low level. U28B controls pins 8 and 9 to connect and pin 7 to disconnect. The voltage of C15 stores the high-level duration of SW. When CLK maintains a high-level pulse width, U34 outputs high, controlling pins 8 and 7 of U30B to connect, and the voltage of capacitor C16 is refreshed to the value of C15. When CLK returns to low level, U34 outputs low, U30B switches off, C16 re-enters the holding state, U33 outputs high, controlling Q5 to conduct, discharging the current in C15 through the current-limiting resistor R34, preparing for the high-level time acquisition of SW in the next cycle.

[0023] Voltage refresh and capacitor discharge are implemented to ensure that accurate voltage values ​​are updated and maintained in each cycle, preparing for continuous measurement and improving system dynamic response and measurement consistency.

[0024] Preferably, the operating timing of the low-level time acquisition path is opposite to that of the high-level time acquisition path; in the feedback compensation unit, one end of the compensation winding is connected to VREF, and the other end is connected to the output of operational amplifier U36 through R38; when the duty cycle is not equal to 50%, the outputs of the high-level time acquisition path and the low-level time acquisition path are inconsistent. After passing through the integration unit, the output control voltage drives the compensation winding until the duty cycle is restored to 50%. At this time, the output voltage of the integration unit is proportional to the magnitude of the measured current and the total impedance of R38 and the compensation winding.

[0025] By using symmetrical timing and feedback compensation, the duty cycle deviation is automatically detected and corrected, restoring the system to balance. The output voltage is linearly related to the measured current, achieving high-precision current measurement and closed-loop stability.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows.

[0027] 1. This invention uses a pure analog architecture duty cycle sample-and-hold unit to replace the traditional PAC or digital solution, significantly reducing system cost. By using common operational amplifiers and analog switches as discrete components, it avoids purchasing dedicated integrated chips or microcontrollers combined with DACs, resulting in lower material costs, more economical and simpler overall manufacturing, and facilitating large-scale production and application.

[0028] 2. This invention directly extracts the duty cycle deviation voltage through a symmetrical sample-and-hold path, significantly improving the signal-to-noise ratio and making the error signal more stable and clear. Deviation output is completed in real time each cycle without the need for additional filtering, thus effectively improving system bandwidth and response speed. Simultaneously, feedback isolation technology suppresses drive spikes, achieving extremely low output voltage ripple, and significantly improving measurement accuracy and stability.

[0029] 3. This invention utilizes a real-time sample-and-hold mechanism with duty cycle to directly extract and output the error voltage in each cycle, eliminating the need for subsequent filtering stages required in traditional PAC schemes, thereby significantly reducing signal processing delay. The stable DC deviation signal allows for the use of smaller integrating capacitors in the subsequent integration stage, coupled with preamplification, greatly improving the system's response speed and closed-loop regulation bandwidth, enabling it to better adapt to the measurement requirements of rapidly changing dynamic currents. Attached Figure Description

[0030] Figure 1 This is a system block diagram of a closed-loop fluxgate current sensor system based on sample-and-hold according to the present invention.

[0031] Figure 2 This is a circuit diagram of the duty cycle sampling and holding unit in one embodiment of a closed-loop fluxgate current sensor system based on sampling and holding according to the present invention.

[0032] Figure 3 This is a circuit diagram of the duty cycle sampling and holding unit in another embodiment of a closed-loop fluxgate current sensor system based on sampling and holding according to the present invention.

[0033] Figure 4 This is a circuit diagram of the self-excited oscillation unit of a closed-loop fluxgate current sensor system based on sample-and-hold according to the present invention.

[0034] Figure 5 This is a timing diagram of the operation of a closed-loop fluxgate current sensor system based on sample-and-hold according to the present invention. Detailed Implementation

[0035] See Figures 1-5 As shown, a closed-loop fluxgate current sensor system based on sample-and-hold includes: The duty cycle sampling and holding unit is connected to the self-excited oscillation unit and receives its CLK and SW signals. It converts the duty cycle into voltage through the sampling and holding circuit and outputs the duty cycle deviation voltage. The duty cycle sampling and holding unit includes an analog switch and its symmetrically designed high-level time acquisition path and low-level time acquisition path. The self-excited oscillation unit is connected to the excitation winding of the magnetic core to generate a symmetrical excitation drive signal. The integration unit is connected to the duty cycle sampling and holding unit and the feedback compensation unit to integrate the deviation voltage and output the integrated signal. The feedback compensation unit is connected to the compensation winding, outputs the integrated signal, and feeds it back to the compensation winding to form a closed-loop feedback control.

[0036] This invention proposes a novel implementation method for a fluxgate current sensor. Employing a purely analog scheme with discrete components, it offers lower cost, better performance, and easier manufacturing. Like the PAC scheme, this invention directly outputs the error per cycle, inheriting the high bandwidth and low ripple advantages of the PAC scheme. Compared to the PAC scheme, it utilizes commonly used operational amplifiers and analog switches, eliminating the need for expensive DAC chips or microcontrollers, thus reducing costs.

[0037] A higher signal-to-noise ratio is beneficial for increasing bandwidth. If the duty cycle is 48%, the output of this invention is a deviation value of 52%-48%=4%, while the output of the PAC chip is compared with 50%, and only 2% deviation is detected. Furthermore, the voltage noise of the sample-and-hold output of this invention is smaller, which can be amplified to accelerate the integral control response speed and thus increase bandwidth.

[0038] like Figure 1 In one embodiment shown, Figure 1 This is a system block diagram of a closed-loop fluxgate current sensor system based on sample-and-hold according to the present invention. The present invention includes a self-excited oscillation unit, a duty cycle sample-and-hold unit, an integration unit, and a feedback compensation unit.

[0039] The self-excited oscillation unit outputs two signals to the subsequent duty cycle sampling and holding unit. The first is the output CLK of the threshold detection comparator, and the other is the fluxgate flip control signal SW.

[0040] A duty cycle holding unit is used to convert the self-oscillating duty cycle into a deviation voltage output. The high and low levels of the duty cycle signal are respectively subjected to RC charging. At the end of charging, the final voltage is sampled and held; the resulting voltage difference is the duty cycle deviation. Controlling the RC parameters within the approximately linear range yields a larger signal difference. This method produces a stable DC output and also eliminates interference from drive spikes to subsequent stages.

[0041] The integrator unit is used to integrate and feedback the deviation of the duty cycle sampling and holding unit output. Its output voltage is proportional to the total impedance of the compensation circuit and the number of winding turns, and can be directly used as the sensor output.

[0042] The feedback compensation unit contains a voltage follower, which enhances the driving capability of the integrator's output voltage and isolates the driving spikes coupled to the compensation coil. This invention employs a duty cycle sample-and-hold circuit and an operational amplifier follower feedback circuit to isolate the fundamental frequency spikes of the drive winding and the compensation winding, ensuring ultra-low ripple in the Vout output (measuring only 4mV ripple at a 1.2V output voltage range k / , with output jitter less than 0.5%), thus improving output accuracy.

[0043] The duty cycle sample-and-hold circuit performs a comparison output once per cycle, obtaining a stable error signal without filtering, thereby improving system bandwidth. Bandwidths from several hundred hertz to several kHz can be easily achieved based on the circuit parameters.

[0044] like Figure 2 In one embodiment shown, Figure 2 This is a circuit diagram of the duty cycle sampling and holding unit in one embodiment of a closed-loop fluxgate current sensor system based on sampling and holding according to the present invention. The self-excited oscillation unit of the present invention is connected to the excitation winding of the magnetic core and is responsible for generating symmetrical excitation drive signals. This unit outputs two key signals: a clock signal CLK for timing control and a toggle control signal SW reflecting the fluxgate state. These two signals are sent to the duty cycle sampling and holding unit for processing. The duty cycle sampling and holding unit adopts a symmetrical dual-path structure, used to acquire the high-level duration and low-level duration of signal SW respectively, and convert them into corresponding voltage values. This unit includes an analog switch and its control logic. Pin 10 of analog switch U25B receives the SW signal, pin 7 is connected to the high-level time acquisition path, pin 9 is connected to the low-level time acquisition path, and pin 8 is connected to the power supply VCC through resistor R33, thus constructing the basic path for signal distribution and power supply.

[0045] The high-level time acquisition path includes AND gates U33 and U34, while the low-level time acquisition path includes AND gates U24 and U25. Together, they receive and process the CLK and SW signals from the self-excited oscillation unit. Specifically, the SW signal is directly input to pin 1 of U24 and U25, and after being inverted by voltage inverter U32, it is input to pin 1 of U33 and U34. The CLK signal is directly input to pin 2 of U25 and U34, and after being inverted by voltage inverter U35, it is input to pin 2 of U33 and U24. This symmetrical signal input design ensures that the two paths can operate independently and complementaryly at different level stages of the SW signal.

[0046] In the high-level time acquisition path, the output of U33 is connected to the gate of NMOS transistor Q5. The drain of Q5 is connected to the input of operational amplifier U29, pin 7 of analog switch U28B, and capacitor C15 through current-limiting resistor R34. The output of U34 is connected to pin 10 of analog switch U30B. Pin 7 of U30B is connected to capacitor C16 and the input of operational amplifier U31 through resistor R35, and its pin 8 is connected to the output of U29. Correspondingly, in the low-level time acquisition path, the output of U24 is connected to the gate of NMOS transistor Q4. The drain of Q4 is connected to the input of operational amplifier U21, pin 9 of analog switch U28B, and capacitor C11 through current-limiting resistor R26. The output of U25 is connected to pin 10 of analog switch U22B. Pin 7 of U22B is connected to capacitor C12 and the input of operational amplifier U23 through resistor R27, and its pin 8 is connected to the output of U21. The outputs of operational amplifiers U31 and U23 are connected to the input of operational amplifier U27 in the integration unit via resistors R29 and R28, respectively, so as to transmit the voltage deviation signal obtained by sampling and holding to the subsequent integration processing stage.

[0047] The system timing closely revolves around the edges of the CLK signal and the toggle of the SW signal. The self-oscillating unit triggers a toggle of the SW signal at the positive edge of CLK. When a positive pulse appears in CLK, SW transitions from low to high. At this time, AND gates U33 and U34 maintain a low output due to the inverting signal, causing NMOS transistor Q5 to turn off. Analog switch U28B connects its eighth and seventh pins, and the power supply VCC charges capacitor C15 through resistor R33. This charging process accumulates the duration of the high level of SW. Simultaneously, analog switch U30B connects its eighth and ninth pins, while disconnecting pins seventh and eighth. Capacitor C16 remains in a holding state, its voltage remaining constant, and this holding voltage is output by operational amplifier U31, thus maintaining the sampled value from the previous cycle.

[0048] When CLK receives another positive pulse, SW jumps back from high to low. At this time, analog switch U28B switches to connect its eighth and ninth pins while disconnecting its seventh pin, allowing the voltage accumulated on capacitor C15 to be stored. This voltage corresponds to the duration of the high-level phase of the SW signal. During the brief pulse width during which CLK remains high, AND gate U34 outputs a high level, controlling analog switch U30B to connect its eighth and seventh pins, thus updating the voltage on capacitor C16 to the value stored in capacitor C15. Subsequently, when the CLK signal returns to low, the output of U34 goes low, U30B switches off, and capacitor C16 re-enters the voltage holding state. Immediately afterwards, U33 outputs a high level, driving NMOS transistor Q5 to conduct. The charge stored in capacitor C15 is quickly released through current-limiting resistor R34, preparing for the acquisition of the high-level time of SW in the next operating cycle.

[0049] The timing sequence of the low-level acquisition path is completely opposite to that of the high-level acquisition path. It is responsible for performing similar time-to-voltage conversion and hold operations during the low-level period of SW. Through the coordinated operation of these two symmetrical paths, the system can convert the high-level and low-level durations of the SW signal into corresponding analog voltages in each oscillation cycle. When the fluxgate system is in equilibrium, i.e., the duty cycle is 50%, the output voltages of the two paths are equal; once the measured current introduces a disturbance that causes the duty cycle to deviate from 50%, the output voltages of the two paths will deviate.

[0050] The deviation voltage is sent to the integrator unit via resistors R29 and R28. The core operational amplifier U27 of the integrator unit integrates this deviation voltage and outputs a control signal that accumulates over time. This signal is then sent to the feedback compensation unit. The feedback compensation unit contains a voltage follower composed of operational amplifier U36, which enhances the driving capability and isolates interference from the compensation winding. One end of the compensation winding is connected to the reference voltage VREF, and the other end is connected to the output of operational amplifier U36 via resistor R38. The control voltage output from the integrator unit drives the compensation winding through U36, generating a compensation magnetic field opposite to the direction of the measured current, forcing the magnetic core to return to balance, thus restoring the duty cycle of the SW signal to 50%.

[0051] When the system reaches equilibrium through closed-loop regulation, the steady-state voltage output by the integrator is proportional to the magnitude of the measured current flowing through the sensor, and also proportional to the total impedance of the resistor R38 and the compensation winding in the feedback loop. This voltage can then be used as the sensor's final measurement output. This sample-and-hold-based pure analog implementation directly extracts and outputs the error signal within each cycle, eliminating the need for additional digital conversion or complex filtering. This significantly improves the system's response bandwidth and output accuracy. Furthermore, by using discrete components such as general-purpose operational amplifiers and analog switches, it avoids the high cost and manufacturing complexity associated with dedicated PAC chips or microcontroller-DAC solutions, achieving a good balance between performance and cost. The entire system has a clear structure, stable loop, and extremely low output ripple, making it highly suitable for current sensing applications with high requirements for accuracy, bandwidth, and cost.

[0052] In another embodiment, U32 and U35 are voltage inverters that invert the SW and CLK signals. U24, U25, U33, and U34 are AND gates used for sequential logic processing. U28B, U22B, and U30B are analog switches used to control on / off states. U21, U23, U29, and U31 are operational amplifiers operating in follower mode to enhance drive performance.

[0053] The operating logic explains that the self-excited oscillation unit triggers the SW to flip once at the positive edge of CLK; therefore, the CLK signal is also the trigger signal for the sample-and-hold function. (Reference) Figure 4 The workflow is explained by the sequence of events.

[0054] When a positive pulse arrives at CLK, SW changes from low to high. At this time, U33 and U34 maintain a low output level because / SW is low, Q5 is turned off, pin 8 of U28B is connected to pin 7, and the power supply charges C15 through R33 to accumulate the high-level time of SW; pin 8 of U30B is connected to pin 9, disconnecting pin 7 from pin 8, so pin 7 is in a high-impedance state, C16 maintains a constant voltage, and op-amp U31 maintains the voltage of C16 to drive the output, thus achieving the previous voltage hold.

[0055] When another positive pulse arrives at CLK, SW changes from high to low. U28B controls pins 8 and 9 to connect, while pin 7 is disconnected and in a high-impedance state. The voltage of C15 stores the duration of the high-level SW. At this time, / SW is high, and CLK will maintain a high-level pulse width for a period of time. When CLK is high, U34 outputs high to control pins 8 and 7 of U30B to connect, and the voltage of capacitor C16 will be refreshed to the value of C15. After a period of time, CLK returns to low, U34 outputs low, disconnecting the U30B switch, and C16 enters the holding state again. Then, U33 outputs high, controlling Q5 to conduct, discharging the current in C15 through the current-limiting resistor R34, preparing for the acquisition of the high-level SW time in the next cycle.

[0056] The upper part operates with the reverse timing of the lower part, sampling the low-level duration of SW. This converts the high and low level durations of each cycle into corresponding voltage magnitudes. When the duty cycle is not 50%, the two outputs will be inconsistent. After passing through the integrator, the output control voltage drives the compensation winding until the duty cycle returns to 50%. At this point, the output voltage of the integrator is proportional to the magnitude of the current on the side, as well as the impedance of R38 and the total impedance of the compensation winding.

[0057] like Figure 3 In one embodiment shown, Figure 3 This is a circuit diagram of the duty cycle sampling and holding unit in another embodiment of a closed-loop fluxgate current sensor system based on sampling and holding according to the present invention. In this embodiment, since the PAC output still requires a large integrating capacitor after amplification due to its low signal-to-noise ratio, but the sampling and holding output voltage is very stable, an additional stage of signal amplification can be added to make the integration speed faster and improve the overall bandwidth.

[0058] like Figure 4 In one embodiment shown, Figure 4 This is a circuit diagram of the self-excited oscillation unit of a closed-loop fluxgate current sensor system based on sample-and-hold according to the present invention.

[0059] The self-excited oscillation unit plays a core driving role in the system, and its circuit layout exhibits significant symmetry and stable operation. This unit integrates a current sampling resistor R1, which is connected to capacitor C1 and comparator U6B via resistor R4. R4 and C1 together form a low-pass filter structure, effectively suppressing transient interference in the circuit, thus ensuring the overall stability and reliability of the sampled signal. Pin 6 of comparator U6B is equipped with voltage divider resistors R2 and R3, and filter capacitor C2. The other ends of R3 and C2 are connected to ground, while the other end of R2 is connected to the power supply VCC. Resistors R2 and R3 are mainly used to set the current switching point during circuit operation, while capacitor C2 serves to purify power supply VCC noise, providing a more stable and accurate reference level for the switching threshold.

[0060] Pin 5 of U6B is connected to the input pin of U6A. The input of U6A is also connected to resistors R21 and R22, and capacitor C10. The other ends of R22 and C10 are grounded, and the other end of R21 is connected to the power supply VCC. These components are used to set the overcurrent protection threshold of the system. The output signal of U6A is transmitted to the gate of NMOS transistor Q3. The drain of Q3 is further connected to the gate of PMOS transistor U20. The drain of U20 is connected to pin 1 of analog switch U5A and pin 7 of analog switch U5B, respectively. The source of U20 is directly connected to the power supply VCC.

[0061] Pin 7 of U6B is connected to pin 2 of the rising-edge triggered D-type flip-flop U3. Pins 1 and 4 of U3 are connected together to pin 4 of analog switch U5A and pin 10 of U5B, which are the selection control terminals for both. Pin 3 of analog switch U5A is connected to pin 8 of analog switch U5B through the excitation winding L1. Pin 9 of U5B and pin 2 of U5A are connected to one end of the sampling resistor R1, and the other end of R1 is grounded, thus forming a complete current detection circuit.

[0062] This invention features a dual-state monitoring and protection mechanism. During normal operation, the current monitoring unit continuously compares the operating signal with a preset protection threshold. When the current is within a safe range, the drive circuit remains on, ensuring the excitation unit operates normally. Upon detecting an overcurrent, the protection circuit immediately outputs a shutdown signal, cutting off the excitation power supply to prevent equipment damage. More importantly, the system incorporates state recovery logic: after protection is triggered, a voltage clamping design temporarily lowers the protection threshold below the operating threshold, ensuring the circuit can preferentially return to normal oscillation after the fault is cleared, thus improving system reliability and self-recovery capability.

[0063] Secondly, by monitoring the excitation current in real time, a switching signal is triggered by the state control unit when the set reversal threshold is reached. This signal drives a bidirectional switching switch to alternately change the flow path of the excitation current, thereby achieving a periodic reversal of the excitation magnetic field direction. This symmetrical current path switching mechanism ensures that the positive and negative half-cycles of the excitation process are highly consistent, thus generating a stable and symmetrical square wave oscillation signal, providing an accurate duty cycle information carrier for subsequent current detection.

[0064] In summary, this invention discloses a closed-loop fluxgate current sensor system based on sample-and-hold, which adopts a purely analog discrete device scheme to achieve high-performance current detection at low cost. The system mainly consists of a self-excited oscillation unit, a duty cycle sample-and-hold unit, an integrator unit, and a feedback compensation unit. The self-excited oscillation unit drives the magnetic core excitation winding to generate a symmetrical square wave signal and outputs a clock signal CLK and a state transition signal SW. The duty cycle sample-and-hold unit is the core innovation, adopting a symmetrical dual-path structure to RC charge and sample the high and low levels of the SW signal, converting them into a DC voltage proportional to the duty cycle deviation. This design directly extracts the error signal in each oscillation cycle without digital conversion or additional filtering, thus significantly improving the system bandwidth and response speed. The integrator unit integrates the deviation voltage and outputs a voltage control signal. The feedback compensation unit drives the compensation winding through a voltage follower to generate a reverse compensation magnetic field, forming a closed-loop control that forces the duty cycle to return to a 50% equilibrium state. At this point, the integrated output voltage is proportional to the measured current. Compared to existing PAC solutions, this invention directly processes duty cycle deviation through fully analog circuits, resulting in a higher signal-to-noise ratio and extremely low output ripple (measured ripple is only 4mV). It also avoids the use of expensive dedicated chips or digital circuits, significantly reducing costs and production complexity while ensuring high precision and high bandwidth.

Claims

1. A closed-loop fluxgate current sensor system based on sample-and-hold, characterized in that, include: The duty cycle sampling and holding unit is connected to the self-excited oscillation unit and receives its CLK and SW signals. The duty cycle is converted into voltage through the sampling and holding circuit, and the duty cycle deviation voltage is output. The duty cycle sampling and holding unit includes an analog switch and a high-level time acquisition path and a low-level time acquisition path with symmetrical control design. The self-excited oscillation unit connects to the excitation winding of the magnetic core to generate a symmetrical excitation drive signal; The integration unit connects the duty cycle sampling and holding unit and the feedback compensation unit to integrate the deviation voltage and output the integrated signal. The feedback compensation unit is connected to the compensation winding, outputs the integrated signal, and feeds it back to the compensation winding to form a closed-loop feedback control.

2. The closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 1, characterized in that, The duty cycle sampling and holding unit includes: pin 10 of analog switch U25B receives the SW signal, pin 7 is connected to the high-level time acquisition path, pin 9 is connected to the low-level time acquisition path, and pin 8 is connected to VCC via R33.

3. The closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 2, characterized in that, The high-level time acquisition path includes AND gates U33 and U34 that receive signals from the self-excited oscillation unit CLK and SW. The low-level time acquisition path includes AND gates U24 and U25 that receive signals from the self-excited oscillation unit CLK and SW. The SW signal is input to pin 1 of U24 and U25, and after passing through voltage inverter U32, the SW signal is input to pin 1 of U33 and U34. The CLK signal is input to pin 2 of U25 and U34, and after passing through voltage inverter U35, the CLK signal is input to pin 2 of U33 and U24.

4. The closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 3, characterized in that, In the high-level time acquisition path, the output terminal of U33 is connected to the gate of NMOS transistor Q5, and the drain of Q5 is connected to the input terminal of operational amplifier U29, pin 7 of U28B, and C15 through current-limiting resistor R34; the output terminal of U34 is connected to pin 10 of analog switch U30B, and pin 7 of U30B is connected to C16 and the input terminal of operational amplifier U31 through resistor R35, and pin 8 is connected to the output terminal of U29.

5. A closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 3, characterized in that, In the low-level time acquisition path, the output terminal of U24 is connected to the gate of NMOS transistor Q4, and the drain of Q5 is connected to the input terminal of operational amplifier U21, pin 9 of U28B, and C11 through current-limiting resistor R26; the output terminal of U25 is connected to pin 10 of analog switch U22B, pin 7 of U22B is connected to C12 and the input terminal of operational amplifier U23 through resistor R27, and pin 8 is connected to the output terminal of U21.

6. A closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 4 or 5, characterized in that, The output terminals of U31 and U23 are connected to the input terminal of operational amplifier U27 in the integrator unit via resistors R29 and R28, respectively.

7. A closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 4 or 5, characterized in that, The outputs of U31 and U23 are connected to the input of operational amplifier U26 in the signal amplification unit via resistors R37 and R31, respectively. The output of U26 is connected to the input of operational amplifier U27 in the integration unit via R28. The input of U27 is also connected to VREF via R29.

8. A closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 4, characterized in that, In the high-level time acquisition path, the self-excited oscillation unit triggers SW to flip once at the positive edge of CLK. When a positive pulse comes to CLK, SW changes from low level to high level. The outputs of U33 and U34 remain low level, Q5 is turned off, pin 8 of U28B is connected to pin 7, and the power supply charges C15 through R33 to accumulate the high-level time of SW. Pin 8 of U30B is connected to pin 9, pin 7 is disconnected from pin 8, C16 keeps its voltage unchanged, and op-amp U31 maintains the voltage of C16 to drive the output, thus achieving the previous voltage holding.

9. A closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 8, characterized in that, In the high-level time acquisition path, when another positive pulse arrives at CLK of the self-excited oscillation unit, SW changes from high level to low level. U28B controls pins 8 and 9 to connect and pin 7 to disconnect. The voltage of C15 stores the high-level duration of SW. When CLK maintains a high-level pulse width, U34 outputs high, controlling pins 8 and 7 of U30B to connect, and the voltage of capacitor C16 is refreshed to the value of C15. When CLK returns to low level, U34 outputs low, U30B switches off, C16 re-enters the holding state, U33 outputs high, controlling Q5 to conduct, discharging the current in C15 through the current-limiting resistor R34, preparing for the high-level time acquisition of SW in the next cycle.

10. A closed-loop fluxgate current sensor system based on sample-and-hold as described in claim 9, characterized in that, The working timing sequence in the low-level time acquisition path is opposite to that in the high-level time acquisition path; in the feedback compensation unit, one end of the compensation winding is connected to VREF, and the other end is connected to the output terminal of operational amplifier U36 through R38; When the duty cycle is not equal to 50%, the outputs of the high-level time acquisition path and the low-level time acquisition path are inconsistent. After passing through the integration unit, the output control voltage drives the compensation winding until the duty cycle is restored to 50%. At this time, the output voltage of the integration unit is proportional to the magnitude of the measured current and the total impedance of R38 and the compensation winding.

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