Preparation process of VA liquid crystal display panel with wide viewing angle and high color consistency

Abstract

The invention provides a preparation process of a wide-view-angle and high-color-consistency VA liquid crystal display panel, and relates to the field of display, and the preparation process sequentially comprises the following steps: preparing a color filter film containing CdSe / ZnS core-shell quantum dots; manufacturing a color filter film array, a color filter film protection layer and an ITO common electrode film layer on the color film substrate; tFT pixels are manufactured on the TFT substrate, photoresist photoetching is carried out to form protrusions, and thermocuring forming is carried out; performing photoetching to form an ITO common electrode; sputtering and depositing an ITO (Indium Tin Oxide) film layer on the TFT substrate and photoetching to form an ITO pixel electrode; the two substrates are coated with PI materials respectively to form orientation layers, UV polarized light is adopted to irradiate the PI materials, and the orientation layers obtain gradient divergence angle orientation ranging from 0 degree to 90 degrees; in the black matrix area of the color filter film substrate, SPACER is manufactured through photoetching, and the two substrates are subjected to box forming treatment. The defects that a traditional VA liquid crystal panel is wide in view angle color cast and poor in brightness uniformity are overcome.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display technology, specifically to the manufacturing process of a VA liquid crystal display panel with wide viewing angle and high color consistency, and to the wide viewing angle optimization design of VA (vertical alignment) type liquid crystal display panels. Background Technology

[0002] VA LCD panels are widely used in TVs, automotive displays, monitors and other applications due to their high contrast and wide color gamut. However, traditional VA panels are prone to color shift and brightness decay when viewed from a wide viewing angle (especially more than ±60° away from the normal). The core reason is that when the liquid crystal molecules are vertically aligned, the optical path difference is inconsistent at different viewing angles, which leads to a decrease in color reproduction.

[0003] To improve the aforementioned wide viewing angle defects, existing compensation film technologies (such as CN10285466B, a VA display mode compensation architecture) can optimize viewing angle performance to a certain extent, but they increase costs and panel thickness, and the compensation effect is unstable under wide temperature conditions. Summary of the Invention

[0004] This invention provides a manufacturing process for a VA liquid crystal display panel with wide viewing angle and high color consistency, in order to solve the technical problems mentioned in the background art.

[0005] To address the aforementioned technical problems, this invention discloses a manufacturing process for a VA liquid crystal display panel with wide viewing angle and high color consistency, comprising: Step 1: Prepare a color filter film by adding 0.5-1.2 wt% core-shell quantum dot CdSe / ZnS material to the color filter film, with a core-shell particle size of 2-10 nm; Step 2: Fabricate a color filter array on the color filter substrate, fabricate a color filter protective layer on the surface of the color filter, and then fabricate an ITO common electrode film layer. Step 3: On the TFT substrate, fabricate TFT pixels, dividing each pixel into four sector subdomains. The orientation angle of each subdomain gradually changes from 0° to 90° along the center of the pixel and is distributed divergently. Step 4: The TFT substrate obtained in Step 3 is photolithographically formed with photoresist, and the protrusions are then thermally cured. Step 5: Pattern the ITO common electrode film layer using photolithography to form the ITO common electrode; For the TFT substrate obtained in Step 4, first deposit an ITO film layer by sputtering, and then pattern the ITO film layer using photolithography to form the ITO pixel electrode. Step 6: Coat the two substrates obtained in Step 5 with PI material to form an alignment layer. Irradiate the PI material with UV polarized light to make the alignment layer obtain a gradual divergence angle alignment from 0° to 90°. Step 7: In the black matrix region of the color filter film substrate obtained in Step 6, SPACER is fabricated using a photolithography process; Step 8: Perform cell assembly process on the color filter substrate and TFT substrate.

[0006] Preferably, the red filter film contains CdSe / ZnS quantum dots with a core size of 4.6–10.0 nm, the green filter film contains CdSe / ZnS quantum dots with a core size of 2.6–3.5 nm, and the blue filter film contains CdSe / ZnS quantum dots with a core size of 2.0–2.5 nm.

[0007] Preferably, the mass percentage of CdSe / ZnS quantum dots in the red filter film, green filter film, and blue filter film is 0.5 to 1.2 wt%.

[0008] Preferably, the central angle of each sector subdomain is 90°.

[0009] Preferably, the thickness of the box in step 8 is controlled at 3 to 4.0 μm.

[0010] Preferably, the orientation layer angle of each subdomain gradually changes from 0° to 30° to 60° to 90° along the pixel center and is distributed divergently, so that the liquid crystal molecule alignment direction transitions continuously and the transition region between subdomains transitions continuously.

[0011] Preferably, the TFT substrate obtained in step 6 is coated with a border adhesive and liquid crystal is then deposited. The TFT substrate is then bonded to the color filter film substrate obtained in step 7 using vacuum bonding technology. Finally, the border adhesive is cured by UV light irradiation to complete the cell assembly of the VA liquid crystal display panel with wide viewing angle and high color consistency.

[0012] Preferably, the height of the protrusion is 1 / 5 to 1 / 3 of the box thickness.

[0013] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0014] Compared with the prior art, the present invention has the following beneficial effects: 1. Viewing angle performance: Both horizontal and vertical viewing angles reach 178°. When deviating from the normal by 60°, the color deviation value (ΔE) is ≤1.5 and the brightness decay rate is ≤10%, which is better than traditional MVA panels (ΔE≤3.0, brightness decay rate≤20%). 2. Process compatibility: No additional compensation film is required. By simply adding 0.5-1.2wt% quantum dot CdSe / ZnS material to the color filter film, it is compatible with existing VA panel production lines, reducing costs by 15-20%. 3. Display performance: The contrast ratio is maintained above 5000:1, and the color gamut coverage is above 95% of DCI-P3, meeting the needs of high-end displays.

[0015] This application, through an innovative technical solution, simultaneously addresses the core defects of traditional VA LCD panels, such as wide viewing angle color bias and poor brightness uniformity, without increasing process complexity or significantly raising manufacturing costs. It balances display performance optimization and mass production feasibility, meeting the high-performance requirements of VA mode LCD panels in various scenarios such as televisions, automotive displays, and professional monitors. Attached Figure Description

[0016] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the process of the present invention; Figure 2 This is a schematic diagram of the VA liquid crystal display panel of the core rod of the present invention; Figure 3 This is a schematic diagram of the pixel subdomain orientation direction of the present invention.

[0017] In the diagram: 1. Color filter substrate; 2. Black matrix; 3. Polarizer 1; 4. Color filter film; 5. Color filter protective layer; 6. ITO common electrode film; 7. Alignment layer; 8. Storage capacitor; 9. Liquid crystal; 10. Protrusion; 11. Frame adhesive; 12. CdSe / ZnS quantum dot; 13. SPACER; 14. Polarizer 2; 15. ITO pixel electrode; 16. TFT substrate; 17. TFT; 1.1 First subdomain; 2.1 Second subdomain; 3.1 Third subdomain; 4.1 Fourth subdomain; 5.1 Subdomain transition region. Detailed Implementation

[0018] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0019] Furthermore, in this invention, the use of terms such as "first" and "second" is for descriptive purposes only and does not specifically refer to any order or sequence, nor is it intended to limit the invention. They are merely used to distinguish components or operations described using the same technical terms and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions and features of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If a combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0020] The present invention provides the following embodiments: This invention provides a fabrication process for a wide-viewing-angle, high-color-consistency VA liquid crystal display panel (including an array substrate, a color filter substrate, and a VA liquid crystal layer sandwiched between the two, wherein the pixel electrodes of the array substrate adopt a "grid-like + micro-bump" structure), such as... Figures 1-3 As shown, it includes: Step 1: Prepare a color filter film by adding 0.5-1.2 wt% core-shell quantum dot CdSe / ZnS material to the color filter film, with a core-shell particle size of 2-10 nm; Step 2: Fabricate a color filter array on the color filter substrate, fabricate a color filter protective layer on the surface of the color filter, and then fabricate an ITO common electrode film layer. Step 3: On the TFT substrate, fabricate TFT pixels, dividing each pixel into four sector subdomains. The orientation angle of each subdomain gradually changes from 0° to 90° along the center of the pixel and is distributed divergently. Step 4: The TFT substrate obtained in Step 3 is photolithographically formed with photoresist, and the protrusions are then thermally cured. Step 5: Pattern the ITO common electrode film layer using photolithography to form the ITO common electrode; For the TFT substrate obtained in Step 4, first deposit an ITO film layer by sputtering, and then pattern the ITO film layer using photolithography to form the ITO pixel electrode. Step 6: Coat the two substrates obtained in Step 5 with PI material to form an alignment layer. Irradiate the PI material with UV polarized light to make the alignment layer obtain a gradual divergence angle alignment from 0° to 90°. Step 7: In the black matrix region of the color filter film substrate obtained in Step 6, SPACER is fabricated using a photolithography process; Step 8: Perform cell assembly process on the color filter substrate and TFT substrate.

[0021] Among them, the red filter film disperses CdSe / ZnS quantum dots with a core size of 4.6–10.0 nm, the green filter film disperses CdSe / ZnS quantum dots with a core size of 2.6–3.5 nm, and the blue filter film disperses CdSe / ZnS quantum dots with a core size of 2.0–2.5 nm.

[0022] The mass percentage of CdSe / ZnS quantum dots in the red, green, and blue filters is 0.5–1.2 wt%.

[0023] The central angle of each sector subdomain is 90°.

[0024] In step 8, the thickness of the box is controlled between 3 and 4.0 μm.

[0025] In this process, the orientation layer angle of each subdomain gradually changes and diverges along the pixel center from 0° to 30° to 60° to 90°, so that the liquid crystal molecule alignment direction transitions continuously and the transition region between subdomains transitions continuously, eliminating color abrupt changes at multidomain boundaries.

[0026] In this process, the TFT substrate obtained in step 6 is coated with frame adhesive and liquid crystal is injected sequentially. The TFT substrate is then bonded to the color filter film substrate obtained in step 7 using vacuum bonding technology. Finally, the frame adhesive is cured by UV light irradiation to complete the cell assembly of the VA liquid crystal display panel with wide viewing angle and high color consistency.

[0027] The height of the protrusion is 1 / 5 to 1 / 3 of the box thickness.

[0028] Example 1:

[0029] 1. Preparation of color filter films: 0.5% CdSe / ZnS quantum dots with a core size of 6.6–8.2 nm are dispersed in the red filter film; 0.5% CdSe / ZnS quantum dots with a core size of 2.8–3.3 nm are dispersed in the green filter film; and 0.5% CdSe / ZnS quantum dots with a core size of 2.2–2.4 nm are dispersed in the blue filter film. Then, a color filter film array is fabricated on the color filter substrate, and a color filter film protective layer is fabricated on the surface of the color filter film. Finally, an ITO common electrode film layer is fabricated. 2. TFT substrate fabrication: TFT pixels are fabricated on the TFT substrate; 3. Protrusion fabrication: The micro-protrusions are formed by photolithography with photoresist and then thermal curing. 4. ITO electrode fabrication: After sputtering the ITO film, ITO common electrodes are fabricated on the color filter substrate and ITO pixel electrodes are fabricated on the TFT substrate using photolithography. 5. Preparation of the orientation layer: Using PI (polyimide) material (such as Nissan Chemical's Sunever 150), the PI is irradiated with UV polarized light to obtain a gradient and diverging angle (0°→90°) orientation, ensuring that the liquid crystal molecules are aligned along the gradient direction; 6. SPACER fabrication: SPACER is fabricated using photolithography in the black matrix area; 7. Cell assembly process: After liquid crystal is injected, vacuum bonding technology is used, the cell thickness is 3.25μm, and the frame adhesive is cured by UV light.

[0030] Example 2:

[0031] 1. Preparation of color filter films: 0.8% CdSe / ZnS quantum dots with a core size of 6.8–7.6 nm are dispersed in the red filter film; 0.8% CdSe / ZnS quantum dots with a core size of 2.9–3.1 nm are dispersed in the green filter film; and 0.8% CdSe / ZnS quantum dots with a core size of 2.2–2.4 nm are dispersed in the blue filter film. Then, a color filter film array is fabricated on the color filter substrate, and a color filter film protective layer is fabricated on the surface of the color filter film. Finally, an ITO common electrode film layer is fabricated. 2. TFT substrate fabrication: TFT pixels are fabricated on the TFT substrate; 3. Protrusion fabrication: The micro-protrusions are formed by photolithography with photoresist and then thermal curing. 4. ITO electrode fabrication: After sputtering the ITO film, ITO common electrodes are fabricated on the color filter substrate and ITO pixel electrodes are fabricated on the TFT substrate using photolithography. 5. Preparation of the orientation layer: Using PI (polyimide) material (such as Nissan Chemical's Sunever 150), the PI is irradiated with UV polarized light to obtain a gradient and diverging angle (0°→90°) orientation, ensuring that the liquid crystal molecules are aligned along the gradient direction; 6. SPACER fabrication: In the black matrix region, SPACER (a micro-pillar structure fabricated in the black matrix region of the color filter substrate to maintain the gap (i.e., cell thickness) between the upper and lower substrates of the liquid crystal cell) is fabricated by photolithography. 7. Cell assembly process: After liquid crystal is injected, vacuum bonding technology is used, the cell thickness is 3.5μm, and the frame adhesive is cured by UV light.

[0032] The following is a table of experimental data: Table 1. Wide viewing angle performance comparison (traditional MVA panel vs. the panel of this invention)

[0033] Table 2 Effect of Quantum Dot Addition Amount on Viewing Performance

[0034] Quantum dot materials are uniformly distributed in the color filter film, and the photoluminescence properties of quantum dots compensate for view-dependent spectral attenuation.

[0035] Figure 3 The pixel subdomain orientation direction of the present invention includes: a first subdomain 1.1, a second subdomain 2.1, a third subdomain 3.1, a fourth subdomain 4.1, and a subdomain transition region 5.1. The first subdomain 1.1, the second subdomain 2.1, the third subdomain 3.1, and the fourth subdomain 4.1 are all 0°→90°.

[0036] Figure 2 The panel of the present invention includes: a color filter substrate 1 and a TFT substrate 16 disposed opposite to each other, and a liquid crystal 9 located between them; the color filter substrate 1 has a black matrix 2, a color filter film 4, a color filter protective layer 5, an ITO common electrode film layer 6, and an alignment layer 7 disposed sequentially on the side facing the TFT substrate 16; a polarizer 3 is disposed on the side of the color filter substrate 1 away from the TFT substrate 16; the TFT substrate 16 has a TFT 17, an ITO pixel electrode 15, an alignment layer 7, and a protrusion 10 disposed on the side facing the color filter substrate 1; a second polarizer 14 is disposed on the side of the TFT substrate 16 away from the color filter substrate 1; the color filter substrate 1 and the TFT substrate 16 are encapsulated by a frame adhesive 11, and the encapsulated area is filled with liquid crystal 9 and a spacer 13 is disposed; a storage capacitor 8 is integrated on the TFT substrate 16. The spacer 13 is uniformly distributed between the color filter substrate 1 and the TFT substrate 16.

[0037] The beneficial effects of the above technical solution are as follows: 1. Viewing angle performance: Both horizontal and vertical viewing angles reach 178°. When deviating from the normal by 60°, the color deviation value (ΔE) is ≤1.5 and the brightness decay rate is ≤10%, which is better than traditional MVA panels (ΔE≤3.0, brightness decay rate≤20%). 2. Process compatibility: No additional compensation film is required. By simply adding 0.5-1.2wt% quantum dot CdSe / ZnS material to the color filter film, it is compatible with existing VA panel production lines, reducing costs by 15-20%. 3. Display performance: The contrast ratio is maintained above 5000:1, and the color gamut coverage is above 95% of DCI-P3, meeting the needs of high-end displays.

[0038] This application, through an innovative technical solution, simultaneously addresses the core defects of traditional VA LCD panels, such as wide viewing angle color bias and poor brightness uniformity, without increasing process complexity or significantly raising manufacturing costs. It balances display performance optimization and mass production feasibility, meeting the high-performance requirements of VA mode LCD panels in various scenarios such as televisions, automotive displays, and professional monitors.

[0039] In one embodiment, before the TFT substrate to be sputtered is quantitatively sputtered and deposited, a reference model of "sputtering power - sputtering temperature rise rate - equivalent average gas pressure" is determined under the corresponding rated sputtering equipment conditions (a mapping table, in which the first column is sputtering power, the second column is sputtering temperature rise rate, and the third column is equivalent average gas pressure). When the sputtered TFT substrate is put into mass production, a pre-testing process is first performed, which includes: Step 5a1: Pre-treatment before sputtering; specifically, it may include: purging the sputtering cavity with argon gas; Step 5a2: Preheat the TFT substrate to be sputtered to the preheating temperature (range 100~150℃) using the test preheating power, and determine the actual preheating temperature change rate based on temperature detection; based on the comparison between the actual preheating temperature change rate and the test preheating temperature change rate (range 0.2~0.5℃ / s), and in conjunction with the aforementioned benchmark model, initially adjust the test sputtering power to obtain the adjusted sputtering power; Step 5a3: Introduce argon and oxygen through the mass flow controllers respectively, with the proportions of argon and oxygen being the corresponding rated test proportions (where the test argon flow rate ranges from 47.5 to 196 sccm, the test oxygen flow rate ranges from 2 to 10 sccm, the test argon proportion ranges from 95% to 98%, and the test oxygen proportion ranges from 2% to 5%). Adjust the total gas pressure in the sputtering chamber to the test gas pressure (range 0.3 to 0.5 Pa). Step 5a4: Turn on the RF sputtering power supply, set the sputtering power and sputtering speed to be the adjusted sputtering power and test sputtering speed corresponding to the TFT substrate to be sputtered, and perform sputtering deposition test; The temperature of the TFT substrate to be sputtered before the sputtering deposition test and the temperature of the ITO film after sputtering deposition were detected, and the gas pressure in the sputtering cavity was detected during the sputtering deposition test, and a gas pressure sequence was constructed according to the working time. Actual sputtering temperature rise rate = (ITO film temperature after sputtering deposition - TFT substrate temperature to be sputtered before testing) ÷ sputtering time; The temperature measurement point can be fixed at the geometric center of the substrate / film layer. "Temperature of the TFT substrate to be sputtered before testing" specifically refers to the stable temperature after the preheating step is completed and before sputtering begins.

[0040] Step 5a5: Determine the actual temperature change rate based on the temperature of the TFT substrate to be sputtered, and determine the actual sputtering power efficiency in combination with the reference model; determine the actual equivalent average gas pressure based on the gas pressure sequence, and determine the actual gas pressure coefficient in combination with the actual equivalent average gas pressure. Step 5a6: When the actual pressure coefficient does not meet the pressure coefficient range (the pressure coefficient range can be [0.95, 1.05]), an alarm is triggered. When the actual sputtering power efficiency coefficient does not meet the efficiency coefficient range (e.g., less than 0.8), an alarm is triggered to remind the equipment to be repaired or parts to be replaced. Step 5a7: If no alarm is triggered in step 5a6, determine the final sputtering power based on the actual sputtering power efficiency coefficient, the adjusted sputtering power, and the reference model. In final mass production: quantitative sputtering deposition is controlled based on the final sputtering power, test preheating power, and other rated process parameters.

[0041] Specific Explanation 1: TFT substrate to be sputtered: refers to the process (step 5) on which an ITO conductive film layer will be sputtered and deposited on its surface; it corresponds to a specific type and has the same composition; Specific Explanation 2: Rated Sputtering Equipment Status: For the mass production (batch production) sputtering deposition process of TFT substrates, in order to unify the process benchmark before formal mass production and eliminate the interference of individual differences in sputtering equipment on the mass production yield, it is necessary to first establish a system of equipment operating benchmark states: Definition: For TFT substrates of the exact same type, multiple sets of process verification experiments are carried out using sputtering equipment. The core criterion is the "production qualification rate of sputtered ITO film layer". The set of equipment hardware (i.e., the same type of equipment) and operating status that meet the standards in terms of film quality (conductivity, transmittance, film thickness uniformity, stress), deposition efficiency and equipment operation stability is selected. This set is the rated sputtering equipment status for the corresponding type of TFT substrate.

[0042] Core components of sputtering equipment status: Sputtering chamber status: chamber sealing status (leakage rate ≤ threshold), target etching status (thickness / uniformity within the lifetime range), magnetic field strength (stable within the factory calibration range), chamber cleanliness (no residual impurities / moisture). Key hardware statuses include: ventilation-related devices (mass flow controller MFC calibrated and leak-free gas path), cooling system (cooling water flow / temperature stable within design range), RF power supply output stability, and substrate support platform flatness. Equipment performance benchmarks include: sputtering power efficiency (the efficiency of converting sputtering power into temperature rise at the substrate deposition site, which remains stable within the calibration range) and plasma discharge stability.

[0043] This state is an ideal stable benchmark at the equipment level. It is only used to ensure the consistency of the hardware environment for different equipment of the same type (model) and different usage durations. It is not required to lock this state during production. It is only used as the equipment reference for subsequent process parameter correction.

[0044] Specific Explanation 3: Determination of Rated Process Parameters (Based on the Qualified Process Range under Rated Equipment Conditions): Under rated sputtering equipment conditions, only process parameters (sputtering power, preheating power, cavity pressure, gas ratio, etc.) are adjusted to conduct gradient experiments. With the production of qualified ITO film as the judgment standard, all process parameter combinations that can achieve qualified deposition are screened out to form the rated process parameter range.

[0045] Example of core rated process parameter range: Rated sputtering power range: commonly used range for mass production (e.g., 2.0~3.5kW); Rated preheating power range: The power range of the preheating stage that matches the sputtering power (e.g., 1.0~2.0kW). Rated equivalent average pressure range: The actual equivalent average pressure range within the sputtering chamber of the sputtering equipment during the sputtering deposition process (e.g., 0.3~0.5 Pa). Rated preheating temperature change rate range: The temperature change rate range of the preheating process (e.g., 0.2~0.5℃ / s); Rated process gas ratio: fixed ratio range; Rated sputtering rate range: The deposition rate range matching the power range (e.g., 0.5~1.0 nm / s).

[0046] Core positioning: Rated process parameters are the range of qualified process values ​​based on rated equipment conditions, providing a process reference for subsequent mass production. In actual production, the parameters can be fine-tuned within this range according to the real-time status of the equipment, rather than being forcibly locked to a single value.

[0047] Among them, the set of process parameters corresponding to the experiment with the highest pass rate in the rated process parameter range is named the rated test process parameter combination (composed of test sputtering power, test preheating power, test gas pressure, test sputtering speed, etc.). Specific Explanation 4: Obtaining the Baseline Model (Based on Rated Equipment Status + Rated Process Parameter Range): The method for obtaining the benchmark model of "sputtering power - TFT substrate surface temperature rise rate - equivalent average gas pressure" under rated sputtering equipment conditions is as follows: The sputtering equipment is operated under rated sputtering conditions. The sputtering power is adjusted only within the rated sputtering power range corresponding to the same type of TFT substrate. All other rated process parameters (gas ratio, cavity pressure reference, preheating conditions, etc.) are fixed within the corresponding rated range. Sputtering experiments are performed according to the preset gradient parameter combination. The actual surface temperature rise rate of the TFT substrate under each sputtering power is determined based on the temperature detection of the TFT substrate before and after sputtering. The corresponding actual equivalent average gas pressure is determined based on the gas pressure monitoring of the sputtering cavity. Finally, a direct mapping relationship between sputtering power and TFT substrate surface temperature rise rate and equivalent average gas pressure is established. This mapping relationship is the reference model.

[0048] Specific Explanation 5: Preheating temperature change rate = (preheating temperature - actual temperature of TFT substrate at the start of preheating) ÷ actual preheating time of TFT substrate when preheating temperature is reached; Rate difference coefficient = (actual preheating temperature change rate - test preheating temperature change rate) ÷ test preheating temperature change rate; The allowable deviation threshold for the rate difference coefficient is ±a; the value of a ranges from greater than 0 to less than 0.1. When the rate difference coefficient satisfies [-a, a], then the adjusted sputtering power = the test sputtering power; When the difference coefficient is greater than a (not exceeding 1.2a), the adjusted sputtering power is 0.92 to 0.95 times the test preheating temperature change rate test sputtering power; When the difference coefficient is greater than -a (not less than -0.8a), the adjusted sputtering power is 1.02 to 1.05 times the test sputtering power. When the difference coefficient is greater than a, it indicates that the thermal response is too strong in the current preheating stage. In order to avoid the substrate overheating during subsequent sputtering deposition, which may cause uneven stress, decreased light transmittance, or poor uniformity of film thickness in the ITO film, the test sputtering power needs to be reduced to correct the problem. When the difference coefficient is less than -a, it indicates that the thermal response in the current preheating stage is weak. In order to ensure that the thermal effect and deposition efficiency during subsequent sputtering deposition meet the mass production benchmark requirements, the test sputtering power needs to be adjusted upward. If the rate difference coefficient exceeds ±1.2a, the pre-test must be suspended and the preheating system or substrate status must be checked. Specific Explanation 6: Actual sputtering power efficiency coefficient = Actual sputtering temperature rise rate detected in step 5a5 ÷ Sputtering temperature rise rate corresponding to the adjusted sputtering power in the reference model; Actual air pressure coefficient = ; In the gas pressure sequence: the average gas pressure during the sputtering process is the actual equivalent average gas pressure (the average value of the gas pressure detection values ​​at the effective sampling points); the effective sampling point is defined as: the cavity pressure data collected at a certain frequency (e.g., 1 second / time) from 10 seconds after the start of sputtering deposition to 10 seconds before the end, and the average value is calculated after removing outliers exceeding ±3σ.

[0049] When sputtered TFT substrates are put into mass production, the first substrate produced each time must undergo a complete pre-test process (steps 5a1~5a7), and the obtained "final sputtering power" will be used as the general process parameter for subsequent substrates in this mass production. Specific Explanation 7: Actual sputtering power efficiency coefficient = Actual sputtering temperature rise rate detected in step 5a5 ÷ Sputtering temperature rise rate corresponding to the adjusted sputtering power in the reference model; The actual sputtering power efficiency coefficient characterizes the efficiency of sputtering power in converting into temperature rise of TFT substrate / ITO film under the current equipment condition, reflecting the degree of attenuation of equipment hardware (such as target etching, magnetic field strength); when the efficiency coefficient is lower than 0.8, the equipment performance is judged to not meet the mass production requirements.

[0050] The final sputtering power satisfies the following condition: "(final sputtering power at the sputtering temperature rise rate in the reference model ÷ adjusted sputtering power at the sputtering temperature rise rate in the reference model) × actual sputtering power efficiency coefficient" is greater than or equal to K (K satisfies 1 < 1.1). "Greater than or equal to 1 < 1.1" is based on actual data calibration when the final sputtering power adjustment is qualified in experimental / historical production (the median or lower limit of the 95% confidence interval of the statistical distribution of qualified batches). The specific process for determining the final sputtering power is as follows: First, determine the target sputtering temperature rise rate = K times (adjusted sputtering power is the sputtering temperature rise rate corresponding to the reference model ÷ actual sputtering power efficiency coefficient), and then find the final sputtering power that satisfies the target sputtering temperature rise rate in the model. The beneficial effects of the above technical solution are as follows: 1. By pre-setting the rated sputtering equipment state, the differences in hardware environment under different equipment and different usage periods are eliminated, avoiding fluctuations in mass production yield due to individual equipment deviations. The rated equipment state serves as a reference for process parameter correction, ensuring that each parameter adjustment has a clear "ideal state" reference, avoiding process instability caused by experience-based debugging, and improving process stability.

[0051] 2. Preheating to 100-150℃ allows the substrate to reach a stable initial temperature, avoiding severe temperature shocks during sputtering and reducing the risk of substrate thermal deformation and uneven film stress.

[0052] By comparing the difference between the actual preheating temperature rise rate and the test preheating temperature rise rate, the thermal response status of the substrate / equipment can be detected in advance. If the actual rate is too fast (preheating is too strong compared to the rated test state), the sputtering power is reduced; if it is too slow (preheating is insufficient compared to the rated test state), the power is increased. Power pre-correction is completed before sputtering to avoid thermal problems being exposed during the sputtering stage, which can easily lead to scrap.

[0053] By adjusting the power in conjunction with the benchmark model, the initial power adjustment is made to match both the thermal response state and the process range of the rated equipment state, thus ensuring the rationality of subsequent sputtering tests.

[0054] The mass flow controller precisely controls the gas flow rate and ratio to ensure stable oxygen content in the ITO film and prevent conductivity and transmittance defects caused by ratio fluctuations. The cavity pressure is controlled within the optimal range of 0.3–0.5 Pa to ensure stable plasma discharge, uniform sputtering rate, and a dense film, thereby improving film quality and deposition efficiency.

[0055] 3. Test sputtering was performed using the adjusted sputtering power to verify the thermal state correction effect of step 5a2, ensuring that the initial power adjustment was adapted to the current substrate / equipment status. Real-time temperature and pressure data before and after sputtering were collected throughout the process to construct a pressure sequence. The actual sputtering temperature rise rate directly quantifies the conversion efficiency of "sputtering power → substrate / film temperature rise," providing a core indicator for subsequent equipment performance evaluation. Actual sputtering power efficiency: quantifies equipment hardware degradation (such as target aging, weakened magnetic field, and unstable RF power output), reflecting the current equipment's energy utilization capability. Actual equivalent average pressure: calculated based on the pressure sequence, reflecting the sealing status and pressure diffusion status of the gas path / chamber throughout the sputtering process.

[0056] More precise anomaly location: If efficiency is abnormal, it points to a hardware problem; if air pressure is abnormal, it points to a problem with the air path / chamber, providing a clear direction for subsequent alarms and repairs.

[0057] 4. The model pre-quantifies the stable mapping relationship between power, temperature rise rate, and equivalent average pressure. In step 5a2, only the actual preheating temperature rise rate needs to be compared with the model calibration value to quickly complete the initial power adjustment. In step 5a7, the final power is obtained by directly looking up the model through the target temperature rise rate, which completely avoids the problems of existing solutions relying on engineers' experience for repeated sputtering trials, long debugging cycles, and poor correction accuracy. It shortens the process adjustment time from several hours to minutes, while ensuring the consistency of each correction.

[0058] The model simultaneously binds three core variables: power, temperature rise, and air pressure. This ensures that the power pre-correction during the preheating stage, the equipment efficiency assessment during the sputtering stage, and the determination of the final power all follow the same logic. This solves the problem that adjusting the power alone in existing solutions can easily lead to imbalances in air pressure / thermal response and fluctuations in membrane quality.

[0059] In one embodiment, step 4 of the current TFT substrate mass production includes: Step 4a1: Coat the current TFT substrate with photoresist (to form the bump) to the corresponding photoresist thickness (which can be 0.6~1.33μm), and select several current TFT substrates as the current temperature-measuring TFT substrates in the current drying feed (current TFT substrate); Step 4a2: Place the TFT substrate from Step 4a1 into the drying device and pre-bake it using the theoretical pre-baking heating power of the drying device corresponding to the current TFT substrate. After heating to the pre-baking temperature, maintain the pre-baking time (30-60 seconds). During the pre-baking process, detect the current temperature of the TFT substrate to be measured and the temperature inside the drying device. Determine the actual thermal hysteresis coefficient and the actual thermal response coefficient based on the temperature detection results. Combine the actual thermal hysteresis coefficient, the actual thermal response coefficient, and the theoretical curing temperature rise rate (within the range of 2-4℃ / min) to determine the target curing temperature rise rate. The thermal hysteresis coefficient is: (Time when the temperature of the TFT substrate to be measured first reaches the theoretical pre-drying temperature - Time when the temperature of the inner wall of the drying chamber first reaches the theoretical pre-drying temperature) ÷ Time when the temperature of the inner wall of the drying chamber first reaches the theoretical pre-drying temperature; Based on the preset preheating temperature T0 (value 90~110℃), the following is defined: Lower limit temperature: T_low = T_0 − 5℃ (e.g., when T_0 = 100℃, T_low = 95℃); Upper limit temperature: T_high = T_0; t_1: the moment when the substrate temperature first reaches T_low; t_2: the moment when the substrate temperature first reaches T_high; directly determine [t_1, t_2] as the effective heating period.

[0060] And determine the actual equivalent heating rate: (Thigh - Tlow) ÷ (t2 - t1); Thermal response coefficient = actual equivalent heating rate ÷ theoretical equivalent heating rate; Step 4a3: Heat the current TFT substrate to the curing temperature (120-130°C) at the target curing rate and cure for 90-120 seconds.

[0061] The acceptable range for the thermal response coefficient is 0.8 to 1.2; the acceptable range for the thermal hysteresis coefficient is 0 to 0.1. The current actual thermosetting process of TFT substrates includes a pre-baking stage and a curing stage. The pre-baking stage needs to reach the theoretical pre-baking temperature. When using the drying device for thermosetting, there is a corresponding theoretical pre-baking power and a corresponding theoretical equivalent temperature rise rate. The curing stage corresponds to a theoretical temperature rise rate and a theoretical curing temperature. The above theoretical parameters are the actual parameters (denoted as theoretical parameters) of the pre-baking and curing stages corresponding to the current TFT substrates that have passed thermosetting using the experimental drying device. The theoretical parameters of the pre-baking stage are: pre-baking temperature (90~110℃) and pre-baking power (e.g., in one application scenario, the pre-baking power of the drying device is 1.5~4.0). The theoretical parameters for the curing stage (kW), equivalent heating rate, pre-baking holding time (30-60 seconds), and curing temperature (120-130℃, 90-120 seconds) were all obtained through single-variable or orthogonal experimental debugging. The combination of each process parameter was tested in the experimental environment, and the flatness, adhesion, curing degree, and electrical performance of the TFT device were used as the criteria for qualification. The experimental parameters that met all the indicators were locked. During mass production, the actual process was corrected by using this set of "theoretical parameters" as a benchmark, combined with the real-time detected thermal hysteresis coefficient and thermal response coefficient, to ensure that the mass production results were close to the qualified level of the experimental stage.

[0062] The target curing temperature rise rate is determined by the actual thermal hysteresis coefficient, the actual thermal response coefficient, and the theoretical curing temperature rise rate (range: 2~4℃ / min). Specifically: Adjustments based on thermal hysteresis coefficient: If the thermal hysteresis coefficient is too large, it indicates that the substrate temperature response lags significantly behind the cavity temperature. The theoretical curing heating rate needs to be reduced by 0.2~0.8℃ / min (for example, if the thermal hysteresis coefficient is greater than or equal to 0.05 and less than 0.08, reduce by 0.2~0.5℃ / min; if the thermal hysteresis coefficient is greater than or equal to 0.08 and less than or equal to 0.1, reduce by 0.5~0.8℃ / min) to avoid excessive thermal stress inside the substrate. The thermal response coefficient is adjusted twice (0.05~0.1 is in the critically high range and still needs adjustment): If the thermal response coefficient is too high, it means that the actual heating rate is faster than the theoretical expectation, and the theoretical curing heating rate needs to be reduced by 0.1~0.5℃ / min (e.g., if greater than 1 and less than or equal to 1.1, take 0.1~0.3℃ / min; if greater than 1.1 and less than or equal to 1.2, take 0.3~0.5℃ / min) to prevent the photoresist from developing internal stress or cracks due to excessive heating; If the thermal response coefficient is too low, it means that the actual heating rate is slower than the theoretical expectation, and the theoretical curing heating rate needs to be increased by 0.1~0.5℃ / min (e.g., if greater than or equal to 0.9 and less than 1, take 0.3~0.5℃ / min; if greater than 0.8 and less than 0.9, take 0.1~0.3℃ / min) to avoid an excessively long curing cycle.

[0063] "Adjusting the theoretical curing heating rate downwards / upwards" is based on a single benchmark value of the theoretical curing heating rate (such as 3℃ / min selected from 2~4℃ / min); Final range constraint: After two adjustments, the result is strictly limited to the range of 2~4℃ / min: if the adjusted rate is lower than 2℃ / min, 2℃ / min is directly taken as the lower limit; if the adjusted rate is higher than 4℃ / min, 4℃ / min is directly taken as the upper limit; finally, the target curing temperature rise rate adapted to the current batch of TFT substrates is obtained.

[0064] The beneficial effects of the above technical solution are as follows: By selecting several TFT substrates to be tested from the dried feed, the differences in thermal characteristics between batches can be detected in advance, providing a data basis for subsequent thermal curing process correction and avoiding deviation of the entire batch process from the qualified range.

[0065] By introducing thermal hysteresis coefficient and thermal response coefficient, real-time closed-loop correction of mass production process is achieved: thermal hysteresis coefficient accurately characterizes the heat transfer delay between the substrate and the drying chamber wall, and thermal response coefficient quantifies the deviation between actual temperature rise and theoretical benchmark. The combination of the two can be used to adjust the curing temperature rise rate in a targeted manner, avoiding problems such as photoresist sagging, cracks and uneven curing caused by substrate batch differences and equipment aging, ensuring the flatness, adhesion and electrical performance of photoresist and the stability of TFT device electrical performance, so that mass production results are always close to the experimental level of qualification.

[0066] Heating to 90–110°C and holding for 30–60 seconds ensures sufficient evaporation of the photoresist solvent, uniform substrate temperature, and elimination of internal thermal gradients, preventing stress cracking during subsequent curing stages. Heating to 120–130°C at the target curing rate and holding for 90–120 seconds ensures complete cross-linking and curing of the photoresist (curing degree ≥90%), while avoiding over-curing that could lead to pattern embrittlement and decreased adhesion. This forms a complete thermal process loop with the pre-baking stage, smoothly transitioning thermal stress through the target curing rate, preventing substrate deformation, residual stress in the photoresist, or cracks, and improving the electrical reliability and long-term stability of the TFT device.

[0067] Define the effective heating period [t1, t2], and extract only the effective heating data of the substrate from the lower limit temperature to the upper limit temperature to avoid interference from invalid data in the low temperature / steady state stage and improve the accuracy of coefficient calculation.

[0068] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A manufacturing process for a VA liquid crystal display panel with wide viewing angle and high color consistency, characterized in that: include: Step 1: Prepare a color filter film by adding 0.5-1.2 wt% core-shell quantum dot CdSe / ZnS material to the color filter film, with a core-shell particle size of 2-10 nm; Step 2: Fabricate a color filter array on the color filter substrate, fabricate a color filter protective layer on the surface of the color filter, and then fabricate an ITO common electrode film layer. Step 3: On the TFT substrate, fabricate TFT pixels, dividing each pixel into four sector subdomains. The orientation angle of each subdomain gradually changes from 0° to 90° along the center of the pixel and is distributed divergently. Step 4: The TFT substrate obtained in Step 3 is photolithographically formed with photoresist, and the protrusions are then thermally cured. Step 5: Pattern the ITO common electrode film layer using photolithography to form the ITO common electrode; For the TFT substrate obtained in Step 4, first deposit an ITO film layer by sputtering, and then pattern the ITO film layer using photolithography to form the ITO pixel electrode. Step 6: Coat the two substrates obtained in Step 5 with PI material to form an alignment layer. Irradiate the PI material with UV polarized light to make the alignment layer obtain a gradual divergence angle alignment from 0° to 90°. Step 7: In the black matrix region of the color filter film substrate obtained in Step 6, SPACER is fabricated using a photolithography process; Step 8: Perform cell assembly process on the color filter substrate and TFT substrate.

2. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 1, characterized in that: CdSe / ZnS quantum dots with a nucleus size of 4.6–10.0 nm are dispersed in the red filter film, CdSe / ZnS quantum dots with a nucleus size of 2.6–3.5 nm are dispersed in the green filter film, and CdSe / ZnS quantum dots with a nucleus size of 2.0–2.5 nm are dispersed in the blue filter film.

3. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 1, characterized in that: The mass percentage of CdSe / ZnS quantum dots in the red, green, and blue filters is 0.5–1.2 wt%.

4. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 1, characterized in that: The central angle of each sector subdomain is 90°.

5. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 1, characterized in that: In step 8, the box thickness is controlled between 3 and 4.0 μm.

6. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 1, characterized in that: The orientation layer angle of each subdomain gradually changes and diverges along the pixel center from 0° to 30° to 60° to 90°, so that the liquid crystal molecule alignment direction transitions continuously and the transition region between subdomains transitions continuously.

7. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 1, characterized in that: The TFT substrate obtained in step 6 is coated with frame adhesive and liquid crystal is then injected. The TFT substrate is bonded to the color filter film substrate obtained in step 7 using vacuum bonding technology. The frame adhesive is then cured by UV light irradiation to complete the cell assembly of the VA liquid crystal display panel with wide viewing angle and high color consistency.

8. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 1, characterized in that: Before the quantized sputtering deposition of the TFT substrate to be sputtered, a reference model of "sputtering power - sputtering temperature rise rate - equivalent average gas pressure" under the corresponding rated sputtering equipment conditions is determined; When the sputtered TFT substrate is put into mass production, a pre-testing process is first performed.

9. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 8, characterized in that: The pre-testing process includes: Step 5a1: Pretreatment before sputtering; Step 5a2: Preheat the TFT substrate to be sputtered to the preheating temperature using the test preheating power of the TFT substrate to be sputtered, and determine the actual preheating temperature change rate based on temperature detection. Based on the comparison between the actual preheating temperature change rate and the test preheating temperature change rate, and in conjunction with the aforementioned benchmark model, the test sputtering power is initially adjusted to obtain the adjusted sputtering power. Step 5a3: Introduce argon and oxygen through the mass flow controller respectively, with the proportions of argon and oxygen being the corresponding rated test proportions, and adjust the total gas pressure in the sputtering chamber to the test gas pressure; Step 5a4: Turn on the RF sputtering power supply, set the sputtering power and sputtering speed to be the adjusted sputtering power and test sputtering speed corresponding to the TFT substrate to be sputtered, and perform sputtering deposition test; The temperature of the TFT substrate to be sputtered before the sputtering deposition test and the temperature of the ITO film after sputtering deposition were detected, and the gas pressure in the sputtering cavity was detected during the sputtering deposition test, and a gas pressure sequence was constructed according to the working time. Step 5a5: Determine the actual temperature change rate based on the temperature of the TFT substrate to be sputtered, and determine the actual sputtering power efficiency in combination with the reference model; determine the actual equivalent average gas pressure based on the gas pressure sequence, and determine the actual gas pressure coefficient in combination with the actual equivalent average gas pressure. Step 5a6: If the actual pressure coefficient does not meet the pressure coefficient range, an alarm will be triggered; if the actual sputtering power efficiency coefficient does not meet the efficiency coefficient range, an alarm will be triggered. Step 5a7: If no alarm is triggered in step 5a6, determine the final sputtering power based on the actual sputtering power efficiency coefficient, the adjusted sputtering power, and the reference model.

10. The manufacturing process of the wide-viewing-angle, high-color-consistency VA liquid crystal display panel according to claim 9, characterized in that: In final mass production: quantitative sputtering deposition is controlled based on the final sputtering power, test preheating power, and other rated process parameters.

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