Method and device for optimizing dynamic power consumption of chip and chip

Abstract

The invention provides a chip dynamic power consumption optimization method and device and a chip, and the method comprises the steps: adjusting the working voltage and working frequency of the chip to default values under the current working condition when the working condition of the chip is changed; the working load of the chip is analyzed in real time, if the working load of the chip meets the voltage lowering condition under the current working condition, the lowest working voltage meeting the key path time sequence requirement under the current working condition is calculated according to the key path power consumption model, and the lowest working voltage is recorded as the target voltage; and adjusting the working voltage of the chip to the target voltage. According to the invention, the working voltage of the chip can be dynamically adjusted to match the real-time working load, and the dynamic power consumption of the chip is remarkably reduced on the premise of ensuring that the time sequence requirement of a critical path is met.

Description

Technical Field

[0001] This application relates to the field of chip power consumption optimization technology, specifically to a chip dynamic power consumption optimization method, apparatus, and chip. Background Technology

[0002] In existing technologies, chip power consumption is closely related to its operating voltage. Specifically, the dynamic power consumption of a chip is proportional to the square of its operating voltage; therefore, increasing the operating voltage will lead to a significant increase in power consumption. The minimum operating voltage required by a chip is determined by the delay of its internal timing critical path, and it must be ensured that the signals on the critical path can be correctly transmitted within a specified clock cycle at this voltage.

[0003] However, this minimum operating voltage is not a fixed value, but a dynamic variable affected by multiple factors such as process variations, ambient temperature, and operating frequency. In extreme cases of high temperature, high frequency, or poor process variations, a higher minimum operating voltage is required; conversely, in cases of low temperature, low frequency, or favorable process conditions, a lower minimum operating voltage is required. If the chip uses a fixed operating voltage, but the chip's required minimum operating voltage is low, it will result in unnecessary power consumption waste.

[0004] In related technologies, chip operating conditions are defined based on the chip's working mode and temperature range. For different operating conditions, the chip's operating voltage and frequency are set, and a voltage-frequency mapping table is constructed and stored in the chip so that the chip can adjust its operating voltage and frequency accordingly when operating conditions change. However, the above power consumption optimization strategies can only achieve chip power consumption optimization in static scenarios, and the optimization effect is poor in dynamic scenarios. Summary of the Invention

[0005] This application provides a method, apparatus, and chip for dynamic power consumption optimization, which can solve the technical problem that existing power consumption optimization strategies can only achieve chip power consumption optimization in static scenarios and have poor optimization effects in dynamic scenarios.

[0006] In a first aspect, embodiments of this application provide a method for optimizing dynamic power consumption of a chip, the method comprising: When the chip's operating conditions change, adjust the chip's operating voltage and operating frequency to the default values ​​under the current operating conditions; The chip's workload is analyzed in real time. If the chip's workload meets the voltage reduction condition under the current operating conditions, the minimum operating voltage that meets the critical path timing requirements under the current operating conditions is calculated based on the critical path power consumption model and denoted as the target voltage. Adjust the chip's operating voltage to the target voltage.

[0007] Furthermore, in one embodiment, the chip dynamic power consumption optimization method further includes: If an abnormal alarm occurs within a preset time after the chip's operating voltage is adjusted to the target voltage, the chip's operating voltage will be increased by a first preset step. If an abnormal alarm occurs within a preset time after the chip's operating voltage is increased, the chip's operating voltage will continue to be increased by the first preset step.

[0008] Furthermore, in one embodiment, the step of calculating the minimum operating voltage that meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the difference between the default value of the chip's operating voltage under the current operating conditions and the second preset step size. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then the difference between the current voltage to be evaluated and the second preset step size is taken as the new voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the second preset step size shall be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions.

[0009] Furthermore, in one embodiment, the step of calculating the minimum operating voltage that meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the default value of the chip's operating voltage under the current operating conditions. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then check whether the current phase error meets the iteration termination condition. If the current phase error is within the first error range, then the current voltage to be evaluated will be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions. If the current phase error is outside the first error range, a new voltage to be evaluated is calculated based on the current phase error and the voltage to be evaluated. The greater the deviation of the phase error from the first error range, the greater the reduction in the voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the third preset step size will be used as the new voltage to be evaluated.

[0010] Further, in one embodiment, the step of detecting whether the current voltage to be evaluated meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: Adjust the operating voltage of the critical path simulation circuit to the current voltage to be evaluated; It generates a reference clock signal and an analog input signal, wherein the phase of the reference clock signal is fixed and the phase of the analog input signal is adjustable; The analog input signal is input into the critical path analog circuit to obtain the analog delay signal; The phase detection module is input with a reference clock signal and an analog delay signal to obtain the phase detection result. The phase difference between the reference clock signal and the analog delay signal is defined as the phase error. The phase error is defined as phase alignment within the second error range and phase misalignment outside the second error range. The second error range is determined according to the timing requirements of the critical path. If the phases are aligned, then the current voltage to be evaluated is determined to meet the critical path timing requirements under the current operating conditions; If the phases are not aligned, adjust the phases of the analog input signals and regenerate the reference clock signal and analog input signals; If phase alignment cannot be achieved by iterating through the phases of all analog input signals, then the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions.

[0011] Furthermore, in one embodiment, the chip's workload is predicted based on preset factors, which include: The chip's operating frequency and operating mode The level of congestion on the system bus. The cumulative number of pending interruptions. The call status of high-load processes.

[0012] Furthermore, in one embodiment, for the MCU chip, the high-load processes include encryption / decryption processes, motor control processes, and DMA data transfer request processes; For SoC chips, high-load processes include high-definition video data encoding and decoding processes, multi-protocol communication data forwarding processes, and complex algorithm calculation processes.

[0013] Furthermore, in one embodiment, the critical path timing requirements include establishing time constraints and maintaining time constraints.

[0014] Secondly, embodiments of this application also provide a chip dynamic power consumption optimization device, the chip dynamic power consumption optimization device comprising: The first adjustment module is used to adjust the chip's operating voltage and operating frequency to the default values ​​under the current operating conditions when the chip's operating conditions change. The theoretical analysis module is used to analyze the chip's workload in real time. If the chip's workload meets the voltage reduction conditions under the current operating conditions, the minimum operating voltage that meets the critical path timing requirements under the current operating conditions is calculated based on the critical path power consumption model and is denoted as the target voltage. The second adjustment module is used to adjust the chip's operating voltage to the target voltage.

[0015] Thirdly, embodiments of this application also provide a chip that achieves power optimization through the aforementioned chip dynamic power optimization method.

[0016] In this application, when the chip's operating conditions change, the chip's operating voltage and frequency are adjusted to their default values ​​under the current operating conditions. The chip's workload is analyzed in real time. If the chip's workload meets the voltage reduction conditions under the current operating conditions, the minimum operating voltage required to meet the critical path timing requirements under the current operating conditions is calculated based on the critical path power consumption model and denoted as the target voltage. The chip's operating voltage is then adjusted to the target voltage. Through this application, the chip's operating voltage can be dynamically adjusted to match the real-time workload, significantly reducing the chip's dynamic power consumption while ensuring that critical path timing requirements are met. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a chip dynamic power consumption optimization method in one embodiment of this application; Figure 2 A schematic diagram illustrating the principle of power consumption optimization for AVS technology; Figure 3 This is a flowchart illustrating a chip dynamic power consumption optimization method in another embodiment of this application; Figure 4 A system architecture diagram for applying the chip dynamic power consumption optimization method of this application to an MCU chip; Figure 5 for Figure 4 A schematic diagram of the AVS monitoring module in the illustrated embodiment; Figure 6 for Figure 5 The internal functional structure diagram of the AVS Monitor in the embodiment shown is as follows; Figure 7 This is a schematic diagram of the functional modules of a chip dynamic power consumption optimization device in one embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0020] In a first aspect, embodiments of this application provide a method for optimizing dynamic power consumption of a chip.

[0021] Figure 1 A flowchart illustrating a chip dynamic power consumption optimization method in one embodiment of this application is shown.

[0022] Reference Figure 1 In one embodiment, the chip dynamic power consumption optimization method includes the following steps: S1. When the chip's operating conditions change, adjust the chip's operating voltage and operating frequency to the default values ​​under the current operating conditions.

[0023] Specifically, the chip stores a voltage-frequency mapping table so that the power optimization program can look up the table to determine whether the operating conditions have changed and the default values ​​of the operating voltage and operating frequency under the current operating conditions.

[0024] For example, based on chip functional requirements and post-silicon validation results, the parameters of the voltage-frequency mapping table are initially set. After chip fabrication, the operating voltage range under different PVT (process, voltage, temperature) conditions can be measured using ATE (Auto Test Equipment) probes during CP (Chip Probing) / FT (Final Test) testing to correct the voltage-frequency mapping table parameters. In subsequent chip applications, a high-precision power supply measurement instrument is used to evaluate actual power consumption, and the simulation results are compared to adjust the voltage-frequency mapping table parameters.

[0025] For example, the operating modes of an MCU (microcontroller) include startup, IDLE, encryption, motor control, ADC sampling, etc.

[0026] S2. Analyze the chip's workload in real time. If the chip's workload meets the voltage reduction conditions under the current operating conditions, calculate the minimum operating voltage that meets the critical path timing requirements under the current operating conditions based on the critical path power consumption model, and denot it as the target voltage.

[0027] Figure 2 This diagram illustrates the principle of power consumption optimization achieved by AVS technology.

[0028] AVS (Adaptive Voltage Scaling) technology dynamically manages the operating voltage within a chip to balance chip performance, power consumption, and stability, thereby reducing chip power consumption. The power consumption formula is P=C·V. 2 The expression f (where C is the capacitive load, V is the operating voltage, and f is the operating frequency) indicates that voltage has the greatest impact on power consumption; reducing the voltage can significantly reduce dynamic power consumption. The core idea of ​​AVS technology is to dynamically adjust the operating voltage based on parameters such as the chip's current operating frequency, temperature, and process deviations, minimizing power consumption while meeting performance requirements.

[0029] Specifically, in this embodiment, by analyzing the chip's workload in real time, it is determined whether there is room for further reduction in the chip's operating voltage. For example, when the workload is relatively low, the operating voltage can be further reduced to decrease power consumption.

[0030] For example, the voltage reduction condition can be expressed as: the chip's workload is below a certain threshold.

[0031] In this embodiment, the goal is to reduce the operating voltage to the required level in one go, avoiding insufficient reduction leading to additional power consumption waste, while also preventing excessive reduction from causing chip malfunctions. By establishing a critical path power consumption model, the delay characteristics of the critical path under different operating voltages, operating frequencies, and temperatures are detected, thereby calculating the minimum operating voltage that meets the timing requirements of the critical path under the current operating conditions.

[0032] Specifically, the timing requirements for the critical path include establishing time constraints and maintaining time constraints.

[0033] Setup time constraints refer to the requirement that data output from the preceding register must be transmitted and stabilized before the next clock edge, before it passes through combinational logic to the following register. Otherwise, the following register will sample unstable "erroneous data," resulting in a setup time violation. Setup time constraints are influenced by the longest combinational logic path, which has the greatest delay among all paths, dictating that the clock cycle cannot be too short.

[0034] The hold-time constraint means that after the subsequent register samples the correct data on the clock edge, the data cannot change immediately; it needs to be held for a certain period of time. Otherwise, a situation of "new data overwriting old data" will occur, causing the subsequent register to sample an incorrect value, i.e., a hold-time violation. The hold-time constraint is affected by the shortest combinational logic path. The longest combinational logic path has the least delay among all paths, but it is most likely to cause the problem of "data being transmitted too quickly."

[0035] Therefore, the critical path power consumption model needs to cover the longest and shortest combinational logic paths in each operating mode of the chip. Critical paths are typically extracted using chip static timing analysis tools. For example, the critical paths of an MCU are usually the pipeline paths for CPU instruction execution, data processing paths, and bus memory access paths.

[0036] It should be noted that in the critical path power consumption model, the timing margin of the critical path under different operating conditions needs to be set reasonably to reserve a certain adjustment space for the operating voltage. In addition, it is also necessary to ensure that the phase difference of the same critical path under FF / SS / TT is kept within the design tolerance.

[0037] S3. Adjust the chip's operating voltage to the target voltage.

[0038] Optionally, the voltage adjustment operation in steps S1 and S3 is implemented by a voltage regulator with precise voltage regulation function. It can be a device built into the chip, such as an LDO (low dropout linear regulator) or a DC / DC (direct current to direct current converter) that supports multiple adjustment levels, or it can be an external device, such as a PMIC (power management integrated circuit) chip.

[0039] Therefore, in this embodiment, when the chip's operating conditions change, the chip's operating voltage and frequency are adjusted to their default values ​​under the current operating conditions. The chip's feedback data is analyzed in real time. If the feedback data meets the voltage reduction conditions under the current operating conditions, the minimum operating voltage required to meet the critical path timing requirements under the current operating conditions is calculated based on the critical path power consumption model and denoted as the target voltage. The chip's feedback data includes the chip's workload and temperature. The chip's operating voltage is then adjusted to the target voltage. Through this embodiment, the chip's operating voltage can be dynamically adjusted to match the real-time workload, significantly reducing the chip's dynamic power consumption while ensuring that critical path timing requirements are met.

[0040] Figure 3 A flowchart illustrating a chip dynamic power consumption optimization method according to another embodiment of this application is shown.

[0041] Furthermore, in one embodiment, the chip dynamic power consumption optimization method further includes: If an abnormal alarm occurs within one monitoring cycle after the chip's operating voltage is adjusted to the target voltage, the chip's operating voltage will be increased by the first preset step. If an abnormal alarm occurs within one monitoring cycle after the chip's operating voltage is increased, the chip's operating voltage will be increased by the first preset step.

[0042] Reference Figure 3In this embodiment, considering that the target voltage analyzed by the critical path power consumption model is not entirely reliable, the abnormal alarm function in the chip is combined to qualitatively determine whether the voltage reduction is too large. If the reduction is found to be too large, the chip's operating voltage is increased in steps such as iteration strategy until no abnormal alarm occurs.

[0043] Furthermore, in one embodiment, the step of calculating the minimum operating voltage that meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the difference between the default value of the chip's operating voltage under the current operating conditions and the second preset step size. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then the difference between the current voltage to be evaluated and the second preset step size is taken as the new voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the second preset step size shall be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions.

[0044] In this embodiment, an iterative strategy is used to decrease the voltage to be evaluated in equal steps when calculating the minimum operating voltage, until the voltage to be evaluated no longer meets the timing requirements of the critical path. The previous voltage to be evaluated is then taken as the minimum operating voltage. This simplifies the calculation process and facilitates program implementation.

[0045] Furthermore, in one embodiment, the step of calculating the minimum operating voltage that meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the default value of the chip's operating voltage under the current operating conditions. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then check whether the current phase error meets the iteration termination condition. If the current phase error is within the first error range, then the current voltage to be evaluated will be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions. If the current phase error is outside the first error range, a new voltage to be evaluated is calculated based on the current phase error and the voltage to be evaluated. The greater the deviation of the phase error from the first error range, the greater the reduction in the voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the third preset step size will be used as the new voltage to be evaluated.

[0046] In this embodiment, an iterative strategy is used to adjust the voltage to be evaluated when calculating the minimum operating voltage until the voltage meets the critical path timing requirements and the phase error is within a first error range. The difference between this embodiment and the previous one is that the adjustment of the voltage to be evaluated is not in constant steps; the adjustment direction is determined based on whether the voltage meets the critical path timing requirements, and the adjustment amount is determined based on the deviation of the phase error from the first error range. This improves the iterative convergence speed while ensuring the precision of the voltage adjustment.

[0047] Further, in one embodiment, the step of detecting whether the current voltage to be evaluated meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: Adjust the operating voltage of the critical path simulation circuit to the current voltage to be evaluated; It generates a reference clock signal and an analog input signal, wherein the phase of the reference clock signal is fixed and the phase of the analog input signal is adjustable; The analog input signal is input into the critical path analog circuit to obtain the analog delay signal; The phase detection module is input with a reference clock signal and an analog delay signal to obtain the phase detection result. The phase difference between the reference clock signal and the analog delay signal is defined as the phase error. The phase error is defined as phase alignment within the second error range and phase misalignment outside the second error range. The second error range is determined according to the timing requirements of the critical path. If the phases are aligned, then the current voltage to be evaluated is determined to meet the critical path timing requirements under the current operating conditions; If the phases are not aligned, adjust the phases of the analog input signals and regenerate the reference clock signal and analog input signals; If phase alignment cannot be achieved by iterating through the phases of all analog input signals, then the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions.

[0048] Specifically, the critical path simulation circuit is built using standard gate devices, timing buffers, diffusion capacitors, etc., to simulate the critical path delay based on the critical path identified by static timing analysis.

[0049] In this embodiment, the reference clock signal, analog input signal, and analog delay signal are all analog electrical signals. By adjusting the voltage of the critical path simulation circuit and inputting the analog input signal into the critical path simulation circuit to simulate the delay of the critical path, the accuracy of the target voltage can be improved.

[0050] Specifically, in the second iteration strategy mentioned above, the first error range is a sub-interval of the second error range. The phase error amount is within the first error range, which not only means that the current voltage to be evaluated meets the critical path timing requirements, but also means that the current voltage to be evaluated has been adjusted in place. If further adjustments are made, the critical path timing requirements will not be met.

[0051] In related technologies, chip back-end simulation tools are used to simulate and estimate the critical path delay of the chip under test under different PVT (Programmable Voltage Transmission) values. A model of the chip's critical path is simulated using different Vt (StdCell) ratios, and this model is used to establish a software entry for subsequent voltage adjustments. Essentially, this is a mathematical model or table lookup method, and its accuracy is relatively lower compared to the analog circuit implementation in this embodiment.

[0052] Furthermore, in one embodiment, the chip's workload is predicted based on preset factors, which include: The chip's operating frequency and operating mode The level of congestion on the system bus. The cumulative number of pending interruptions. The call status of high-load processes.

[0053] Furthermore, in one embodiment, for the MCU chip, the high-load processes include encryption / decryption processes, motor control processes, and DMA data transfer request processes; For SoC chips, high-load processes include high-definition video data encoding and decoding processes, multi-protocol communication data forwarding processes, and complex algorithm calculation processes.

[0054] It should be noted that, due to the different hardware configurations of different chips, some chips do not require external hardware to implement the steps of this application. For example, MCU chips can store power optimization programs and voltage-frequency mapping tables in the built-in FLASH and use the internal PMU to control LDO or DC / DC to perform voltage adjustment. Other chips require external hardware, such as SoC chips (system-on-a-chip), which usually require external high-capacity high-speed storage (DDR or SSD, etc.) to store power optimization programs and voltage-frequency mapping tables, and external PMIC to perform voltage adjustment.

[0055] Figure 4 A system architecture diagram is shown for applying the chip dynamic power consumption optimization method of this application to an MCU chip.

[0056] Reference Figure 4The MCU chip includes a CPU, bus, temperature monitoring module, AVS monitoring module, voltage management module, alarm monitoring module, CPU load monitoring module, bus flow monitoring module, clock management module, PMU (Power Management Module), OTP (One-Time Programmable Memory), SRAM, and FLASH.

[0057] Figure 5 It shows Figure 4 The illustrated embodiment is a schematic diagram of the AVS monitoring principle.

[0058] Reference Figure 5 Each AVS Monitor is responsible for monitoring the delay characteristics of a corresponding critical path under different operating voltages, operating frequencies, and temperatures. It outputs the phase monitoring results (whether timing requirements are met, and the phase error when timing requirements are met) corresponding to the voltage to be evaluated to the Monitor control module, which is responsible for summarizing and sending them to the PMU.

[0059] Figure 6 It shows Figure 5 The internal functional structure diagram of the AVS Monitor in the illustrated embodiment is shown.

[0060] Reference Figure 6 The functional implementation process of AVS Monitor is as follows: a) Modify the LDO regulator to configure the voltage of the critical path simulation circuit to the initial voltage to be evaluated; b) The clock generator generates a reference clock signal (pulse signal) and a preliminary delay signal; c) After the initial delay signal is input to the adjustable delay line function module, the analog input signal is output; d) After the analog input signal is input to the critical path analog circuit, the analog delay signal is output; e) After the reference clock signal and analog delay signal are input to the phase detection module, the phase detection result is output; f) After the phase detection result is input into the Monitor control module, if the phases are aligned, proceed to step g; if the phases are not aligned, proceed to step h. g) If the phase error is within the first error range, the Monitor control module determines that the voltage adjustment is in place and takes the current voltage to be evaluated as the target voltage; if the phase error is outside the first error range, the Monitor control module determines that the voltage can be further reduced, calculates the voltage adjustment amount based on the deviation between the phase error and the first error range, sends the voltage reduction amount to the AVS control module, and the AVS control module notifies the PMU to control the LDO voltage regulator to modify the voltage to be evaluated. h) Generate analog input signals of different phases by using a clock generator and an adjustable delay line function module, and repeat steps b to e; i) If phase alignment cannot be achieved by iterating through the phases of all analog input signals, the Monitor control module determines that the voltage is too high and sends the voltage increase amount (corresponding to the third preset step size) to the AVS control module. The AVS control module then notifies the PMU to control the LDO voltage regulator to modify the voltage to be evaluated.

[0061] It should be noted that, Figure 6 In the embodiment shown, a preliminary delay signal is first generated by a clock generator, and then the phase is finely adjusted by an adjustable delay line function module to obtain an analog input signal, thereby achieving fine and complete phase adjustment at a low hardware cost.

[0062] For example, the clock generator can generate clk0, clk1, clk2, and clk3, with phase differences of 0°, 90°, 180°, and 270° from the pulse signal, respectively. One of them is taken as the initial delay signal each time, and the phase adjustment range of the adjustable delay line function module is 0-90°.

[0063] Secondly, embodiments of this application also provide a chip dynamic power consumption optimization device.

[0064] Figure 7 A schematic diagram of the functional modules of a chip dynamic power consumption optimization device in one embodiment of this application is shown.

[0065] Reference Figure 7 In one embodiment, the chip dynamic power consumption optimization device includes: The first adjustment module 10 is used to adjust the chip's operating voltage and operating frequency to the default values ​​under the current operating conditions when the chip's operating conditions change. Theoretical analysis module 20 is used to analyze the chip's workload in real time. If the chip's workload meets the voltage reduction condition under the current operating conditions, the minimum operating voltage that meets the critical path timing requirements under the current operating conditions is calculated based on the critical path power consumption model and is denoted as the target voltage. The second adjustment module 30 is used to adjust the chip's operating voltage to the target voltage.

[0066] Furthermore, in one embodiment, the chip dynamic power consumption optimization device further includes a third adjustment module, used for: If an abnormal alarm occurs within a preset time after the chip's operating voltage is adjusted to the target voltage, the chip's operating voltage will be increased by a first preset step. If an abnormal alarm occurs within a preset time after the chip's operating voltage is increased, the chip's operating voltage will continue to be increased by the first preset step.

[0067] Furthermore, in one embodiment, the theoretical analysis module 20 is used for: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the difference between the default value of the chip's operating voltage under the current operating conditions and the second preset step size. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then the difference between the current voltage to be evaluated and the second preset step size is taken as the new voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the second preset step size shall be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions.

[0068] Furthermore, in one embodiment, the theoretical analysis module 20 is used for: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the default value of the chip's operating voltage under the current operating conditions. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then check whether the current phase error meets the iteration termination condition. If the current phase error is within the first error range, then the current voltage to be evaluated will be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions. If the current phase error is outside the first error range, a new voltage to be evaluated is calculated based on the current phase error and the voltage to be evaluated. The greater the deviation of the phase error from the first error range, the greater the reduction in the voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the third preset step size will be used as the new voltage to be evaluated.

[0069] Furthermore, in one embodiment, the theoretical analysis module 20 is used for: Adjust the operating voltage of the critical path simulation circuit to the current voltage to be evaluated; It generates a reference clock signal and an analog input signal, wherein the phase of the reference clock signal is fixed and the phase of the analog input signal is adjustable; The analog input signal is input into the critical path analog circuit to obtain the analog delay signal; The phase detection module is input with a reference clock signal and an analog delay signal to obtain the phase detection result. The phase difference between the reference clock signal and the analog delay signal is defined as the phase error. The phase error is defined as phase alignment within the second error range and phase misalignment outside the second error range. The second error range is determined according to the timing requirements of the critical path. If the phases are aligned, then the current voltage to be evaluated is determined to meet the critical path timing requirements under the current operating conditions; If the phases are not aligned, adjust the phases of the analog input signals and regenerate the reference clock signal and analog input signals; If phase alignment cannot be achieved by iterating through the phases of all analog input signals, then the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions.

[0070] Furthermore, in one embodiment, the chip's workload is predicted based on preset factors, which include: The chip's operating frequency and operating mode The level of congestion on the system bus. The cumulative number of pending interruptions. The call status of high-load processes.

[0071] Furthermore, in one embodiment, for the MCU chip, the high-load processes include encryption / decryption processes, motor control processes, and DMA data transfer request processes; For SoC chips, high-load processes include high-definition video data encoding and decoding processes, multi-protocol communication data forwarding processes, and complex algorithm calculation processes.

[0072] Furthermore, in one embodiment, the critical path timing requirements include establishing time constraints and maintaining time constraints.

[0073] The functions of each module in the above-mentioned chip dynamic power consumption optimization device correspond to the steps in the above-mentioned chip dynamic power consumption optimization method embodiment, and their functions and implementation processes will not be described in detail here.

[0074] Thirdly, embodiments of this application provide a chip, such as an MCU chip or a SoC chip, which achieves power optimization through the aforementioned chip dynamic power optimization method.

[0075] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0076] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.

[0077] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.

[0078] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0079] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.

[0080] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as OTP, SRAM, FLASH) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.

[0081] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for optimizing dynamic power consumption of a chip, characterized in that, The chip dynamic power consumption optimization method includes: When the chip's operating conditions change, adjust the chip's operating voltage and operating frequency to the default values ​​under the current operating conditions; The chip's workload is analyzed in real time. If the chip's workload meets the voltage reduction condition under the current operating conditions, the minimum operating voltage that meets the critical path timing requirements under the current operating conditions is calculated based on the critical path power consumption model and denoted as the target voltage. Adjust the chip's operating voltage to the target voltage.

2. The chip dynamic power optimization method of claim 1, wherein, The chip dynamic power consumption optimization method also includes: If an abnormal alarm occurs within a preset time after the chip's operating voltage is adjusted to the target voltage, the chip's operating voltage will be increased by a first preset step. If an abnormal alarm occurs within a preset time after the chip's operating voltage is increased, the chip's operating voltage will continue to be increased by the first preset step.

3. The chip dynamic power optimization method of claim 1, wherein, The step of calculating the minimum operating voltage that meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the difference between the default value of the chip's operating voltage under the current operating conditions and the second preset step size. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then the difference between the current voltage to be evaluated and the second preset step size is taken as the new voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the second preset step size shall be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions.

4. The chip dynamic power optimization method of claim 1, wherein, The step of calculating the minimum operating voltage that meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: The current voltage to be evaluated is determined based on the critical path power consumption model to determine whether it meets the critical path timing requirements under the current operating conditions. The initial voltage to be evaluated is equal to the default value of the chip's operating voltage under the current operating conditions. If the current voltage to be evaluated meets the critical path timing requirements under the current operating conditions, then check whether the current phase error meets the iteration termination condition. If the current phase error is within the first error range, then the current voltage to be evaluated will be taken as the minimum operating voltage that meets the critical path timing requirements under the current operating conditions. If the current phase error is outside the first error range, a new voltage to be evaluated is calculated based on the current phase error and the voltage to be evaluated. The greater the deviation of the phase error from the first error range, the greater the reduction in the voltage to be evaluated. If the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions, then the sum of the current voltage to be evaluated and the third preset step size will be used as the new voltage to be evaluated.

5. The chip dynamic power optimization method of claim 3 or 4, wherein, The step of detecting whether the current voltage to be evaluated meets the critical path timing requirements under the current operating condition based on the critical path power consumption model includes: Adjust the operating voltage of the critical path simulation circuit to the current voltage to be evaluated; It generates a reference clock signal and an analog input signal, wherein the phase of the reference clock signal is fixed and the phase of the analog input signal is adjustable; The analog input signal is input into the critical path analog circuit to obtain the analog delay signal; The phase detection module is input with a reference clock signal and an analog delay signal to obtain the phase detection result. The phase difference between the reference clock signal and the analog delay signal is defined as the phase error. The phase error is defined as phase alignment within the second error range and phase misalignment outside the second error range. The second error range is determined according to the timing requirements of the critical path. If the phases are aligned, then the current voltage to be evaluated is determined to meet the critical path timing requirements under the current operating conditions; If the phases are not aligned, adjust the phases of the analog input signals and regenerate the reference clock signal and analog input signals; If phase alignment cannot be achieved by iterating through the phases of all analog input signals, then the current voltage to be evaluated does not meet the critical path timing requirements under the current operating conditions.

6. The method of claim 1, wherein, The chip's workload is predicted based on preset factors, which include: The chip's operating frequency and operating mode The level of congestion on the system bus. The cumulative number of pending interruptions. The call status of high-load processes.

7. The chip dynamic power optimization method of claim 6, wherein, For MCU chips, high-load processes include encryption / decryption processes, motor control processes, and DMA data transfer request processes. For SoC chips, high-load processes include high-definition video data encoding and decoding processes, multi-protocol communication data forwarding processes, and complex algorithm calculation processes.

8. The method of claim 1, wherein, The timing requirements for the critical path include establishing time constraints and maintaining time constraints.

9. A chip dynamic power optimization apparatus, comprising: The chip dynamic power consumption optimization device includes: The first adjustment module is used to adjust the chip's operating voltage and operating frequency to the default values ​​under the current operating conditions when the chip's operating conditions change. The theoretical analysis module is used to analyze the chip's workload in real time. If the chip's workload meets the voltage reduction conditions under the current operating conditions, the minimum operating voltage that meets the critical path timing requirements under the current operating conditions is calculated based on the critical path power consumption model and is denoted as the target voltage. The second adjustment module is used to adjust the chip's operating voltage to the target voltage.

10. A chip, characterized by Power optimization is achieved through the chip dynamic power optimization method as described in any one of claims 1 to 8.

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