System and method for data access management based on pairing check between command queues

Abstract

Systems and methods for data access management are provided. In one embodiment, a method includes determining, by a device, that a first command in a first command queue of the device and a second command in a second command queue of the device are associated with a same address in a memory, the first command queue configured to store a command type different from a command type of the second command queue, the method further includes determining that the first command has a higher execution priority than the second command, sending, by the device, the first command for execution, and applying, by the device, a hold to the second command such that the second command is retained in the second command queue based on the first command being executed.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to U.S. Provisional Application No. 63 / 708,597, entitled “DATA ACCESS BASED ON AXI WITH DATA COHERENCE”, filed October 17, 2024; U.S. Non-Provisional Application No. 19 / 187,922, filed April 23, 2025; and Korean Patent Application No. 10-2025-138474, filed September 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some aspects of embodiments of this disclosure relate to systems and methods for data access management. Background Technology

[0004] In the field of computing, a computing system may include one or more hosts and one or more memory devices connected to (e.g., communicatively coupled to) said one or more hosts. Such computing systems have become increasingly popular, in part because they allow many different users to share the system's computing resources. As the number of users of such systems, as well as the number and complexity of applications running on such systems, increase, the demand for memory also increases over time.

[0005] This background section is intended to provide context only, and the disclosure of any embodiments or concepts in this section does not constitute an admission that the embodiments or concepts are prior art. Summary of the Invention

[0006] Some aspects of embodiments of this disclosure relate to computing systems for improved data access management.

[0007] According to some embodiments of this disclosure, a method for data access management is provided, the method comprising: determining by a device that a first command in a first command queue of the device and a second command in a second command queue of the device are associated with the same address in memory, the first command queue being configured to store command types different from those in the second command queue; determining that the first command has a higher execution priority than the second command; sending the first command by the device for execution; and imposing a hold on the second command by the device such that the second command is held in the second command queue based on the first command being executed.

[0008] The method may also include the device sending a third command from the second command queue for execution, the third command being later in the second command queue than the second command.

[0009] Sending a first command to execute may include: the device sending the first command to the slave device via an on-chip communication bus protocol, and the on-chip communication bus protocol may be the Advanced Extensible Interface (AXI) protocol.

[0010] The memory may include volatile memory or non-volatile memory, and the slave device may include a controller associated with one of the volatile memory or non-volatile memory.

[0011] The command type can be either a read command or a write command.

[0012] The first command may include a first read command, the first command queue may include a read command queue, the second command may include a first write command, and the second command queue may include a write command queue.

[0013] The first command may include a first write command, the first command queue may include a write command queue, the second command may include a first read command, and the second command queue may include a read command queue.

[0014] The method may further include generating priority information in a register by the device, the register including an identifier for a first command and an identifier for a second command, wherein determining that the first command has a higher execution priority than the second command may include reading the priority information from the register by the device.

[0015] The method may further include the device determining that a fourth command in the device's first command queue and a fifth command in the device's second command queue are also associated with the same address in the memory, and the device determining that the first command and the second command have a higher execution priority based on fields in a register, the register including information that associates the fourth command with the fifth command.

[0016] The method may further include the device determining that the first command and the second command are valid commands and generating a validity determination, wherein the device performs a determination that the first command and the second command are associated with the same address based on the validity determination.

[0017] According to some other embodiments of this disclosure, a system for data access management is provided, the system comprising: a bridging device connected to a master device and a slave device; and a controller of the slave device communicatively coupled to the bridging device, wherein the bridging device is configured to perform: determining that a first command in a first command queue of the bridging device and a second command in a second command queue of the bridging device are associated with the same address in a memory associated with the controller, the first command queue being configured to store command types different from those in the second command queue; determining that the first command has a higher execution priority than the second command; sending the first command for execution; and applying a hold condition to the second command such that the second command is held in the second command queue based on the first command being executed.

[0018] The bridging device can be configured to execute a third command sent from the second command queue, the third command being later in the second command queue than the second command.

[0019] Sending the first command to execute may include sending the first command to the controller via an on-chip communication bus protocol by the bridging device, and the on-chip communication bus protocol may be the Advanced Extensible Interface (AXI) protocol.

[0020] The command type can be either a read command or a write command.

[0021] The memory may include volatile memory or non-volatile memory, and the controller may be associated with volatile memory or non-volatile memory.

[0022] The first command may include a first read command, the first command queue may include a read command queue, the second command may include a first write command, and the second command queue may include a write command queue.

[0023] The first command may include a first write command, the first command queue may include a write command queue, the second command may include a first read command, and the second command queue may include a read command queue.

[0024] The bridging device can be configured to execute priority information in a generation register, which may include an identifier for a first command and an identifier for a second command, and determining that the first command has a higher execution priority than the second command may include reading the priority information from the register.

[0025] The bridging device can be configured to execute a fourth command in a first command queue of the bridging device and a fifth command in a second command queue of the bridging device that are also associated with the same address in memory, and to determine by the bridging device that the first and second commands have a higher execution priority based on fields in a register, the register including information that associates the fourth and fifth commands.

[0026] According to some other embodiments of this disclosure, a system for data access management is provided, the system including processing circuitry and a non-transitory computer-readable medium storing instructions that, upon execution by the processing circuitry, cause the processing circuitry to perform actions such as determining that a first command in a first command queue and a second command in a second command queue are associated with the same address in memory, the first command queue being configured to store command types different from those in the second command queue, determining that the first command has a higher execution priority than the second command, sending the first command for execution, and applying a hold condition to the second command such that the second command is held in the second command queue based on the first command being executed. Attached Figure Description

[0027] Non-limiting and non-exhaustive embodiments of this disclosure are described with reference to the following figures, wherein, unless otherwise stated, the same reference numerals refer to the same parts in the various figures.

[0028] Figure 1 This is a block diagram depicting a system for data access management according to some embodiments of the present disclosure.

[0029] Figure 2A This is a diagram depicting a method for pairing checks between command queues according to some embodiments of the present disclosure.

[0030] Figure 2B This describes some embodiments of the present disclosure for performing in Figure 2A The diagram depicts the pairing check registers for pairing checks between command queues.

[0031] Figure 3 This is a block diagram depicting a method for data access management according to some embodiments of the present disclosure, the method having operations for processing commands that do not have the same address pair and operations for processing commands that have the same address pair.

[0032] Figure 4 This is a block diagram depicting a system for data access management using a multiplexed and write-to-data buffer memory according to some embodiments of the present disclosure.

[0033] Figure 5 This is a diagram depicting a method for data access management according to some embodiments of the present disclosure, the method having a determining operation for pairing checks between command queues.

[0034] Throughout the various views of the accompanying drawings, corresponding figure characters indicate the corresponding components. Those skilled in the art will understand that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements, layers, and areas in the drawings may be exaggerated relative to other elements, layers, and areas to help improve the clarity and understanding of the various embodiments. Furthermore, common but well-understood elements and components unrelated to the description of the embodiments may not be shown to help to less obstruct the views of these various embodiments and to make the description clearer. Detailed Implementation

[0035] The aspects of this disclosure and its implementation methods can be more readily understood by referring to the detailed description and accompanying drawings of one or more embodiments. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be sufficient and complete, and will fully convey the aspects of this disclosure to those skilled in the art; therefore, descriptions of processes, elements, and techniques unnecessary for those skilled in the art to fully understand the aspects and features of this disclosure may be omitted.

[0036] Unless otherwise stated, the same reference numerals, characters, or combinations thereof denote the same elements throughout the drawings and written description, and therefore their description will not be repeated. Those skilled in the art will understand that the elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements, layers, and areas in the drawings may be exaggerated relative to other elements, layers, and areas to help improve the clarity and understanding of the various embodiments. Furthermore, common but well-understood elements and components unrelated to the description of the embodiments may not be shown to help to less obstruct the view of these various embodiments and to make the description clearer.

[0037] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a full understanding of the various embodiments. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements.

[0038] It will be understood that although the terms “zeroth,” “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or section described below may be referred to as the second element, component, region, layer, or section.

[0039] It will be understood that when an element or component is referred to as being "on," "connected to," or "coupled to" another element or component, it can be directly on, directly connected to, or coupled to the other element or component, or there can be one or more intermediate elements or components. However, "direct connection / direct coupling" means that one component is directly connected to or coupled to another component without any intermediate components. Similarly, other expressions describing relationships between components, such as "between," "directly between," or "adjacent to" and "directly adjacent to," can be interpreted in a similar way. Furthermore, it will be understood that when an element or component is referred to as being "between" two elements or components, it can be the only element or component between the two elements or components, or there can be one or more intermediate elements or components.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “having,” and “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, each of the terms “or” and “and / or” includes any one of the associated listed items and all combinations of one or more. For example, the expression “A and / or B” means A, B, or A and B.

[0041] For the purposes of this disclosure, expressions such as “at least one of…” modify the entire list of elements when they follow the list of elements, and not the individual elements in the list. For example, “at least one of X, Y or Z,” “at least one of X, Y and Z,” and “at least one selected from the group consisting of X, Y and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y and Z, such as XYZ, XYY, YZ, and ZZ.

[0042] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to describe the inherent bias of a measured or calculated value that will be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” encompasses the value and means within an acceptable range of deviation for a particular value, as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the value. Furthermore, the use of “may” in describing embodiments of this disclosure means “one or more embodiments of this disclosure.”

[0043] When one or more embodiments can be implemented differently, a particular order of processing can be performed differently from the order in which they are described. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0044] (For example, in any system diagram included herein) any component or combination of components described may be used to perform one or more of the operations in any flowchart included herein. Furthermore, (i) the operations are merely examples and may involve various additional operations not explicitly covered, and (ii) the temporal order of the operations may vary.

[0045] The electronic or electrical devices and / or any other related devices or components according to embodiments of this disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices may be formed on an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices may be implemented on a flexible printed circuit film, tape-on-a-carrier package (TCP), printed circuit board (PCB), or formed on a substrate.

[0046] Furthermore, the various components of these devices may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices such as, for example, random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as, for example, CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0047] Any functionality described herein, including any functionality that can be implemented by a host, device, or combination thereof, can be implemented by hardware, software, firmware, or any combination thereof, including, for example, hardware and / or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memory (such as dynamic RAM (DRAM) and / or static RAM (SRAM)), non-volatile memory (including flash memory), persistent memory (such as cross-grid non-volatile memory, volume resistance varying memory, phase change memory (PCM), etc.) and / or any combination thereof, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), etc., including complex instruction set computer (CISC) processors and / or reduced instruction set computer (RISC) processors, which execute instructions stored in any type of memory. In some embodiments, one or more components may be implemented as a system-on-a-chip (SoC).

[0048] Any computing device disclosed herein may be implemented using any connector configuration such as Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), U.2, etc., in any form factor such as 3.5-inch, 2.5-inch, 1.8-inch, M.2, Enterprise and Data Center Standard Form Factors (EDSFF, NF1, etc.). Any computing device disclosed herein may be implemented entirely or partially using server chassis, server racks, data centers, data centers, edge data centers, mobile edge data centers, and / or any combination thereof.

[0049] Any device disclosed herein that can be implemented as a storage device can be implemented using any type of non-volatile storage medium based on solid-state media, magnetic media, optical media, etc. For example, in some embodiments, the storage device (e.g., a computing storage device) can be implemented as an SSD based on NAND flash memory, persistent memory such as cross-grid non-volatile memory, volume resistance variable memory, PCM, etc., or any combination thereof.

[0050] Any communication connection and / or communication interface disclosed herein may be implemented using any type of interface and / or protocol, utilizing one or more interconnects, one or more networks, networks of networks (e.g., the Internet), or combinations thereof. Examples include Fast Peripheral Component Interconnect (PCIe), Fast Non-Volatile Memory (NVMe), Network-based NVMe (NVMe-over-fabric, NVMe-oF), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, SATA, SCSI, SAS, Internet Wide Area RDMA Protocol (iWARP), and / or coherence protocols (such as Compute Express Link (CXL), CXL.mem, CXL.cache, CXL.10, etc.), Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Accelerator Cache Coherent Interconnect (CCIX), Advanced Scalable Interface (AXI), including any generation of wireless networks such as 2G, 3G, 4G, 5G, 6G, etc., any generation of Wi-Fi, Bluetooth, Near Field Communication (NFC), etc., or any combination thereof.

[0051] In some embodiments, the software stack may include a communication layer that implements one or more communication interfaces, protocols, such as PCIe, NVMe, CXL, Ethernet, NVMe-oF, TCP / IP, etc., to enable the host and / or applications running on the host to communicate with computing devices or storage devices.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in their idealized or overly literal sense unless expressly defined herein.

[0053] As described above, in the field of computing, a computing system may include one or more hosts and one or more memory devices, such as storage devices, connected to (e.g., communicatively coupled to) one or more hosts. For example, a data center may perform data access management to provide users with computing resources from one or more hosts and / or one or more memory devices. Computing resources may be provided based on multiple interconnect nodes in the computing system. For example, a first node may include a master device (e.g., a host), and a second node may include a slave device (e.g., a controller for a storage device). The slave device may provide an interface operating according to an on-chip communication bus protocol (e.g., AXI) to allow access to data associated with the slave device. As used herein, an "on-chip communication bus protocol" refers to a protocol that enables communication between components of one or more integrated circuits (e.g., between Internet Protocol (IP) blocks, devices, sub-circuits, etc.). For example, AXI is an on-chip communication bus protocol that can be used as a protocol for separating combined read and write channels into separate read channels and separate write channels. One of the features (e.g., a key feature) of the AXI protocol is separate read and write data channels. To improve data access efficiency, the system may be suitably configured to include multiple (e.g., many) read and write command queues to allow the system to change the order in which commands are executed. The system may also be suitable for providing data consistency between read and write commands associated with the same address.

[0054] Problems can arise in systems that include multiple read and write command queues. In some systems, to ensure data consistency, a single command queue (e.g., a first-in-first-out (FIFO) queue) can be implemented to handle both read and write commands to provide data consistency. As used herein, "data consistency" refers to maintaining the relative order (e.g., sequence) of executing two or more commands. For example, the first command might be a write command to add new data to a given memory location, and the second command might be a read command to read new data from a given memory location. If the second command (to read data from a given memory location) is executed before the first command writes new data to the given memory location, the system's data may become inconsistent.

[0055] A system that provides a single command queue that includes both read and write commands may be able to provide data consistency. However, such a system may be less efficient compared to other systems because each command received later in the FIFO queue may have to wait for each earlier command to be executed before the later command can be executed.

[0056] In some systems, to improve performance (e.g., to reduce latency), two separate command queues can be provided. For example, a first command queue can be provided to manage write commands, and a second command queue can be provided to manage read commands. However, due to uneven data traffic between the two queues, read and write commands associated with the same memory location may be executed out of order, resulting in data mismatch (e.g., inconsistency).

[0057] Some embodiments of this disclosure provide systems and methods with improved performance and improved data consistency, based on: pairing checks between commands in a read queue and commands in a write queue; ensuring the execution order of command pairs with the same address; and reordering later-received commands to be executed before earlier-received commands, which are kept in the queue to maintain data consistency with the other half of their same-address command pairs.

[0058] Figure 1 This is a block diagram depicting a system 1 for data access management according to some embodiments of the present disclosure.

[0059] refer to Figure 1 System 1 may include a master device 100 (e.g., an AXI master device) and a slave device 220 (e.g., an AXI slave device). In some embodiments, the master device 100 may be a host that sends data access commands (e.g., read and write commands) to the slave device 220. In some embodiments, the slave device 220 may be a controller that performs operations associated with the data access commands on data in a memory 230 communicatively coupled to the slave device 220. In some embodiments, the slave device 220 may be a volatile memory controller (e.g., a DRAM controller), and the memory 230 may include volatile memory (e.g., it may include DRAM). In some embodiments, the slave device 220 may be a non-volatile memory controller (e.g., a NAND flash memory controller), and the memory 230 may include non-volatile memory (e.g., it may include NAND flash memory). The memory 230 may include memory locations identified by addresses. For example, the memory 230 may include a first address A1 (e.g., a first memory location), a second address A2 (e.g., a second memory location), and an Nth address AN (e.g., an Nth memory location).

[0060] In some embodiments, master device 100 may be communicatively connected to slave device 220 via bridging device 300. Bridging device 300 may include a first queue Q1 (e.g., a first command queue, such as a read command queue). Bridging device 300 may include a second queue Q2 (e.g., a second command queue, such as a write command queue). In some embodiments, first queue Q1 stores commands having a first command type (e.g., a read command), which is different from a second command type (e.g., a write command) stored in second queue Q2. In some embodiments, first queue Q1 may store only commands of the first command type (e.g., it may store only read commands and not write commands), and second queue Q2 may store only commands of the second command type (e.g., it may store only write commands and not read commands).

[0061] The first queue Q1 and the second queue Q2 may each include N registers (e.g., first register R1 to Nth register RN). The bridging device 300 may include one or more pair checking registers (PCRs). In some embodiments, the bridging device 300 may include N pair checking registers (PCRs) equal to the number of registers R in each of the first queue Q1 and the second queue Q2. In some embodiments, the bridging device 300 may be implemented in hardware. As discussed in further detail below, the bridging device 300 may be provided between the master device 100 and the slave device 220 to provide improved performance and / or improved data consistency based on pair checking between the first queue Q1 and the second queue Q2.

[0062] In some embodiments, the bridging device 300 may be located within the storage device 200. For example, the bridging device 300 may be provided together with the slave device 220 and the memory 230 as a component of the storage device 200. However, this disclosure is not limited thereto. For example, in some embodiments, the bridging device 300 may be located within the master device 100, or it may be located in a device external to both the master device 100 and the storage device 200.

[0063] Figure 2A This is a diagram depicting a method for pairing checks between command queues according to some embodiments of the present disclosure.

[0064] Figure 2B This describes some embodiments of the present disclosure for use in Figure 2A The diagram depicts the pairing check register (PCR) that performs pairing checks between command queues.

[0065] Reference Figure 2AThe bridging device 300 may include a first queue Q1 and a second queue Q2. For example, the first queue Q1 may be a read command queue (also called a read queue), and the second queue Q2 may be a write command queue (also called a write queue). Each queue may include N registers R (e.g., N command registers). Each given command in each given register R may be associated with an identifier ID. In some implementations, the identifier ID may be controlled by the master device 100 and applied to (e.g., assigned to) each given command. For example, according to the AXI protocol, each command may have an identifier ID and may be associated with address information. For instance, in the AXI protocol, a read command may have ARID and ARADDR (e.g., may be associated with them), and a write command may have AWID and AWADDR (e.g., may be associated with them). AWID may be associated with an AXI write channel, and ARID may be associated with an AXI read channel. The identifier IDs (e.g., ARID and AWID) may be controlled by the master AXI (e.g., the host) and may not indicate the relative priority of the processed commands. In some embodiments, priority can be determined using a FIFO scheme unless a given command is associated with a valid pair check register (PCR), as discussed in further detail below.

[0066] like Figure 2A As shown, the identifier ID of the command in the first register R1 of the first queue Q1 is 0, and the identifier ID of the command in the fourth register R4 of the first queue Q1 is 3. However, it should be understood that this disclosure is not limited to having identifier IDs that correspond to the order of the registers R within a given command queue. For example, the identifier ID may include (e.g., could be) any appropriate unique identifier used to distinguish two given commands. For example, in AXI, each command may have a unique identifier ID provided by the master device 100.

[0067] In some embodiments, bridging device 300 can determine whether a given register R in the first queue Q1 and / or the second queue Q2 contains a valid command. For example, some registers R in the queue may not contain commands. Registers R without commands can be considered invalid. Bridging device 300 can determine (e.g., can check) whether any valid command in the first queue Q1 (e.g., a read queue) and the second queue Q2 (e.g., a write queue) is related to memory 230 (see [link to memory 230]). Figure 1 Commands in the same queue Q1 and the same queue Q2 associated with the same memory location (e.g., the same or overlapping address AD or address range) can be referred to as a pair of PRs (e.g., the same address pair). The bridging device 300 can store information used to manage each pair of PRs in the pairing check register PCR (see...). Figure 2B For example, in some embodiments, the bridging device 300 may generate information (e.g., priority information) in each pairing check register (PCR) to determine whether a read command has a higher priority than a write command paired with that read command, or whether a write command has a higher priority than a read command.

[0068] In some embodiments, each pair check register (PCR) may include information for determining the order in which each pair of commands is processed relative to each other. In some embodiments, each pair check register (PCR) may include information for determining the order in which commands of each pair are processed relative to commands of other pair check registers (PCRs).

[0069] For example, in some embodiments, a first segment of the Pairing Check Register (PCR) (e.g., the Validity Field V) may include information for determining whether a given PCR includes information about a valid pair of PRs (e.g., information for determining whether a given PCR includes information about a given command pair of PRs). In some embodiments, a second segment (e.g., the Read ID Field RID) may include an identifier ID of a given paired read command (e.g., a given paired read command from a first queue Q1). In some embodiments, a third segment (e.g., the Read Priority Field RP) may include information for determining whether a read command has an execution priority higher than its paired write command. In some embodiments, a fourth segment (e.g., the Write ID Field WID) may include an identifier ID of a given paired write command (e.g., a given paired write command from a second queue Q2). In some embodiments, a fifth segment (e.g., the Write Priority Field WP) may include information for determining whether a write command has an execution priority higher than its paired read command. In some embodiments, the Read Priority Field RP and the Write Priority Field WP may be replaced by a single priority field (e.g., a single bit) indicating whether a read command or a write command has priority. For example, a value of 0 can indicate that a read command has a higher priority than a write command, and a value of 1 can indicate that a write command has a higher priority than a read command, or vice versa. In some embodiments, the sixth section (e.g., the wait field W) may include information for determining whether a given pair check register PCR should wait for a command associated with another pair check register PCR to be executed before a command in a given pair check register PCR can be executed. In some embodiments, the subject pair check register PCR (e.g., Figure 2B The seventh segment of PCR3 (e.g., the pairing register ID field PRID) may include the second pairing check register PCR (e.g., Figure 2BThe identifier ID of PCR2) is a second pair check register PCR that has a higher execution priority than the topic pair check register PCR (e.g., PCR3). In other words, the pair check register ID field PRID may contain the pair check register PCR value of the pair check register PCR that contains pairs that the topic PCR is configured to wait for (e.g., the topic PCR should wait for).

[0070] In some embodiments, bridging device 300 (see Figure 2A The bridging device 300 can check for identical addresses among valid commands in the queue. If a valid command is associated with the same address, the bridging device 300 can process the commands in the order they were provided (e.g., commands can be sent for execution). For example, the bridging device 300 can maintain the order of commands associated with the same address.

[0071] In some embodiments, if a valid pair of identical address PRs exists (e.g., in the pair check register PCR), the bridging device 300 can change the execution order of the valid address pair PRs. For example, if there is no address conflict between the two address pair PRs, each address pair PR can be executed independently. If there is an identical address (e.g., the same address range) between the two address pair PRs, the second address pair PR (e.g., the later received address pair PR) can be made to wait until the execution of the first address pair PR (e.g., the earlier received address pair PR) is completed.

[0072] In some embodiments, if no valid identical address pair PR exists, the execution order can be maintained (e.g., the original execution order). For example, commands can be executed based on a FIFO sequence.

[0073] For example, Figure 2A A scenario is depicted where the first queue Q1 and the second queue Q2 comprise three pairs of PRs (e.g., three pairs of the same address). For example, the bridging device 300 may determine that: the first pair of PRs 1 comprises (i) a read command to the fourth register R4 in the first queue Q1 with read ID 3, and (ii) a write command to the fifth register R5 in the second queue Q2 with write ID 4; the second pair of PRs 2 comprises (i) a read command to the twelfth register R12 in the first queue Q1 with read ID 11, and (ii) a write command to the seventh register R7 in the second queue Q2 with write ID 6; and the third pair of PRs 3 comprises (i) a read command to the twelfth register R12 in the first queue Q1 with read ID 11, and (ii) a write command to the sixteenth register R16 in the second queue Q2 with write ID 15.

[0074] refer to Figure 2BThe three pairing check registers (PCRs) can be filled to provide information for each of the first pair (PR1), the second pair (PR2), and the third pair (PR3). For example, the first pairing check register (PCR1) may include information about the first pair (PR1). For example, the validity field V may initially be filled with 0 (indicating that the first pairing check register (PCR1) does not include a valid pair of PRs), and may be changed to be filled with 1 to indicate that the first pairing check register (PCR1) includes information about a valid pair of PRs (e.g., the first pair of PRs). The read ID field RID may indicate a read ID of 3, and the write ID field WID may indicate a write ID of 4. The read priority field RP may indicate 1 to indicate that a read command has a higher execution priority than a write command. The write priority field WP may indicate 0 to indicate that a write command does not have a higher execution priority than a read command. The wait field W may indicate 0 to indicate that the first pair of PRs does not have a memory location overlapping with any other pair of PRs (e.g., any earlier received pair of PRs) (e.g., no conflicting addresses). Based on the wait field W indicating 0, the pairing register ID field PRID may be filled with 0.

[0075] The second pair check register PCR2 can include information about the second pair of PR2. For example, the validity field V can initially be filled with 0 (indicating that the second pair check register PCR2 does not include a valid pair of PRs), and can be changed to be filled with 1 to indicate that the second pair check register PCR2 includes information about a valid pair of PRs (e.g., the second pair of PR2). The read ID field RID can indicate a read ID of 11, and the write ID field WID can indicate a write ID of 6. The read priority field RP can indicate 0 to indicate that a read command does not have a higher execution priority than a write command. The write priority field WP can indicate 1 to indicate that a write command has a higher execution priority than a read command. The wait field W can indicate 0 to indicate that the second pair of PR2 does not have a memory location overlapping with any other pair of PRs (e.g., any earlier received pair of PRs, such as the first pair of PR1) (e.g., no conflicting addresses). Based on the wait field W indicating 0, the pair register ID field PRID can be filled with 0.

[0076] The third pair check register PCR3 can include information about the third pair of PR3. For example, the validity field V can initially be filled with 0 (indicating that the third pair check register PCR3 does not include a valid pair of PRs), and can be changed to be filled with 1 to indicate that the third pair check register PCR3 includes information about a valid pair of PRs (e.g., the third pair of PR3). The read ID field RID can indicate a read ID of 11, and the write ID field WID can indicate a write ID of 15. The read priority field RP can indicate 1 to indicate that a read command has a higher execution priority than a write command. The write priority field WP can indicate 0 to indicate that a write command does not have a higher execution priority than a read command. The wait field W can indicate 1 to indicate that the third pair of PR3 has a memory location that overlaps with another pair of PRs (e.g., an earlier received pair of PRs, such as the second pair of PR2) (e.g., a conflicting address). The pair register ID field PRID can be filled with information to identify the earlier received pair of PRs that is in conflict. For example, the Pairing Register ID field PRID of the third pairing check register PCR3 can be filled with information identifying the second pairing check register PCR2, which includes information about conflict pairs PR, which have a higher execution priority than the third pair PR3.

[0077] Refer again Figure 2A The bridging device 300 can ensure data consistency based on information associated with the pairing check register (PCR). For example, when the bridging device 300 sends a read command with read ID 3 to the slave device 220 (see... Figure 1 During execution, bridging device 300 can apply a hold condition to the write command with write ID 4, keeping it in the second queue Q2 until the read command with read ID 3 is completed. In other words, based on the fact that the read command with read ID 3 is being executed (e.g., based on the fact that the execution of the read command with read ID 3 has not yet been completed), the write command with write ID 4 can be kept in the second queue Q2 (e.g., it may not be executed). Therefore, bridging device 300 can ensure that the order of operations between the same address pairs in the read queue and the write queue is maintained, thereby achieving data consistency.

[0078] In some embodiments, to improve efficiency, bridging device 300 may reorder one or more commands that do not involve the same address as the one currently being executed. For example, if a read command with read ID 3 has not yet completed, and a write command with write ID 4 is pending execution ahead of the second queue Q2, bridging device 300 may send a later write command in the second queue Q2 (e.g., a write command with write ID 5) so that it executes before the write command with write ID 4, because the write command with write ID 4 is held (e.g., held to wait for the read command with read ID 3 to complete).

[0079] When a write command with write ID 6 is sent by bridging device 300 to slave device 220 (see...) Figure 1 During execution, bridging device 300 can hold the read command with read ID 11, keeping it in the first queue Q1 until the write command with write ID 6 completes execution. In other words, based on the fact that the write command with write ID 6 is being executed (e.g., based on the fact that the execution of the write command with write ID 6 has not yet completed), the read command with read ID 11 can be kept in the first queue Q1 (e.g., it may not be executed). Therefore, and as described above, bridging device 300 can ensure that the order of operations between the same address pairs in the read queue and the write queue is maintained, thereby achieving data consistency.

[0080] When the bridging device 300 sends a read command with read ID 11 to the slave device 220 (see...) Figure 1 During execution, bridging device 300 can apply a hold condition to the write command with write ID 15, keeping it in the second queue Q2 until the read command with read ID 11 completes execution. In other words, based on the fact that the read command with read ID 11 is being executed (e.g., based on the fact that the execution of the read command with read ID 11 has not yet completed), the write command with write ID 15 can be kept in the second queue Q2 (e.g., it may not be executed). Therefore, as described above, bridging device 300 can ensure that the order of operations between the same address pairs in the read queue and the write queue is maintained, thereby achieving data consistency.

[0081] In some embodiments, for example, the third pairing check register PCR3 includes a wait field W filled with 1 and a pairing register ID field PRID, the pairing register ID field PRID indicating that the command in the second pairing check register PCR2 has a higher execution priority than the command in the third pairing check register PCR3. Based on the information associated with the wait field W and / or the pairing register ID field PRID, the bridging device 300 can prevent a write command with write ID 15 from being reordered to execute before a write command with write ID 6.

[0082] In some embodiments, to improve efficiency, bridging device 300 may reorder one or more commands that do not involve the same address pair as those currently being executed. In other words, command reordering may involve reordering both paired and unpaired commands. For example, if a read command with read ID 11 has not yet completed, and a write command with write ID 15 is pending execution ahead of the second queue Q2, bridging device 300 may send a later write command in the second queue Q2 (e.g., a write command with write ID 16) to execute before the write command with write ID 15, because the write command with write ID 15 is held (e.g., held to wait for the read command with read ID 11 to complete). That is, in addition to the valid pair check register (PCR), a default ordering (e.g., basic ordering) of commands may be determined on a first-come, first-served basis (e.g., based on reception time).

[0083] It should be understood that various aspects of embodiments of this disclosure allow for data consistency regardless of whether one queue (e.g., Q1) has more commands than another queue (e.g., Q2) when a given pair of read commands (PRs) is received, and regardless of whether some commands in one queue (e.g., Q1) are processed faster than those in another queue (e.g., Q2). For example, if queues Q1 and Q2 start empty and receive 10 read commands (e.g., read requests), but initially no write commands are received, then registers R1-R10 of read command queue Q1 will be occupied by read identifiers IDs 0 to 9. Then, if a read-before-write pair of read commands (e.g., with read priority) enters, then that read command (e.g., with identifier ID 10) will occupy (e.g., will be stored in) register R11 of Q1, and that write command (e.g., with identifier 0) will occupy register R1 of Q2. Upon receiving a read command with identifier ID 10, the read command with identifier ID 10 will be redirected to an AXI read based on information in the corresponding priority check register (PCR) indicating that the read command has a higher priority than the write command with identifier ID 0 (e.g., it will be executed before the write command with identifier ID 0). The write command with identifier ID 0 will not be executed until the read command with identifier ID 10 has completed execution.

[0084] Figure 3 This is a block diagram depicting a method 3000 for data access management according to some embodiments of the present disclosure, the method 3000 having operations for processing commands that do not have the same address pair and operations for processing commands that have the same address pair.

[0085] refer to Figure 3 Method 3000 may include one or more of the following operations. In some embodiments, bridging device 300 may determine that a command is valid (e.g., operation 3001). For example, bridging device 300 may determine a queue (e.g., Figure 2A A new command (e.g., a new valid read command or a new valid write command) is received in either the first queue Q1 or the second queue Q2. The bridging device 300 can check for identical address pairs within the valid commands (e.g., within the valid commands of the first queue Q1 and / or the second queue Q2) (operation 3002). The bridging device 300 can determine whether any of the previously received commands (e.g., previously received valid commands) includes the same memory location (e.g., the same memory address) as the new command (e.g., a new read command or a new write command, as appropriate) (operation 3003).

[0086] Based on the fact that the bridging device 300 determines that there are no (N) previously received commands in the command queue associated with the same memory location as the new command, the bridging device 300 can send read commands and write commands so that the slave device 220 can perform the operation associated with each command (operation 3004A).

[0087] Based on the determination by bridging device 300 that one or more previously received commands in the command queue are associated with the same memory location (Y) as the new command, bridging device 300 can generate (e.g., populate) information about the new command and the previously received commands associated with the same address into the pair check register PCR, and can check the priority in the valid pair check register PCR (e.g., read the priority field RP and write the priority field WP) to determine the execution order of the commands (operation 3004B). For example, bridging device 300 can generate priority information into a given pair check register PCR, and can determine (e.g., can be determined later) which command in a pair of commands identified by the given pair check register PCR has a higher priority.

[0088] As described above, if the priority field (e.g., reading the priority field RP or writing the priority field WP) indicates that the first given command in the pair check register PCR does not have a higher execution priority than the second given command in the pair check register PCR (e.g., if the priority field indicates 0) (N), then the bridging device 300 may hold the first given command in its corresponding queue until its paired second given command has completed execution (operation 3005). If the priority field indicates that the first given command in the pair check register PCR has a higher execution priority than the second given command in the pair check register PCR (e.g., if the priority field indicates 1) (Y), then the bridging device 300 may send a priority command to the slave device 220 to execute before its paired second given command (operation 3006). The process of checking the priority field in a valid pair check register PCR can be repeated for each valid pair check register PCR.

[0089] Figure 4 This is a block diagram depicting a system for managing data access using a multiplexed and write-to-data buffer memory 250 according to some embodiments of the present disclosure.

[0090] refer to Figure 4As described above, bridging device 300 can be implemented as a bridge (e.g., an AXI bridge) to provide read and write data consistency in System 1. In some embodiments, one or more master devices 100 (e.g., AXI master devices) can send read and write commands as input to master device multiplexer 242 (e.g., an AXI multiplexer). Bridging device 300 can receive multiplexed output from master device multiplexer 242. In some embodiments, one or more master devices 100 can send write data for processing using one or more write commands. In some embodiments, AXI write data can be stored in write data buffer memory 250 via an AXI write channel. In some embodiments, a given master device 100 can directly store AXI write data into write data buffer memory 250.

[0091] In some embodiments, one or more master devices 100 may send write data to write data buffer memory 250 via write data buffer multiplexer 244. Write data buffer memory 250 may store write data associated with write commands. As described above, bridging device 300 may ensure data consistency based on pairing checks between command queues and may receive and process write data from write data buffer memory 250 and corresponding write commands in the write queues. Bridging device 300 may send read commands and write commands, along with write data, to slave device 220 as appropriate for operations to be performed at memory 230.

[0092] Figure 5 This is a diagram depicting a method for data access management with a determination operation for pairing checks between command queues, according to some embodiments of the present disclosure.

[0093] refer to Figure 5 Method 5000 may include one or more of the following operations. A device (e.g., bridging device 300) may determine a first command in a first command queue (e.g., ...). Figure 2A The read command in the first queue Q1) and the second command in the second command queue (e.g., Figure 2A The write command in the second queue Q2) is the same memory location (e.g., Figure 1 or Figure 4The bridging device 300 associates the read command with the same address in memory 230 (operation 5001). Based on the determination by the bridging device 300 that the read command has a higher execution priority than the write command, the bridging device 300 can send the read command for execution (operation 5002). Furthermore, based on the determination by the bridging device 300 that the read command has a higher execution priority than the write command, the bridging device 300 can apply a hold to the write command, such that the write command is held in the second queue Q2 until the read command completes execution (operation 5003). Based on the hold applied to the write command, the bridging device 300 can reorder the commands in the second queue Q2 by sending another write command later in the second queue Q2 to execute before the hold applied write command (operation 5004).

[0094] Therefore, aspects of some embodiments of this disclosure can ensure data consistency through appropriate execution ordering of identical address pairs, thereby providing improvements to data access management. Furthermore, aspects of some embodiments of this disclosure can improve performance (e.g., reduce latency) by reordering commands in the command queue when earlier commands in the queue are held in a hold-for-data-consistency-purpose manner, thereby providing improvements to data access management.

[0095] The exemplary embodiments disclosed herein can be extended to, but are not limited to, the following statements:

[0096] Statement 1. An exemplary method includes a device determining that a first command in a first command queue of the device and a second command in a second command queue of the device are associated with the same address in memory, the first command queue being configured to store command types different from those in the second command queue; determining that the first command has a higher execution priority than the second command; sending the first command by the device for execution; and imposing a hold on the second command by the device such that the second command is held in the second command queue based on the first command being executed.

[0097] Statement 2. The example method includes the method of Statement 1, and further includes the execution of a third command sent by the device from the second command queue, the third command being later in the second command queue than the second command.

[0098] Statement 3. An example method includes the methods of Statements 1 and 2, wherein sending the first command to execute comprises: the device sending the first command to a slave device via an on-chip communication bus protocol, and wherein the on-chip communication bus protocol is an Advanced Extensible Interface (AXI) protocol.

[0099] Statement 4. The example method includes the method of any one of statements 1-3, wherein the memory includes volatile memory or non-volatile memory; and the slave device includes a controller associated with one of the volatile memory or the non-volatile memory.

[0100] Statement 5. Example methods include any of the methods in Statements 1-4, wherein the command type is either a read command or a write command.

[0101] Statement 6. The example method includes the method of any one of Statements 1-5, wherein the first command includes a first read command; the first command queue includes a read command queue; the second command includes a first write command; and the second command queue includes a write command queue.

[0102] Statement 7. The example method includes the method of any one of Statements 1-5, wherein the first command includes a first write command; the first command queue includes a write command queue; the second command includes a first read command; and the second command queue includes a read command queue.

[0103] Statement 8. The example method includes the method of any one of Statements 1-7, and further includes: generating priority information in a register by the device, the register including an identifier of the first command and an identifier of the second command, wherein determining that the first command has a higher execution priority than the second command includes: reading the priority information from the register by the device.

[0104] Statement 9. The example method includes the method of any one of Statements 1-7, and further includes: determining by the device that a fourth command in the first command queue of the device and a fifth command in the second command queue of the device are also associated with the same address in the memory; and determining by the device that the first command and the second command have a higher execution priority based on a field of a register, the register including information that associates the fourth command with the fifth command.

[0105] Statement 10. The example method includes the method of any one of statements 1-9, and further includes: the device determining that the first command and the second command are valid commands and generating a validity determination, wherein the device performs the determination that the first command and the second command are associated with the same address based on the validity determination.

[0106] Statement 11. An example system for performing the method of any one of statements 1-10 includes the device connected as a bridging device to the master device and the slave device, and a controller of the slave device communicatively coupled to the bridging device.

[0107] While embodiments of this disclosure have been specifically shown and described with reference to the examples described herein, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as set forth in the appended claims and their equivalents.

Claims

1. A method for data access management, the method comprising: The device determines that a first command in the device's first command queue and a second command in the device's second command queue are associated with the same address in memory, wherein the first command queue is configured to store command types that are different from the command types in the second command queue; The first command is determined to have a higher execution priority than the second command; The device sends the first command to execute it; as well as The device applies a hold condition to the second command, such that the second command is retained in the second command queue based on the fact that the first command is being executed.

2. The method according to claim 1, further comprising: The device sends a third command from the second command queue for execution, the third command being later in the second command queue than the second command.

3. The method according to claim 1, wherein, Sending the first command to execute includes: The device sends the first command to the slave device via the on-chip communication bus protocol, and The on-chip communication bus protocol is the Advanced Extensible Interface (AXI) protocol.

4. The method according to claim 3, wherein: The memory includes volatile memory or non-volatile memory; and The slave device includes a controller associated with one of the volatile memory or the non-volatile memory.

5. The method according to claim 1, wherein, The command type is either a read command or a write command.

6. The method according to claim 1, wherein: The first command includes a first read command; The first command queue includes a read command queue; The second command includes a first write command; and The second command queue includes a write command queue.

7. The method according to claim 1, wherein: The first command includes a first write command; The first command queue includes a write command queue; The second command includes the first read command; and The second command queue includes a read command queue.

8. The method according to claim 1, further comprising: The device generates priority information in a register, the register including the identifier of the first command and the identifier of the second command. Wherein, determining that the first command has a higher execution priority than the second command includes: The priority information is read from the register by the device.

9. The method according to claim 1, further comprising: The device determines that the fourth command in the first command queue of the device and the fifth command in the second command queue of the device are also associated with the same address in the memory; as well as The device determines that the first command and the second command have a higher execution priority based on fields in a register, the register including information that associates the fourth command with the fifth command.

10. The method according to claim 1, further comprising: The device determines that the first command and the second command are valid commands and generates a validity determination. The device executes the determination associated with the first command and the second command and the same address based on the validity determination.

11. A system for data access management, comprising: A bridging device that connects to both the master and slave devices; as well as The controller of the slave device is communicatively coupled to the bridging device, wherein the bridging device is configured to perform: A first command in a first command queue of the bridging device and a second command in a second command queue of the bridging device are determined to be associated with the same address in a memory associated with the controller, wherein the first command queue is configured to store command types that are different from the command types in the second command queue; The first command is determined to have a higher execution priority than the second command; Send the first command to execute; as well as The second command is held in the second command queue such that the second command is retained based on the first command being executed.

12. The system according to claim 11, wherein, The bridging device is configured to perform: A third command is sent from the second command queue for execution, the third command being later in the second command queue than the second command.

13. The system according to claim 11, wherein, Sending the first command to execute includes: The bridging device sends the first command to the controller via the on-chip communication bus protocol, and The on-chip communication bus protocol is the Advanced Extensible Interface (AXI) protocol.

14. The system according to claim 11, wherein, The command type is either a read command or a write command.

15. The system according to claim 13, wherein: The memory includes volatile memory or non-volatile memory; and The controller is associated with either the volatile memory or the non-volatile memory.

16. The system according to claim 11, wherein: The first command includes a first read command; The first command queue includes a read command queue; The second command includes a first write command; and The second command queue includes a write command queue.

17. The system according to claim 11, wherein: The first command includes a first write command; The first command queue includes a write command queue; The second command includes the first read command; and The second command queue includes a read command queue.

18. The system according to claim 11, wherein, The bridging device is configured to execute priority information in a generation register, the register including the identifier of the first command and the identifier of the second command, and The step of determining that the first command has a higher execution priority than the second command includes reading the priority information from the register.

19. The system according to claim 11, wherein, The bridging device is configured to perform: It is determined that the fourth command in the first command queue of the bridging device and the fifth command in the second command queue of the bridging device are also associated with the same address in the memory; as well as The bridging device determines, based on fields in a register, that the first command and the second command have a higher execution priority, and the register includes information that associates the fourth command with the fifth command.

20. A system for data access management, comprising: Processing circuitry; as well as A non-transitory computer-readable medium storing instructions that cause the processing circuit to execute based on being executed by the processing circuit: It is determined that a first command in a first command queue and a second command in a second command queue are associated with the same address in memory, wherein the first command queue is configured to store command types that are different from the command types in the second command queue; The first command is determined to have a higher execution priority than the second command; Send the first command to execute; as well as The second command is held in the second command queue such that the second command is retained based on the first command being executed.

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