Signal transmission method, IJTAG circuit and chip

Abstract

The application discloses a signal transmission method, an IJTAG circuit and a chip. The signal transmission method is applied to the IJTAG circuit. In the case that a TAP controller receives a transmission instruction, the TAP controller transmits a control signal and a target TDI signal to a plurality of first SIB nodes. The control signal comprises a first selection signal and a second selection signal. In the case that the first selection signal indicates that the IJTAG circuit selects the plurality of first SIB nodes and the second selection signal indicates that the IJTAG circuit selects to broadcast the target TDI signal, a plurality of target SIB nodes are determined in the plurality of first SIB nodes according to at least a storage value of a first register in the plurality of first SIB nodes, and the target SIB nodes are in a broadcast mode. The target TDI signal is broadcast to TDRs respectively mounted with the plurality of target SIB nodes through the plurality of target SIB nodes. Thus, based on a parallel transmission link of the IJTAG circuit and the broadcast mode of the DIB node, the TDI signal broadcast is realized, and the signal transmission efficiency of the IJTAG circuit is improved.

Description

Technical Field

[0001] This application relates to the field of circuit testing, and in particular to a signal transmission method, an IJTAG circuit, and a chip. Background Technology

[0002] The built-in Internal Joint Test Action Group (IJTAG) is an extended architecture of the traditional Joint Test Action Group (JTAG). By introducing a dynamically reconfigurable scan network, it improves the efficiency and flexibility of chip testing and can meet the testing and debugging needs of complex on-chip integrated circuit design modules.

[0003] JTAG circuits are essentially serial control systems, a characteristic inherited by IJTAG circuits. In IJTAG circuits, a serial transmission link is formed through the Segment Insertion Bit (SIB) node and the Test Data Register (TDR), and serial control is achieved based on this serial transmission link.

[0004] However, the aforementioned IJTAG circuit suffers from low signal transmission efficiency. Summary of the Invention

[0005] This application provides a signal transmission method, an IJTAG circuit, and a chip, which at least solves the problem of low signal transmission efficiency in IJTAG caused by the serial transmission link.

[0006] In a first aspect, embodiments of this application provide a signal transmission method applied to an IJTAG circuit. The IJTAG circuit includes a TAP controller, a plurality of first SIB nodes connected to the TAP controller, and TDRs respectively mounted on the plurality of first SIB nodes. The first SIB node includes a first register, which is used to control the broadcast mode of the first SIB node to be turned on or off.

[0007] The signal transmission method includes:

[0008] When the TAP controller receives a transmission command, it transmits control signals and target test data input TDI signals to multiple first SIB nodes through the TAP controller. The control signals include a first selection signal and a second selection signal.

[0009] When the first selection signal instructs the IJTAG circuit to select multiple first SIB nodes and the second selection signal instructs the IJTAG circuit to select broadcasting the target TDI signal, multiple target SIB nodes are determined among the multiple first SIB nodes based at least on the stored values ​​of the first registers in the multiple first SIB nodes, and the target SIB nodes are in the broadcast mode.

[0010] The target TDI signal is broadcast to the TDRs mounted on the target SIB nodes through multiple target SIB nodes.

[0011] In a second aspect, embodiments of this application provide an IJTAG circuit, which is used to perform the signal transmission method as described in the first aspect, the IJTAG circuit comprising:

[0012] TAP controller;

[0013] The TAP controller is connected to multiple first SIB nodes, each of which includes a first register. The first register is used to control the broadcast mode of the first SIB node to be turned on or off.

[0014] The TDRs are mounted on multiple first SIB nodes respectively.

[0015] Thirdly, embodiments of this application provide a chip, including:

[0016] The IJTAG circuit as described in the first aspect.

[0017] In this embodiment, multiple first SIB nodes in the IJTAG circuit are connected to the TAP controller, forming multiple parallel transmission links connecting the TAP controller. Each first SIB node includes a first register, which controls whether the broadcast mode of the first SIB node is enabled or disabled, allowing the first SIB node to selectively support signal broadcasting. Thus, at the hardware level, a serial transmission link and a broadcast mode for the first SIB nodes are prepared. In the signal transmission method, the TAP controller sends a control signal and a target TDI signal to be transmitted to the first SIB nodes. When a first selection signal in the control signal instructs the IJTAG circuit to select multiple first SIB nodes, and a second selection signal in the control signal instructs the IJTAG circuit to select a broadcast target TDI signal, multiple target DIB nodes are determined from among the multiple first SIB nodes. These target SIB nodes are in broadcast mode, and the target TDI signal is broadcast to the TDR attached to them through these multiple target SIB nodes. Thus, based on the aforementioned serial transmission link and the broadcast mode of the first SIB nodes, by adding a second selection signal indicating the broadcast TDI signal to the control signal, the broadcast of the TDI signal in the IJTAG circuit is realized. Thus, by improving the hardware structure and control logic of the IJTAG circuit, signal broadcasting of the JITAG circuit is realized, thereby improving the signal transmission efficiency of the IJTAG circuit. Attached Figure Description

[0018] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0019] Figure 1 This is a structural example diagram of an IJTAG circuit.

[0020] Figure 2 A schematic diagram of the IJTAG circuit provided in the embodiments of this application. Figure 1 .

[0021] Figure 3 This is a flowchart illustrating a signal transmission method provided in an embodiment of this application.

[0022] Figure 4 A schematic diagram of the IJTAG circuit provided in the embodiments of this application. Figure 2 .

[0023] Figure 5 A schematic diagram of the IJTAG circuit provided in the embodiments of this application. Figure 3 .

[0024] Figure 6 This is a schematic diagram of the structure of the first SIB node provided in an embodiment of this application.

[0025] Explanation of icon numbers:

[0026] 10. TAP Controller; 11. Serial TDI Pin; 12. Broadcast TDI Pin; 13. First Select Pin; 14. Second Select Pin; 15. Capture Enable Pin; 16. Update Enable Pin; 17. Shift Enable Pin; 18. Reset Pin; 19. Test Clock Pin; 110. TDO Pin; 20. First SIB Node; 21. First Register; 22. Second Register; 23. SIB Controller; 24. First Selector; 25. Second Selector; 30. TDR. Detailed Implementation

[0027] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions provided in this application will be described in detail below with reference to the accompanying drawings.

[0028] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, the described exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.

[0029] As used herein, the term “and / or” includes any and all combinations of one or more related enumerations.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of a feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0031] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0032] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in the embodiments of this application.

[0033] To facilitate understanding of the solutions in the embodiments of this application, some contents involved in the embodiments of this application are described below:

[0034] The Joint Test Action Group (JTAG) is a common name in the IEEE 1149.1 standard (named Test Port and Boundary Scan Architecture). The Internal Joint Test Action Group (IJTAG) is an extension of JTAG, designed to address the testing and debugging needs of complex on-chip integrated circuit design modules. These integrated circuit design modules include intellectual property cores (IP cores), also known as IP modules, which are reusable and independently functional integrated circuit design modules in the chip design field, such as processor cores. The advantages of IJTAG lie in its flexibility and standardization, enabling the management, testing, and verification of IP modules on complex on-chip systems.

[0035] The implementation of IJTAG circuits relies on additional hardware resources, such as Segment Insertion Bits (SIBs) and Test Data Registers (TDRs), which are crucial for chip design. The SIBs in IJTAG circuits adopt a multi-level plug-and-play architecture, which has the convenience and flexibility of "building blocks". By configuring the SIBs, on-demand interconnection between TDRs and IP modules at different levels can be achieved.

[0036] See Figure 1 , Figure 1 This is a structural example diagram of an IJTAG circuit.

[0037] like Figure 1 As shown, the IJTAG circuit includes a Test Access Port (TAP) controller, multiple SIB nodes (SIB_1, SIB_2, ..., SIB_n), and multiple TDRs (TDR_1, TDR_2, ..., TDR_n) mounted on each SIB node. These TDRs are interconnected with multiple IP modules (IP_1, IP_2, ..., IP_n) to enable management and testing of the IP modules. Here, n is a positive integer greater than 1. In practical applications, a standardized configuration process can be executed to flexibly activate the circuit. Figure 1One or more TDR scanning networks (including SIBs and TDRs, for example, SIB_1 and TDR_1 constitute one TDR scanning network, and SIB_2 and TDR_2 constitute another TDR scanning network) are used to complete the data scanning and control of one or more IP modules.

[0038] It can be seen that, Figure 1 In this system, the TAP controller, multiple SIBs (SIB_1, SIB_2, ..., SIB_n_), and the TDRs mounted on each SIB form a serial transmission link, or in other words, a serially connected TDR scanning network. During the data scanning and manipulation of the IP module, the Test Data Input (TDI) signal can be transmitted from the TAP controller to SIB_1, from SIB_1 to TDR_1, from TDR_1 through SIB_1 to SIB_2, from SIB_2 to TDR_2, and from TDR_2 through SIB_2 and so on, thus realizing the serial transmission of the TDI signal.

[0039] However, under the above-mentioned serial transmission method, the signal transmission efficiency of the IJTAG circuit is low, which in turn leads to low efficiency in chip testing or chip debugging based on the IJTAG circuit.

[0040] In large-scale chips, IJTAG circuits are the primary test control circuits. Large-scale chips are characterized by complex circuitry, large logic volumes, and a large number of duplicated cores, all of which operate in a consistent manner during the testing phase. Therefore, by implementing signal broadcasting within the IJTAG circuit, the signal transmission efficiency can be improved, thereby increasing the efficiency of chip testing or debugging based on the IJTAG circuit.

[0041] The embodiments of this application incorporate the following improvements: At the hardware level, a parallel transmission link and an SIB node supporting broadcast mode are provided for TDI signal broadcasting; at the control logic level, broadcast-related control signals are added; based on the aforementioned improvements at the hardware and control logic levels, TDI signal broadcasting of the IJTAG circuit is achieved. This enables broadcast control of the IJTAG circuit, improves the signal transmission efficiency of the IJTAG circuit, and consequently improves the efficiency of chip testing or debugging based on the IJTAG circuit, saving chip testing / debugging time and reducing chip testing / debugging costs.

[0042] See Figure 2 , Figure 2 A schematic diagram of the IJTAG circuit provided in the embodiments of this application. Figure 1 .

[0043] like Figure 2 As shown, the IJTAG circuit includes a test access interface (TAP) controller 10, multiple first SIB nodes 20 connected to the TAP controller 10, and TDRs 30 mounted on the multiple first SIB nodes 20 respectively. Each first SIB node 20 includes a first register 21, which is used to control the broadcast mode of the first SIB node 20 to be turned on or off.

[0044] As can be seen, the embodiments of this application do not make large-scale changes to the original connection topology of the IJTAG structure, the circuit structure is simple, and while improving the testing efficiency of the IJTAG circuit, it can be compatible with the existing structure of the JITAG circuit.

[0045] See Figure 3 , Figure 3 This is a flowchart illustrating a signal transmission method provided in an embodiment of this application. This signal transmission method is applied to, for example... Figure 2 The IJTAG circuit shown.

[0046] like Figure 3 As shown, the signal transmission method includes, but is not limited to, the following steps:

[0047] S301, when the TAP controller 10 receives a transmission command, the TAP controller 10 transmits control signals and target TDI signals to be transmitted to multiple first SIB nodes 20. The control signals include a first selection signal and a second selection signal.

[0048] Among them, TAP controller 10 is the hardware interface controller in the IJTAG circuit.

[0049] The first selection signal is used to indicate whether the IJTAG circuit selects multiple first SIB nodes 20, and the second selection signal is used to indicate whether the JTAG circuit selects the broadcast target TDI signal.

[0050] For example, the first selection signal is the select signal output by TAP controller 10, which is output from the select pin on TAP controller 10. The second selection signal is the broadcast select signal (BroadCast_select) output by TAP controller 10, which is output from the BroadCast_select pin on TAP controller 10.

[0051] The transmission instruction can be an instruction in the instruction register (IR) of the TAP controller 10.

[0052] In this embodiment, when the TAP controller 10 receives a transmission command, it parses the transmission command and, based on the parsing result, transmits control signals and the target TDI signal to be transmitted to multiple first SIB nodes 20. The control signals include a first selection signal and a second selection signal. When the transmission command indicates that multiple first SIB nodes 20 are selected and the target TDI signal is broadcast, the first selection signal instructs the IJTAG circuit to select the multiple first SIB nodes 20, and the second selection signal instructs the IJTAG circuit to select the target TDI signal to be broadcast.

[0053] S302, when the first selection signal indicates that the IJTAG circuit selects multiple first SIB nodes 20 and the second selection signal indicates that the IJTAG circuit selects a broadcast target TDI signal, multiple target SIB nodes are determined among the multiple first SIB nodes 20 based at least on the stored value of the first register 21 in the multiple first SIB nodes 20, and the target SIB nodes are in broadcast mode.

[0054] The value stored in the first register 21 is used to indicate whether the broadcast mode of the first SIB node 20 is enabled or disabled. The value stored in the first register 21 can be pre-configured or dynamically configured.

[0055] In this embodiment, when the first selection signal indicates that the IJTAG circuit selects multiple first SIB nodes 20 and the second selection signal indicates that the IJTAG circuit selects a broadcast target TDI signal, the first SIB node 20 in broadcast mode can be identified among the multiple first SIB nodes 20 based on the stored value of the first register 21 in the multiple first SIB nodes 20. The first SIB node 20 in broadcast mode is the first SIB node 20 with broadcast mode enabled. For ease of distinction, the first SIB node 20 in broadcast mode is referred to as the target SIB node.

[0056] S303 broadcasts target TDI signals to the TDR 30 mounted on each of the multiple target SIB nodes.

[0057] In this embodiment, since multiple first SIB nodes 20 are connected in parallel to TAP controller 10, multiple target SIB nodes in broadcast mode can receive the target TDI signal output by TAP controller 10 and forward the target TDI signal to the TDR 30 mounted on each of the multiple target SIB nodes, thereby broadcasting the target TDI signal to multiple TDR 30.

[0058] In this embodiment, the IJTAG circuit includes a TAP controller 10, multiple first SIB nodes 20 connected to the TAP controller 10, and TDRs 30 respectively mounted on the multiple first SIB nodes 20. The multiple first SIB nodes 20 and the TDRs 30 respectively mounted on the multiple first SIB nodes 20 form a parallel transmission link. The multiple first SIB nodes 20 include a first register 21, and the stored value of the first register 21 indicates whether the broadcast mode of the first SIB node 20 is enabled or disabled. When the control signal output by the TAP controller 10 instructs the IJTAG circuit to select multiple first SIB nodes 20 and the second selection signal output by the TAP controller 10 instructs the IJTAG circuit to select the broadcast target TDI signal, the stored value of the first register 21 instructs the first SIB node 20 with broadcast mode enabled to broadcast the target TID signal output by the TAP controller 10 to the TDRs 30 mounted on the first SIB node 20 with broadcast mode enabled. This enables the TDI signal broadcasting function of the IJTAG circuit, which significantly improves the transmission efficiency of the TDI signal compared to serial transmission. This, in turn, improves the efficiency of chip testing or debugging based on the IJTAG circuit, saves chip testing / debugging time, and reduces chip testing / debugging costs.

[0059] Furthermore, in this embodiment, the broadcast mode of the first SIB node 20 is controllable. The control over whether the first SIB node 20 enables the broadcast mode can be achieved by storing the value in the first register 21. When the second selection signal instructs the JTAG circuit to select the broadcast target TDI signal, the TDR30 attached to the first SIB node 20, which does not enable the broadcast mode, will not be disturbed during the entire signal broadcast process.

[0060] In some embodiments, the stored value of the first register 21 can be a 1-bit value. When the stored value of the first register 21 is 0, the broadcast mode of the first SIB node 20 where the first register 21 is located is turned off; when the stored value of the first register 21 is 1, the broadcast mode of the first SIB node 20 where the first register 21 is located is turned on, that is, the first SIB node 20 where the first register 21 is located is in broadcast mode. The stored value of the first register 21 in the target SIB node is 1. Thus, by using the stored value of the first register 21 as 0 or 1, accurate control and indication of whether the broadcast mode of the first SIB node 20 where the first register 21 is located is turned on or off can be achieved.

[0061] See Figure 4 , Figure 4 A schematic diagram of the IJTAG circuit provided in the embodiments of this application. Figure 2 .in, Figure 4 and Figure 2 The same structure can be referenced Figure 2 The description of that will not be repeated here.

[0062] like Figure 4 As shown, the first SIB node 20 also includes a second register 22, which is used to control whether the TDR 30 mounted on the first SIB node 20 is in bypass or access mode. Based on the first register 21 and the second register 22 in the first SIB node 20, the first SIB node 20 supports broadcast operating mode and broadcast bypass mode. Thus, by combining the first register 21 and the second register 22, the first SIB node 20 can support broadcast operating mode and broadcast bypass mode, realizing accurate control of signal broadcasting in the IJTAG circuit.

[0063] Specifically, when the first register 21 controls the first SIB node 20 to enable the broadcast mode and the second register 22 controls the TDR 30 attached to the first SIB node 20 to be in the access state, the first SIB node 20 is in the broadcast working mode. The first SIB node 20 can forward the TDI signal selected by the IJTAG circuit to the TDR 30 attached to itself.

[0064] Specifically, when the first register 21 controls the first SIB node 20 to enable the broadcast mode and the second register 22 controls the TDR 30 attached to the first SIB node 20 to be in bypass mode, the first SIB node 20 is in broadcast bypass mode. Since the TDR 30 attached to the first SIB node 20 is in bypass mode, the first SIB node 20 cannot forward the TDI signal selected by the IJTAG circuit to its own attached TDR 30.

[0065] Specifically, the second register 22 controls whether the TDR 30 attached to the first SIB node 20 is in bypass or access mode through its stored value. Therefore, the stored value of the second register 22 can indicate whether the TDR 30 attached to the first SIB node 20 is in bypass or access mode. The stored value of the second register 22 can be pre-configured or dynamically configured.

[0066] In some embodiments, the stored value of the second register 22 can be a 1-bit value. When the stored value of the second register 22 is 0, the TDR 30 mounted on the first SIB node 20 where the second register 22 is located is in a bypass state; when the stored value of the second register 22 is 1, the TDR 30 mounted on the first SIB node 20 where the second register 22 is located is in an access state. Thus, by storing a value of 0 or 1 in the second register 22, accurate control and indication can be achieved regarding whether the TDR 30 mounted on the first SIB node 20 where the second register 22 is located is in a bypass state or an access state.

[0067] Based on the fact that the first SIB node 20 also includes a second register 22, some embodiments of the signal transmission method are provided below:

[0068] In some embodiments, the target SIB node is in broadcast mode and the TDR 30 attached to the target SIB node is in access state. Multiple target SIB nodes are determined among the multiple first SIB nodes 20 based at least on the stored values ​​of the first registers 21 in the multiple first SIB nodes 20. This includes determining the multiple target SIB nodes among the multiple first SIB nodes 20 based on the stored values ​​of the first registers 21 and the second registers 22 in the multiple first SIB nodes 20. Therefore, by using the stored values ​​of the first registers 21 and the second registers 22 in the multiple first SIB nodes 20, the first SIB nodes 20 in broadcast mode are accurately identified, i.e., the target SIB nodes are accurately identified, improving the accuracy of TDI signal broadcasting.

[0069] The stored value of the first register 21 indicates whether the broadcast mode of the first SIB node 20 is enabled or disabled, and the stored value of the second register 22 indicates whether the TDR 30 mounted on the first SIB node 20 is in bypass or access mode.

[0070] In some embodiments, before broadcasting the target TDI signal to the TDR 30 mounted on each of the multiple target SIB nodes, the method further includes disabling write permissions for the first register 21 and the second register 22 in the multiple target SIB nodes. By disabling write permissions for the first register 21 and the second register 22, changes in the stored values ​​of the first register 21 and the second register 22 are prevented from causing instability in the broadcasting operation of the target SIB nodes, thus improving the stability of broadcasting the TDI signal in the IJTAG circuit.

[0071] like Figure 4 As shown, multiple first SIB nodes 20 can be connected serially. Therefore, the IJTAG circuit not only includes parallel connections between multiple first SIB nodes 20 and the TAP controller 10, forming multiple parallel transmission links through these parallel connections and the mounting of corresponding TDRs 30 on the multiple first SIB nodes 20, but also includes serial connections between multiple first SIB nodes 20 and the TAP controller 10, forming serial transmission links through these serial connections and the mounting of corresponding TDRs 30 on the multiple first SIB nodes 20. This allows the IJTAG circuit to achieve both serial and parallel transmission of TDI signals.

[0072] Based on the serial connection of multiple first SIB nodes 20, some embodiments of the signal transmission method are provided below.

[0073] In some embodiments, the first SIB node 20 also supports a serial operating mode and a serial bypass mode. When the TAP controller 10 receives a transmission command, after transmitting control signals and the target TDI signal to be transmitted to multiple first SIB nodes 20 via the TAP controller 10, the method further includes: when a first selection signal instructs the IJTAG circuit to select multiple first SIB nodes 20 and a second selection signal instructs the IJTAG circuit to select serial transmission of the target TDI signal, determining the SIB node in serial operating mode among the multiple first SIB nodes 20 based on the stored values ​​of the first register 21 and the second register 22 in the multiple first SIB nodes 20; and transmitting the target TDI signal serially to the TDR 30 mounted on the SIB node in serial operating mode via the SIB node in serial operating mode. Thus, serial transmission of the TDI signal is achieved in the IJTAG circuit.

[0074] In this embodiment, by combining the first selection signal, the second selection signal, the stored values ​​of the first registers 21 in the plurality of first SIB nodes 20, and the stored values ​​of the second registers 22 in the plurality of first SIB nodes 20, the plurality of first SIB nodes 20 can be in one or more of the following modes: non-operating mode, serial operating mode, serial bypass mode, broadcast operating mode, and broadcast bypass mode. For each first SIB node 20, these operating modes are as follows:

[0075] Non-operating mode: When the first selection signal indicates that the IJTAG circuit has not selected the first SIB node 20, the first SIB node 20 is in non-operating mode.

[0076] Serial operating mode: When the first selection signal indicates that the IJTAG circuit selects the first SIB node 20, the second selection signal indicates that the IJTAG circuit selects the serial transmission target TDI signal, the stored value of the first register 21 in the first SIB node 20 indicates that the broadcast mode of the first SIB node 20 is off, and the stored value of the second register 22 in the first SIB node 20 indicates that the TDR 30 mounted on the first SIB node 20 is in the access state, the first SIB node 20 is in serial operating mode.

[0077] Serial bypass mode: When the first selection signal indicates that the IJTAG circuit selects the first SIB node 20, the second selection signal indicates that the IJTAG circuit selects the serial transmission target TDI signal, the stored value of the first register 21 in the first SIB node 20 indicates that the broadcast mode of the first SIB node 20 is turned off, and the stored value of the second register 22 in the first SIB node 20 indicates that the TDR 30 attached to the first SIB node 20 is in bypass state, the first SIB node 20 is in serial bypass mode.

[0078] Broadcast operating mode: When the first selection signal indicates that the IJTAG circuit selects the first SIB node 20, the second selection signal indicates that the IJTAG circuit selects the broadcast target TDI signal, the stored value of the first register 21 in the first SIB node 20 indicates that the broadcast mode of the first SIB node 20 is enabled, and the stored value of the second register 22 in the first SIB node 20 indicates that the TDR 30 mounted on the first SIB node 20 is in the access state, the first SIB node 20 is in broadcast operating mode.

[0079] Broadcast Bypass Mode: When the first selection signal indicates that the IJTAG circuit selects the first SIB node 20, the second selection signal indicates that the IJTAG circuit selects the broadcast target TDI signal, the stored value of the first register 21 in the first SIB node 20 indicates that the broadcast mode of the first SIB node 20 is enabled, and the stored value of the second register 22 in the first SIB node 20 indicates that the TDR 30 mounted on the first SIB node 20 is in bypass mode, the first SIB node 20 is in broadcast bypass mode.

[0080] In some embodiments, when the first selection signal is low, it indicates that the IJTAG circuit has not selected multiple first SIB nodes 20; when the first selection signal is high, it indicates that the IJTAG circuit has selected multiple first SIB nodes 20. And / or, when the second selection signal is low, it indicates that the IJTAG circuit selects a serial transmission target TDI signal; when the second selection signal is high, it indicates that the IJTAG circuit selects a broadcast target TDI signal. Thus, the high and low level signals accurately indicate whether the IJTAG circuit has selected multiple first SIB nodes 20 and the transmission mode of the TDI signal.

[0081] As an example, the various modes of the first SIB node 20 are shown in Table 1 below:

[0082] Table 1

[0083]

[0084] Wherein, the first selection signal being 0 indicates that the first selection signal is a low-level signal, and the first selection signal being 1 indicates that the first selection signal is a high-level signal; the second selection signal being 0 indicates that the second selection signal is a low-level signal, and the second selection signal being 1 indicates that the second selection signal is a high-level signal; the first register 21 being 0 indicates that the stored value of the first register 21 is 0, and the first register 21 being 1 indicates that the stored value of the first register 21 is 1; the second register 22 being 0 indicates that the stored value of the second register 22 is 0, and the second register 22 being 1 indicates that the stored value of the second register 22 is 1.

[0085] As shown in Table 1, when the first selection signal is a low-level signal, that is, when the first selection signal indicates that the IJTAG circuit has not selected the first SIB node 20, the first SIB node 20 is in a non-working mode regardless of the second selection signal, the stored value of the first register 21, or the stored value of the second register 22.

[0086] As shown in Table 1, when the first selection signal is a high-level signal (the first selection signal indicates that the IJTAG circuit selects the first SIB node 20), the second selection signal is a low-level signal (the second selection signal indicates that the IJTAG circuit selects the serial transmission TDI signal), the storage value of the first register 21 is 0 (the first register 21 controls the broadcast mode of the first SIB node 20 to be turned off), and the storage value of the second register 22 is 0 (the second register 22 controls the TDR 30 attached to the first SIB node 20 to be in bypass mode), the first SIB node 20 is in serial bypass mode.

[0087] As shown in Table 1, when the first selection signal is a high-level signal (the first selection signal indicates that the IJTAG circuit selects the first SIB node 20), the second selection signal is a low-level signal (the second selection signal indicates that the IJTAG circuit selects the serial transmission TDI signal), the storage value of the first register 21 is 0 (the first register 21 controls the broadcast mode of the first SIB node 20 to be turned off), and the storage value of the second register 22 is 1 (the second register 22 controls the TDR 30 mounted on the first SIB node 20 to be in the access state), the first SIB node 20 is in the serial working mode.

[0088] As shown in Table 1, when the first selection signal is a high-level signal (the first selection signal indicates that the IJTAG circuit selects the first SIB node 20), the second selection signal is a high-level signal (the second selection signal indicates that the IJTAG circuit selects the broadcast TDI signal), the storage value of the first register 21 is 1 (the first register 21 controls the broadcast mode of the first SIB node 20 to be enabled), and the storage value of the second register 22 is 0 (the second register 22 controls the TDR 30 mounted on the first SIB node 20 to be in bypass mode), the first SIB node 20 is in broadcast bypass mode.

[0089] As shown in Table 1, when the first selection signal is a high-level signal (the first selection signal indicates that the IJTAG circuit selects the first SIB node 20), the second selection signal is a high-level signal (the second selection signal indicates that the IJTAG circuit selects the broadcast TDI signal), the storage value of the first register 21 is 1 (the first register 21 controls the broadcast mode of the first SIB node 20 to be enabled), and the storage value of the second register 22 is 1 (the second register 22 controls the TDR 30 mounted on the first SIB node 20 to be in the access state), the first SIB node 20 is in the broadcast working mode.

[0090] See Figure 5 , Figure 5 A schematic diagram of the IJTAG circuit provided in the embodiments of this application. Figure 3 .in, Figure 5 Compared with the previous figure ( Figure 2 and Figure 4 The same structure that appears can be referred to the description in the previous figure, and will not be repeated here.

[0091] like Figure 5As shown, the TAP controller 10 may include the following pins: a serial TDI pin 11, a broadcast TDI pin 12, a first select pin 13, a second select pin 14, a capture enable (CaptureEN) pin 15, an update enable (UpdateEN) pin 16, a shift enable (ShiftEN) pin 17, a rest / reset pin 18, a test clock (TCK) pin 19, and a test data output (TDO) pin 110. The serial TDI pin 11 is connected to the broadcast TDI pin 12, and the serial TDI pin 11 is connected to the first of the plurality of first SIB nodes 20. The broadcast TDI pin 12 is connected to each of the plurality of first SIB nodes 20. Thus, in serial operation mode, a TDI signal can be output to the first first SIB node 20 via the serial TDI pin 11, and the TDI signal can be serially transmitted through the serial transmission link formed by the multiple first SIB nodes 20 and the TDRs 30 respectively connected to the multiple first SIB nodes 20; in parallel operation mode, a TDI signal can be output to the multiple first SIB nodes 20 via the broadcast TDI pin 12, and the TDI signal can be broadcast to the TDRs 30 respectively connected to the target SIB node (the target SIB node can be referred to the description in the previous embodiment, and will not be repeated here) among the multiple first SIB nodes 20, thereby realizing the broadcast of the TDI signal.

[0092] like Figure 5 As shown, the first selection pin 13, the second selection pin 14, the capture enable pin 15, the update enable pin 16, the shift enable pin 17, the reset pin 18, and the test clock pin 19 are all connected to multiple first SIB nodes 20. The TAP controller 10 can output control signals to multiple first SIB nodes 20 through the first selection pin 13, the second selection pin 14, the capture enable pin 15, the update enable pin 16, the shift enable pin 17, the reset pin 18, and the test clock pin 19. Specifically, the first selection pin 13 is used to output the first selection signal (the first selection signal can be referred to the description of the previous embodiment, and will not be repeated here), the second selection pin 14 is used to output the second selection signal (the second selection signal can be referred to the description of the previous embodiment, and will not be repeated here), the capture enable pin 15, update enable pin 16, shift enable pin 17, reset pin 18 and test clock pin 19 are used to output the capture enable signal, update enable signal, shift enable signal, reset enable signal and test clock signal respectively. The capture enable signal, update enable signal, shift enable signal, reset enable signal and test clock signal are conventional control signals in IJTAG circuits, and will not be described in detail in this solution.

[0093] like Figure 5 As shown, the TDO pin 110 can be connected to the last first SIB node 20 among multiple first SIB nodes 20, and is used to read test results or status data from the last first SIB node 20. The TDO pin 110 is a standard pin in the IJTAG circuit and will not be described in detail in this solution.

[0094] See Figure 6 , Figure 6 This is a schematic diagram of the structure of the first SIB node 20 provided in an embodiment of this application.

[0095] like Figure 6 As shown, the first SIB node 20 also includes an SIB controller 23 and a first selector 24. The SIB controller 23 is connected to the selection terminal of the first selector 24. The input terminal of the first selector 24 is used to input the TDI signal transmitted by the IJTAG circuit in a broadcast manner and the TDI signal transmitted by the IJTAG circuit in a serial manner.

[0096] Based on this structure, TDI signals are broadcast to TDRs 30 connected to multiple target SIB nodes. This includes: in each target SIB node, the SIB controller 23 controls the first selector 24 to output the target TDI signal to the TDR 30 connected to the target SIB node. Thus, through the control of the first selector 24 by the SIB controller 23, the target SIB node selects the broadcast target TDI signal from the IJTAG circuit and outputs it to the corresponding TDR 30, thereby realizing the output of the broadcast TDI signal by the first SIB node 20. Furthermore, the control of the first selector 24 by the SIB controller 23 can also realize the output of a serial TDI signal.

[0097] Among them, the TDI signal transmitted by the IJTAG circuit in a broadcast manner is as follows: Figure 6 The broadcast TDI signal in the IJTAG circuit is transmitted serially, such as the TDI signal. Figure 6 The serial TDI signal in the middle.

[0098] When the SIB controller 23 controls the first selector 24 to select a TDI signal to be transmitted in broadcast mode from a TDI signal transmitted in serial mode and a TDI signal transmitted in serial mode, the first selector 24 outputs the TDI signal to be transmitted in broadcast mode (e.g., Figure 6 The T_Si signal in the example is the broadcast TDI signal; when the SIB controller 23 controls the first selector 24 to select the serially transmitted TDI signal from the broadcast-mode TDI signal and the serially transmitted TDI signal, the first selector 24 outputs the serially transmitted TDI signal (e.g., Figure 6 The T_Si signal in the signal is the serial TDI signal.

[0099] In some embodiments, such as Figure 6 As shown, the SIB controller 23 is also connected to the first register 21 and the second register 22.

[0100] Based on the above structure, before the SIB controller 23 controls the first selector 24 to output the target TDI signal to the TDR 30 attached to the target SIB node, the method further includes: in each target SIB node, by inputting a first signal to the SIB controller 23, a second signal is obtained output by the SIB controller 23; in each target SIB node, the first signal includes a control signal, the output signal of the first register 21, and the output signal of the second register 22; the second signal includes a control signal for the first register 21, a control signal for the second register 22, and a control signal for the first selector 24; the first register 21 and the second register 22 are shift registers, and the control signal for the first register 21 and the control signal for the second register 22 are used to control the shifting process of the first register 21 and the second register 22. Therefore, the SIB controller 23 can control the first register 21, the second register 22, and the first selector 24 based on the control signal, the output signal of the first register 21, and the output signal of the second register 22.

[0101] The output signal of the first register 21 may include the stored value of the first register 21, and the output signal of the second register 22 may include the stored value of the second register 22.

[0102] from Figure 6 As can be seen, the input signals (i.e., the first signals) of the SIB controller 23 include the output signals of the first register 21, the output signals of the second register 22, and control signals (including the first selection signal, the second selection signal, the capture enable signal, the update enable signal, the shift enable signal, the reset signal, and the test clock signal); the output signals (i.e., the second signals) of the SIB controller 23 include control signals for the first register 21, control signals for the second register 22, and control signals for the first selector 24. Thus, based on the input control signals, the SIB controller 23 achieves dynamic control of the first register 21, the second register 22, and the first selector 24.

[0103] When the first register 21 controls the broadcast mode of the first SIB node 20, the second register 22 controls the TDR 30 mounted on the first SIB node 20 to be in the access state, the first selection signal indicates that the IJTAG circuit selects the first SIB node 20, and the second selection signal indicates that the IJTAG circuit selects the broadcast target TDI signal: the SIB controller 23 can determine that the first SIB node 20 is in the broadcast working mode according to the first selection signal, the second selection signal, the output signal of the first register 21, and the output signal of the second register 22. The SIB controller 23 controls the stored values ​​of the first register 21 and the second register 22 to remain unchanged by outputting the control signal of the first register 21 and the control signal for the second register 22. For example, the write permission of the first register 21 and the write permission of the second register 22 can be controlled to be closed to improve the stability of the broadcast working mode. The SIB controller 23 can control the first selector 24 to output the target TDI signal selected by the IJTAG circuit by outputting the control signal for the first selector 24, that is, output the broadcast TDI signal.

[0104] In some embodiments, for each first SIB node 20: the output signal of the SIB controller 23 further includes a third selection signal (such as... Figure 6 The third selection signal indicates whether the first SIB node 20 selects the TDR 30 mounted on the first SIB node 20; when the first SIB node 20 is in broadcast bypass mode or broadcast working mode, the SIB controller 23 outputs the third selection signal according to the second selection signal and the stored value of the first register 21; when the first SIB node 20 is in serial bypass mode or serial working mode, the SIB controller 23 outputs the third selection signal according to the first selection signal and the stored value of the second register 22.

[0105] In this embodiment, when the first SIB node 20 is in broadcast bypass mode or broadcast working mode, if the second selection signal indicates that the IJTAG circuit selects the broadcast target TDI signal and the stored value of the first register 21 indicates that the broadcast mode of the first SIB node 20 is enabled, then the third selection signal indicates that the TDR 30 mounted on the first SIB node 20 is selected to transmit the broadcast target TDI signal to the TDR 30; otherwise, the third selection signal indicates that the TDR 30 mounted on the first SIB node 20 is not selected. When the first SIB node 20 is in serial bypass mode or serial working mode, if the first selection signal indicates that the IJTAG circuit selects the first SIB node 20 and the second register 22 indicates that the TDR 30 mounted on the first SIB node 20 is in an access state, then the third selection signal indicates that the TDR 30 mounted on the first SIB node 20 is selected to transmit the serially transmitted TDI signal to the TDR 30; otherwise, the third selection signal indicates that the TDR 30 mounted on the first SIB node 20 is not selected. Therefore, in broadcast mode (broadcast bypass mode or broadcast working mode), the third selection signal is determined by logical judgment using the second selection signal and the stored value of the first register 21. In serial mode (serial bypass mode or serial working mode), the third selection signal is determined by logical judgment using the first selection signal and the stored value of the second register 22, which improves the accuracy of the third selection signal and thus improves the accuracy of TDI signal transmission.

[0106] For example, with Figure 6 For example, in broadcast bypass mode or broadcast working mode, the T_Se signal is jointly controlled by the second selection signal (such as the broadcast select signal) and the first register 21. T_Se will be 1 only when the second selection signal is a high-level signal and the storage value of the first register 21 is 1. In serial bypass mode or serial working mode, the T_Se signal is controlled by the first selection signal (such as the select signal) and the second register 22. T_Se will be 1 only when the first selection signal is a high-level signal and the storage value of the second register 22 is 1.

[0107] In some embodiments, such as Figure 6 As shown, the first SIB node 20 also includes a second selector 25, the selection end of the second selector 25 is connected to the second register 22, and the output end of the second selector 25 is connected to the first register 21.

[0108] The input and output signals of the second selector 25 are as follows: The input signals of the second selector 25 include the TDR 30 mounted on the previous SIB node of the first SIB node 20. Figure 6 The test output signal (not shown) Figure 6The T_So signal in the IJTAG circuit and the TDI signal transmitted serially (such as...) Figure 6 (The serial TDI signal in the middle), the output signal of the second selector 25 is the test output signal or the TDI signal transmitted serially by the IJTAG circuit.

[0109] The control logic of the second selector 25 is as follows: When the first SIB node 20 is in serial bypass mode or serial operating mode, the second selector 25 selects to input the test output signal of the TDR 30 attached to the previous SIB node or the TDI signal transmitted serially to the first register 21 based on the output signal of the second register 22. Therefore, when the first SIB node 20 is in serial bypass mode or serial operating mode, the output signal of the second selector 25 is accurately controlled based on the output signal of the second register 22.

[0110] The output signal of the second register 22 includes the stored value of the second register 22, which indicates whether the TDR 30 connected to the first SIB node 20 is in bypass or connected state. When the stored value of the second register 22 indicates that the TDR 30 connected to the first SIB node 20 is in bypass state, the second selector 25 can be controlled to input the test output signal of the TDR 30 connected to the previous SIB node to the first register 21. When the stored value of the second register 22 indicates that the TDR 30 connected to the first SIB node 20 is in connected state, the second selector 25 can be controlled to input a TDI signal transmitted serially to the first register 21, so as to transmit the serially transmitted TDI signal to the TDR 30.

[0111] In some embodiments, the IJTAG circuit further includes at least one second SIB node (not shown in the figure), which is serially connected to a plurality of first SIB nodes 20. The second SIB node supports serial operating mode and serial bypass mode. When the TAP controller 10 receives a transmission command, after transmitting control signals and the target TDI signal to be transmitted to the plurality of first SIB nodes 20 via the TAP controller 10, the circuit further includes: if a first selection signal instructs the IJTAG circuit to select the plurality of first SIB nodes 20 and a second selection signal instructs the IJTAG circuit to select serial transmission of the target TDI signal, based on the stored values ​​of the first register 21 and the second register 22 in the plurality of first SIB nodes 20, determining the SIB node in serial operating mode among the plurality of first SIB nodes 20 and second SIB nodes; and transmitting the target TDI signal to the TDR 30 mounted on the SIB node in serial operating mode via the SIB node in serial operating mode in a serial transmission manner. Therefore, the IJTAG circuit can be compatible with conventional SIB nodes (i.e., SIB nodes that support serial operating mode and serial bypass mode) as well as the broadcast SIB nodes innovatively proposed in this application (i.e., SIB nodes that support broadcast mode, which can further include broadcast operating mode and broadcast control mode). The broadcast SIB nodes can be connected to the entire IJTAG circuit in the same way as conventional SIB nodes, avoiding significant changes to the IJTAG circuit and reducing the deployment cost of the IJTAG circuit.

[0112] In this embodiment, the transmission command received by the TAP controller 10 indicates the selection of multiple first SIB nodes 20 and second SIB nodes, and instructs the serial transmission of the target TDI signal. Upon receiving the transmission command, the TAP controller 10 parses the transmission command and, based on the parsing result, transmits control signals to the multiple first SIB nodes 20 and second SIB nodes, sends the target TDI signal to be transmitted to the first SIB node on the serial transmission link where the multiple first SIB nodes 20 and second SIB nodes are located, and determines the SIB node in serial operating mode among the multiple first SIB nodes 20 and second SIB nodes based on the stored values ​​of the first register 21 and the second register 22 in the multiple first SIB nodes 20. The target TDI signal is then transmitted along the serial transmission link to the TDR 30 mounted on the SIB node in serial operating mode via the SIB node in serial operating mode.

[0113] This application also provides a chip, which includes the IJTAG circuit provided in any of the foregoing embodiments.

[0114] This application also provides an electronic device, which includes the chip provided in any of the foregoing embodiments.

[0115] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0116] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0117] The above description, with reference to the accompanying drawings, illustrates some embodiments of this application, but does not limit the scope of this application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and spirit of this application shall be within the scope of this application.

Claims

1. A signal transmission method, characterized by, It is applied to the built-in Joint Test Group (IJTAG) circuit, which includes a Test Access Interface (TAP) controller, multiple First Field Insertion Bit (SIB) nodes connected to the TAP controller, and Test Data Registers (TDRs) mounted on the multiple first SIB nodes respectively. The first SIB node includes a first register, which is used to control the broadcast mode of the first SIB node to be enabled or disabled. The signal transmission method includes: When the TAP controller receives a transmission command, it transmits control signals and target test data input TDI signals to multiple first SIB nodes through the TAP controller. The control signals include a first selection signal and a second selection signal. When the first selection signal instructs the IJTAG circuit to select multiple first SIB nodes and the second selection signal instructs the IJTAG circuit to select broadcasting the target TDI signal, multiple target SIB nodes are determined among the multiple first SIB nodes based at least on the stored values ​​of the first registers in the multiple first SIB nodes, and the target SIB nodes are in the broadcast mode. The target TDI signal is broadcast to the TDRs mounted on the target SIB nodes through multiple target SIB nodes.

2. The signal transmission method of claim 1, wherein, The first SIB node also includes a second register, which is used to control whether the TDR mounted on the first SIB node is in bypass or access state. Based on the first register and the second register, the first SIB node supports broadcast working mode and broadcast bypass mode, and the target SIB node is in the broadcast working mode. The TDR mounted on the target SIB node is in an access state. The step of determining multiple target SIB nodes among the multiple first SIB nodes based at least on the stored values ​​of the first registers in the multiple first SIB nodes includes: Based on the stored values ​​of the first registers in the plurality of first SIB nodes and the stored values ​​of the second registers in the plurality of first SIB nodes, a plurality of target SIB nodes are determined among the plurality of first SIB nodes.

3. The signal transmission method of claim 2, wherein, Before broadcasting the target TDI signal to the TDRs mounted on the multiple target SIB nodes through the multiple target SIB nodes, the method further includes: Write permissions to the first and second registers in multiple target SIB nodes are disabled.

4. The signal transmission method according to claim 2, characterized in that, Multiple first SIB nodes are connected serially; The first SIB node also supports serial operating mode and serial bypass mode; After the TAP controller receives the transmission instruction and transmits control signals and the target TDI signal to be transmitted to multiple first SIB nodes through the TAP controller, the process further includes: When the first selection signal indicates that the IJTAG circuit selects multiple first SIB nodes and the second selection signal indicates that the IJTAG circuit selects serial transmission of the target TDI signal, the SIB node in the serial working mode is determined among the multiple first SIB nodes based on the stored values ​​of the first registers in the multiple first SIB nodes and the stored values ​​of the second registers in the multiple first SIB nodes. The target TDI signal is transmitted serially to the TDR mounted on the SIB node in the serial operating mode via the SIB node in the serial operating mode.

5. The signal transmission method according to claim 4, characterized in that, The first SIB node also includes an SIB controller and a first selector. The SIB controller is connected to the selection terminal of the first selector. The input terminal of the first selector is used to input the TDI signal transmitted by the IJTAG circuit in a broadcast manner and the TDI signal transmitted by the IJTAG circuit in a serial manner. The step of broadcasting the TDI signal to the TDRs mounted on the multiple target SIB nodes through multiple target SIB nodes includes: In each of the target SIB nodes, the SIB controller controls the first selector to output the target TDI signal to the TDR attached to the target SIB node.

6. The signal transmission method according to claim 5, characterized in that, The SIB controller is also connected to the first register and the second register; Before controlling the first selector to output the target TDI signal to the TDR mounted on the target SIB node via the SIB controller, the method further includes: In each of the target SIB nodes, a second signal is obtained by inputting a first signal to the SIB controller; In each of the target SIB nodes, the first signal includes the control signal, the output signal of the first register, and the output signal of the second register. The second signal includes the control signal for the first register, the control signal for the second register, and the control signal for the first selector. The first register and the second register are shift registers, and the control signals of the first register and the second register are used to control the shifting process of the first register and the second register.

7. The signal transmission method according to claim 6, characterized in that, For each of the first SIB nodes: the output signal of the SIB controller further includes a third selection signal, which indicates whether the first SIB node selects the TDR mounted on the first SIB node; When the first SIB node is in the broadcast bypass mode or the broadcast working mode, the SIB controller outputs the third selection signal based on the second selection signal and the stored value of the first register; When the first SIB node is in the serial bypass mode or the serial working mode, the SIB controller outputs the third selection signal based on the first selection signal and the stored value of the second register.

8. The signal transmission method according to claim 5, characterized in that, The first SIB node also includes a second selector, the selection terminal of which is connected to the second register, and the output terminal of which is connected to the first register; The input signal of the second selector includes the test output signal of the TDR mounted on the previous SIB node of the first SIB node and the TDI signal transmitted serially by the IJTAG circuit. The output signal of the second selector is either the test output signal or the TDI signal transmitted serially by the IJTAG circuit. When the first SIB node is in the serial bypass mode or the serial operating mode, the second selector selects to output the test output signal or the TDI signal transmitted serially by the IJTAG circuit according to the output signal of the second register.

9. The signal transmission method according to any one of claims 4 to 8, characterized in that, The IJTAG circuit further includes at least one second SIB node, which is serially connected to multiple first SIB nodes, and the second SIB node supports the serial operating mode and the serial bypass mode. After the TAP controller receives the transmission instruction and transmits control signals and the target TDI signal to be transmitted to multiple first SIB nodes through the TAP controller, the process further includes: When the first selection signal indicates that the IJTAG circuit selects multiple first SIB nodes and the second selection signal indicates that the IJTAG circuit selects serial transmission of the target TDI signal, the SIB node in the serial operating mode is determined among the multiple first SIB nodes and the second SIB nodes based on the stored values ​​of the first registers in the multiple first SIB nodes and the stored values ​​of the second registers in the multiple first SIB nodes. The target TDI signal is transmitted serially to the TDR mounted on the SIB node in the serial operating mode via the SIB node in the serial operating mode.

10. An IJTAG circuit, characterized in that, The IJTAG circuit is used to perform the signal transmission method as described in any one of claims 1 to 9, and the IJTAG circuit includes: TAP controller; The TAP controller is connected to multiple first SIB nodes, each of which includes a first register. The first register is used to control the broadcast mode of the first SIB node to be turned on or off. The TDRs are mounted on multiple first SIB nodes respectively.

11. A chip, characterized in that, include: The IJTAG circuit as described in claim 10.

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