Analog calculation circuit and decision tree classification method
By constructing a decision tree using a control module and a memory array in a simulated computing circuit, the latency and power consumption problems caused by the memory wall in traditional decision tree algorithms are solved, and the efficient execution of the decision tree algorithm is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI INTEGRATED CIRCUIT RESEARCH & DEVELOPMENT CENTER CO LTD
- Filing Date
- 2024-10-15
- Publication Date
- 2026-04-17
AI Technical Summary
Traditional decision tree algorithm execution units, such as central processing units or graphics processing units, suffer from latency and high power consumption issues due to memory walls, which are caused by data computation and storage.
The system employs an analog computing circuit, receives the data to be decided through a control module, determines the target path and applies a read voltage, constructs a decision tree using storage units in the storage array, avoids data latency and power consumption in the storage wall, and outputs the decision results.
It improves the execution efficiency of the decision tree algorithm, avoids the data latency and power consumption problems of the storage wall, and enhances computational efficiency.
Smart Images
Figure CN121881118A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to an analog computing circuit and a decision tree classification method. Background Technology
[0002] With the rapid development of machine learning technology, decision trees, as a commonly used classification and regression method, have been widely applied in fields such as data mining and pattern recognition. Because the construction and inference of decision trees involve a large number of computational tasks, such as feature selection and data segmentation, processing units are needed to perform these calculations.
[0003] Traditional decision tree algorithms utilize execution units such as central processing units (CPUs) or graphics processing units (GPUs) that can meet the computational resource requirements for execution. However, the memory wall inherent in the von Neumann architecture of CPUs and GPUs leads to latency and high power consumption issues between computation and storage. Therefore, the current challenge is to improve the efficiency of decision tree algorithm execution. Summary of the Invention
[0004] This application provides an analog computing circuit and a decision tree classification method to improve the efficiency of decision tree algorithm execution.
[0005] On one hand, this application provides an analog computing circuit for executing a decision tree algorithm. The analog computing circuit includes: a control module, a storage array, and an output module; the storage array includes multiple storage units, which serve as nodes in the decision tree to form multiple paths of the decision tree; the control module, connected to the storage units, is used to receive data to be decided, determine a target path from the multiple paths based on the data to be decided, apply a read voltage to the storage units under the target path, and sequentially select each path so that the storage array outputs the read result of that path; the output module, connected to the storage array, is used to obtain an output vector based on the read results of the multiple paths; the output vector represents the decision result.
[0006] In one possible implementation, the control module includes: a classification module, a first decoder, and a second decoder; the classification module is used to receive data to be decided and obtain an indication signal based on the data to be decided, the indication signal representing the target path; the first decoder is connected to the classification module and the storage unit, and is used to output the bit line signal of the storage array according to the indication signal; the bit line signal is used to apply a read voltage to the storage unit under the target path; the second decoder is connected to the storage unit, and is used to sequentially output the word line signal for selecting each path of the storage array in cooperation with the bit line signal output by the first decoder, so that the storage array outputs the read result of each path.
[0007] In one possible implementation, the first decoder is a bitline decoder and the second decoder is a wordline decoder.
[0008] In one possible implementation, the classification module is also connected to the output module, which is used to obtain the decision result based on the output vector obtained by the output module.
[0009] In one possible implementation, when the classification module obtains a decision result based on the output vector obtained by the output module, it specifically performs the following steps: calculates the error value by comparing the output vector with a preset vector; if the error value is less than a preset threshold, it determines that the classification type of the data to be decided belongs to the type of the preset vector; if the error value is not less than the preset threshold, it determines that the classification type of the data to be decided does not belong to the type of the preset vector.
[0010] In one possible implementation, there are multiple preset vectors; the classification module is also used to: take the type of the preset vector corresponding to the smallest error value as the decision result.
[0011] In one possible implementation, the storage unit includes at least one resistive switching memory.
[0012] In one possible implementation, the indication signal is binary data, the length of which is equal to the number of bit lines of the first decoder.
[0013] On the other hand, this application provides a decision tree classification method based on the above-mentioned analog computing circuit. The method includes: receiving data to be decided, determining a target path from multiple paths of the storage array based on the data to be decided, applying a read voltage to the storage cell under the target path; and sequentially selecting each path so that the storage array outputs the read result of the path; and obtaining a decision result based on the output vector obtained by the output module based on the read result.
[0014] In one possible implementation, the method further includes: establishing an initial analog computing circuit, writing resistance values to the storage cells in the storage array, and obtaining a preset vector including training data and the labels of the training data; obtaining the output vector corresponding to the training data obtained under the initial analog computing circuit; and adjusting the resistance values in the storage cells based on the output vector corresponding to the training data and the preset vector corresponding to the labels of the training data until the distance error between the output vector corresponding to the training data and the preset vector is less than a training threshold, so as to complete the training of the initial analog computing circuit.
[0015] The analog computing circuit and decision tree classification method provided in this application include a control module, a storage array, and an output module. The control module receives the data to be decided and determines the target path from multiple paths based on the data. It then applies a read voltage to the storage unit under the target path and sequentially selects each path to cause the storage array to output the read result of that path. The output module obtains an output vector representing the decision result based on the read results of multiple paths. In the analog computing circuit of this application, a decision tree is constructed through the storage units in the storage array. The control module can perform decision calculations on the data to be decided under the decision tree structure, avoiding the data latency and power consumption problems of the storage wall, thereby improving the efficiency of the decision tree algorithm. Attached Figure Description
[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0017] Figure 1 The diagram above illustrates the structure of an analog computing circuit.
[0018] Figure 2 The diagram above illustrates the structure of an analog computing circuit.
[0019] Figure 3 The diagram above illustrates the structure of an analog computing circuit.
[0020] Figure 4 The diagram above illustrates the structure of an analog computing circuit.
[0021] Figure 5 The diagram above illustrates the structure of an analog computing circuit.
[0022] Figure 6 The diagram below illustrates the flowchart of the decision tree classification method.
[0023] Figure 7 The diagram above illustrates a flowchart of the decision tree classification method.
[0024] Explanation of reference numerals in the attached figures: Control module: 01, Storage array: 02, Output module: 03; Classification module: 11, First decoder: 12, Second decoder: 13; Storage unit: 21; Transistor: 211, Variable resistor unit: 212.
[0025] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0027] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning. The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to be omnipresent but not exclusive. For example, a product or device that comprises a series of components is not necessarily limited to those components that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such products or devices. The term "module" as used in this application refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.
[0028] As a crucial part of modern technology, artificial intelligence (AI) encompasses theories, methods, technologies, and application systems capable of simulating, extending, and expanding human intelligence. Machine learning, a subfield of AI, focuses on training models through data to enable computers to learn and improve automatically. Within machine learning, numerous algorithms are used for various tasks, such as linear regression, support vector machines, and neural networks. Decision tree algorithms, due to their intuitiveness and ease of interpretation, have become an important tool in classification and regression tasks.
[0029] The construction and inference process of decision trees involves numerous computational tasks, such as feature selection, information gain calculation, and data segmentation. These tasks require efficient computing resources, primarily provided by processing units such as the Central Processing Unit (CPU) and Graphics Processing Unit (GPU). However, these processing units typically employ the von Neumann architecture, which suffers from memory walls between computation and storage units. This physical latency between computation and storage impacts computational efficiency. Furthermore, the frequent data movement between memory and the processor contributes to the high power consumption of the processing units.
[0030] The technical content provided in this application aims to solve the aforementioned technical problems in related technologies. In the analog computing circuit and decision tree classification method of this application, the circuit includes a control module, a storage array, and an output module. The control module receives the data to be decided and determines the target path from multiple paths based on the data, applies a read voltage to the storage unit under the target path, and sequentially selects each path to cause the storage array to output the read result of that path. The output module can obtain an output vector representing the decision result based on the read results of multiple paths. In the analog computing circuit of this application, a decision tree is constructed through the storage units in the storage array, and the control module can perform decision calculations on the data to be decided under the decision tree structure, avoiding the data latency and power consumption problems of the storage wall, thereby improving the efficiency of the decision tree algorithm execution.
[0031] The technical solutions of this application will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. In the description of this application, unless otherwise expressly specified and limited, the terms should be broadly understood within the art. The embodiments of this application will now be described with reference to the accompanying drawings.
[0032] Example 1
[0033] Figure 1 The diagram illustrates a schematic of an analog computing circuit used to execute decision tree algorithms, such as... Figure 1 As shown, the circuit includes: a control module 01, a storage array 02, and an output module 03;
[0034] The storage array 02 includes multiple storage units 21, which serve as nodes in the decision tree to form multiple paths in the decision tree;
[0035] The control module 01, connected to the storage unit 21, is used to receive the data to be decided, determine the target path from multiple paths based on the data to be decided, apply a read voltage to the storage unit 21 under the target path, and sequentially select each path so that the storage array 02 outputs the read result of the path.
[0036] Output module 03, connected to storage array 02, is used to obtain an output vector based on the reading results of multiple paths; the output vector represents the decision result.
[0037] The decision tree is composed of nodes, and logical relationships exist between these nodes. For example, a decision tree can consist of a root node, internal nodes, branches, and leaf nodes. Storage units 21 serve as nodes in the decision tree. Each storage unit 21 is independently controlled by the control module 01, and each storage unit 21 is independently output through the output module 03. The path in the decision tree refers to the path formed by the nodes of the decision tree. Figure 1 For example, the decision tree in this example contains four paths: Path 1 is formed by the storage units in the first row, the first storage unit in the second row, and the first storage unit in the third row; Path 2 is formed by the storage units in the first row, the first storage unit in the second row, and the second storage unit in the third row; Path 3 is formed by the storage units in the first row, the second storage unit in the second row, and the third storage unit in the third row; and Path 4 is formed by the storage units in the first row, the second storage unit in the second row, and the fourth storage unit in the third row. When a path is selected, the storage units corresponding to the nodes under that path are selected. The outputs of the selected storage units are then aggregated to output module 03 as the read result for that path. For instance, when control module 01 selects path 1, the storage units in the first row, the first storage unit in the second row, and the first storage unit in the third row are all selected, and the aggregated output of these storage units serves as the read result for path 1.
[0038] Specifically, each storage unit is controlled by the control module 01. As an example, the tree structure can be a binary decision tree, a multi-branch decision tree, or a continuous value decision tree. Exemplarily, the storage array 02 can be formed on a substrate by multiple storage units 21 arranged in a tree-like logical architecture. Alternatively, a storage array typically arranged in a matrix can be remapped to obtain a logically tree-like storage array 02. It should be noted that the decision tree undergoes a pre-training phase to determine the weight value of each node, i.e., the resistance value in the storage unit 21. For example, when the first storage unit represents the judgment of whether the attribute of height exceeds a threshold, a high or low resistance value of the first storage unit can represent that the height exceeds the threshold and activate another storage unit, i.e., the next node. In practical applications, the storage unit 21 can be a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase-change memory (PCM), or a resistive random access memory (RRAM), and the corresponding storage array 02 can also be a combination of one or more types of memory.
[0039] In this example, control module 01 receives decision data, which can be raw data such as height 180 cm and weight 80 kg. Control module 01 converts this raw data into binary data using an encoder or mapping rules to determine the target path for the decision data. Optionally, the decision data is binary data, which can be directly used as machine language instructions, thereby improving the computational efficiency of the decision tree. It should be noted that multiple paths in the decision tree are determined during construction and training, with the path from the root node to a leaf node being called a path. Control module 01 determines the target path from multiple paths based on the decision data and applies a read voltage to the storage unit 21 under the target path, allowing it to read the data stored in each node, i.e., the storage unit 21, under the target path. Furthermore, control module 01 selects each path to cause the storage array 02 to output the read result of that path. This scheme ensures consistency in output by traversing the path, thereby improving computational efficiency. In practical applications, the selection order can be based on the decision tree structure, from shallow to deep, or according to a fixed order pattern, etc. After obtaining the reading results of multiple paths, the output module 03 obtains an output vector representing the decision result based on the reading results of multiple paths. For example, the output module 03 can perform signal conversion on the received reading results, such as converting the analog circuit signal output by the storage unit 21 into a digital signal using an analog-to-digital converter to form the output vector. For example, this output vector is an n-dimensional vector, where n represents the total number of paths in the decision tree. After obtaining the output vector, the output module 03 can determine the decision result of the data to be decided by performing threshold detection on the output vector, or by calculating the distance between the output vector and a preset vector and then comparing the calculation result with the threshold. For example, the distance calculation between vectors can be Euclidean distance or Manhattan distance calculation.
[0040] The analog computing circuit in this example includes a control module, a storage array, and an output module. The control module receives the data to be decided and determines the target path from multiple paths based on the data. It then applies a read voltage to the storage cells along the target path and sequentially selects each path to cause the storage array to output the read result for that path. The output module obtains an output vector representing the decision result based on the read results of multiple paths. In the analog computing circuit of this application, a decision tree is constructed using the storage cells in the storage array. The control module performs decision calculations on the data to be decided within the decision tree structure, avoiding the data latency and power consumption problems of the storage wall, thereby improving the efficiency of the decision tree algorithm.
[0041] As yet another example, Figure 2 The diagram illustrates a schematic representation of an analog computing circuit. Figure 2As shown, the control module 01 includes: a classification module 11, a first decoder 12, and a second decoder 13;
[0042] The classification module 11 is used to receive the data to be decided and to obtain an indication signal based on the data to be decided. The indication signal represents the target path.
[0043] The first decoder 12 is connected to the classification module 11 and the storage unit 21, and is used to output the bit line signal of the storage array 02 according to the indication signal; the bit line signal is used to apply the read voltage to the storage unit 21 under the target path;
[0044] The second decoder 13 is connected to the storage unit 21 and is used to sequentially output word line signals for selecting each path of the storage array 02 in cooperation with the bit line signals output by the first decoder 12, so that the storage array 02 outputs the read results of each path.
[0045] For example, the classification module 11 can design encoding rules or mapping rules to convert the received decision-making data into an indication signal, which is used to interact with the first decoder 12. In practical applications, the generation of the indication signal can be determined based on the data transmission protocol between the classification module 11 and the first decoder 12. After receiving the indication signal, the first decoder 12 outputs the bit line signal of the storage array 02 according to the indication signal; wherein, the bit line signal is used to apply a read voltage to the storage cell 21 under the target path. For example, the read voltage can be a low-level voltage or a high-level voltage. The second decoder 13 outputs a word line signal after the bit line signal output by the first decoder 12. The output time of the word line signal can be determined by the second decoder 13 through the connected first decoder 12. Optionally, the second decoder 13 can also be connected to the classification module 11 to receive an indication signal including the one that determines the output time of the word line signal. In practical applications, in order to maintain the standardization of the output results, the order in which the second decoder 13 selects each path can be specified, such as the selection order from left to right according to the decision tree structure, or the selection order from shallow to deep for each path. It should be noted that multiple storage units at the same depth in the decision tree are independently controlled by the first decoder and the second decoder. For example, Figure 2Each of the four storage units in the third layer requires four bit lines and four word lines. It should be noted that the decision tree structure represented by the storage units in this example is merely illustrative. In practical applications, more storage units can be used to form deeper decision tree structures, or the positions of the storage units can be changed to form different decision tree structures. In this example, the classification module 11 performs signal conversion on the data to be decided to obtain an indication signal. The first decoder 12 and the second decoder 13 cooperate to sequentially select and output the results of different paths combined by the storage units 21 in the storage array 02. By directly connecting the data computation unit and the data storage unit, a storage-computing integrated structure is achieved, thereby improving the efficiency of decision tree computation.
[0046] As yet another example, the first decoder 12 is a bitline decoder, and the second decoder 13 is a wordline decoder.
[0047] In this example, the bit line decoder is used as the first decoder 12 and the word line decoder is used as the second decoder 13. The bit line decoder is responsible for selecting a specific bit line, while the word line decoder is responsible for selecting a specific word line. By combining these two decoders, a specific cell in the memory array can be accessed efficiently.
[0048] As yet another example, Figure 3 The diagram illustrates a schematic representation of an analog computing circuit. Figure 3 As shown, the classification module 11 is also connected to the output module 03. The classification module 11 is used to obtain the decision result based on the output vector obtained by the output module 03.
[0049] In this example, the classification module 11 determines the decision result for the data to be decided by performing threshold detection on the output vector obtained by the output module 03, or by calculating the distance between the output vector and a preset vector and then comparing the calculation result with the threshold. For example, the distance calculation between vectors can be Euclidean distance or Manhattan distance calculation. In this example, the classification module 11 further calculates the output vector to quantitatively evaluate the decision result.
[0050] As yet another example, when classification module 11 obtains a decision result based on the output vector obtained by output module 03, it is specifically used for:
[0051] The error value is obtained by calculating the output vector and the preset vector.
[0052] If the error value is less than the preset threshold, the data to be decided is determined to be of the type of the preset vector.
[0053] If the error value is not less than the preset threshold, then the classification type of the data to be decided is determined to be different from the type to which the preset vector belongs.
[0054] For example, the preset vector can be the result of the decision data with data labels output to the analog computing circuit after the decision tree training is completed. Optionally, the preset vector can also be a preset vector directly obtained from the data labels. In this example, the classification module 11 calculates the error value by comparing the output vector and the preset vector; if the error value is less than a preset threshold, the classification type of the data to be decided is determined to be the type to which the preset vector belongs; if the error value is not less than the preset threshold, the classification type of the data to be decided is determined not to be the type to which the preset vector belongs. The scheme in this example detects the error value between the output vector and the preset vector to determine the classification type of the decision tree, and the accuracy of type classification can be improved by quantitative calculation.
[0055] As yet another example, there are multiple preset vectors; classification module 11 is also used for:
[0056] The type of the preset vector corresponding to the smallest error value is taken as the decision result.
[0057] In practical applications, when multiple preset vectors exist, the error value between the output vector and each preset vector can be calculated separately to obtain an error value sequence. Furthermore, this error value sequence is sorted by size, and the type of the preset vector corresponding to the smallest error value is taken as the decision result. The solution in this example, by calculating and comparing the output vector with multiple preset vectors, can improve the accuracy and comprehensiveness of the type classification of the data to be decided.
[0058] As yet another example, storage cell 21 includes at least one resistive switching memory.
[0059] In practical applications, the storage unit 21 can be different resistive switching memories (RSMs) based on different material modifications, such as oxide-based RSMs, sulfide-based RSMs, or organic RSMs. Optionally, the RSM in this example can also be an RSM with structural or material improvements based on a specific RSM. Exemplarily, at least one RSM can be managed by a controller to achieve the desired effect, such as locating a specific RSM and performing read / write operations. In practical applications, this controller can be a transistor combination device. The scheme in this example, using RSM for storage, can reduce energy consumption and improve read / write performance during decision tree algorithm calculations.
[0060] As yet another example, Figure 4 The diagram illustrates a schematic representation of an analog computing circuit. Figure 4 As shown, the resistive variable memory includes: transistor 211 and variable resistor unit 212;
[0061] One end of transistor 211 is connected to the first decoder 12 through the bit line of its column, and the control terminal of transistor 211 is connected to the second decoder 13 through the word line of its row. The other end of transistor 211 is connected to the variable resistor unit 212. When the control terminal receives a first level signal, transistor 211 turns on one end and the other end so that the variable resistor unit 212 outputs current under the reading voltage.
[0062] In this example, a resistive random access memory (RRAM) may include a transistor 211 and a variable resistor unit 212 forming a 1T1R structure, or the number of transistors 211 or variable resistor units 212 may be adjusted to form a 1TnR structure or an nT1R structure. For example, when the first decoder 12 receives an indication signal, it applies a read voltage to one end of the transistor 211 in the connected RRAM according to the indication signal. Correspondingly, when the second decoder 13 selects each path according to a preset selection sequence, it applies a first level signal to the control terminal of the transistor 211 in the RRAM under the selected path, so that one end and the other end of the transistor 211 in the RRAM are turned on, thereby outputting the current of that path. In practical applications, different transistors 211, such as MOSFETs, transistors, and insulated-gate bipolar transistors 211, can be selected according to requirements. In this example, the first decoder 12 and the second decoder 13 can control the reading of data stored in the variable resistor unit 212 according to the selection sequence through the transistor 211, improving the accuracy of the decision tree algorithm calculation.
[0063] As yet another example, the indicator signal is binary data, and the data length of the binary data is equal to the number of bit lines of the first decoder 12.
[0064] For example, the classification module 11 sends a binary indication signal with a length equal to the number of bit lines of the first decoder 12. The first decoder 12 can directly output this binary signal as a bit line signal. In this example, the classification module 11 sends a binary indication signal, which can be directly used as the bit line signal output of the first decoder 12, simplifying circuit design and improving data transmission efficiency.
[0065] Figure 5 The diagram illustrates a schematic representation of an analog computing circuit. Figure 5As shown, seven memory cells 21 form a memory array 02, creating a binary tree structure with four paths from the root node to the leaf nodes. The gate of the MOS transistor under each memory cell 21 is connected to the second decoder 13 via a word line, the source is connected to the first decoder 12 via a bit line, and the drain is connected to a resistive random access memory (RRAM). Furthermore, each RRAM is connected to the output of an analog-to-digital converter (ADC), and both the first decoder 12 and the ADC (as output module 03) are connected to the classification module 11. For ease of description, a memory cell 21 is designated according to its depth and the order from right to left in the decision tree structure; for example, the root node's memory cell 21 is [0,0], the leftmost memory cell 21 in the second layer is [1,1], and the fourth memory cell 21 from right to left in the third layer is [2,3]. As an example, the classification module 11 converts the received decision data into a 7-bit binary indicator signal and sends the indicator signal to the first decoder 12. As an example, the 7-bit binary is 0111000, and the bit line signals are output from the first bit line to the seventh bit line from left to right. When an indication signal representing the target path [0,0], [1,1], [2,2] is received, the first decoder 12 applies a read voltage to the source of the MOS transistor in the three memory cells 21. The second decoder 13 conducts multiple paths with the cooperation of the read voltage, and the ADC collects the current I when each path is conducted. For example, the second decoder 13 outputs binary data 1010010 from the first word line to the seventh word line from top to bottom to conduct the target path representing [0,0], [1,1], [2,2], and conducts the path representing [0,0], [1,1], [2,3] through 1010001, and the other two paths are similar. After receiving the output current I of each path, the ADC converts the current signal into a digital signal and forms a 1*4 vector. For example, the ADC output signal is an 8-bit unsigned int type, and the numerical range of the parameters in the corresponding vector is 0~255. For instance, if the second decoder 13 operates according to the right-to-left conduction order, the corresponding output vector is [100, 100, 175, 100]. Furthermore, the classification module 11 also calculates the distance between this 1*4 vector and a preset vector. If the result of the distance calculation is less than a threshold, the classification type of the data to be decided is the type to which the preset vector belongs.
[0066] The analog computing circuit of this embodiment includes a control module, a storage array, and an output module. The control module receives the data to be decided and determines the target path from multiple paths based on the data. It then applies a read voltage to the storage unit under the target path and sequentially selects each path to cause the storage array to output the read result of that path. The output module obtains an output vector representing the decision result based on the read results of multiple paths. In the analog computing circuit of this application, a decision tree is constructed through the storage units in the storage array. The control module can perform decision calculations on the data to be decided under the decision tree structure, avoiding the data latency and power consumption problems of the storage wall, thereby improving the efficiency of the decision tree algorithm.
[0067] Example 2
[0068] Figure 6 The diagram illustrates a flowchart of a decision tree classification method, based on an analog computing circuit of any embodiment, such as... Figure 6 As shown, the method includes:
[0069] Step 101: Receive the data to be decided, and determine the target path from multiple paths of the storage array based on the data to be decided, apply a read voltage to the storage cell under the target path; and sequentially select each path so that the storage array outputs the read result of the path.
[0070] Step 102: Obtain the decision result based on the output vector obtained by the output module based on the reading result.
[0071] A decision tree is composed of nodes, and these nodes have logical relationships. For example, a decision tree can consist of a root node, internal nodes, branches, and leaf nodes. Storage units act as nodes in the decision tree; each storage unit is independently controlled by a control module, and each storage unit outputs data independently through an output module. The path in a decision tree refers to the path formed by the nodes of the tree. Figure 1 For example, the decision tree in this example contains four paths: Path 1 is formed by the storage units in the first row, the first storage unit in the second row, and the first storage unit in the third row; Path 2 is formed by the storage units in the first row, the first storage unit in the second row, and the second storage unit in the third row; Path 3 is formed by the storage units in the first row, the second storage unit in the second row, and the third storage unit in the third row; and Path 4 is formed by the storage units in the first row, the second storage unit in the second row, and the fourth storage unit in the third row. When a path is selected, the storage units corresponding to the nodes under that path are selected. The outputs of the selected storage units are then aggregated to the output module as the read result for that path. For instance, when the control module selects Path 1, the storage units in the first row, the first storage unit in the second row, and the first storage unit in the third row are all selected, and the aggregated output of these storage units serves as the read result for Path 1.
[0072] Specifically, each storage unit is controlled by a control module. As an example, the tree structure can be a binary decision tree, a multi-branch decision tree, or a continuous value decision tree. Exemplarily, the storage array can be fabricated on a substrate by multiple storage units arranged in a tree-like logical architecture. Alternatively, a storage array typically arranged in a matrix can be remapped to obtain a logically tree-like storage array. It should be noted that the decision tree undergoes a pre-training phase to determine the weight value of each node, i.e., the resistance value in the storage unit. For example, when the first storage unit represents the judgment of whether the attribute of height exceeds a threshold, a high or low resistance value of the first storage unit can represent that the height exceeds the threshold and activate another storage unit, i.e., the next node. In practical applications, the storage units can be dynamic random access memory (DRAM), static random access memory (SRAM), phase-change memory (PCM), or resistive random access memory (RRAM), and the corresponding storage array can be a combination of one or more types of memory.
[0073] In this example, the control module receives the data to be decided, which can be raw data such as height 180 cm and weight 80 kg. The control module converts this raw data into binary data using an encoder or mapping rules to determine the target path for the decision data. Optionally, the data to be decided is binary data, which can be directly used as machine language instructions, thereby improving the computational efficiency of the decision tree. It should be noted that the multiple paths in the decision tree are determined during construction and training, and the path from the root node to the leaf node is called a path. The control module determines the target path from multiple paths based on the data to be decided, applies a read voltage to the storage units under the target path, and can read the data stored in each node, i.e., the storage unit, under the target path. Furthermore, the control module selects each path so that the storage array outputs the read result of that path. This scheme ensures the consistency of the output method by traversing the output, thereby improving computational efficiency. In practical applications, the selection order can be based on the decision tree structure from shallow to deep or according to a fixed order pattern, etc. After obtaining the reading results from multiple paths, the output module obtains an output vector representing the decision result based on these results. For example, the output module can perform signal conversion on the received reading results, such as converting the analog circuit signal output from the storage unit into a digital signal using an analog-to-digital converter to form the output vector. For example, this output vector is an n-dimensional vector, where n represents the total number of paths in the decision tree. After obtaining the output vector, the output module can determine the decision result for the data to be decided by performing threshold detection on the output vector, or by calculating the distance between the output vector and a preset vector and then comparing the calculated result with the threshold. For example, the distance calculation between vectors can be Euclidean distance or Manhattan distance calculation.
[0074] Optionally, in decision tree classification, multi-level path selection can be introduced when determining the target path to gradually narrow down the range of possible paths through phased path filtering. Specifically, coarse-grained features or conditions are used for initial filtering to quickly eliminate irrelevant paths. This can be achieved through simple threshold judgment or low-complexity calculations. Next, more refined conditions are applied to the set of paths after initial filtering for further filtering to determine the final target path. In this example, multi-level path selection can reduce unnecessary path traversal, lower computational complexity, and speed up the decision-making process. Optionally, decision speed can also be improved by simultaneously gating and reading multiple paths. Specifically, in hardware design, a multi-path parallel access mechanism is implemented in the storage array, and the data bus and processor are ensured to handle parallel data reads to support parallel operations on multiple paths. At the software level, a parallel scheduling algorithm needs to be designed to allocate resources reasonably. The parallel path gating in this example can significantly improve the system throughput and is suitable for application scenarios with high real-time requirements.
[0075] In the decision tree classification method of this example, the control module receives the data to be decided and determines the target path from multiple paths based on the data. It then applies a read voltage to the storage unit under the target path and sequentially selects each path to cause the storage array to output the read result of that path. The output module obtains an output vector representing the decision result based on the read results of multiple paths. In the analog computing circuit of this application, a decision tree is constructed using the storage units in the storage array. The control module can perform decision calculations on the data to be decided within the decision tree structure, avoiding the data latency and power consumption problems of the storage wall, thereby improving the efficiency of the decision tree algorithm.
[0076] Figure 7 The diagram illustrates a flowchart of a decision tree classification method. Figure 7 As shown, the method also includes:
[0077] Step 201: Establish the initial simulation calculation circuit, write resistance values to the storage cells in the storage array, and obtain the preset vectors including training data and the labels corresponding to the training data.
[0078] Step 202: Obtain the output vector corresponding to the training data obtained under the initial analog computing circuit;
[0079] Step 203: Based on the output vector corresponding to the training data and the preset vector corresponding to the label of the training data, adjust the resistance value in the storage unit until the distance error between the output vector corresponding to the training data and the preset vector is less than the training threshold, so as to complete the training of the initial analog computing circuit.
[0080] In this example, the decision tree structure can be determined based on requirements such as algorithm complexity, fitting ability, accuracy, and computational resources, and an initial analog computing circuit can be established. For instance, resistance values can be randomly assigned to the storage cells in the storage array. In practical applications, to facilitate calculations between vectors, the precision of the preset vector corresponding to the labels of the training data should be consistent with the precision of the output vector output by the analog computing circuit. During training, the resistance values in the storage cells are adjusted based on the output vector corresponding to the training data and the preset vector corresponding to the labels of the training data until the distance error between the output vector corresponding to the training data and the preset vector is less than a training threshold, thus completing the training of the initial analog computing circuit. This example, by establishing an initial analog computing circuit and training it based on training data to determine the resistance values of the storage cells in the circuit, can improve the accuracy and efficiency of decision calculations.
[0081] In the decision tree classification method of this embodiment, the control module receives the data to be decided and determines the target path from multiple paths based on the data. It then applies a read voltage to the storage unit under the target path and sequentially selects each path to cause the storage array to output the read result of that path. The output module can obtain an output vector representing the decision result based on the read results of multiple paths. In the analog computing circuit of this application, a decision tree is constructed using the storage units in the storage array. The control module can perform decision calculations on the data to be decided under the decision tree structure, avoiding the data latency and power consumption problems of the storage wall, thereby improving the efficiency of the decision tree algorithm execution.
[0082] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0083] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. An analog computing circuit, characterized in that, The analog computing circuit, used to execute decision tree algorithms, includes: a control module, a storage array, and an output module; The storage array includes multiple storage units, which serve as nodes in the decision tree to form multiple paths in the decision tree; The control module, connected to the storage unit, is used to receive data to be decided, determine a target path from the plurality of paths based on the data to be decided, apply a read voltage to the storage unit under the target path, and sequentially select each path so that the storage array outputs the read result of that path. The output module, connected to the storage array, is used to obtain an output vector based on the reading results of the multiple paths; the output vector represents the decision result.
2. The circuit according to claim 1, characterized in that, The control module includes: a classification module, a first decoder, and a second decoder; The classification module is used to receive data to be decided and to obtain an indication signal based on the data to be decided, wherein the indication signal represents the target path; The first decoder is connected to the classification module and the storage unit, and is used to output the bit line signal of the storage array according to the indication signal; the bit line signal is used to apply a read voltage to the storage unit under the target path; The second decoder is connected to the storage unit and is used to sequentially output word line signals for selecting each path of the storage array in cooperation with the bit line signals output by the first decoder, so that the storage array outputs the read results of each path.
3. The circuit according to claim 2, characterized in that, The first decoder is a bitline decoder, and the second decoder is a wordline decoder.
4. The circuit according to claim 2, characterized in that, The classification module is also connected to the output module, and the classification module is used to obtain the decision result based on the output vector obtained by the output module.
5. The circuit according to claim 4, characterized in that, When the classification module obtains the decision result based on the output vector obtained by the output module, it is specifically used for: The error value is obtained by calculating the output vector and the preset vector. If the error value is less than a preset threshold, then the classification type of the data to be decided is determined to be the type to which the preset vector belongs; If the error value is not less than a preset threshold, then it is determined that the classification type of the data to be decided is not the type to which the preset vector belongs.
6. The circuit according to claim 5, characterized in that, There are multiple preset vectors; the classification module is also used for: The type of the preset vector corresponding to the smallest error value is taken as the decision result.
7. The circuit according to claim 2, characterized in that, The storage unit includes at least one resistive random access memory.
8. The circuit according to claim 7, characterized in that, The indication signal is binary data, and the data length of the binary data is equal to the number of bit lines of the first decoder.
9. A decision tree classification method, characterized in that, Based on the analog computing circuit as described in any one of claims 1 to 8, the method includes: The system receives data to be decided, determines a target path from multiple paths of the storage array based on the data to be decided, applies a read voltage to the storage cell under the target path, and sequentially selects each path so that the storage array outputs the read result of the path. The decision result is obtained based on the output vector obtained by the output module from the reading results.
10. The method according to claim 9, characterized in that, The method further includes: An initial simulation calculation circuit is established, resistance values are written to the storage cells in the storage array, and a preset vector including training data and the labels corresponding to the training data is obtained. Obtain the output vector corresponding to the training data obtained under the initial analog computing circuit; Based on the output vector corresponding to the training data and the preset vector corresponding to the label of the training data, the resistance value in the storage unit is adjusted until the distance error between the output vector corresponding to the training data and the preset vector is less than the training threshold, so as to complete the training of the initial analog computing circuit.