Bias voltage circuit for non-volatile memory, bias voltage rapid establishment method and non-volatile memory
By using a current mirror module and a bias voltage circuit controlled by a time pulse signal, the problems of high power consumption and circuit complexity in the bias voltage establishment process of the prior art are solved. This enables rapid establishment of bias voltage and reduces chip area, meeting the needs of high-speed applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING TONGFANG MICROELECTRONICS
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-17
AI Technical Summary
The bias voltage setup process of existing non-volatile memories is characterized by high power consumption and complex circuit structure, making it difficult to meet the dual requirements of high-speed applications and reducing chip area.
The bias voltage circuit, which employs a current mirror module and a time pulse signal control, establishes the initial voltages at the PBIAS and VOUT points by momentarily turning on the mirror current input module and the bias voltage generation module before the circuit is turned on, and quickly establishes the target voltage after the circuit starts up, thereby reducing power consumption and simplifying the circuit structure.
It enables rapid establishment of bias voltage with low power consumption, reduces chip area, and meets the needs of high-speed applications.
Smart Images
Figure CN121884907A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of memory chip technology, such as a bias voltage circuit for non-volatile memory, a method for fast bias voltage establishment, and non-volatile memory. Background Technology
[0002] Existing microprocessors have built-in on-chip non-volatile memory. The bias voltage generated by the bias circuit is used to stabilize the voltage of the bit line in order to realize operations such as reading data from the non-volatile memory. Figure 1 This is an existing conventional bias circuit. The bias voltage establishment process mainly involves the PBIAS' voltage point being established first, followed by the VOUT' voltage point. The bias voltage establishment speed can be increased by increasing the Ibias current (increasing the mirror ratio of PM1' and PM2' is equivalent to increasing the Ibias current). However, this method generates significant energy consumption when rapidly establishing the bias voltage.
[0003] A circuit and method for rapidly establishing a reference current are disclosed in related technologies. The circuit includes: an operational amplifier; a first MOSFET, the source of which is connected to the supply voltage, the drain of which is connected to the output terminal of the operational amplifier, and the gate of which is connected to an enable signal; a second MOSFET, the source of which is connected to the supply voltage, the drain of which is connected to the inverting input terminal of the operational amplifier, the gate of which is connected to the output terminal of the operational amplifier, and the drain of which is the reference current output terminal; a current mirror module, which is connected to a bias current, the negative power supply terminal of the operational amplifier, a common ground terminal, an enable delay signal, and an enable signal; and a switch module, which is connected to the output terminal of the operational amplifier and the enable signal, and is used to turn on or off the output terminal of the operational amplifier according to the enable signal.
[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art: While the related technologies achieve rapid establishment of bias voltage with relatively low power consumption, the complex circuit structure results in a large chip area.
[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0006] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0007] This disclosure provides a bias voltage circuit, a method for rapidly establishing bias voltage, and a non-volatile memory, to ensure low power consumption and a small chip area while rapidly establishing bias voltage.
[0008] In some embodiments, the circuit includes: a current mirror module, a mirror current input module, a bias voltage generation module, a load capacitor, and a first GND, wherein, The current mirror module is configured to be controlled by a first enable signal and a second enable signal; the mirror current input module and the bias voltage generation module are respectively controlled by a third enable signal and a fourth enable signal, as well as a first time pulse signal and a second time pulse signal generated by an external digital circuit; When the first enable signal is low, the voltage at point PBIAS in the current mirror module and the voltage at point VOUT in the bias voltage generation module are both power supply voltages. During the transition of the first enable signal from low to high, the mirror current input module and the bias voltage generation module are controlled by the first time pulse signal and the second time pulse signal, respectively. The power supply voltages at points PBIAS and VOUT decrease, and the first initial voltage and the second initial voltage are established, respectively. After the third and fourth enable signals are high and the second enable signal is low, the first initial voltage at point PBIAS and the second initial voltage at point VOUT are transformed into the first target voltage and the second target voltage, respectively.
[0009] In some embodiments, the method includes: when the first enable signal is low, the voltage at the PBIAS point in the current mirror module and the voltage at the VOUT point in the bias voltage generation module are both power supply voltages; during the transition of the first enable signal from low to high, an external digital circuit generates a first time pulse signal and a second time pulse signal, which are respectively input to the current mirror input module and the bias voltage generation module, and the power supply voltages at the PBIAS point and the VOUT point begin to decrease, establishing a first initial voltage and a second initial voltage, respectively; when the third enable signal and the fourth enable signal are high, and the second enable signal is low, the first initial voltage and the second initial voltage at the PBIAS point and the VOUT point are respectively converted into a first target voltage and a second target voltage.
[0010] In some embodiments, the non-volatile memory includes: a sensitive amplifier circuit, a memory cell array, an NMOS transistor, and a bias voltage circuit as described above; The drain of the NMOS transistor is connected to the sensitive amplifier circuit, the source is connected to the memory cell array, and the gate is connected to the bias voltage circuit.
[0011] The bias voltage circuit, fast bias voltage establishment method, and non-volatile memory provided in this disclosure can achieve the following technical effects: Before the circuit is turned on, a first time pulse signal and a second time pulse are used to momentarily turn on the current mirroring module and the bias voltage generation module, respectively, to establish the voltages at the PBIAS point in the current mirroring module and the VOUT point in the bias voltage generation module to their respective initial voltages. After the circuit starts working, the PBIAS point and VOUT point can quickly establish their respective target voltages from their initial voltages. In this way, the bias voltage can be quickly established with low power consumption, and the relatively simple circuit structure helps to reduce chip area.
[0012] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description
[0013] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of the bias voltage circuit in the prior art; Figure 2 This is a waveform diagram of each signal in the bias voltage circuit of the prior art; Figure 3 This is a schematic diagram of a bias voltage circuit for a non-volatile memory provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of another bias voltage circuit for a non-volatile memory provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a method for rapidly establishing the bias voltage for a non-volatile memory provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of timing control in the circuit provided in the embodiments of this disclosure; Figure 7 This is a simulation waveform diagram provided in the embodiments of this disclosure; Figure 8 This is a schematic diagram of a non-volatile memory provided in an embodiment of this disclosure.
[0014] illustrate: 10: Bias voltage circuit for non-volatile memory; 11: Current mirror input module; 12: Current mirror module; 13: Bias voltage generation module; 14: Load capacitor; 20: Sensitive amplifier circuit; 30: Memory cell array. Detailed Implementation
[0015] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0016] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0017] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0018] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0019] Combination Figure 1 and Figure 2 This paper briefly explains the specific control and waveform establishment of a conventional voltage bias circuit. The voltage bias circuit aims to obtain VOUT' = 2 × Vgs (Vgs is the Vgs of the NM2' / NM3' transistors; since these two MOSFETs have the same size, their Vgs are essentially equal). When the EN' signal is low, the PBIAS' voltage is the power supply voltage, and the VOUT' voltage is GND. As the EN' signal changes from low to high, PBIAS' begins to decrease from the power supply voltage, gradually decreasing to the target voltage. The VOUT' voltage gradually changes from GND to the target voltage. The EN' and ENB' signals are digitally inverse signals. When the non-volatile memory is not in read mode, this bias circuit can be turned off to save power, but there is a certain setup time required for the bias voltage to reach the target voltage from the off state to the on state. The non-volatile memory can only start reading data after the bias voltage is fully established. This cannot meet the requirements of high-speed applications, nor can it simultaneously meet the requirements of low power consumption and reduced chip area.
[0020] To achieve rapid bias voltage establishment while ensuring low power consumption and a small circuit area, combined with Figure 3 This disclosure provides a bias voltage circuit 10 for a non-volatile memory, comprising: a mirror current input module 11, a current mirror module 12, a bias voltage generation module 13, a load capacitor 14, and a first GND connected in sequence.
[0021] The current mirror module is configured to be controlled by the first enable signal EN and the second enable signal EN2_B. The mirror current input module and the bias voltage generation module are controlled by the third enable signal EN2_1 and the fourth enable signal EN2_2, as well as the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 generated by the external digital circuit, respectively.
[0022] Specifically, when the first enable signal EN is low, the voltage at point PBIAS in the current mirror module and the voltage at point VOUT in the bias voltage generation module are both power supply voltages. During the transition from low to high level of the first enable signal EN, the current mirror module and the bias voltage generation module receive the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 generated by the external digital circuit. The power supply voltages at both points PBIAS and VOUT decrease, establishing the first initial voltage and the second initial voltage, respectively. When the third enable signal EN2_1 and the fourth enable signal EN2_2 are high, and the second enable signal EN2_B is low, the first initial voltage at point PBIAS and the second initial voltage at point VOUT transform into the first target voltage and the second target voltage, respectively.
[0023] Here, when the first enable signal EN is low, the current mirror module is connected to the power supply and establishes preset voltages for the PBIAS point in the current mirror module and the VOUT point in the bias voltage generation module, respectively. Understandably, the PBIAS point and VOUT point can be set to a preset voltage using either a pull-up or pull-down method. This preset voltage can be the power supply voltage, ground voltage, or other reference voltage. In this embodiment, a PMOS transistor is used in a pull-up manner, i.e., the PMOS in the current mirror module uses the low-level first enable signal EN to preset the voltages of the PBIAS point and VOUT point to the power supply voltage. This provides a suitable initial state for rapid voltage establishment and also helps reduce power consumption during circuit shutdown.
[0024] When the first enable signal EN is high, the current mirror module disconnects from the power supply. Simultaneously, the mirror current input module receives the first time pulse signal EN_SP1 generated by the external digital circuit, and the bias voltage generation module receives the second time pulse signal EN_SP2 generated by the external digital circuit. Both the mirror current input module and the bias voltage generation module are turned on, creating a short-term path to ground, which pulls down the voltages at both PBIAS and VOUT points, establishing their preset voltages to the corresponding first and second initial voltages, respectively. In this way, before the bias voltage circuit starts operating, the voltages at PBIAS and VOUT points are established to their corresponding initial voltages, enabling rapid establishment of the bias voltage after the circuit starts operating. The first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 are short pulse signals generated by digital logic.
[0025] The third enable signal EN2_1 and the fourth enable signal EN2_2 control the switching states of the current mirror input module and the bias voltage generation module, respectively, while the second enable signal EN2_B controls the switching state of the current mirror module. When the third enable signal EN2_1 and the fourth enable signal EN2_2 are high, and the second enable signal EN2_B is low, the bias voltage circuit is turned on and connected to the external bias voltage NBIAS to output a bias voltage (this external bias voltage NBIAS is used to provide the bias current Ibias for the current mirror module). That is, the first initial voltage at point PBIAS and the second initial voltage at point VOUT are transformed into the first target voltage and the second target voltage, respectively.
[0026] During the initial voltage establishment process, the PBIAS and VOUT points are disconnected from the external bias voltage NBIAS of the mirror current input module 11. After the bias voltage circuit 10 is turned on, the PBIAS and VOUT points establish their values from the corresponding initial voltages to the corresponding target voltages.
[0027] In detail, the current mirror input module 11 and the bias voltage generation module 13 are respectively equipped with MOSFET switches controlled by the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2. Therefore, the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 can activate the current mirror input module 12 and the bias voltage generation module 13. The switches of the current mirror input module 11 and the bias voltage generation module 13 are momentarily turned on, connecting the PBIAS point in the current mirror module 12 and the VOUT point in the bias voltage generation module 13 to the reference potentials determined by the gate-source voltage of the MOSFETs inside the corresponding modules, thereby causing the preset voltages of the PBIAS point and the VOUT point to drop and establish to the corresponding initial voltages. In this process, a reasonable initial voltage is quickly set for the PBIAS point and the VOUT point, which is close to the target voltage. Thus, the establishment of the initial voltage is achieved by the momentary turn-on of the MOSFET switches, and its energy consumption is much lower than that of continuous external bias voltage supply. Furthermore, controlling the on / off state of the circuit path through MOSFET switching reduces the complexity of the circuit structure and minimizes the increase in chip area.
[0028] As mentioned earlier, during the initial voltage establishment process, the PBIAS and VOUT points are disconnected from the external bias voltage NBIAS of the current mirroring module 11. Thus, the PBIAS voltage and the bias voltage VOUT are unaffected by the external bias voltage NBIAS and the bias current provided by it. Simultaneously, the first enable signal EN changes from low to high, the current mirroring module is disconnected from the power supply and is in a non-conductive state, and the other modules are not yet officially operational. Therefore, there is no path connecting the PBIAS and VOUT points to the power supply or ground. Consequently, the PBIAS voltage and the bias voltage VOUT can be quickly established to their respective initial voltages.
[0029] Furthermore, it should be noted that the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 can be the same signal generated by an external digital circuit, but connected to different modules. Similarly, the third enable signal EN2_1 and the fourth enable signal EN2_2 can also be the same signal, but connected to different modules. Alternatively, the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 can also be a pair of signals generated simultaneously by an external digital circuit. The third enable signal EN2_1 and the fourth enable signal EN2_2 are also a pair of signals generated simultaneously.
[0030] The bias voltage circuit for non-volatile memory provided in this embodiment controls the instantaneous conduction of the mirror current input module and the bias voltage generation module via a first time pulse signal and a second time pulse, respectively, before the circuit is turned on. This establishes the voltages at the PBIAS point in the current mirror module and the VOUT point in the bias voltage generation module to their corresponding initial voltages. After the circuit starts operating, the PBIAS point and VOUT point can quickly establish their respective target voltages from their initial voltages. Thus, rapid bias voltage establishment is achieved with relatively low power consumption, and the relatively simple circuit structure helps reduce chip area.
[0031] Optionally, during the transition of the first enable signal EN from low to high, the mirror current input module and the bias voltage generation module are controlled by the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2, respectively. The power supply voltages at both the PBIAS point and the VOUT point decrease, including: when the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 transition to high, the voltage at the PBIAS point becomes the first gate-source voltage, and the voltage at the VOUT point becomes the second gate-source voltage.
[0032] Here, when the first enable signal EN transitions from low to high, the mirror current input module and the bias voltage generation module are controlled by the high-level first time pulse signal EN_SP1 and the second time pulse signal EN_SP2, respectively. The corresponding paths in the mirror current input module and the bias voltage generation module are turned on, rapidly pulling down the preset voltages at the PBIAS and VOUT points. The voltages at the PBIAS and VOUT points are then converted into the gate-source voltages of the corresponding MOS transistors in the paths. As an example, the paths in the mirror current input module and the bias voltage generation module controlled by the time pulse signals are each composed of several NMOS transistors. Taking the path of the mirror current input module as an example, one NMOS transistor acts as a switch controlled by the time pulse signal, and the gates of the other series-connected NMOS transistors are all connected to their own drains. Thus, when this path is turned on, the voltage at the PBIAS point is pulled down to the first gate-source voltage. The first gate-source voltage is the gate-source voltage of the NMOS transistor connected to the PBIAS point. Similarly, the voltage at point VOUT is transformed into the second gate-source voltage, which is the gate-source voltage of the NMOS transistor connected to point VOUT.
[0033] After the first enable signal EN transitions from low to high, and the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 transition to high, there is no path connecting the PBIAS point and VOUT point in the bias voltage circuit to the power supply terminal or ground terminal. When the path between the current mirror input module and the bias voltage generation module is momentarily turned on, the first initial voltage of the PBIAS point and the second initial voltage of the VOUT point are rapidly established. During the initial voltage establishment process, the second enable signal EN2_B remains high, causing the path between the current mirror containing the PBIAS point in the current mirror module and the power supply to be turned off. In this way, the initial voltages of the PBIAS point and VOUT point are rapidly established, and the initial voltages are close to the corresponding target voltages. After the bias voltage circuit is turned on, the PBIAS point and VOUT point can be established from the first initial voltage and the second initial voltage to the corresponding target voltage, respectively. This greatly shortens the bias voltage establishment time, meeting the circuit's requirement for rapid bias voltage establishment.
[0034] Optionally, the second enable signal EN2_B is logically opposite to the third enable signal EN2_1 and the fourth enable signal EN2_2, respectively.
[0035] Here, logically opposite enable signals are used to control the up and down paths (i.e., the paths from the two nodes to the power supply and to ground, respectively) of the PBIAS and VOUT points. During the initial voltage setup process or in low-power mode, the third enable signal EN2_1 and the fourth enable signal EN2_2 respectively cut off the paths from the PBIAS and VOUT points to ground, and the second enable signal EN2_B cuts off the paths from the PBIAS and VOUT points to the power supply. This ensures the synchronization and simplicity of the control. For example, the current mirror module 12 is typically composed of PMOS transistors, and the mirror current input module 11 and the bias voltage generation module 13 are typically composed of NMOS transistors. In this case, in low-power mode, the third enable signal EN2_1 and the fourth enable signal EN2_2 are both low-level signals to turn off the NMOS transistors they control, thus turning off the path of the NMOS transistor. The second enable signal EN2_B is a high-level signal to turn off the PMOS transistors it controls, thus turning off the path of the PMOS transistor.
[0036] Optionally, when the third enable signal EN2_1 and the fourth enable signal EN2_2 are at low level and the second enable signal EN2_B is configured to be at high level, the voltages at the PBIAS point and the VOUT point remain within the predetermined error range of the corresponding target voltage, and the bias voltage circuit enters the off state.
[0037] Here, after the target voltage is established, if the memory is not in a read state, the bias voltage circuit can be turned off to save power. Specifically, the mirror current input module 11 and the bias voltage generation module 13 are controlled to turn off by the low-level third enable signal EN2_1 and the fourth enable signal EN2_2, respectively, so that the PBIAS node and the bias voltage node are disconnected from the ground. At the same time, the current mirror module 12 is controlled to turn off by the high-level second enable signal EN2_B, so that the PBIAS point and the VOUT point are disconnected from the power supply. In this way, both the PBIAS point and the VOUT point are in a high-impedance state. On the one hand, the bias voltage circuit is turned off and there is no current path, so the circuit has no static power consumption. On the other hand, the PBIAS point and the VOUT point are in a high-impedance state, so that the voltages of the PBIAS point and the VOUT point are maintained near their respective target voltages, that is, within the predetermined error range of the corresponding target voltages. When the circuit restarts, the voltages of the PBIAS point and the VOUT point can still quickly reach the target voltage. The predetermined error range is determined based on actual needs and circuit structure.
[0038] Combination Figure 4 As shown, the current mirror module 12 includes: a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, and a sixth PMOS transistor PM6.
[0039] In this configuration, the first PMOS transistor PM1 and the second PMOS transistor PM2 form the first mirror current, and the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 form the second mirror current. The first PMOS transistor PM1 and the second PMOS transistor PM2 form the PBIAS point. The drain of the third PMOS transistor PM3 is connected to the gates of the first PMOS transistor PM1 and the second PMOS transistor PM2, respectively. The gate and source of the first PMOS transistor PM1 are both connected to the mirror current input module, and the drains of the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are respectively connected to the load capacitor 14. The gates of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are both connected to the first enable signal EN, and the gates of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are both connected to the second enable signal EN2_B.
[0040] Here, the first current mirror includes a first PMOS transistor PM1 and a second PMOS transistor PM2. The gate and drain of the first PMOS transistor PM1 are connected and connected to the current mirroring input module 11 to receive the bias current generated by the external bias voltage NBIAS for mirroring. The drain of the second PMOS transistor PM2 is connected to the bias voltage generation module 13 and the load capacitor 14. The node where the gates of the first PMOS transistor PM1 and the second PMOS transistor PM2 are located is the PBIAS point. The second current mirror is connected in series between the first current mirror and the power supply and is controlled by the second enable signal EN2_B. The sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 are both connected to the power supply, the gates are both connected to the second enable signal EN2_B, and the drains are respectively connected to the sources of the corresponding first PMOS transistor PM1 and the second PMOS transistor PM2. The gate of the third PMOS transistor PM3 is connected to the first enable signal EN, the source is connected to the power supply, and the drain is respectively connected to the gates of the first PMOS transistor PM1 and the second PMOS transistor PM2. The gate of the fourth PMOS transistor PM4 is connected to the first enable signal EN, the source is connected to the power supply, and the drain is connected to the bias voltage generation module 13 and the load capacitor 14.
[0041] The third PMOS transistor PM3 provides a preset voltage to the PBIAS point. The fourth PMOS transistor PM4 is connected in parallel across the sixth PMOS transistor PM6 and the second PMOS transistor PM2, providing a preset voltage to the VOUT point of the bias voltage generation module 13. As mentioned earlier, the preset voltage is the power supply voltage; that is, the preset voltage values for the PBIAS and VOUT points are the power supply voltage values. The sources of the fifth PMOS transistor PM5 and the sixth PMOS transistor PM6 of the second current mirror are both connected to the power supply, and their gates are both connected to the second enable signal EN2_B. During the initial voltage establishment process or at low power consumption, the second enable signal EN2_B controls the second current mirror to turn off, cutting off the path between the PBIAS and VOUT points and the power supply. During the target voltage establishment process, the second current mirror is controlled by the second enable signal EN2_B to turn on, and the first current mirror also conducts. The second and first current mirrors ensure the stability of the output current.
[0042] Optionally, the mirror current input module 11 includes a first NMOS transistor NM1, a fourth NMOS transistor NM4, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, and a second GND.
[0043] In this configuration, the fourth NMOS transistor NM4 and the first NMOS transistor NM1 are connected in series. The gate of the fourth NMOS transistor NM4 is connected to the third enable signal EN2_1, and the gate of the first NMOS transistor NM1 is connected to the external bias voltage NBIAS. The seventh NMOS transistor NM7 and the sixth NMOS transistor NM6 are connected in series. The gate of the seventh NMOS transistor NM7 is connected to its drain, and the gate of the sixth NMOS transistor NM6 is connected to the first time pulse signal EN_SP1. The sources of the first NMOS transistor NM1 and the sixth NMOS transistor NM6 are connected to the bias voltage generation module 13 via the second GND.
[0044] Here, the fourth NMOS transistor NM4 and the first NMOS transistor NM1, connected in series, form a mirror current branch. The gate of the fourth NMOS transistor NM4 is connected to the third enable signal EN2_1, and the gate of the first NMOS transistor NM1 is connected to the external bias voltage NBIAS. The seventh NMOS transistor NM7 and the sixth NMOS transistor NM6, connected in series, form the first initial voltage branch. The first initial voltage branch is connected in parallel with the mirror current branch. The first initial voltage branch is the conduction branch when the initial voltage is established. This branch is controlled by the first time pulse signal EN_SP1 to clamp the voltage at point PBIAS to the gate-source voltage of the seventh NMOS transistor NM7 corresponding to this branch, so that the first initial voltage at point PBIAS is independent of the external bias voltage. Specifically, at the instant the first time pulse signal EN_SP1=1, the sixth NMOS transistor NM6 turns on, and then the seventh NMOS transistor NM7 turns on, clamping the voltage at point PBIAS to the gate-source voltage of the seventh NMOS transistor NM7, i.e., PBIAS voltage = Vgs. NM7 .
[0045] The mirror current branch is the conducting branch when the first target voltage of PBIAS point is established. This branch is controlled by the third enable signal EN2_1 to connect the external bias voltage NBIAS and the PBIAS point. Under the influence of the external bias voltage, the PBIAS point establishes from the first initial voltage to the first target voltage. Specifically, when the third enable signal EN2_1=1 (at which time the first initial voltage branch is closed), the mirror current branch is turned on, and the external bias voltage NBIAS exerts its influence on the PBIAS point through the fourth NMOS transistor NM4 and the first NMOS transistor NM1, causing the voltage of the PBIAS point to establish from the first initial voltage to the first target voltage. In this way, the establishment of the first initial voltage and the first target voltage of the PBIAS point are achieved through two parallel branches. Furthermore, disconnecting the connection between the PBIAS point and the external bias voltage NBIAS during the first initial voltage establishment stage helps to quickly establish the initial voltage.
[0046] Optionally, the bias voltage generation module 13 includes a second NMOS transistor NM2, a third NMOS transistor NM3, a fifth NMOS transistor NM5, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, and a third GND.
[0047] In this configuration, the gates and drains of the third NMOS transistor NM3 and the ninth NMOS transistor NM9 are connected to the current mirror module and the load capacitor 14, respectively; the drain of the ninth NMOS transistor NM9 is the VOUT point. The third NMOS transistor NM3, the second NMOS transistor NM2, and the fifth NMOS transistor NM5 are connected in series. The gate of the fifth NMOS transistor NM5 is connected to the fourth enable signal EN2_2, and the gate and drain of the second NMOS transistor NM2 are connected together; the source of the fifth NMOS transistor NM5 is connected to the second GND. The ninth NMOS transistor NM9 and the eighth NMOS transistor NM8 are connected in series. The gate of the eighth NMOS transistor NM8 is connected to the second time pulse signal EN_SP2, and its source is connected to the third GND.
[0048] Here, the bias voltage generation module 13 also includes two parallel branches: a bias voltage output branch and a second initial voltage branch. The series-connected ninth NMOS transistor NM9 and eighth NMOS transistor NM8 constitute the second initial voltage branch, which is the conduction branch when the second initial voltage at point VOUT is established. This branch is controlled by the second time pulse signal EN_SP2 to clamp the second initial voltage at point VOUT onto the gate-source voltage of the ninth NMOS transistor NM9 in this branch, so that the second initial voltage at point VOUT is not affected by the external bias voltage NBIAS. At the instant the first time pulse signal EN_SP1=1, the eighth NMOS transistor NM8 turns on, and then the ninth NMOS transistor NM9 turns on, clamping the voltage at point VOUT to the gate voltage of the ninth NMOS transistor NM9, i.e., the bias voltage VOUT=Vgs. NM9 .
[0049] The third NMOS transistor NM3, the second NMOS transistor NM2, and the fifth NMOS transistor NM5, connected in series, constitute the bias voltage output branch. This branch is the conduction branch when the second target voltage is established. It is controlled by the fourth enable signal EN2_2 to connect to the current mirror module 12, allowing the mirrored bias current Ibias to flow through this branch, thus establishing the voltage at point VOUT from the second initial voltage to the second target voltage. When the fourth enable signal EN2_2=1 (at which point the second initial voltage branch is closed), the bias voltage output branch is turned on. The mirrored current output by the current mirror module 12 flows through the series-connected third NMOS transistor NM3 and second NMOS transistor NM2, rapidly establishing the bias voltage VOUT from the second initial voltage to the second target voltage. Furthermore, the output bias voltage VOUT depends on the gate-source voltage Vgs of the third NMOS transistor NM3 and the second NMOS transistor NM2. Thus, the establishment of the second initial voltage and the second target voltage at the VOUT node is achieved through two parallel branches.
[0050] Furthermore, it should be noted that the first time pulse signal EN_SP1 of the first initial voltage branch of the mirror current input module 11 and the second time pulse signal EN_SP2 of the second initial voltage branch of the bias voltage generation module are the same time pulse signal. This allows for simultaneous establishment of initial voltages at both the PBIAS and VOUT points, achieving synchronous and rapid startup of the two critical nodes of the circuit. Additionally, the third enable signal EN2_1 of the mirror current branch of the mirror current input module 11 and the fourth enable signal EN2_2 of the bias voltage output branch of the bias voltage generation module are also the same control signal. During the initial voltage establishment phase, this ensures that the PBIAS and VOUT points are disconnected from the external bias voltage, thereby guaranteeing that the voltages of the critical nodes are reliably and quickly established to the corresponding initial voltages. During the target voltage establishment phase, this ensures that the voltages of the two critical nodes are established from their corresponding initial voltages to their corresponding target voltages. Furthermore, during the low-power phase, the control of the third enable signal EN2_1 and the fourth enable signal EN2_2 disconnects the corresponding two branches, and the PBIAS and VOUT points are disconnected from ground. At the same time, the second enable signal EN2_B of the current mirror module 12 is synchronously turned off, and the PBIAS point and VOUT point are disconnected from the power supply terminal, making these two nodes in a high impedance state.
[0051] In addition, it should be noted that the first GND, the second GND, and the third GND refer to the grounding of different circuit modules, providing a zero-potential reference point for each module.
[0052] Based on the above bias voltage circuit, combined with Figure 5 As shown, this disclosure provides a method for rapidly establishing the bias voltage for non-volatile memory, including: S501, when the first enable signal EN is low, the voltage at point PBIAS in the current mirror module and the voltage at point VOUT in the bias voltage generation module are both power supply voltages.
[0053] S502, when the first enable signal EN changes from low level to high level, the external digital circuit generates a first time pulse signal EN_SP1 and a second time pulse signal EN_SP2, which are input to the mirror current input module and the bias voltage generation module. The power supply voltage at PBIAS point and VOUT point begins to drop, and the first initial voltage and the second initial voltage are established respectively.
[0054] S503, when the third enable signal EN2_1 and the fourth enable signal EN2_2 are at high level and the second enable signal EN2_B is at low level, the first initial voltage and the second initial voltage of PBIAS point and VOUT point are transformed into the first target voltage and the second target voltage, respectively.
[0055] This is further combined with timing control diagrams, i.e. Figure 6 The method for rapidly establishing bias voltage is explained. Figure 6 The third enable signal EN2_1 and the fourth enable signal EN2_2 are the same enable signal, therefore Figure 6 In this context, EN2 represents the same time pulse signal. The first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 are also the same time pulse signal. Figure 6 In this circuit, EN_SP is used as the denoting signal. When the first enable signal EN=0 of the bias voltage circuit, the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are turned on, making the voltages at points PBIAS and VOUT the supply voltage. When the first enable signal EN=1, the first initial voltage branch of the current mirroring module and the second initial voltage branch of the bias voltage generation module are provided with the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2, respectively. During the process of EN_SP1=1 and EN_SP2=1, the voltage at point PBIAS will rapidly change to Vgs. NM7 The voltage at VOUT will also quickly change to Vgs. NM9 At this time, the branch containing the external bias voltage is in the off state (i.e., the third enable signal EN2_1=0), so that the PBIAS and VOUT points are not affected by the external bias voltage and the bias current generated by it. During this process, the fourth enable signal EN2_2=0 and the second enable signal EN2_B=1; so that there is no path from the PBIAS and VOUT points to the power supply terminal and the ground terminal. Thus, the PBIAS voltage and the bias voltage are established to their respective initial voltages, i.e., the gate-source voltages of their respective MOSFETs. During the initial voltage establishment process, the circuit is in the off state, and the power consumption is extremely low only when the initial voltage branch is instantaneously turned on.
[0056] After the initial voltage is established, the third enable signal EN2_1=1 and the fourth enable signal EN2_2=1 (simultaneously, the second enable signal EN2_B=0). This activates the mirror current branch of the mirror current input module, the bias voltage output branch of the bias voltage generation module, and the two current mirrors of the current mirror module. The voltages at points PBIAS and VOUT then build up from their respective initial voltages to their corresponding target voltages. In other words, once the bias voltage circuit is in the startup state, the voltages at points PBIAS and VOUT begin to build up from their respective initial voltages, significantly shortening the time required to build up to the target voltage.
[0057] The method for rapidly establishing bias voltage for non-volatile memory provided in this disclosure involves instantaneously turning on the initial voltage branches of the mirror current input module and the bias voltage generation module when the first enable signal EN transitions from low to high. This is achieved by using time pulse signals (i.e., the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2) to establish the voltages at the PBIAS and VOUT points to their respective initial voltages. Subsequently, by controlling the second enable signal EN2_B, the third enable signal EN2_1, and the fourth enable signal EN2_2 to start the circuit, the PBIAS and VOUT points can rapidly establish their respective target voltages from their initial voltages. This achieves rapid bias voltage establishment with minimal power consumption.
[0058] Optionally, after step S503, the method further includes: when the third enable signal EN2_1 and the fourth enable signal EN2_2 are at a low level and the second enable signal EN2_B is at a high level, the path connecting the PBIAS point and the VOUT point to the power supply and GND is disconnected, and the bias voltage circuit is in a low power consumption state.
[0059] Here, after establishing the bias voltage to the second target voltage, if the non-volatile memory is not in read mode, the control circuit enters a low-power mode. This means controlling the third enable signal EN2_1=0 and the fourth enable signal EN2_2=0 (while simultaneously, the second enable signal EN2_B=1), shutting off the paths from VOUT and PBIAS points to the power supply and to ground. This puts both PBIAS and VOUT points in a high-impedance state, maintaining their voltages within the predetermined error range of their respective target voltages. In other words, both PBIAS and VOUT points are in a floating state, and their voltages remain near their respective target voltages. When the circuit restarts, controlling the third enable signal EN2_1=1 and the fourth enable signal EN2_2=1 (while simultaneously, the second enable signal EN2_B=0) allows the voltages of PBIAS and VOUT points to quickly change to their corresponding target voltages. Thus, the circuit restarts without additional power consumption and quickly reaches the corresponding target voltage.
[0060] Simulations were performed on the bias voltage circuits in the prior art and the bias voltage circuits in the embodiments of this disclosure to compare the settling time of the target voltage. Combined with... Figure 7 The actual simulation waveform is shown in the figure, where Vout is the output voltage of the traditional scheme and Vout_new is the output voltage of this scheme. Under the same external bias voltage, it can be seen that the target voltage settling time in the embodiment of this disclosure is accelerated by more than 60%. Figure 7 The signals from top to bottom are: the first enable signal EN, the third enable signal EN2_1, and the fourth enable signal EN2_2 (these two are the same enable signal, therefore...). Figure 7 (represented by EN2 in Chinese), the first time pulse signal EN_SP1 and the second time pulse signal EN_SP2 (both are the same time pulse signal, therefore...) Figure 7 (represented by EN_SP in Chinese), Vout, and Vout_new.
[0061] Combination Figure 8 As shown, this embodiment of the present disclosure provides a non-volatile memory, including: a sensitive amplifier circuit 20, a memory cell array 30, an NMOS transistor NM10, and the aforementioned bias voltage circuit 10. The drain of the NMOS transistor NM10 is connected to the sensitive amplifier circuit 20, the source is connected to the memory cell array 30, and the gate is connected to the bias voltage circuit 10.
[0062] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0063] It should also be noted that, in this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified. The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0064] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A bias voltage circuit for a non-volatile memory, characterized in that, include: The system includes a current mirror module, a mirrored current input module, a bias voltage generation module, a load capacitor, and a first GND. The current mirror module is configured to be controlled by a first enable signal and a second enable signal; The mirror current input module and the bias voltage generation module are controlled by the third enable signal and the fourth enable signal, as well as the first time pulse signal and the second time pulse signal generated by the external digital circuit, respectively. When the first enable signal is low, the voltage at point PBIAS in the current mirror module and the voltage at point VOUT in the bias voltage generation module are both the power supply voltage. During the transition from low to high level of the first enable signal, the mirror current input module and the bias voltage generation module are controlled by the first time pulse signal and the second time pulse signal, respectively. The power supply voltages at PBIAS point and VOUT point both decrease, and the first initial voltage and the second initial voltage are established, respectively. When the third and fourth enable signals are high and the second enable signal is low, the first initial voltage at point PBIAS and the second initial voltage at point VOUT are converted into the first target voltage and the second target voltage, respectively.
2. The bias voltage circuit according to claim 1, characterized in that, During the transition of the first enable signal EN from low to high, the mirror current input module and the bias voltage generation module are controlled by the first time pulse signal and the second time pulse signal, respectively. The power supply voltages at PBIAS and VOUT points both decrease, including: when the first time pulse signal and the second time pulse signal transition to high, the voltage at PBIAS point becomes the first gate-source voltage, and the voltage at VOUT point becomes the second gate-source voltage.
3. The bias voltage circuit according to claim 1, characterized in that, The second enable signal is logically opposite to the third and fourth enable signals, respectively.
4. The bias voltage circuit according to claim 1, characterized in that, Also includes: When both the third and fourth enable signals are low and the second enable signal is high, the voltages at the PBIAS and VOUT points remain within the predetermined error range of the corresponding target voltages, and the bias voltage circuit enters the off state.
5. The bias voltage circuit according to any one of claims 1 to 4, characterized in that, The current mirror module includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor; The first PMOS transistor and the second PMOS transistor form the first mirror current, and the fifth PMOS transistor and the sixth PMOS transistor form the second mirror current; the gates of the first PMOS transistor and the second PMOS transistor form the PBIAS point; the drain of the third PMOS transistor is connected to the gates of the first PMOS transistor and the second PMOS transistor respectively. The gate and source of the first PMOS transistor are both connected to the mirror current input module, and the drains of the second and fourth PMOS transistors are respectively connected to the load capacitor. The gates of the third and fourth PMOS transistors are both connected to the first enable signal, and the gates of the fifth and sixth PMOS transistors are both connected to the second enable signal.
6. The bias voltage circuit according to any one of claims 1 to 4, characterized in that, The mirror current input module includes: a first NMOS transistor, a fourth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and a second GND; The fourth NMOS transistor is connected in series with the first NMOS transistor. The gate of the fourth NMOS transistor is connected to the third enable signal EN2_1, and the gate of the first NMOS transistor is connected to an external bias voltage. The seventh NMOS transistor and the sixth NMOS transistor are connected in series. The gate and drain of the seventh NMOS transistor are connected, and the gate of the sixth NMOS transistor is connected to the first time pulse signal. The sources of the first and sixth NMOS transistors are connected to the bias voltage generation module via the second GND.
7. The bias voltage circuit according to any one of claims 1 to 4, characterized in that, The bias voltage generation module includes: a second NMOS transistor, a third NMOS transistor, a fifth NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a third GND; Among them, the gate and drain of the third NMOS transistor and the ninth NMOS transistor are connected to the current mirror module and the load capacitor respectively; the drain of the ninth NMOS transistor is the VOUT point. The third NMOS transistor, the second NMOS transistor, and the fifth NMOS transistor are connected in series. The gate of the fifth NMOS transistor is connected to the fourth enable signal, and the gates of the second NMOS transistors are all connected to the drain. The ninth NMOS transistor and the eighth NMOS transistor are connected in series. The gate of the eighth NMOS transistor is connected to the second time pulse signal, and its source is connected to the third GND.
8. A method for rapidly establishing bias voltage for non-volatile memory, characterized in that, Based on the bias voltage circuit according to any one of claims 1 to 7, the method includes: When the first enable signal is low, the voltage at the PBIAS point in the current mirror module and the voltage at the VOUT point in the bias voltage generation module are both the power supply voltage. When the first enable signal changes from low level to high level, the external digital circuit generates a first time pulse signal and a second time pulse signal, which are respectively input to the mirror current input module and the bias voltage generation module. The power supply voltage at PBIAS point and VOUT point begins to drop, and the first initial voltage and the second initial voltage are established respectively. When the third and fourth enable signals are high and the second enable signal is low, the first initial voltage and the second initial voltage at PBIAS and VOUT points are converted into the first target voltage and the second target voltage, respectively.
9. The method according to claim 8, characterized in that, Also includes: When the third and fourth enable signals are low and the second enable signal is high, the path connecting the PBIAS point and VOUT point to the power supply and GND is disconnected, and the bias voltage circuit is in a low-power state.
10. A non-volatile memory, characterized in that, include: A sensitive amplifier circuit, a memory cell array, an NMOS transistor, and a bias voltage circuit as described in any one of claims 1 to 7; The drain of the NMOS transistor is connected to the sensitive amplifier circuit, its source is connected to the memory cell array, and its gate is connected to the bias voltage circuit.