Zero-voltage switch control device, audio amplifier and chip

Abstract

The embodiment of the invention provides a zero-voltage switch control device, an audio amplifier and a chip. The voltage switch control device comprises a voltage detection module and a zero-voltage switch control module, the voltage detection module is used for detecting the change of the output voltage of a positive power unit and the change of the input voltage of a negative power unit included in the power stage, and the zero voltage switch control module is used for delaying a driving signal according to the change of the output voltage of the positive power unit and the change of the input voltage of the negative power unit. According to the invention, the zero-voltage switch control device delays the driving signal according to the change of the output voltage of the positive power unit and the input voltage of the negative power unit included in the power level, so that the signal distortion problem caused by additional delay can be avoided while zero-voltage starting of part of power tubes in the power level is realized; and the working frequency and the duty ratio of the power level are not changed in the process of performing zero-voltage starting so as to reduce the switching loss.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a zero-voltage switching control device, an audio amplifier, and a chip. Background Technology

[0002] Existing Class D audio amplifiers have certain advantages in efficiency compared to other types (Class A, Class AB). Currently, in low-voltage, low-to-medium power applications, the output power transistors of Class D audio amplifiers are relatively small in size, resulting in a relatively small proportion of switching losses. However, as the output voltage increases, the proportion of switching losses introduced by the crossover between the voltage and current of the power transistors increases.

[0003] Currently, in order to reduce the total harmonic distortion (THD) of Class D audio amplifiers, a fixed dead time control (DTC) is introduced to prevent common circuitry when the high-side and low-side transistors of the power stage are turned on. Moreover, this dead time should be as small as possible, close to 0, without causing common circuitry.

[0004] However, in the field of half-bridge drive, the introduction of fixed dead-time control to prevent common switching will inevitably lead to hard switching of power transistors. That is to say, when the power transistor is turned on, the voltage difference between the source and drain of the power transistor is relatively large, close to the power supply voltage. As the power supply voltage and output power in power application scenarios become higher and higher, hard switching leads to increased switching losses, thereby affecting the reliability of system operation. Summary of the Invention

[0005] In view of this, embodiments of this application provide a zero-voltage switching control device, an audio amplifier, and a chip to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of the present application, a zero-voltage switching control device is provided, comprising: a voltage detection module and a zero-voltage switching control module; the voltage detection module is used to detect changes in the output voltage of a positive power unit and the input voltage of a negative power unit included in a power stage, wherein a first terminal of the positive power unit is electrically connected to a first power supply, a second terminal of the positive power unit is electrically connected to the first terminal of the negative power unit, the second terminal of the negative power unit is grounded, and the second terminal of the positive power unit is electrically connected to a speaker; the power stage is used to amplify the power of a drive signal output by an output drive, and the amplified drive signal is used to drive the speaker to emit sound; the zero-voltage switching control module is used to delay the drive signal according to the changes in the output voltage of the positive power unit and the input voltage of the negative power unit, and the power transistors in the positive power unit and the negative power unit perform on-off and off actions based on the delayed drive signal.

[0007] In one possible implementation, the positive power unit includes a first power transistor electrically connected to the first power supply, and the negative power unit includes a second power transistor grounded; the gates of the first power transistor and the second power transistor are both electrically connected to the output drive, and the voltage output terminal of the first power transistor is electrically connected to the voltage input terminal of the second power transistor and the input terminal of the low-pass filter.

[0008] In one possible implementation, the voltage detection module is used to detect the slope of the source voltage of the first power transistor; the zero-voltage switching control module is used to determine the first power transistor as the target power transistor when the slope of the source voltage of the first power transistor is less than 0 and the absolute value of the slope of the source voltage of the first power transistor is greater than a first slope threshold corresponding to the first power transistor, and to determine a first target duration based on the duration of the change in the source voltage of the first power transistor; when the slope of the source voltage of the first power transistor is greater than 0 and the slope of the source voltage of the first power transistor is greater than a second slope threshold corresponding to the second power transistor, to determine the second power transistor as the target power transistor, and to determine a second target duration based on the duration of the change in the source voltage of the first power transistor; within one signal cycle of the power level, if the first power transistor is determined to be the target power transistor, the second power transistor is determined to be a non-target power transistor. If the first power transistor is identified as the target power transistor and the first power transistor is identified as a non-target power transistor, then within one signal cycle of the power level, the turn-on signal, the turn-off signal, the turn-on signal, and the turn-off signal of the second power transistor are all delayed by the first target duration. If both the first power transistor and the second power transistor are identified as the target power transistors, then within one signal cycle of the power level, the turn-on signal, the turn-off signal, the turn-on signal, and the turn-off signal of the second power transistor are all delayed by the second target duration.

[0009] In one possible implementation, the voltage detection module is configured to acquire a first drain-source voltage difference of the first power transistor and a second drain-source voltage difference of the second power transistor according to a preset time interval; the zero-voltage switching control module is configured to determine the first power transistor as the target power transistor when the absolute value of the first drain-source voltage difference is greater than 0, and determine a third target duration based on the duration for which the first drain-source voltage difference decreases to less than or equal to a voltage threshold; when the absolute value of the second drain-source voltage difference is greater than 0, determine the second power transistor as the target power transistor, and determine a fourth target duration based on the duration for which the second drain-source voltage difference decreases to less than or equal to a voltage threshold; within one signal cycle of the power level, if the first power transistor is determined to be the target power transistor and the second power transistor is determined to be a non-target power transistor, then within one signal cycle of the power level, the first power transistor is... The turn-on signal of the first power transistor, the turn-off signal of the second power transistor, and the turn-on signal of the second power transistor are all delayed by the third target duration. If the second power transistor is determined to be the target power transistor and the first power transistor is determined to be a non-target power transistor, then within one signal cycle of the power level, the turn-on signal of the first power transistor, the turn-off signal of the first power transistor, the turn-on signal of the second power transistor, and the turn-off signal of the second power transistor are all delayed by the fourth target duration. If both the first power transistor and the second power transistor are determined to be the target power transistors, then within one signal cycle of the power level, the turn-on signal of the first power transistor and the turn-off signal of the first power transistor are delayed by the third target duration, and the turn-on signal of the second power transistor and the turn-off signal of the second power transistor are delayed by the fourth target duration.

[0010] In one possible implementation, the voltage detection module includes: a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a first NMOS transistor, a first PMOS transistor, a first current mirror, a second current mirror, a buffer, and an inverter; the first terminal of the first capacitor is electrically connected to the voltage output terminal of the first power transistor, the second terminal of the first capacitor is electrically connected to the source of the first NMOS transistor and the source of the first PMOS transistor, the gate of the first NMOS transistor is electrically connected to the gate of the first PMOS transistor, the first terminal of the first resistor, the first terminal of the second resistor, the first terminal of the second capacitor, and the first terminal of the third capacitor, the drain of the first NMOS transistor is electrically connected to the input terminal of the first current mirror, the output terminal of the first current mirror is electrically connected to the input terminal of the buffer, the drain of the first PMOS transistor is electrically connected to the input terminal of the second current mirror, and the output terminal of the second current mirror is electrically connected to the input terminal of the inverter; the output terminals of the buffer and the inverter are electrically connected to the zero-voltage switch control module.

[0011] In one possible implementation, the first current mirror includes a second PMOS transistor, a third PMOS transistor, and a first current source; the second current mirror includes a second NMOS transistor, a third NMOS transistor, and a second current source; the drain of the second PMOS transistor is electrically connected to the drain of the first NMOS transistor and the gate of the second PMOS transistor; the source of the second PMOS transistor is electrically connected to the second terminal of the first resistor, the second terminal of the second capacitor, the second power supply, and the source of the third PMOS transistor; the gate of the third PMOS transistor is electrically connected to the gate of the second PMOS transistor; and the drain of the third PMOS transistor is electrically connected to the first... The input terminal of the current source is electrically connected to the input terminal of the buffer, and the output terminal of the first current source is grounded; the drain of the second NMOS transistor is electrically connected to the drain of the first PMOS transistor and the gate of the second NMOS transistor, the source of the second NMOS transistor is electrically connected to the second terminal of the second resistor, the second terminal of the third capacitor and the source of the third NMOS transistor and grounded, the gate of the third NMOS transistor is electrically connected to the gate of the second NMOS transistor, the drain of the third NMOS transistor is electrically connected to the output terminal of the second current source and the input terminal of the inverter, and the input terminal of the second current source is electrically connected to the second power supply.

[0012] In one possible implementation, the ratio of the width-to-length ratio of the second NMOS transistor to that of the third NMOS transistor is K1, and the ratio of the width-to-length ratio of the second PMOS transistor to that of the third PMOS transistor is K2, wherein K1 and K2 are greater than 1; correspondingly, the first slope threshold is determined by the following formula:

[0013] in, Used to characterize the first slope threshold Used to characterize the current value output by the second current source. The capacitance value of the first capacitor is used to characterize the second slope threshold, which is determined by the following formula:

[0014] in, Used to characterize the second slope threshold, Used to characterize the current value output by the first current source. The capacitance value used to characterize the first capacitor.

[0015] In one possible implementation, the zero-voltage switch control module is configured to set the third target duration or the fourth target duration to be less than or equal to the duration threshold when the third target duration or the fourth target duration is greater than the duration threshold.

[0016] In one possible implementation, the low-pass filter includes an inductor, a fourth capacitor, and a third resistor. The first end of the inductor is electrically connected to the voltage output terminal of the first power transistor, and the second end of the inductor is electrically connected to the first end of the fourth capacitor and the first end of the third resistor. The second end of the fourth capacitor is grounded, and the second end of the third resistor is grounded.

[0017] According to a second aspect of the embodiments of this application, a zero-voltage switching control device is provided, comprising: a voltage detection module and a zero-voltage switching control module, wherein the zero-voltage switching control module includes a delay unit; the voltage detection module includes: a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a first NMOS transistor, a first PMOS transistor, a first current mirror, a second current mirror, a buffer, and an inverter; a first terminal of the first capacitor is electrically connected to the voltage output terminal of a first power transistor included in the forward power unit and electrically connected to a first power supply, and a second terminal of the first capacitor is connected to the source of the first NMOS transistor and the first PMOS transistor. The source of the OS transistor is electrically connected. The gate of the first NMOS transistor is electrically connected to the gate of the first PMOS transistor, the first terminal of the first resistor, the first terminal of the second resistor, the first terminal of the second capacitor, and the first terminal of the third capacitor. The drain of the first NMOS transistor is electrically connected to the input terminal of the first current mirror. The output terminal of the first current mirror is electrically connected to the input terminal of the buffer. The drain of the first PMOS transistor is electrically connected to the input terminal of the second current mirror. The output terminal of the second current mirror is electrically connected to the input terminal of the inverter. The output terminals of the buffer and the inverter are electrically connected to the delay unit.

[0018] According to a third aspect of the embodiments of this application, an audio amplifier is provided, comprising: a zero-voltage switching control device, an analog-to-digital converter, a pulse width modulator, an output driver, a power stage, and a low-pass filter as described in any of the first and second aspects of the embodiments; the power stage comprising a positive power unit and a negative power unit; the analog-to-digital converter for converting a first analog audio signal into an audio digital signal; the pulse width modulator for outputting a pulse width modulation signal based on the audio digital signal and a reference signal; the output driver for outputting a drive signal based on the pulse width modulation signal; and the power stage for processing the drive signal. The power is amplified and the amplified drive signal is input to the low-pass filter. The low-pass filter is used to generate a second analog audio signal based on the amplified drive signal, and the second analog audio signal is used to drive the speaker to produce sound. The zero-voltage switching control device is used to detect the changes in the output voltage of the positive power unit and the input voltage of the negative power unit included in the power stage, and to delay the drive signal based on the changes in the output voltage of the positive power unit and the input voltage of the negative power unit. The power transistors in the positive power unit and the negative power unit perform on and off actions based on the delayed drive signal.

[0019] According to a fourth aspect of the embodiments of this application, a chip is provided, including the zero-voltage switching control device or the audio amplifier described in the second aspect of the embodiments, as described in any one of the first and second aspects of the embodiments.

[0020] As can be seen from the above technical solution, by delaying the drive signal according to the changes in the output voltage of the positive power unit and the input voltage of the negative power unit included in the power stage by the zero-voltage switching control device, it is possible to achieve zero-voltage turn-on of some power transistors in the power stage, thereby reducing switching losses and avoiding signal distortion caused by additional delay. This ensures that the operating frequency and duty cycle of the power stage do not change during the zero-voltage turn-on process. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0022] Figure 1 This is a schematic diagram of a zero-voltage switch control device provided in an embodiment of this application; Figure 2 This is a schematic diagram of a power stage provided in an embodiment of this application; Figure 3 This is a schematic diagram of another power stage provided in an embodiment of this application; Figure 4 This is a schematic diagram of delaying the drive signal when only the first power transistor is the target power transistor within the signal cycle of a power level; Figure 5 This is a schematic diagram of delaying the drive signal when only the second power transistor is the target power transistor within the signal cycle of a power level; Figure 6 This is a schematic diagram of delaying the drive signal when both the first and second power transistors are target power transistors within a signal cycle of a power level. Figure 7 This is a schematic diagram of a voltage detection module provided in an embodiment of this application; Figure 8 This is a schematic diagram of another voltage detection module provided in an embodiment of this application; Figure 9 This is a schematic diagram of a low-pass filter provided in an embodiment of this application; Figure 10 This is a schematic diagram of an audio amplifier provided in an embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0024] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0025] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0026] This application provides a zero-voltage switching control device, including a voltage detection module and a zero-voltage switching control module. The voltage detection module detects changes in the output voltage of the positive power unit and the input voltage of the negative power unit within a power stage. A first terminal of the positive power unit is electrically connected to a first power supply, a second terminal of the positive power unit is electrically connected to the first terminal of the negative power unit, the second terminal of the negative power unit is grounded, and the second terminal of the positive power unit is electrically connected to a speaker. The power stage amplifies the output drive signal, and the amplified drive signal drives the speaker to produce sound. The zero-voltage switching control module delays the drive signal based on changes in the output voltage of the positive power unit and the input voltage of the negative power unit. The power transistors in the positive and negative power units then perform on / off actions based on the delayed drive signal.

[0027] The voltage detection module detects changes in the output voltage of the positive power unit and the input voltage of the negative power unit within the power stage. The zero-voltage switching control module determines which power transistors in the positive and negative power units can be switched at zero voltage based on these voltage changes. It then delays the drive signal from the output drive to the power stage, causing the power transistors in the positive and negative power units to turn on and off based on the delayed drive signal. The power stage utilizes high-power devices (such as MOSFETs) in the positive and negative power units to convert and amplify the voltage of the first power supply according to the drive signal, outputting a second analog audio signal. This second analog audio signal is used to drive the speaker to produce sound.

[0028] Specifically, Figure 1 This is a schematic diagram of a zero-voltage switch control device provided in an embodiment of this application, as shown below. Figure 1 As shown, the zero-voltage switching control device 10 includes a voltage detection module 11 and a zero-voltage switching control module 12. The voltage detection module 11 is used to detect changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22 included in the power stage 20. The first terminal of the positive power unit 21 is electrically connected to a first power supply PVDD (power supply), the second terminal of the positive power unit 21 is electrically connected to the first terminal of the negative power unit 22, the second terminal of the negative power unit 22 is grounded, and the second terminal of the positive power unit 21 is electrically connected to the input terminal of the low-pass filter 30. The power stage 20 is used to amplify the drive signal output by the output drive 40, so that the low-pass filter 30 generates a second analog audio signal based on the amplified drive signal. The second analog audio signal is used to drive the speaker 200 to produce sound.

[0029] The zero-voltage switching control module 12 is used to delay the drive signal according to the changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22. The power transistors in the positive power unit 21 and the negative power unit 22 perform turn-on and turn-off actions based on the delayed drive signal.

[0030] In the audio amplifier, the input first analog audio signal undergoes oversampling and noise shaping to convert it into a high-frequency digital audio signal, improving signal accuracy, suppressing quantization noise, and distributing noise to the high-frequency range. Then, the digital audio signal is modulated according to the input reference signal, outputting a pulse-width modulated (PWM) signal. The output driver 40 in the audio amplifier then performs preliminary amplification and shaping of the PWM signal to enhance its driving capability and outputs a drive signal. The power stage 20 utilizes high-power devices (such as MOSFETs) in the positive power unit 21 and negative power unit 22 to convert and amplify the voltage of the first power supply PVDD according to the drive signal, outputting a second analog audio signal to the low-pass filter 30. The low-pass filter 30 (LPF) filters out the high-frequency carrier component in the second analog audio signal, restoring a smooth analog audio signal, which then drives the speaker 200 to produce sound.

[0031] In this process, to reduce total harmonic distortion (THD), zero-voltage switching (ZVS) is performed on the high-power devices in the positive power unit 21 and negative power unit 22 of the power stage 20 via the zero-voltage switching control device 10. Specifically, the voltage detection module 11 in the zero-voltage switching control device 10 detects changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22 of the power stage 20. The zero-voltage switching control module 12 determines which power transistors in the positive power unit 21 and negative power unit 22 can be zero-voltage switched based on the voltage changes. Then, the zero-voltage switching control module 12 delays the drive signal output from the output drive 40 to the power stage 20, causing the power transistors in the positive power unit 21 and negative power unit 22 to perform turn-on and turn-off actions based on the delayed drive signal.

[0032] Specifically, the positive power unit 21 includes a first power transistor 211 electrically connected to the first power supply PVDD, and the negative power unit 22 includes a second power transistor 221 grounded. The gate of the first power transistor 211 and the gate of the second power transistor 221 are both electrically connected to the output driver 40, and the voltage output terminal of the first power transistor 211 is electrically connected to the voltage input terminal of the second power transistor 221 and the input terminal of the low-pass filter 30.

[0033] The first power transistor 211 and the second power transistor 221 can both be PMOS transistors, both be NMOS transistors, or both be gallium nitride transistors (GaN FETs).

[0034] When both the first power transistor 211 and the second power transistor 221 are NMOS transistors, such as Figure 2 As shown, the positive power unit 21 includes a first power transistor 211, a first diode 212, and a first capacitor 213, and the negative power unit 22 includes a second power transistor 221, a second diode 222, and a second capacitor 223.

[0035] The source of the first power transistor 211 is electrically connected to the drain of the second power transistor 221 and the input terminal of the low-pass filter 30. The drain of the first power transistor 211 is electrically connected to the first power supply PVDD, the cathode of the first diode 212, and the first terminal of the first capacitor 213. The anode of the first diode 212 is electrically connected to the second terminal of the first capacitor 213 and the source of the first power transistor 211. The source of the second power transistor 221 is electrically connected to the anode of the second diode 222 and the second terminal of the second capacitor 223 and grounded. The cathode of the second diode 222 is electrically connected to the first terminal of the second capacitor 223 and the drain of the second power transistor 221. The gates of the first power transistor 211 and the second power transistor 221 are electrically connected to the output driver 40. When both the first power transistor 211 and the second power transistor 221 are PMOS transistors, the structure of the power stage 20 is as follows: Figure 3 As shown, with Figure 2 Similarly, Figure 2 The first power transistor 211 and the second power transistor 221 are replaced with PMOS transistors, and the remaining connections are similar and will not be described again. When both the first power transistor 211 and the second power transistor 221 are gallium nitride transistors, the structure of power stage 20 is the same as... Figure 2 Similarly, but excluding parasitic capacitances 213 (first capacitor) and 223, and excluding parasitic diodes 212 (first diode) and 222 (second diode).

[0036] The voltage detection module 11 is used to detect the slope of the voltage at the voltage output terminal of the first power transistor 211.

[0037] The zero-voltage switching control module 12 is used to determine the first power transistor 211 as the target power transistor when the slope of the voltage at the voltage output terminal of the first power transistor 211 is less than 0 and the absolute value of the slope of the voltage at the voltage output terminal of the first power transistor 211 is greater than the first slope threshold corresponding to the first power transistor 211, and to determine the first target duration based on the duration of the voltage change at the voltage output terminal of the first power transistor 211; and to determine the second power transistor 221 as the target power transistor when the slope of the voltage at the voltage output terminal of the first power transistor 211 is greater than 0 and the slope of the voltage at the voltage output terminal of the first power transistor 211 is greater than the second slope threshold corresponding to the second power transistor 221, and to determine the second target duration based on the duration of the voltage change at the voltage output terminal of the first power transistor 211.

[0038] based on Figure 2 The circuit shown detects the changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22 in the power stage 20 by detecting the slope (dV / dt) of the source voltage of the first power transistor 211. Simultaneously, since the first analog audio signal input to the audio amplifier is a sine wave, this causes the current I flowing through the inductor in the low-pass filter 30 to... L The direction of the current changes with the sign of the first analog audio signal. When the first power transistor 211 is in the off state, when the current flows from the first terminal of the inductor to the second terminal connected to the source of the first power transistor 211, I... L <0, corresponding to a slope of the output voltage of the first power transistor 211 being less than 0. Within one signal cycle of power stage 20 (the first power transistor 211 and the second power transistor 221 each perform a complete turn-on and turn-off operation once), if I L <0, during this process the source voltage of the first power transistor 211 will be affected by I L The output voltage of the first power transistor 211 is affected by the first diode 212, causing the source voltage of the first power transistor 211 to continue to increase. One of the conditions for the second power transistor 221 to achieve zero-voltage switching is that the source voltage of the first power transistor 211 approaches 0. Therefore, only the first power transistor 211 can achieve zero-voltage switching at this time. Furthermore, if the absolute value of the slope of the source voltage of the first power transistor 211 is greater than the first slope threshold corresponding to the first power transistor 211, it proves that the first power transistor 211 can achieve zero-voltage switching. In this case, the first power transistor 211 is determined as the target power transistor, and the first target duration is determined based on the duration of the change in the source voltage of the first power transistor 211. The first target duration is the additional dead time. Similarly, if the slope of the source voltage of the first power transistor 211 is greater than 0 and the slope of the source voltage of the first power transistor 211 is greater than the second slope threshold corresponding to the second power transistor 221, then the second power transistor 221 is determined as the target power transistor.

[0039] Within a signal cycle of power stage 20, if the first power transistor 211 is determined to be the target power transistor and the second power transistor 221 is determined to be a non-target power transistor, then within a signal cycle of power stage 20, the turn-on signal of the first power transistor 211, the turn-off signal of the first power transistor 211, the turn-on signal of the second power transistor 221, and the turn-off signal of the second power transistor 221 are all delayed by a first target duration. A schematic diagram illustrating the delay of the drive signal when only the first power transistor is the target power transistor within a signal cycle of power stage is shown below. Figure 4 As shown, where I L I is used to characterize the current flowing through the inductor in the low-pass filter 30. L It can be broken down into I, which corresponds to the audio frequency. OUT_AC I and the switching frequency of power stage 20 are consistent OUT_RIP `slope_rise_H` is used to characterize the slope of the source voltage of the first power transistor 211 being less than 0, V. OUT V is used to characterize the source voltage of the first power transistor 211. GSH_pre V is used to characterize the drive signal for the first power transistor 211 in the drive signal. GSH V is used to characterize the drive signal for the first power transistor 211 in the delayed drive signal. GSL_pre V is used to characterize the drive signal for the second power transistor 221 in the drive signal. GSL T is used to characterize the drive signal for the second power transistor 221 in the delayed drive signal. d1 Used to characterize the duration of the first target. When the first power transistor 211 is determined to be the target power transistor and the second power transistor 221 is determined to be a non-target power transistor, if a slope signal is detected after the second power transistor 221 is turned off, the first power transistor 211 will be immediately blocked from turning on. The first power transistor 211 will only be allowed to turn on after the detected slope has been reset.

[0040] Within a signal cycle of power stage 20, if the second power transistor 221 is determined to be the target power transistor and the first power transistor 211 is determined to be a non-target power transistor, then within a signal cycle of power stage 20, the turn-on signal of the first power transistor 211, the turn-off signal of the first power transistor 211, the turn-on signal of the second power transistor 221, and the turn-off signal of the second power transistor 221 are all delayed by a second target duration. A schematic diagram illustrating the delay of the drive signal when only the second power transistor is the target power transistor within a signal cycle of a power stage is shown below. Figure 5 As shown, where I L I is used to characterize the current flowing through the inductor in the low-pass filter 30. L It can be broken down into I, which corresponds to the audio frequency. OUT_AC I and the switching frequency of power stage 20 are consistentOUT_RIP `slope_fall_H` is used to characterize the slope of the source voltage of the first power transistor 211 being greater than 0. OUT V is used to characterize the source voltage of the first power transistor 211. GSH_pre V is used to characterize the drive signal for the first power transistor 211 in the drive signal. GSH V is used to characterize the drive signal for the first power transistor 211 in the delayed drive signal. GSL_pre V is used to characterize the drive signal for the second power transistor 221 in the drive signal. GSL T is used to characterize the drive signal for the second power transistor 221 in the delayed drive signal. d2 This is used to characterize the duration of the second target. When the second power transistor 221 is determined to be the target power transistor and the first power transistor 211 is determined to be a non-target power transistor, if a slope signal is detected after the first power transistor 211 is turned off, the second power transistor 221 will be immediately blocked from turning on. The second power transistor 221 will only be allowed to turn on after the detected slope has been reset.

[0041] Within a signal cycle of power stage 20, if both the first power transistor 211 and the second power transistor 221 are identified as target power transistors, then within a signal cycle of power stage 20, the turn-on signal and the turn-off signal of the first power transistor 211 are both delayed by a first target duration, and the turn-on signal and the turn-off signal of the second power transistor 221 are both delayed by a second target duration, wherein I L I is used to characterize the current flowing through the inductor in the low-pass filter 30. L It can be broken down into I, which corresponds to the audio frequency. OUT_AC I and the switching frequency of power stage 20 are consistent OUT_RIP V OUT Used to characterize the source voltage of the first power transistor 211, slope_rise_H is used to characterize the slope of the source voltage of the first power transistor 211 being less than 0, and slope_fall_H is used to characterize the slope of the source voltage of the first power transistor 211 being greater than 0. GSH_pre V is used to characterize the drive signal for the first power transistor 211 in the drive signal. GSH V is used to characterize the drive signal for the first power transistor 211 in the delayed drive signal. GSL_pre V is used to characterize the drive signal for the second power transistor 221 in the drive signal. GSL T is used to characterize the drive signal for the second power transistor 221 in the delayed drive signal. d1 T is used to characterize the duration of the first objective. d2 Used to characterize the duration of the second objective.

[0042] A schematic diagram illustrating the delay of the drive signal when both the first and second power transistors are target power transistors within a signal cycle of a power level can be shown below. Figure 6 As shown.

[0043] Within an audio cycle of a first analog audio signal, Figures 4-6 The delay scenarios shown are all possible because power stage 20 is a high-frequency switch. Within one audio cycle of the first analog audio signal, the first power transistor 211 and the second power transistor 221 in power stage 20 will perform multiple on and off operations.

[0044] It should be noted that, within a power level's signal cycle, if the target power transistor is not identified in subsequent power level signal cycles after delaying the drive signal, the same delay can be applied to the drive signals in subsequent power level signal cycles. Alternatively, after delaying the drive signal in one or more consecutive power level signal cycles, no further delay can be applied to the drive signals in subsequent power level signal cycles of the same number of consecutive power levels.

[0045] Or, based on Figure 2-3 The circuit shown includes a voltage detection module 11, which is used to obtain the first drain-source voltage difference of the first power transistor 211 and the second drain-source voltage difference of the second power transistor 221 according to a preset time interval.

[0046] The zero-voltage switching control module 12 is used to determine the first power transistor 211 as the target power transistor when the absolute value of the first drain-source voltage difference is greater than 0, and to determine a third target duration based on the time it takes for the first drain-source voltage difference to decrease to less than or equal to a voltage threshold. When the absolute value of the second drain-source voltage difference is greater than 0, the second power transistor 221 is determined as the target power transistor, and a fourth target duration is determined based on the time it takes for the second drain-source voltage difference to decrease to less than or equal to a voltage threshold.

[0047] The drain-source voltage difference can be reduced to less than or equal to the voltage threshold, reduced to 0, or reduced to a negative value, all of which can be used as the basis for zero-voltage switching control. Therefore, the third target duration is determined based on the duration of the first drain-source voltage difference being reduced to less than or equal to the voltage threshold, and the fourth target duration is determined based on the duration of the second drain-source voltage difference being reduced to less than or equal to the voltage threshold.

[0048] Within a signal cycle of a power level, if the first power transistor 211 is determined to be the target power transistor and the second power transistor 221 is determined to be a non-target power transistor, then within a signal cycle of power level 20, the turn-on signal, turn-off signal, turn-on signal, and turn-off signal of the target power transistor are all delayed by a third target duration. If the second power transistor 221 is determined to be the target power transistor and the first power transistor 211 is determined to be a non-target power transistor, then within a signal cycle of power level 20, the turn-on signal, turn-off signal, turn-on signal, and turn-off signal of the target power transistor are all delayed by a fourth target duration. If both the first power transistor 211 and the second power transistor 221 are determined to be target power transistors, then within a signal cycle of power level 20, the turn-on signal and the turn-off signal of the first power transistor 211 are delayed by a third target duration, and the turn-on signal and the turn-off signal of the second power transistor 221 are delayed by a fourth target duration.

[0049] The delay of the drive signal can also be achieved by detecting the first drain-source voltage difference of the first power transistor 211 and the second drain-source voltage difference of the second power transistor 221. As long as the drain-source voltage difference of the power transistor is not zero, the power transistor can be switched at zero voltage.

[0050] It should be noted that if the detected drain-source voltage difference is too small, the determined delay duration (the third target duration or the fourth target duration) will be too long. Therefore, a maximum value for the delay duration, i.e., a duration threshold, can be set to control the delay duration from becoming too long. Specifically, the zero-voltage switch control module 12 is used to set the third target duration or the fourth target duration to be less than or equal to the duration threshold when the third target duration or the fourth target duration is greater than the duration threshold.

[0051] Specifically, Figure 7 This is a schematic diagram of a voltage detection module provided in an embodiment of this application, as shown below. Figure 2 , 3 As shown in Figure 7, the voltage detection module 11 includes: First capacitor 111, second capacitor 112, third capacitor 113, first resistor 114, second resistor 115, first NMOS transistor 116, first PMOS transistor 117, first current mirror 118, second current mirror 119, buffer 120 and inverter 121; The first terminal of the first capacitor 111 is electrically connected to the voltage output terminal of the first power transistor 211. The second terminal of the first capacitor 111 is electrically connected to the source of the first PMOS transistor 116 and the source of the first PMOS transistor 117. The gate of the first PMOS transistor 116 is electrically connected to the gate of the first PMOS transistor 117, the first terminal of the first resistor 114, the first terminal of the second resistor 115, the first terminal of the second capacitor 112, and the first terminal of the third capacitor 113. The drain of the first NMOS transistor 116 is electrically connected to the input terminal of the first current mirror 118. The output terminal of the first current mirror 118 is electrically connected to the input terminal of the buffer 120. The drain of the first PMOS transistor 117 is electrically connected to the input terminal of the second current mirror 119. The output terminal of the second current mirror 119 is electrically connected to the input terminal of the inverter 121. The output terminals of the buffer 120 and the inverter 121 are electrically connected to the zero-voltage switch control module 12.

[0052] When the voltage at the output terminal of the first power transistor 211 decreases, the first capacitor 111 discharges, and current flows from the first capacitor 111 to the output terminal of the first power transistor 211. Therefore, it can be detected that the slope of the current voltage at the output terminal of the first power transistor 211 is less than 0. When the voltage at the output terminal of the first power transistor 211 increases, the first capacitor 111 charges, and current flows from the output terminal of the first power transistor 211 to the first capacitor 111. Therefore, it can be detected that the slope of the current voltage at the output terminal of the first power transistor 211 is greater than 0. The magnitude of the corresponding slope can be determined by the change in the source voltage of the first power transistor 211 per unit time.

[0053] Specifically, such as Figure 8 As shown, the first current mirror 118 includes a second PMOS transistor 1181, a third PMOS transistor 1182, and a first current source 1183, and the second current mirror 119 includes a second NMOS transistor 1191, a third NMOS transistor 1192, and a second current source 1193.

[0054] The drain of the second PMOS transistor 1181 is electrically connected to the drain of the first NMOS transistor 116 and the gate of the second PMOS transistor 1181. The source of the second PMOS transistor 1181 is electrically connected to the second terminal of the first resistor 114, the second terminal of the second capacitor 112, the second power supply VDD, and the source of the third PMOS transistor 1192. The gate of the third PMOS transistor 1192 is electrically connected to the gate of the second PMOS transistor 1181. The drain of the third PMOS transistor 1192 is electrically connected to the input terminal of the first current source 1183 and the input terminal of the buffer 120. The output terminal of the first current source 1183 is grounded.

[0055] The drain of the second NMOS transistor 1181 is electrically connected to the drain of the first PMOS transistor 117 and the gate of the second NMOS transistor 1191. The source of the second NMOS transistor 1191 is electrically connected to the second terminal of the second resistor 115, the second terminal of the third capacitor 113, and the source of the third NMOS transistor 1192 and grounded. The gate of the third NMOS transistor 1192 is electrically connected to the gate of the second NMOS transistor 1191. The drain of the third NMOS transistor 1192 is electrically connected to the output terminal of the second current source 1193 and the input terminal of the inverter 121. The input terminal of the second current source 1193 is electrically connected to the second power supply VDD.

[0056] Specifically, the ratio of the width-to-length ratio of the second NMOS transistor 1191 to that of the third NMOS transistor 1192 is K1, and the ratio of the width-to-length ratio of the second PMOS transistor 1181 to that of the third PMOS transistor 1182 is K2, wherein K1 and K2 are greater than 1.

[0057] Correspondingly, the first slope threshold is determined by the following formula:

[0058] in, Used to characterize the first slope threshold, Used to characterize the current value output by the second current source. The capacitance value used to characterize the first capacitor; The second slope threshold is determined by the following formula:

[0059] in, Used to characterize the second slope threshold, Used to characterize the current value output by the first current source. The capacitance value used to characterize the first capacitor.

[0060] As can be seen from the calculation formulas for the first slope threshold and the second slope threshold, the first slope threshold and the second slope threshold can be flexibly adjusted by adjusting at least a portion of the following: the capacitance value of the first capacitor, the ratio of the width-to-length ratio of the second NMOS transistor 1191 to the width-to-length ratio of the third NMOS transistor 1192, the ratio of the width-to-length ratio of the second PMOS transistor 1181 to the width-to-length ratio of the third PMOS transistor 1182, the current value output by the first current source, and the current value output by the second current source.

[0061] Specifically, such as Figure 9As shown, the low-pass filter 30 includes an inductor 31, a fourth capacitor 32, and a third resistor 33. The first end of the inductor 31 is electrically connected to the voltage output terminal of the first power transistor 211. The second end of the inductor 31 is electrically connected to the first end of the fourth capacitor 32 and the first end of the third resistor 33. The second end of the fourth capacitor 32 is grounded, and the second end of the third resistor 33 is grounded.

[0062] When the power transistor in power stage 20 switches, inductor 31 utilizes the characteristic that current cannot change abruptly to store or release magnetic field energy, maintaining continuous current. Inductor 31 can also suppress the current ripple generated by power stage 20, making the output current more stable. The fourth capacitor 32 can absorb voltage ripple to make the output voltage more stable. The third resistor 33 can simulate a load to verify the circuit's load-carrying capacity.

[0063] In this embodiment, the zero-voltage switching control device 10 delays the drive signal based on the changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22 included in the power stage 20. This enables zero-voltage switching of some power transistors in the power stage 20, thereby reducing switching losses and avoiding signal distortion caused by additional delay. It also ensures that the operating frequency and duty cycle of the power stage 20 remain unchanged during the zero-voltage switching process.

[0064] One embodiment of this application provides a zero-voltage switching control device, such as... Figure 2 , 3As shown in Figure 7, the zero-voltage switching control device includes a voltage detection module 11 and a zero-voltage switching control module 12, wherein the zero-voltage switching control module 12 includes a delay unit. The voltage detection module 11 includes a first capacitor 111, a second capacitor 112, a third capacitor 113, a first resistor 114, a second resistor 115, a first NMOS transistor 116, a first PMOS transistor 117, a first current mirror 118, a second current mirror 119, a buffer 120, and an inverter 121. The first terminal of the first capacitor 111 is electrically connected to the voltage output terminal of the first power transistor 211, which is electrically connected to the first power supply PVDD, included in the positive power unit 21. The second terminal of the first capacitor 111 is electrically connected to the source of the first PMOS transistor 116 and the source of the first PMOS transistor 117. The gate of the first PMOS transistor 116 is electrically connected to the gate of the first PMOS transistor 117, the first terminal of the first resistor 114, the first terminal of the second resistor 115, the first terminal of the second capacitor 112, and the first terminal of the third capacitor 113. The drain of the first NMOS transistor 116 is electrically connected to the input terminal of the first current mirror 118. The output terminal of the first current mirror 118 is electrically connected to the input terminal of the buffer 120. The drain of the first PMOS transistor 117 is electrically connected to the input terminal of the second current mirror 119. The output terminal of the second current mirror 119 is electrically connected to the input terminal of the inverter 121. The output terminals of the buffer 120 and the inverter 121 are electrically connected to the delay unit.

[0065] When the voltage at the output terminal of the first power transistor 211 decreases, the first capacitor 111 discharges, and current flows from the first capacitor 111 to the output terminal of the first power transistor 211. Therefore, it can be detected that the slope of the current voltage at the output terminal of the first power transistor 211 is less than 0. When the voltage at the output terminal of the first power transistor 211 increases, the first capacitor 111 charges, and current flows from the output terminal of the first power transistor 211 to the first capacitor 111. Therefore, it can be detected that the slope of the current voltage at the output terminal of the first power transistor 211 is greater than 0. The magnitude of the corresponding slope can be determined by the change in the source voltage of the first power transistor 211 per unit time.

[0066] The delay unit is used to determine the first power transistor 211 as the target power transistor when the slope of the voltage at the voltage output terminal of the first power transistor 211 is less than 0 and the absolute value of the slope of the voltage at the voltage output terminal of the first power transistor 211 is greater than the first slope threshold corresponding to the first power transistor 211, and to determine the first target duration based on the duration of the voltage change at the voltage output terminal of the first power transistor 211; and to determine the second power transistor 221 as the target power transistor when the slope of the voltage at the voltage output terminal of the first power transistor 211 is greater than 0 and the slope of the voltage at the voltage output terminal of the first power transistor 211 is greater than the second slope threshold corresponding to the second power transistor 221, and to determine the second target duration based on the duration of the voltage change at the voltage output terminal of the first power transistor 211. Within a signal cycle of power stage 20, if both the first power transistor 211 and the second power transistor 221 are identified as target power transistors, then within a signal cycle of power stage 20, the turn-on signal and the turn-off signal of the first power transistor 211 are both delayed by a first target duration, and the turn-on signal and the turn-off signal of the second power transistor 221 are both delayed by a second target duration, wherein I L I is used to characterize the current flowing through the inductor in the low-pass filter 30. L It can be broken down into I, which corresponds to the audio frequency. OUT_AC I and the switching frequency of power stage 20 are consistent OUT_RIP V OUT Used to characterize the source voltage of the first power transistor 211, slope_rise_H is used to characterize the slope of the source voltage of the first power transistor 211 being less than 0, and slope_fall_H is used to characterize the slope of the source voltage of the first power transistor 211 being greater than 0. GSH_pre V is used to characterize the drive signal for the first power transistor 211 in the drive signal. GSH V is used to characterize the drive signal for the first power transistor 211 in the delayed drive signal. GSL_pre V is used to characterize the drive signal for the second power transistor 221 in the drive signal. GSL T is used to characterize the drive signal for the second power transistor 221 in the delayed drive signal. d1 T is used to characterize the duration of the first objective. d2 This is used to characterize the duration of the second target. A schematic diagram illustrating the delay of the drive signal when both the first and second power transistors are target power transistors within a signal cycle of a power level can be shown as follows: Figure 6 As shown.

[0067] Within an audio cycle of a first analog audio signal, Figures 4-6The delay scenarios shown are all possible because power stage 20 is a high-frequency switch. Within one audio cycle of the first analog audio signal, the first power transistor 211 and the second power transistor 221 in power stage 20 will perform multiple on and off operations.

[0068] It should be noted that, within a power level's signal cycle, if the target power transistor is not identified in subsequent power level signal cycles after delaying the drive signal, the same delay can be applied to the drive signals in subsequent power level signal cycles. Alternatively, after delaying the drive signal in one or more consecutive power level signal cycles, no further delay can be applied to the drive signals in subsequent power level signal cycles of the same number of consecutive power levels.

[0069] Figure 10 This is a schematic diagram of an audio amplifier provided in an embodiment of this application, as shown below. Figure 10 As shown, the audio amplifier 300 includes: a zero-voltage switching control device 10, an analog-to-digital converter 50, a pulse width modulator 60, an output driver 40, a power stage 20, and a low-pass filter 30, as described in the above embodiment. The power stage 20 includes a positive power unit 21 and a negative power unit 22. An analog-to-digital converter 50 is used to convert a first analog audio signal into an audio digital signal. A pulse width modulator 60 is used to output a pulse width modulated signal based on the audio digital signal and a reference signal. An output driver 40 is used to output a drive signal based on the pulse width modulated signal. A power stage 20 is used to amplify the drive signal and input the amplified drive signal to a low-pass filter 30. The low-pass filter 30 is used to generate a second analog audio signal based on the amplified drive signal, which is used to drive the speaker 200 to produce sound. A zero-voltage switching control device 10 is used to detect changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22 included in the power stage 20, and delays the drive signal based on the changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22. The power transistors in the positive power unit 21 and the negative power unit 22 then perform on and off actions based on the delayed drive signal.

[0070] The analog-to-digital converter 50 can be a Σ-Δ modulator. The Σ-Δ modulator first oversamples and shapes the input first analog audio signal (left waveform) to convert it into a high-frequency digital audio signal, thereby improving signal accuracy, suppressing quantization noise, and distributing the noise to the high-frequency band. The pulse-width modulator 60 receives the audio digital signal output from the analog-to-digital converter 50 and modulates it according to the input reference signal (right sawtooth wave), outputting a pulse-width modulated signal. The output driver 40 performs preliminary amplification and shaping of the pulse-width modulated signal to enhance its driving capability and outputs a drive signal. The power stage 20 utilizes high-power devices (such as MOSFETs) in the positive power unit 21 and negative power unit 22 to convert and amplify the voltage of the first power supply PVDD according to the drive signal, outputting a second analog audio signal to the low-pass filter 30. The low-pass filter 30 (LPF) filters out the high-frequency carrier component in the second analog audio signal, restoring a smooth analog audio signal, which in turn drives the speaker 200 to produce sound.

[0071] In this process, to reduce total harmonic distortion (THD), zero-voltage switching (ZVS) is performed on the high-power devices in the positive power unit 21 and negative power unit 22 of the power stage 20 via the zero-voltage switching control device 10. Specifically, the voltage detection module 11 in the zero-voltage switching control device 10 detects changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22 of the power stage 20. The zero-voltage switching control module 12 determines which power transistors in the positive power unit 21 and negative power unit 22 can be zero-voltage switched based on the voltage changes. Then, the zero-voltage switching control module 12 delays the drive signal output from the output drive 40 to the power stage 20, causing the power transistors in the positive power unit 21 and negative power unit 22 to perform turn-on and turn-off actions based on the delayed drive signal.

[0072] In this embodiment, the zero-voltage switching control device 10 delays the drive signal based on the changes in the output voltage of the positive power unit 21 and the input voltage of the negative power unit 22 included in the power stage 20. This enables zero-voltage switching of some power transistors in the power stage 20 while avoiding signal distortion caused by additional delay, ensuring that the operating frequency and duty cycle of the power stage 20 remain unchanged during the zero-voltage switching process.

[0073] One embodiment of this application provides a chip, including the zero-voltage switching control device 10 in the foregoing embodiments or the audio amplifier 300 in the foregoing embodiments.

[0074] The specific implementation of the zero-voltage switching control device 10 in the chip can be found in the corresponding descriptions of the devices and connections in the aforementioned zero-voltage switching control device embodiments. Similarly, the specific implementation of the audio amplifier 300 in the chip can be found in the corresponding descriptions of the devices and connections in the aforementioned audio amplifier embodiments, and will not be repeated here. Those skilled in the art will understand that, for ease of description and brevity, the specific working processes of the devices described above can be referred to the corresponding process descriptions in the aforementioned zero-voltage switching control device embodiments and audio amplifier embodiments, and will not be repeated here.

[0075] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0076] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.

[0077] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A zero voltage switching control device, characterized by, include: Voltage detection module and zero-voltage switch control module; The voltage detection module is used to detect changes in the output voltage of the positive power unit and the input voltage of the negative power unit included in the power stage. The first terminal of the positive power unit is electrically connected to a first power supply, the second terminal of the positive power unit is electrically connected to the first terminal of the negative power unit, the second terminal of the negative power unit is grounded, and the second terminal of the positive power unit is electrically connected to a speaker. The power stage is used to amplify the output drive signal, and the amplified drive signal is used to drive the speaker to produce sound. The zero-voltage switching control module is used to delay the drive signal according to the changes in the output voltage of the positive power unit and the input voltage of the negative power unit. The power transistors in the positive power unit and the negative power unit perform turn-on and turn-off actions based on the delayed drive signal.

2. The zero-voltage switching control device of claim 1, wherein, The positive power unit includes a first power transistor electrically connected to the first power supply, and the negative power unit includes a second power transistor grounded. The gates of the first power transistor and the second power transistor are both electrically connected to the output driver, and the voltage output terminal of the first power transistor is electrically connected to the voltage input terminal of the second power transistor and the input terminal of the low-pass filter.

3. The zero-voltage switching control device according to claim 2, characterized in that, The voltage detection module is used to detect the slope of the voltage at the voltage output terminal of the first power transistor. The zero-voltage switch control module is used to determine the first power transistor as the target power transistor when the slope of the voltage at the voltage output terminal of the first power transistor is less than 0 and the absolute value of the slope of the voltage at the voltage output terminal of the first power transistor is greater than the first slope threshold corresponding to the first power transistor, and to determine the first target duration based on the duration of the voltage change at the voltage output terminal of the first power transistor. When the slope of the voltage at the output terminal of the first power transistor is greater than 0 and the slope of the voltage at the output terminal of the first power transistor is greater than the second slope threshold corresponding to the second power transistor, the second power transistor is determined as the target power transistor, and the second target duration is determined according to the duration of the voltage change at the output terminal of the first power transistor. Within a signal cycle of the power level, if the first power transistor is determined to be the target power transistor and the second power transistor is determined to be a non-target power transistor, then within a signal cycle of the power level, the turn-on signal, the turn-off signal, the turn-on signal, and the turn-off signal of the first power transistor are all delayed by the first target duration; if the second power transistor is determined to be the target power transistor and the first power transistor is determined to be a non-target power transistor, then within a signal cycle of the power level, the turn-on signal, the turn-off signal, the turn-on signal, and the turn-off signal of the second power transistor are all delayed by the second target duration; if both the first power transistor and the second power transistor are determined to be the target power transistors, then within a signal cycle of the power level, the turn-on signal and the turn-off signal of the first power transistor are both delayed by the first target duration, and the turn-on signal and the turn-off signal of the second power transistor are both delayed by the second target duration.

4. The zero-voltage switching control device according to claim 2, characterized in that, The voltage detection module is used to acquire the first drain-source voltage difference of the first power transistor and the second drain-source voltage difference of the second power transistor according to a preset time interval. The zero-voltage switching control module is used to determine the first power transistor as the target power transistor when the absolute value of the first drain-source voltage difference is greater than 0, and to determine a third target duration based on the duration during which the first drain-source voltage difference decreases to less than or equal to the voltage threshold. When the absolute value of the second drain-source voltage difference is greater than 0, the second power transistor is determined as the target power transistor, and the fourth target duration is determined based on the duration during which the second drain-source voltage difference decreases to less than or equal to the voltage threshold. Within a signal cycle of the power level, if the first power transistor is determined to be the target power transistor and the second power transistor is determined to be a non-target power transistor, then within a signal cycle of the power level, the turn-on signal, the turn-off signal, the turn-on signal, and the turn-off signal of the first power transistor are all delayed by the third target duration. If the second power transistor is determined to be the target power transistor and the first power transistor is determined to be a non-target power transistor, then within a signal cycle of the power level, the turn-on signal, the turn-off signal, the turn-on signal, and the turn-off signal of the second power transistor are all delayed by the fourth target duration. If both the first power transistor and the second power transistor are determined to be the target power transistors, then within a signal cycle of the power level, the turn-on signal and the turn-off signal of the first power transistor are delayed by the third target duration, and the turn-on signal and the turn-off signal of the second power transistor are delayed by the fourth target duration.

5. The zero-voltage switching control device of claim 3, wherein, The voltage detection module includes: First capacitor, second capacitor, third capacitor, first resistor, second resistor, first NMOS transistor, first PMOS transistor, first current mirror, second current mirror, buffer, and inverter; The first terminal of the first capacitor is electrically connected to the voltage output terminal of the first power transistor. The second terminal of the first capacitor is electrically connected to the source of the first NMOS transistor and the source of the first PMOS transistor. The gate of the first NMOS transistor is electrically connected to the gate of the first PMOS transistor, the first terminal of the first resistor, the first terminal of the second resistor, the first terminal of the second capacitor, and the first terminal of the third capacitor. The drain of the first NMOS transistor is electrically connected to the input terminal of the first current mirror. The output terminal of the first current mirror is electrically connected to the input terminal of the buffer. The drain of the first PMOS transistor is electrically connected to the input terminal of the second current mirror. The output terminal of the second current mirror is electrically connected to the input terminal of the inverter. The output terminals of the buffer and the inverter are electrically connected to the zero-voltage switch control module.

6. The zero-voltage switching control device of claim 5, wherein, The first current mirror includes a second PMOS transistor, a third PMOS transistor, and a first current source; the second current mirror includes a second NMOS transistor, a third NMOS transistor, and a second current source. The drain of the second PMOS transistor is electrically connected to the drain of the first NMOS transistor and the gate of the second PMOS transistor. The source of the second PMOS transistor is electrically connected to the second terminal of the first resistor, the second terminal of the second capacitor, the second power supply, and the source of the third PMOS transistor. The gate of the third PMOS transistor is electrically connected to the gate of the second PMOS transistor. The drain of the third PMOS transistor is electrically connected to the input terminal of the first current source and the input terminal of the buffer. The output terminal of the first current source is grounded. The drain of the second NMOS transistor is electrically connected to the drain of the first PMOS transistor and the gate of the second NMOS transistor. The source of the second NMOS transistor is electrically connected to the second terminal of the second resistor, the second terminal of the third capacitor, and the source of the third PMOS transistor and grounded. The gate of the third NMOS transistor is electrically connected to the gate of the second NMOS transistor. The drain of the third NMOS transistor is electrically connected to the output terminal of the second current source and the input terminal of the inverter. The input terminal of the second current source is electrically connected to the second power supply.

7. The zero-voltage switching control device according to claim 6, characterized in that, The ratio of the width-to-length ratio of the second NMOS transistor to that of the third NMOS transistor is K1, and the ratio of the width-to-length ratio of the second PMOS transistor to that of the third PMOS transistor is K2, wherein K1 and K2 are greater than 1. Correspondingly, the first slope threshold is determined by the following formula: in, Used to characterize the first slope threshold Used to characterize the current value output by the second current source. Used to characterize the capacitance value of the first capacitor; The second slope threshold is determined by the following formula: in, Used to characterize the second slope threshold, Used to characterize the current value output by the first current source. The capacitance value used to characterize the first capacitor.

8. The zero-voltage switching control device according to claim 4, characterized in that, The zero-voltage switch control module is used to set the duration of the third target or the duration of the fourth target to be less than or equal to the duration threshold when the duration of the third target or the duration of the fourth target is greater than the duration threshold.

9. The zero-voltage switching control device according to claim 2, characterized in that, The low-pass filter includes an inductor, a fourth capacitor, and a third resistor. The first end of the inductor is electrically connected to the voltage output terminal of the first power transistor. The second end of the inductor is electrically connected to the first end of the fourth capacitor and the first end of the third resistor. The second end of the fourth capacitor is grounded, and the second end of the third resistor is grounded.

10. A zero-voltage switching control device, characterized in that, include: A voltage detection module and a zero-voltage switch control module, wherein the zero-voltage switch control module includes a delay unit; The voltage detection module includes: First capacitor, second capacitor, third capacitor, first resistor, second resistor, first NMOS transistor, first PMOS transistor, first current mirror, second current mirror, buffer, and inverter; The first terminal of the first capacitor is electrically connected to the voltage output terminal of the first power transistor, which is electrically connected to the first power supply, in the positive power unit. The second terminal of the first capacitor is electrically connected to the source of the first NMOS transistor and the source of the first PMOS transistor. The gate of the first NMOS transistor is electrically connected to the gate of the first PMOS transistor, the first terminal of the first resistor, the first terminal of the second resistor, the first terminal of the second capacitor, and the first terminal of the third capacitor. The drain of the first NMOS transistor is electrically connected to the input terminal of the first current mirror. The output terminal of the first current mirror is electrically connected to the input terminal of the buffer. The drain of the first PMOS transistor is electrically connected to the input terminal of the second current mirror. The output terminal of the second current mirror is electrically connected to the input terminal of the inverter. The output terminals of the buffer and the inverter are electrically connected to the delay unit.

11. An audio amplifier, characterized in that, Includes a zero-voltage switching control device, an analog-to-digital converter, a pulse width modulator, an output driver, and a power stage as described in any of claims 1-9, wherein the power stage includes a positive power unit and a negative power unit; The analog-to-digital converter is used to convert the first analog audio signal into an audio digital signal; The pulse width modulator is used to output a pulse width modulated signal according to the audio digital signal and the reference signal; The output driver is used to output a drive signal according to the pulse width modulation signal; The power stage is used to amplify the power of the drive signal, and the amplified drive signal is used to drive the speaker to produce sound. The zero-voltage switching control device is used to detect changes in the output voltage of the positive power unit and the input voltage of the negative power unit included in the power stage, and to delay the drive signal according to the changes in the output voltage of the positive power unit and the input voltage of the negative power unit. The power transistors in the positive power unit and the negative power unit perform turn-on and turn-off actions based on the delayed drive signal.

12. A chip, characterized in that, Includes the zero-voltage switching control device as described in any one of claims 1-10, or the audio amplifier as described in claim 11.

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