Amplifier and analog-to-digital converter using same
By employing a vertically stacked FIA structure and a self-biased amplifier design, the speed and power consumption issues in high-gain and high-voltage applications are addressed, enabling efficient circuit design and operation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JOULWATT TECH (SHENZHEN) CO LTD
- Filing Date
- 2025-07-15
- Publication Date
- 2026-04-17
AI Technical Summary
Existing FIA-structured amplifiers cannot meet the requirements of high-gain applications, and the I/O tubes cause slow operation in high-voltage applications.
The FIA structure is stacked vertically. Each amplifier stage is connected to the low-potential end of the previous stage through a connection module. Combined with the connection of capacitors in different phases, high voltage is evenly distributed. The self-biased form with input and output connected is used to avoid additional bias voltage.
It achieves high gain while improving system operating speed, reducing power consumption, providing more circuit design margin, and is compatible with I/O tubes and core tubes in high-voltage applications.
Smart Images
Figure CN121887136A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics technology, and more specifically to an amplifier and an analog-to-digital converter using the same. Background Technology
[0002] Figure 1 The diagram shows a simplified representation of an FIA (floating inverter amplifier) amplifier. During the reset phase, capacitor CL charges to the power supply, and capacitor CDEG is pulled down to ground. During the amplification phase, capacitor CL provides charge, and capacitor CDEG accumulates charge, amplifying the input signal accordingly. The FIA structure offers advantages such as high linearity, low noise, and high energy efficiency. However... Figure 1 The FIA structure shown cannot achieve high gain, making it unsuitable for applications requiring high gain. Therefore, Figure 2 This is a simplified schematic diagram of another amplifier using an FIA structure, which employs a two-stage FIA configuration, compared to... Figure 1 While this structure can achieve high gain, when applied to scenarios with generally high I / O voltages, it requires I / O transistors, which result in slower operation. Therefore, it is necessary to provide a new amplifier structure to address the problems existing in the prior art. Summary of the Invention
[0003] To address the aforementioned technical problems, the present invention provides an amplifier and an analog-to-digital converter using the same.
[0004] According to a first aspect of the present invention, an amplifier is provided, characterized in that the amplifier includes a first-stage amplifier, the first-stage amplifier including N vertically stacked FIAs, the low-potential end of the preceding FIA being connected to the high-potential end of the following FIA via a connection module; N is greater than or equal to 2;
[0005] The first stage amplifier also includes a first capacitor and a second capacitor;
[0006] In the first phase, the first capacitor is connected between the power supply voltage and the ground terminal, the first terminal of the second capacitor is connected to the high potential terminal of the first stage FIA, and the second terminal of the second capacitor is connected to the low potential terminal of the Nth stage FIA.
[0007] In the second phase, the second capacitor is connected between the power supply voltage and the ground terminal, the first terminal of the first capacitor is connected to the high potential terminal of the first stage FIA, and the second terminal of the first capacitor is connected to the low potential terminal of the Nth stage FIA; the first phase is the reset phase, and the second phase is the amplification phase.
[0008] Optionally, the connection module includes a switch and a capacitor connected in parallel, wherein the switch is turned on during the first phase.
[0009] Optionally, the first end of the input signal outputs N sub-first input signals through the first module; the second end of the input signal outputs N sub-second input signals through the second module; the first module and the second module each include N capacitors.
[0010] Optionally, the i-th sub-first input signal and the i-th sub-second input signal are used as inputs to the i-th level FIA, and the output signal of the i-th level FIA includes the i-th sub-first output signal and the i-th sub-second output signal, 1≤i≤N;
[0011] In the first phase, the i-th sub-first input signal is connected to the i-th sub-second output signal, and the i-th sub-second input signal is connected to the i-th sub-first output signal.
[0012] Optionally, the i-th stage FIA includes a first P-type transistor and a first N-type transistor connected in series between the high-potential terminal and the low-potential terminal of the i-th stage FIA, and a second P-type transistor and a second N-type transistor connected in series between the high-potential terminal and the low-potential terminal of the i-th stage FIA; 1≤i≤N
[0013] The input terminals of the first P-type transistor and the first N-type transistor are connected together and connected to the i-th sub-first input signal. The common node of the series connection of the first P-type transistor and the first N-type transistor serves as the i-th sub-second output signal.
[0014] The input terminals of the second P-type transistor and the second N-type transistor are connected together and connected to the i-th sub-second input signal. The common node of the series connection of the second P-type transistor and the second N-type transistor serves as the i-th sub-first output signal.
[0015] Optionally, a first switch is provided between the common node connecting the first P-type transistor and the first N-type transistor in series and the input terminal of the first P-type transistor and the first N-type transistor; a second switch is provided between the common node connecting the second P-type transistor and the second N-type transistor in series and the input terminal of the second P-type transistor and the second N-type transistor; in the first phase, the first switch and the second switch are turned on.
[0016] Optionally, N sub-first output signals are used as inputs to the third module, and the output of the third module is used as the first terminal signal of the output signal; N sub-second output signals are used as inputs to the fourth module, and the output of the fourth module is used as the second terminal signal of the output signal; the third module and the fourth module each include N capacitors;
[0017] In the first phase, the first terminal and the second terminal of the output signal are connected to the common-mode voltage.
[0018] Optionally, the amplifier further includes a second-stage amplifier, with the output signal serving as the input signal for the second-stage amplifier.
[0019] Optionally, the transistors in each FIA stage are core transistors.
[0020] The present invention also provides an analog-to-digital converter, characterized in that it includes an amplifier as described in any one of claims 1-9, for amplifying the corresponding input signal.
[0021] The beneficial effects of the present invention include at least the following:
[0022] The present invention provides an amplifier and an analog-to-digital converter using the same. The amplifier includes a first-stage amplifier, which comprises N vertically stacked FIAs. The low-potential terminal of the preceding FIA is connected to the high-potential terminal of the following FIA via a connection module; N is greater than or equal to 2. The first-stage amplifier also includes a first capacitor and a second capacitor. In the first phase, the first capacitor is connected between the power supply voltage and ground, the first terminal of the second capacitor is connected to the high-potential terminal of the first-stage FIA, and the second terminal of the second capacitor is connected to the low-potential terminal of the Nth-stage FIA. In the second phase, the second capacitor is connected between the power supply voltage and ground, the first terminal of the first capacitor is connected to the high-potential terminal of the first-stage FIA, and the second terminal of the first capacitor is connected to the low-potential terminal of the Nth-stage FIA. The first phase is the reset phase, and the second phase is the amplification phase. The present invention, by employing a vertically stacked structure, can evenly distribute high voltage to each stage of FIA, allowing each stage's FIA to use core transistors without worrying about overvoltage risks, thereby improving the system's operating speed. In other words, through the above-described configuration, this invention achieves high gain while allowing each FIA stage to be compatible with both I / O transistors and core transistors in high-voltage applications. When using core transistors, the operating speed can be improved. Furthermore, the structure of this invention provides greater design margin in circuit design, making amplifier design easier.
[0023] Furthermore, in the first phase, each FIA stage can use a self-biasing form with input and output connected to obtain the initial bias voltage, so that each FIA stage can have a suitable initial static operating point, that is, there is no need to set the corresponding bias voltage separately, thus reducing the power consumption of the system.
[0024] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the present invention. Attached Figure Description
[0025] Figure 1 This diagram illustrates a schematic of an FIA structure amplifier in the prior art;
[0026] Figure 2 Another schematic diagram of an FIA structure amplifier in the prior art is shown;
[0027] Figure 3 A schematic diagram of the first-stage amplifier provided by the present invention is shown;
[0028] Figure 4 A schematic diagram of the circuits for generating various input and output signals is shown.
[0029] Figure 5 An embodiment of each level of FIA provided by the present invention is shown;
[0030] Figure 6 This invention provides an embodiment of a first-stage amplifier with a vertical stacking quantity of 3;
[0031] Figure 7 It shows Figure 6 A schematic diagram of the circuits that generate various input and output signals.
[0032] Figure 8 It shows Figure 6 Bode plot of the circuit shown;
[0033] Figure 9 A schematic diagram of an amplifier provided by the present invention is shown. Detailed Implementation
[0034] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.
[0035] This invention provides an amplifier comprising a first-stage amplifier. Figure 3 The diagram shown is a schematic of the first-stage amplifier provided by this invention. Figure 3As shown, the first-stage amplifier includes N vertically stacked FIAs, i.e., the first-stage FIA to the Nth-stage FIA, where N is greater than or equal to 2. The low-potential terminal of the previous-stage FIA is connected to the high-potential terminal of the next-stage FIA through the connection module 10. The first-stage amplifier also includes a first capacitor C1 and a second capacitor C2. Switches are respectively provided between the power supply voltage VDD and the first terminal of the first capacitor C1, and between the second terminal of the first capacitor C1 and the ground terminal. These two switches are turned on in the first phase φ1. Between the first terminal of the first capacitor C1 and the high-potential terminal of the first-stage FIA... A switch is provided between the second terminal of the first capacitor C1 and the low-potential terminal of the Nth stage FIA. These two switches are turned on in the second phase φ2. A switch is also provided between the power supply voltage VDD and the first terminal of the second capacitor C2, and between the second terminal of the second capacitor C2 and the ground terminal. These two switches are turned on in the second phase φ2. A switch is provided between the first terminal of the second capacitor C2 and the high-potential terminal of the first stage FIA, and between the second terminal of the second capacitor C2 and the low-potential terminal of the Nth stage FIA. These two switches are turned on in the first phase φ1. That is, in the first phase φ1, the first capacitor C1 is connected between the power supply voltage VDD and the ground terminal, the first terminal of the second capacitor C2 is connected to the high-potential terminal of the first stage FIA, and the second terminal of the second capacitor C2 is connected to the low-potential terminal of the Nth stage FIA. In the second phase φ2, the second capacitor C2 is connected between the power supply voltage VDD and the ground terminal, the first terminal of the first capacitor C1 is connected to the high-potential terminal of the first stage FIA, and the second terminal of the first capacitor C1 is connected to the low-potential terminal of the Nth stage FIA. In the above text, the first phase φ1 can be regarded as the reset phase, and the second phase φ2 can be regarded as the amplification phase.
[0036] The amplifier using the structure of this invention can also achieve high gain. In high-voltage applications, the invention utilizes a vertically stacked structure to evenly distribute the high voltage to each FIA stage. For example, with VDD of 2.5V, when N equals 3, the voltage range of each FIA stage is approximately 0.83V. This allows each FIA stage to use core transistors without worrying about overvoltage risks, thereby improving system operating speed. In other words, through the above configuration, this invention achieves high gain while ensuring compatibility with both I / O transistors and core transistors in high-voltage applications; for high-speed applications, core transistors can be used.
[0037] Figure 3 The input voltages Vip1 to VipN and Vin1 to VinN of each stage of the FIA are... Figure 4 The circuit shown generates N sub-first input signals Vip1 to VipN through the first module; the second input signal Vin1 through the second module outputs N sub-second input signals Vin1 to VinN; as shown... Figure 4 As shown, the first module and the second module each include N capacitors.
[0038] Furthermore, such as Figure 3 As shown, the connection module 10 includes a switch and a capacitor (denoted as C3) connected in parallel. During the first phase φ1, the switch in the connection module 10 is turned on. During the second phase φ2, the capacitor in the connection module 10 enables the connection between different levels of the FIA, and corresponding amplification occurs during this stage.
[0039] from Figure 2 As can be seen from the structure shown, it requires additional bias voltages VBP and VBN, which undoubtedly increases the system's power consumption. Further, in one embodiment of the i-th FIA provided by this invention, 1≤i≤N; the i-th sub-first input signal Vipi and the i-th sub-second input signal Vini serve as the inputs to the i-th stage FIA, and the output signals of the i-th stage FIA include the i-th sub-first output signal Vopi and the i-th sub-second output signal Voni; in the first phase φ1, the i-th sub-first input signal Vipi is connected to the i-th sub-second output signal Voni, and the i-th sub-second input signal Vini is connected to the i-th sub-first output signal Vopi. Through the above configuration, this invention can obtain the initial bias voltage in the self-biased form of input-output connection in each stage FIA in the first phase φ1, so that each stage FIA can have a suitable initial static operating point. In the second phase φ2, amplification is performed based on this operating point, i.e., no additional bias voltage is required, thus reducing the system's power consumption.
[0040] Furthermore, Figure 5 The diagram shows a specific embodiment of the i-th level FIA, where 1 ≤ i ≤ N; it includes a first P-type transistor MP1i and a first N-type transistor MN1i connected in series between the high-potential terminal VSPi and the low-potential terminal VSNi of the i-th level FIA, and a second P-type transistor MP2i and a second N-type transistor MN2i connected in series between the high-potential terminal VSPi and the low-potential terminal VSNi of the i-th level FIA; the input terminals of the first P-type transistor MP1i and the first N-type transistor MN1i are connected together and connected to the i-th sub-first input signal Vipi, and the common node of the series connection of the first P-type transistor MP1i and the first N-type transistor MN1i serves as the i-th sub-second output signal Voni; the input terminals of the second P-type transistor MP2i and the second N-type transistor MN2i are connected together and connected to the i-th sub-second input signal Vini, and the common node of the series connection of the second P-type transistor MP2i and the second N-type transistor MN2i serves as the i-th sub-first output signal Vopi.
[0041] Furthermore, such as Figure 5As shown, a first switch S1 is provided between the common node of the first P-type transistor MP1i and the first N-type transistor MN1i connected in series and the input terminals of these two transistors; a second switch S2 is provided between the common node of the second P-type transistor MP2i and the second N-type transistor MN2i connected in series and the input terminals of these two transistors; in the first phase φ1, the first switch S1 and the second switch S2 are turned on, and are connected through the input and output to achieve a self-biasing function. That is, relative to... Figure 2 The structure in the system eliminates the need for additional bias voltage settings, thus reducing system power consumption.
[0042] Furthermore, such as Figure 4 As shown, N sub-first output signals Vop1 to VopN serve as inputs to the third module, and the output of the third module serves as the first terminal signal Vop of the output signal; N sub-second output signals Von1 to VonN serve as inputs to the fourth module, and the output of the fourth module serves as the second terminal signal Von of the output signal; the third module and the fourth module each include N capacitors; in the first phase φ1, the first terminal Vop and the second terminal Von of the output signal are connected to the common-mode voltage VCM. Capacitors CL are respectively placed between the first terminal signal Vop and the ground terminal, and between the second terminal signal Von and the ground terminal.
[0043] Figure 6 This illustration shows an embodiment where the number of first-stage amplifiers stacked, N, is 3, and each FIA stage employs... Figure 5 The structure in Figure 7 for Figure 6 The circuit diagram for generating the input signal and the output signal. Figure 8 for Figure 6 The Bode plot of the circuit shown is from Figure 8 As can be seen, as the number of stacked amplifiers increases, the gain of the first-stage amplifier remains unchanged, but the bandwidth will be higher. Therefore, the design margin of the circuit can be increased. For example, if only the noise bandwidth when N equals 1 is required, a capacitor can be added at the load of the first-stage amplifier to reduce the bandwidth during circuit design, and at the same time, lower noise performance can be obtained.
[0044] It should be noted that the figures above are merely illustrative embodiments of the present invention, and achieving the same function through corresponding modifications is also within the scope of this document.
[0045] Furthermore, the amplifier provided by the present invention may also include a second-stage amplifier, such as... Figure 9 The image shows an embodiment of the amplifier of the present invention as a two-stage amplifier. Figure 9In this design, the first-stage amplifier can adopt the structure described above, converting the input signals Vip and Vin into output signals Vop and Von. Vop and Von serve as the input to the second-stage amplifier, which then amplifies and outputs Voutp and Voutn signals. The second-stage amplifier can be implemented using existing amplifiers, or it can employ the same structure as the first-stage amplifier, or other existing FIA structures. This two-stage amplification is used in scenarios requiring high gain. Furthermore, the input signal to the first-stage amplifier can also be the output signal of other amplifiers; the specific settings can be adapted according to the actual application.
[0046] The amplifier described above in this invention can be applied to analog-to-digital converters (ADCs), especially in pipelined successive approximation ADCs, where the power consumption of interstage amplifiers accounts for a large proportion. The amplifier described above employs an FIA (Fixed-Area Interoperability) structure. Since the FIA structure itself has advantages such as high energy efficiency, low noise, and high linearity, the amplifier described above can be applied to ADCs as an interstage operational amplifier to reduce power consumption. Furthermore, the vertical stacking structure of the first-stage amplifier described in this invention can improve circuit design margin and achieve high gain. In high-voltage applications, core transistors can be used to improve operating speed. Preferably, when the first-stage amplifier adopts the self-biased structure described above, power consumption can be further reduced.
[0047] In summary, the amplifier and analog-to-digital converter using the present invention include a first-stage amplifier comprising N vertically stacked FIAs. The low-potential terminal of the preceding FIA is connected to the high-potential terminal of the following FIA via a connection module; N is greater than or equal to 2. The first-stage amplifier also includes a first capacitor and a second capacitor. In the first phase, the first capacitor is connected between the power supply voltage and ground, the first terminal of the second capacitor is connected to the high-potential terminal of the first-stage FIA, and the second terminal of the second capacitor is connected to the low-potential terminal of the Nth-stage FIA. In the second phase, the second capacitor is connected between the power supply voltage and ground, the first terminal of the first capacitor is connected to the high-potential terminal of the first-stage FIA, and the second terminal of the first capacitor is connected to the low-potential terminal of the Nth-stage FIA. The first phase is the reset phase, and the second phase is the amplification phase. By employing a vertically stacked structure, the present invention can evenly distribute high voltage to each stage of FIA, allowing each stage's FIA to use core transistors without worrying about overvoltage risks, thereby improving system operating speed. In other words, through the above-described configuration, this invention achieves high gain while allowing each FIA stage to be compatible with both I / O transistors and core transistors in high-voltage applications. When using core transistors, the operating speed can be improved. Furthermore, the structure of this invention provides greater design margin in circuit design, making amplifier design easier.
[0048] Furthermore, in the first phase, the present invention uses a self-biasing form with input and output connected in each FIA stage to obtain the initial bias voltage, so that each FIA stage can have a suitable initial static operating point, that is, there is no need to set the corresponding bias voltage separately, thus reducing the power consumption of the system.
[0049] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.
Claims
1. An amplifier characterized by, The amplifier includes a first-stage amplifier, which includes N vertically stacked FIAs. The low-potential terminal of the previous FIA is connected to the high-potential terminal of the next FIA through a connection module; N is greater than or equal to 2. The first stage amplifier also includes a first capacitor and a second capacitor; In the first phase, the first capacitor is connected between the power supply voltage and the ground terminal, the first terminal of the second capacitor is connected to the high potential terminal of the first stage FIA, and the second terminal of the second capacitor is connected to the low potential terminal of the Nth stage FIA. In the second phase, the second capacitor is connected between the power supply voltage and the ground terminal, the first terminal of the first capacitor is connected to the high potential terminal of the first stage FIA, and the second terminal of the first capacitor is connected to the low potential terminal of the Nth stage FIA; the first phase is the reset phase, and the second phase is the amplification phase.
2. The amplifier of claim 1, wherein, The connection module includes a switch and a capacitor connected in parallel, and the switch is turned on during the first phase.
3. The amplifier of claim 1, wherein, The first end of the input signal outputs N sub-first input signals through the first module; the second end of the input signal outputs N sub-second input signals through the second module; the first module and the second module each include N capacitors.
4. The amplifier of claim 3, wherein, The i-th sub-first input signal and the i-th sub-second input signal are used as inputs to the i-th level FIA. The output signal of the i-th level FIA includes the i-th sub-first output signal and the i-th sub-second output signal, 1≤i≤N; In the first phase, the i-th sub-first input signal is connected to the i-th sub-second output signal, and the i-th sub-second input signal is connected to the i-th sub-first output signal.
5. The amplifier according to claim 3, characterized in that, The i-th stage FIA includes a first P-type transistor and a first N-type transistor connected in series between the high-potential terminal and the low-potential terminal of the i-th stage FIA, and a second P-type transistor and a second N-type transistor connected in series between the high-potential terminal and the low-potential terminal of the i-th stage FIA; 1≤i≤N The input terminals of the first P-type transistor and the first N-type transistor are connected together and connected to the i-th sub-first input signal. The common node of the series connection of the first P-type transistor and the first N-type transistor serves as the i-th sub-second output signal. The input terminals of the second P-type transistor and the second N-type transistor are connected together and connected to the i-th sub-second input signal. The common node of the series connection of the second P-type transistor and the second N-type transistor serves as the i-th sub-first output signal.
6. The amplifier according to claim 5, characterized in that, A first switch is provided between the common node of the first P-type transistor and the first N-type transistor connected in series and the input terminal of the first P-type transistor and the first N-type transistor; a second switch is provided between the common node of the second P-type transistor and the second N-type transistor connected in series and the input terminal of the second P-type transistor and the second N-type transistor; in the first phase, the first switch and the second switch are turned on.
7. The amplifier according to any one of claims 4-6, characterized in that, N sub-first output signals serve as inputs to the third module, and the output of the third module serves as the first terminal signal of the output signal; N sub-second output signals serve as inputs to the fourth module, and the output of the fourth module serves as the second terminal signal of the output signal; the third module and the fourth module each include N capacitors; In the first phase, the first terminal and the second terminal of the output signal are connected to the common-mode voltage.
8. The amplifier according to claim 7, characterized in that, The amplifier also includes a second-stage amplifier, and the output signal serves as the input signal for the second-stage amplifier.
9. The amplifier according to any one of claims 1-6, characterized in that, The transistors in each FIA stage are core transistors.
10. An analog-to-digital converter, characterized in that, The amplifier includes the amplifier described in any one of claims 1-9, used to amplify the corresponding input signal.