Impedance adjustment circuit and amplifier circuit

Abstract

The invention provides an impedance adjusting circuit and an amplifier circuit. The impedance adjusting circuit comprises an input end, an output end and an impedance adjusting sub-circuit. The impedance adjustment sub-circuit includes a metal oxide semiconductor transistor-capacitor (MOSCAP) and a switching circuit. The first end of the metal oxide semiconductor transistor-capacitor is coupled to the input end. The control end of the metal oxide semiconductor transistor-capacitor receives a control signal. The control end of the switching circuit receives a switching control signal. A base terminal of the metal oxide semiconductor transistor-capacitor is coupled to the output terminal. The capacitance value of the impedance adjustment sub-circuit is changed by changing the switch control signal.

Description

Technical Field

[0001] This invention relates to a signal processing technique in electronic circuits, and more particularly to an impedance adjustment circuit and an amplifier circuit. Background Technology

[0002] Amplifier circuits are used in many technical fields, such as radio frequency (RF) applications and signal processing. Impedance matching devices or corresponding matching circuits are set at the input or output terminals of amplifier circuits to reduce noise in the input signal and, ideally, to reduce signal loss after amplification and increase gain. Summary of the Invention

[0003] The impedance adjustment circuit of this invention is used to provide different capacitance values. The impedance adjustment circuit includes an input terminal, an output terminal, and an impedance adjustment sub-circuit. The impedance adjustment sub-circuit includes a metal-oxide-semiconductor capacitor (MOSCAP) and a switching circuit. The MOSCAP includes a first terminal, a second terminal, a control terminal, and a base terminal, wherein the first terminal is coupled to the input terminal, and the control terminal of the MOSCAP receives a control signal. The control terminal of the switching circuit receives a switching control signal, and the base terminal of the MOSCAP is coupled to the output terminal through the switching circuit. The capacitance value of the impedance adjustment sub-circuit is changed by changing the switching control signal.

[0004] The impedance adjustment circuit of this invention provides different capacitance values. The impedance adjustment circuit includes an input terminal, an output terminal, and an impedance adjustment sub-circuit. The impedance adjustment sub-circuit includes a metal-oxide-semiconductor transistor-capacitor (MOSFET-CUC) and a switching circuit. The MOSFET-CUC includes a first terminal, a second terminal, a control terminal, and a base terminal, wherein the control terminal of the MOSFET-CUC is coupled to the input terminal. The control terminal of the switching circuit receives a switching control signal, and the base terminal of the MOSFET-CUC is coupled to the output terminal through the switching circuit. Changing the switching control signal alters the capacitance value of the impedance adjustment sub-circuit.

[0005] The amplifier circuit of this embodiment includes an amplifier and a matching circuit. The matching circuit is coupled to the amplifier. The matching circuit includes the impedance adjustment circuit as described above. Attached Figure Description

[0006] Figure 1A and Figure 1B This is a schematic diagram of an amplifier circuit according to various embodiments of the present invention.

[0007] Figure 2A This is a schematic diagram of an impedance adjustment circuit according to the first embodiment of the present invention.

[0008] Figure 2B This is a schematic diagram of an impedance adjustment circuit according to a second embodiment of the present invention.

[0009] Figure 2C This is a schematic diagram of an impedance adjustment circuit according to a third embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of an impedance adjustment circuit according to the fourth embodiment of the present invention.

[0011] Figure 4A This is a schematic diagram of the cross-section of a metal-oxide-semiconductor transistor-capacitor (MOScap) and corresponding components in the impedance adjustment sub-circuit according to the first embodiment of the present invention.

[0012] Figure 4B This is a schematic diagram of the cross-section of a metal-oxide-semiconductor transistor-capacitor (MOScap) and corresponding components in the impedance adjustment sub-circuit according to the second embodiment of the present invention.

[0013] Figure 5A and Figure 5B This is a schematic diagram of the switching circuit according to various embodiments of the present invention.

[0014] Figure 6A and Figure 6B This is the first embodiment of the present invention. Figure 4A A schematic diagram of the impedance adjustment sub-circuit and its capacitor value.

[0015] Figure 7 This is a schematic diagram of an impedance adjustment circuit according to the fifth embodiment of the present invention.

[0016] Figure 8 This is a schematic diagram of an impedance adjustment circuit according to the fifth embodiment of the present invention.

[0017] Figure 9 This is a schematic diagram of the cross-section of a metal-oxide-semiconductor transistor-capacitor (MOScap) and corresponding components in the impedance adjustment sub-circuit according to the fifth embodiment of the present invention.

[0018] Figure 10 This is a circuit diagram of the control circuit according to various embodiments of the present invention.

[0019] Symbol explanation:

[0020] 100A, 100B: Amplifier circuits

[0021] 105. AMP: Amplifier

[0022] 110, 110A~110F: Impedance adjustment circuit

[0023] 110-1a, 110-1b, 110-1c, 110-2a, 110-11~110-13, 110-21~110-23: Impedance adjustment sub-circuit

[0024] 120, 120A, 120B: Switching circuit

[0025] 210: Control Circuit

[0026] RFIN: Signal input terminal

[0027] RFOUT: Signal output terminal

[0028] INP: Input terminal

[0029] OUTP: Output terminal

[0030] Vref: Reference voltage

[0031] MOScap: Metal Oxide Semiconductor - Capacitor

[0032] Vgctl: Control signal

[0033] VgctlB: Inverted control signal

[0034] BN: Metal-Oxide-Semiconductor - Base Terminal of Capacitor

[0035] Ssw, Ssw1~Ssw3: Switch control signals

[0036] SswB: Inverted switch control signal

[0037] N1: First terminal of a metal-oxide-semiconductor capacitor

[0038] N2: Metal-oxide-semiconductor capacitor - second terminal

[0039] GN: Control terminal of a metal-oxide-semiconductor capacitor

[0040] BN: Metal-Oxide-Semiconductor - Base Terminal of Capacitor

[0041] R1~R3: Bias resistors

[0042] C2-1~C2-3: Matching capacitors

[0043] Vgnd: Grounding voltage

[0044] P-we11: P-type well layer

[0045] Deep N-well: Deep N-type well layer

[0046] P-substrate: P-type basal layer

[0047] VDD: System voltage terminal

[0048] GND: Ground terminal

[0049] NM1, PM1: Switching transistors

[0050] Cmos(high), Cmos(low), Csw: Capacitance values

[0051] INV1, INV2: Inverters

[0052] Sin: Input signal

[0053] C1: Control capacitor Detailed Implementation

[0054] Figure 1A and Figure 1B These are schematic diagrams of amplifier circuits 100A and 100B according to various embodiments of the present invention. Figure 1A and Figure 1B The amplifier circuits 100A and 100B in the middle include an amplifier AMP 105 and an impedance adjustment circuit 110 as a matching circuit, respectively.

[0055] Amplifier AMP 105 has a signal input terminal RFIN and a signal output terminal RFOUT. In this embodiment, amplifier AMP 105 can be a low-noise amplifier (LNA), and users of this embodiment can adjust the characteristics of amplifier AMP 105 according to their needs. In one embodiment, amplifier AMP 105 can be a power amplifier (PA).

[0056] The impedance adjustment circuit 110 includes an input terminal INP, an output terminal OUTP, and one or more impedance adjustment sub-circuits. Figure 1A The input terminal INP of the impedance adjustment circuit 110 is coupled to the signal input terminal RFIN of the AMP 105. On the other hand, Figure 1BThe input terminal INP of the impedance adjustment circuit 110 is coupled to the signal output terminal RFOUT of the AMP 105. Users of this embodiment can selectively couple the impedance adjustment circuit 110, which serves as a matching circuit, to either the signal input terminal RFIN or the signal output terminal RFOUT of the AMP 105, depending on their needs. Users of this embodiment can couple different impedance adjustment circuits 110 to the signal input terminal RFIN and / or the signal output terminal RFOUT of the AMP 105 to serve as matching circuits. Users of this embodiment can also place the impedance adjustment circuit 110 at the input or output terminal of other types of circuits to serve as corresponding matching circuits.

[0057] Impedance adjustment circuit 110 is used to adjust the impedance of the signal input terminal RFIN or the signal output terminal RFOUT of AMP 105. Users of this embodiment can provide a reference signal at the signal input terminal RFIN and selectively adjust the capacitance value in the impedance adjustment circuit 110 according to the reflection coefficient or corresponding parameters of the reference signal. In one embodiment, the circuit designer can apply the impedance adjustment circuit 110 to other applications requiring corresponding static / dynamic adjustment circuitry. In one embodiment, the frequency of the signal input terminal RFIN is inversely proportional to the capacitance value of the impedance adjustment circuit 110.

[0058] Passing here Figures 2A to 2C , Figure 3 , Figures 4A to 4B , Figures 6A to 6B , Figures 7 to 8 This will illustrate the various states of the impedance adjustment circuit 110.

[0059] Figure 2A This is a schematic diagram of an impedance adjustment circuit 110A according to a first embodiment of the present invention. The impedance adjustment circuit 110A includes an input terminal INP, an output terminal OUTP, and an impedance adjustment sub-circuit 110-1a. The impedance adjustment sub-circuit 110-1a includes a metal-oxide-semiconductor transistor-capacitor (MOScap) and a switching circuit 120. In this embodiment, the MOScap is an N-type transistor; however, a P-type transistor can also be used to implement the MOScap.

[0060] The MOSCAP (Metal-Oxide-Semiconductor Transistor-Capacitor) includes a first terminal N1 (e.g., source), a second terminal N2 (e.g., drain), a control terminal GN (e.g., gate), and a base terminal BN. The control terminal GN of the MOSCAP receives the control signal Vgctl. In this embodiment, the second terminal N2 is coupled to the input terminal INP. In this embodiment, the first terminal N1 and the second terminal N2 are mutually coupled. In this embodiment, the first terminal N1, the second terminal N2, and the input terminal INP can be directly coupled.

[0061] The control terminal of the switching circuit 120 receives the switching control signal Ssw. The base terminal BN is coupled to the output terminal OUTP through the switching circuit 120. The impedance adjustment circuit 110A also includes a control circuit 210 for generating a control signal Vgctl. Specifically, one end of the switching circuit 120 is directly coupled to the base terminal BN, and the other end of the switching circuit 120 is directly coupled to the output terminal OUTP. In this embodiment, the output terminal OUTP can be a reference voltage terminal. The reference voltage terminal provides a reference voltage Vref (e.g., ground voltage) to the other end of the switching circuit. When the control signal Vgctl is enabled, this embodiment of the invention changes the capacitance value of the impedance adjustment sub-circuit 110-2a by changing the switching control signal Ssw. In other words, by changing the switching control signal Ssw, the capacitance value of the switching circuit 120 itself can be changed, thereby further changing the capacitance value of the impedance adjustment sub-circuit 110-1a. The "capacitance value of the switching circuit 120 itself" mentioned in this embodiment can be a discrete capacitor, or a switched capacitor. In other words, the capacitance value of the switching circuit 120 itself can have a discretely changing capacitance value through switching.

[0062] The capacitance value of the impedance adjustment sub-circuit 110-1a is determined based on the capacitance value between the gate terminal GN and the base terminal BN of the metal-oxide-semiconductor transistor-capacitor MOScap, and the capacitance value of the switching circuit 120 located between the base terminal BN and the output terminal OUTP. Since the switching circuit 120 is located between the base terminal BN and the output terminal OUTP, and the conduction of the switching circuit 120 is controlled by the switching control signal Ssw, thus changing the capacitance value of the switching circuit 120 itself, the capacitance value of the impedance adjustment sub-circuit 110-1a is changed by the switching control signal Ssw.

[0063] Figure 2B This is a schematic diagram of the impedance adjustment circuit 110B according to the second embodiment of the present invention. Figure 2B Impedance adjustment circuit 110B and Figure 2A The difference between impedance adjustment circuits 110A and 110-1b is that the control terminal GN of the metal oxide semiconductor transistor-capacitor MOScap in the impedance adjustment sub-circuit 110-1b is coupled to the input terminal INP, and receives the inverted control signal VgtlB through the bias resistor R1. Figure 2B The impedance adjustment circuit 110B also includes a bias resistor R1. One end of the bias resistor R1 is coupled to the control terminal GN of the metal-oxide-semiconductor transistor-capacitor MOScap, and the other end of the bias resistor R1 receives an inverted control signal VgtlB. Furthermore, the second terminal N2 and the first terminal N1 are not coupled to the input terminal INP.

[0064] Therefore, when the control signal Vgctl is enabled, the capacitance value of the impedance adjustment sub-circuit 110-1n is determined based on the capacitance value between the control terminal GN and the base terminal BN in the metal-oxide-semiconductor transistor-capacitor MOScap, and the capacitance value of the switching circuit 120. In this embodiment of the invention, the capacitance value of the switching circuit 120 is changed by altering the switching control signal Ssw, thereby changing the capacitance value of the impedance adjustment sub-circuit 110-1b.

[0065] Figure 2C This is a schematic diagram of the impedance adjustment circuit 110C according to the third embodiment of the present invention. Figure 2C Impedance adjustment circuit 110C and Figure 2B The difference between the impedance adjustment circuits 110B lies in that the first terminal N1 and the second terminal N2 of the metal-oxide-semiconductor transistor-capacitor MOScap in the impedance adjustment sub-circuit 110-1c are all coupled to the base terminal BN. Therefore, when the control signal Vgctl is enabled, the capacitance value of the impedance adjustment sub-circuit 110-1c is determined based on the capacitance value between the control terminal GN and the base terminal BN in the metal-oxide-semiconductor transistor-capacitor MOScap, and the capacitance value of the switching circuit 120. In this embodiment of the invention, the capacitance value of the switching circuit 120 is changed by altering the switching control signal Ssw, thereby changing the capacitance value of the impedance adjustment sub-circuit 110-1c.

[0066] Figure 3 This is a schematic diagram of an impedance adjustment circuit 110D according to a fourth embodiment of the present invention. In addition to the input terminal INP and the output terminal OUTP, the impedance adjustment circuit 110D also includes at least two impedance adjustment sub-circuits, for example, one impedance adjustment sub-circuit (e.g., Figure 3 Impedance adjustment sub-circuit 110-11) and another impedance adjustment sub-circuit (e.g., Figure 3 Impedance adjustment sub-circuit 110-12). Figure 3 Any of the impedance adjustment sub-circuits 110-12 may include another metal-oxide-semiconductor transistor-capacitor MOScap and another switching circuit 120.

[0067] Figure 3 The impedance adjustment circuit 110D presents at least three impedance adjustment sub-circuits 110-11 to 110-13, and the user of this embodiment can adjust the number of impedance adjustment sub-circuits as needed. Figure 3 The circuit structures in impedance adjustment sub-circuits 110-11 to 110-13 are the same as those in the impedance adjustment sub-circuits. Figure 2A Impedance adjustment sub-circuit 110-1a. Users of this embodiment can adapt it to their needs. Figure 3 The circuit structure in impedance adjustment sub-circuits 110-11 to 110-13 is as follows: Figures 2A to 2CThis can be achieved using one or a combination of medium impedance adjustment sub-circuits 110-1a to 110-1c. This embodiment can... Figure 3 Impedance adjustment sub-circuits 110-11 to 110-13 provide their own independent switching control signals Ssw1 to Ssw3, so that... Figure 3 Impedance adjustment sub-circuits 110-11 to 110-13 respectively display the capacitance values ​​set by the switch control signals Ssw1 to Ssw3. Figure 3 The overall capacitance value of the impedance adjustment circuit 110D is based on Figure 3 The capacitance values ​​of the impedance adjustment sub-circuits 110-11 to 110-13 after parallel connection. That is, Figure 3 The overall capacitance value of the impedance adjustment circuit 110D is Figure 3 The summation of the capacitance values ​​in impedance adjustment sub-circuits 110-11 to 110-13.

[0068] Figure 4A This is a schematic diagram of the cross-section of the metal-oxide-semiconductor transistor-capacitor MOScap and corresponding components in the impedance adjustment sub-circuit 110-1a according to the first embodiment of the present invention. The metal-oxide-semiconductor transistor-capacitor MOScap and the switching circuit 120 of the impedance adjustment sub-circuit 110-1a are shown in... Figure 4A ,and Figure 4A The coupling method of each component in the medium impedance adjustment sub-circuit 110-1a and Figure 2A same. Figure 4A In this context, "P-we11" represents a P-type well layer, "Deep N well" represents a deep N-type well layer, and "P-substrate" represents a P-type substrate layer. VDD represents the system voltage terminal, and GND represents the ground terminal.

[0069] Figure 4B This is a schematic diagram of the cross-section of the metal-oxide-semiconductor transistor-capacitor MOScap and corresponding components in the impedance adjustment sub-circuit 110-1b according to the second embodiment of the present invention. The metal-oxide-semiconductor transistor-capacitor MOScap, the switching circuit 120, and the bias resistor R1 of the impedance adjustment sub-circuit 110-1b are shown in... Figure 4B ,and Figure 4B The coupling method of each component in the medium impedance adjustment sub-circuit 110-1b and Figure 2B same.

[0070] Figure 5A and Figure 5B This is a schematic diagram of switch circuits 120A and 120B according to various embodiments of the present invention. The switch circuit 120 in various embodiments of the present invention may selectively be composed of… Figure 5A and Figure 5BThe switching circuits 120A and 120B are used to implement this, but users of this embodiment can also implement the switching circuit 120 in each embodiment using other types of switching circuits.

[0071] Figure 5A The switching circuit 120A includes a switching transistor NM1. The first terminal (e.g., source terminal) of the switching transistor NM1 is coupled to the base terminal BN of a metal-oxide-semiconductor transistor-capacitor MOScap. The second terminal (e.g., drain terminal) of the switching transistor NM1 is coupled to the output terminal OUTP. The control terminal (e.g., gate terminal) of the switching transistor NM1 receives an inverted switching control signal SswB. Based on... Figure 5A The circuit structure allows for changing the conduction of the switching circuit 120A by altering the inverted switching control signal SswB, thereby changing the capacitance value of the switching circuit 120A itself. In this embodiment, the switching transistor NM1 can be an N-type transistor. In one embodiment, Figure 5A The switching transistor in the circuit can be a P-type transistor, and the control terminal of the P-type transistor receives a positive switching control signal.

[0072] Figure 5A and Figure 5B compared to, Figure 5B The switching circuit 120B includes a switching transistor PM1 in addition to a switching transistor NM1. The first terminal (e.g., source terminal) of switching transistor PM1 is coupled to the output terminal OUTP. The second terminal (e.g., drain terminal) of switching transistor PM1 is coupled to the base terminal BN of the metal-oxide-semiconductor transistor-capacitor MOScap. The control terminal (e.g., gate terminal) of switching transistor PM1 receives the switching control signal Ssw. Figure 5B The circuit structure allows for the corresponding change of the inverted switch control signal SswB by altering the switch control signal Ssw, thereby changing the capacitance value of the switch circuit 120A itself. In this embodiment, the switch transistor NM1 can be an N-type transistor, and the control terminal of the N-type transistor receives the inverted switch control signal; the switch transistor PM1 can be a P-type transistor, and the control terminal of the P-type transistor receives the positive switch control signal.

[0073] Figure 6A and Figure 6B This is the first embodiment of the present invention. Figure 4A A schematic diagram of the impedance adjustment sub-circuit 110-1a and its capacitor value is shown below. Please refer to... Figure 6AWhen the control signal Vgctl is enabled (e.g., logic high "high") and the switching circuit 120 is turned on (e.g., "ON") by the switch control signal Ssw to couple the reference voltage Vref (e.g., ground voltage Vgnd) on the output terminal OUTP to the base terminal BN of the metal-oxide-semiconductor transistor-capacitor MOScap, the switching circuit 120 is turned on and has no capacitance value. Therefore, the equivalent capacitance value of the impedance adjustment sub-circuit 110-1a is the capacitance value Cmos(high) between the oxide layer on the gate terminal GN of the metal-oxide-semiconductor transistor-capacitor MOScap and the P-type doped layer (e.g., "P+body") on the base terminal BN, as shown. Figure 6A As shown in the right-hand section.

[0074] On the other hand, the capacitance between the oxide layer on the gate terminal GN and the P-type doped layer (e.g., "P+body") of the metal-oxide-semiconductor transistor-capacitor MOScap varies depending on whether the control signal Vgctl is enabled (e.g., logic high "high") or disabled (e.g., logic low "low"). Here, the equivalent capacitance values ​​of the metal-oxide-semiconductor transistor-capacitor MOScap are referred to as capacitance value Cmos(high) (when the control signal Vgctl is enabled) and capacitance value Cmos(low) (when the control signal Vgctl is disabled). Therefore, if the control signal Vgctl is disabled and the switching circuit 120 is turned on (e.g., "ON"), the equivalent capacitance value of the impedance adjustment sub-circuit 110-1a is capacitance value Cmos(low).

[0075] Please refer to Figure 6B When the control signal Vgctl is enabled (e.g., logic high "high") and the switching circuit 120 is turned off (e.g., "OFF") under the control of the switch control signal Ssw, the switching circuit 120 is turned off at both ends, giving the switching circuit 120 itself a capacitance value Csw. Therefore, the equivalent capacitance value of the impedance adjustment sub-circuit 110-1a is the equivalent capacitance value of "the capacitance value Cmos between the oxide layer on the gate terminal GN of the metal oxide semiconductor transistor-capacitor MOScap and the P-type doped layer (e.g., "P+body") on the base terminal BN" and "the capacitance value Csw of the switching circuit 120" in series, as follows: Figure 6B As shown in the right-hand section.

[0076] On the other hand, if the control signal Vgctl is disabled and the switching circuit 120 is turned off (e.g., "OFF"), the equivalent capacitance value of the impedance adjustment sub-circuit 110-1a is the equivalent capacitance value of "capacitance value Cmos(low)" and "capacitance value Csw of the switching circuit 120" after being connected in series.

[0077] Figure 7 This is a schematic diagram of an impedance adjustment circuit 110E according to a fifth embodiment of the present invention. The impedance adjustment circuit 110E includes an input terminal INP, an output terminal OUTP, and an impedance adjustment sub-circuit 110-2a. Figure 7 Impedance adjustment sub-circuit 110-2a and Figure 2A The difference in impedance adjustment sub-circuit 110-1a is that, Figure 7 The impedance adjustment sub-circuit 110-2a also includes a matching capacitor C2-1 and a bias resistor R1. Furthermore, in this embodiment, the first terminal N1 of the metal-oxide-semiconductor transistor-capacitor MOScap is coupled to the output terminal OUTP, rather than to the second terminal N2 or the input terminal INP.

[0078] In this embodiment, the matching capacitor can be coupled between the input terminal INP and either the first terminal N1 or the second terminal N2 of the metal-oxide-semiconductor transistor-capacitor MOScap. For example, Figure 7 The matching capacitor C2-1 is disposed between the input terminal INP and the second terminal N2 of the metal-oxide-semiconductor transistor-capacitor MOScap. In other embodiments, the matching capacitor may be disposed between the input terminal INP and the second terminal N2 of the metal-oxide-semiconductor transistor-capacitor MOScap. Figure 2A The input terminal INP is connected to the first terminal N1 of the metal-oxide-semiconductor transistor-capacitor MOScap, or a matching capacitor can be set. Figure 2A The input terminal INP is between the second terminal N2 of the metal-oxide-semiconductor transistor-capacitor MOScap.

[0079] Figure 7 The first terminal of the bias resistor R1 is coupled to one end of the metal-oxide-semiconductor transistor-capacitor MOScap (e.g., the first terminal N1), and the second terminal of the bias resistor R1 receives an inverted control signal VgctlB. In other embodiments, the first terminal of the bias resistor may be coupled to either the first or second terminal of the metal-oxide-semiconductor transistor-capacitor MOScap. When the control signal Vgctl is enabled, embodiments of the present invention change the capacitance value of the impedance adjustment sub-circuit 110-2a by changing the switch control signal Ssw. In other words, by changing the switch control signal Ssw, the capacitance value of the switch circuit 120 itself can be changed, thereby further changing the capacitance value of the impedance adjustment sub-circuit 110-2a. In one embodiment, the impedance adjustment circuit 110E may include at least one of a matching capacitor C2-1 and a bias resistor R1.

[0080] Figure 8 This is a schematic diagram of an impedance adjustment circuit 110F according to a fifth embodiment of the present invention. In addition to the input terminal INP and the output terminal OUTP, the impedance adjustment circuit 110F also includes at least two impedance adjustment sub-circuits. Figure 8The impedance adjustment circuit 110F presents at least three impedance adjustment sub-circuits 110-21 to 110-23, and the user of this embodiment can adjust the number of impedance adjustment sub-circuits as needed. Figure 3 The circuit structures in impedance adjustment sub-circuits 110-21 to 110-23 are the same as those in the impedance adjustment sub-circuits. Figure 7 Impedance adjustment sub-circuit 110-2a.

[0081] Users of this embodiment can make it according to their needs. Figure 8 The circuit structure in impedance adjustment sub-circuits 110-21 to 110-23 is based on Figures 2A to 2C , Figure 7 This is achieved using one or a combination of medium impedance adjustment sub-circuits 110-1a to 110-1c and 110-2a. This embodiment can respectively... Figure 8 Impedance adjustment sub-circuits 110-21 to 110-23 provide their own independent switching control signals Ssw1 to Ssw3, so that... Figure 8 Impedance adjustment sub-circuits 110-21 to 110-33 respectively display the capacitance values ​​set by the switch control signals Ssw1 to Ssw3. Figure 8 The matching capacitors C2-1 to C2-3 and the bias resistors R1 to R3 in the impedance adjustment sub-circuits 110-21 to 110-33 can be adjusted according to the needs of the user of this embodiment and the circuit design requirements. Figure 8 The overall capacitance value of the impedance adjustment circuit 110F is based on Figure 8 The capacitance values ​​of the impedance adjustment sub-circuits 110-21 to 110-23 after parallel connection. That is, Figure 8 The overall capacitance value of impedance adjustment sub-circuits 110-21 to 110-23 is Figure 8 The summation of the capacitance values ​​in impedance adjustment sub-circuits 110-21 to 110-23.

[0082] Figure 9 This is a schematic diagram of the cross-section of the metal-oxide-semiconductor transistor-capacitor MOScap and corresponding components in the impedance adjustment sub-circuit 110-2a according to the fifth embodiment of the present invention. The metal-oxide-semiconductor transistor-capacitor MOScap and the switching circuit 120 of the impedance adjustment sub-circuit 110-2a are shown in... Figure 7 ,and Figure 9 The coupling method of each component in the medium impedance adjustment sub-circuit 110-2a and Figure 7 same.

[0083] Figure 10 This is a circuit diagram of the control circuit 210 according to various embodiments of the present invention. Figure 10The control circuit 210 is one of the examples of the control circuit 210 in various embodiments of the present invention. Users of this embodiment can select a suitable circuit structure to implement the control circuit 210 according to their needs. Figure 10 The control circuit 210 includes inverters INV1 and INV2, and a control capacitor C1. The input terminal of inverter INV1 receives the input signal Sin and serves as the input terminal of control circuit 210. The output terminal of inverter INV1 is coupled to the input terminal of inverter INV2. The first terminal of control capacitor C1 is coupled to the output terminal of inverter INV2 to serve as the output terminal of control circuit 210. The output terminal of control circuit 210 is used to generate a control signal Vgctl. Control capacitor C1 is used to regulate the voltage at the output terminal of control circuit 210.

[0084] In one embodiment, the control circuit 210 may further include digital control circuitry for controlling the states of the control signal Vgctl and the switch control signal Ssw. That is, the control circuit 210 can simultaneously control the states of the control signal Vgctl and the switch control signal Ssw to adjust the capacitor value. For example, such as... Figure 2A The circuit diagram can achieve four capacitance values ​​by controlling the states of the control signal Vgctl and the switch control signal Ssw. When the control state is state one, the minimum capacitance value can be obtained; when the control state is state four, the maximum capacitance value can be obtained. On the other hand, when the control state is state two or state three, the obtained capacitance value depends on the size, which can be determined by the transistor size selected according to the designer's needs.

[0085]

[0086] Table 1

[0087] In one embodiment, when the frequency of the signal input terminal RFIN is high, the control state is set to state one; conversely, when the frequency of the signal input terminal RFIN is low, the control state is set to state four to maintain a better reflection coefficient.

[0088] In summary, the impedance adjustment circuit and amplifier circuit of this invention add a switching circuit between the base terminal of the metal-oxide-semiconductor transistor-capacitor and the output terminal (e.g., ground terminal) in each impedance adjustment sub-circuit. By controlling the gate voltage of the metal-oxide-semiconductor transistor-capacitor and the conduction of the switching circuit, the capacitance value in the impedance adjustment circuit can be varied in multiple stages. Therefore, the impedance adjustment circuit and amplifier circuit of this invention can adaptively adjust the capacitance value in the impedance adjustment circuit according to different situations, reducing noise in the input signal of the amplifier circuit and increasing its gain by minimizing signal amplification loss. This invention provides an impedance adjustment circuit and amplifier circuit that can adjust the capacitance value in the impedance adjustment circuit in multiple stages and increase the bandwidth during signal processing.

Claims

1. An impedance adjustment circuit for providing different capacitance values, characterized by, include: One input terminal; One output terminal; as well as An impedance adjustment sub-circuit, the impedance adjustment sub-circuit comprising: A metal-oxide-semiconductor transistor-capacitor includes a first terminal, a second terminal, a control terminal and a base terminal, wherein the second terminal is coupled to the input terminal and the control terminal of the metal-oxide-semiconductor transistor-capacitor receives a control signal. as well as A switching circuit, wherein a control terminal of the switching circuit receives a switching control signal, and the base terminal of the metal-oxide-semiconductor transistor-capacitor is coupled to the output terminal through the switching circuit, wherein the capacitance value of the impedance adjustment sub-circuit is changed by changing the switching control signal.

2. The impedance adjustment circuit of claim 1, wherein, The capacitance value of the switching circuit is changed by altering the switch control signal.

3. The impedance adjustment circuit according to claim 1, characterized in that, The first terminal of the metal-oxide-semiconductor transistor-capacitor is coupled to the input terminal.

4. The impedance adjustment circuit according to claim 3, characterized in that, Also includes: Another impedance adjustment sub-circuit, the other impedance adjustment sub-circuit comprising: Another metal-oxide-semiconductor transistor-capacitor includes a first terminal, a second terminal, a control terminal, and a base terminal, wherein the first terminal and the second terminal are coupled to the input terminal, and the control terminal of the other metal-oxide-semiconductor transistor-capacitor receives a control signal; and Another switching circuit, wherein a control terminal of the switching circuit receives a switching control signal, wherein by changing the switching control signal, the base terminal of the other metal-oxide-semiconductor transistor-capacitor is selectively coupled to the output terminal.

5. The impedance adjustment circuit according to claim 1, characterized in that, The first terminal of the metal oxide semiconductor transistor-capacitor is coupled to the output terminal.

6. The impedance adjustment circuit according to claim 5, characterized in that, Also includes: Another impedance adjustment sub-circuit, the other impedance adjustment sub-circuit comprising: Another metal-oxide-semiconductor transistor-capacitor includes a first terminal, a second terminal, a control terminal, and a base terminal, wherein the first terminal is coupled to the output terminal, the second terminal is coupled to the input terminal, and the control terminal of the other metal-oxide-semiconductor transistor-capacitor receives a control signal. as well as Another switching circuit, a control terminal of which receives a switching control signal, the base terminal of the other metal-oxide-semiconductor transistor-capacitor is coupled to the output terminal through the switching circuit, wherein the capacitance value of the impedance adjustment sub-circuit is changed by changing the switching control signal.

7. The impedance adjustment circuit according to claim 1, characterized in that, The switching circuit is a discrete capacitor.

8. The impedance adjustment circuit according to claim 7, characterized in that, The switching circuit includes: A first switching transistor, the first terminal of which is coupled to the base terminal of the metal-oxide-semiconductor transistor-capacitor, the second terminal of which is coupled to the output terminal, and the control terminal of which is coupled to the switching control signal.

9. The impedance adjustment circuit according to claim 7, characterized in that, The switching circuit includes: A first switching transistor, wherein a first terminal is coupled to the base terminal of the metal-oxide-semiconductor transistor-capacitor, a second terminal of the first switching transistor is coupled to the output terminal, and a control terminal of the first switching transistor is coupled to the switching control signal; and A second switching transistor, the first terminal of which is coupled to the output terminal, the second terminal of which is coupled to the base terminal of the metal-oxide-semiconductor transistor-capacitor, and the control terminal of which is coupled to the inverted switching control signal.

10. The impedance adjustment circuit according to claim 1, characterized in that, The impedance adjustment sub-circuit also includes: A matching capacitor, wherein the matching capacitor is coupled between the input terminal and one of the first terminal and the second terminal of the metal-oxide-semiconductor transistor-capacitor.

11. The impedance adjustment circuit according to claim 1, characterized in that, The impedance adjustment sub-circuit also includes: A bias resistor, the first end of which is coupled to one of the first and second ends of the metal-oxide-semiconductor transistor-capacitor, and the second end of the bias resistor receives the inverted control signal.

12. The impedance adjustment circuit according to claim 1, characterized in that, The impedance adjustment sub-circuit also includes: One input terminal; One output terminal; and An impedance adjustment sub-circuit, the impedance adjustment sub-circuit comprising: A metal-oxide-semiconductor transistor-capacitor includes a first terminal, a second terminal, a control terminal, and a base terminal, wherein the control terminal of the metal-oxide-semiconductor transistor-capacitor is coupled to the input terminal; and A switching circuit, wherein a control terminal of the switching circuit receives a switching control signal, and the base terminal of the metal-oxide-semiconductor transistor-capacitor is coupled to the output terminal through the switching circuit, wherein the capacitance value of the impedance adjustment sub-circuit is changed by changing the switching control signal.

13. The impedance adjustment circuit according to claim 12, characterized in that, The first terminal of the metal oxide semiconductor transistor-capacitor is coupled to the second terminal of the metal oxide semiconductor transistor-capacitor.

14. The impedance adjustment circuit according to claim 13, characterized in that, The first terminal of the metal oxide semiconductor transistor-capacitor is coupled to the base terminal of the metal oxide semiconductor transistor-capacitor.

15. An amplifier circuit, characterized in that, include: An amplifier; as well as A matching circuit is coupled to the amplifier. The matching circuit includes an impedance adjustment circuit according to any one of claims 1 to 14.

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