Frequency generation circuit, chip and electronic equipment

Abstract

According to the frequency generation circuit, the chip and the electronic equipment provided by the embodiment of the invention, the calibration mode is introduced to the gain filtering module, and the calibration voltage is accessed when the gain filtering module is in the calibration mode, so that the offset voltage during gain is calibrated, the calibration state signal is obtained, whether calibration is completed or not can be intuitively indicated through the calibration state signal, and the calibration efficiency is improved. Under the condition that the calibration state signal indicates that calibration is completed, errors caused by offset voltage can be suppressed, the stability of the calibrated gain filtering module is higher, therefore, when the gain filtering module is switched to the filtering mode to filter the target voltage, the integral leakage phenomenon can be effectively reduced, and the stability of the gain filtering module is improved. Therefore, the stability of the target frequency signal generated by the subsequent oscillation module is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a frequency generation circuit, chip, and electronic device. Background Technology

[0002] A phase-locked loop (PLL) circuit is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a frequency signal. A loop filter is usually set in the PLL circuit for filtering.

[0003] In related technologies, a gain unit is usually introduced to reduce the capacitance value of the loop filter in the phase-locked loop circuit. However, the offset voltage of the gain unit will cause the voltage at its input and output terminals to be different. The voltage difference will generate current that will continuously interfere with the voltage on the capacitor of the loop filter, causing the input voltage of the loop filter to change continuously, thereby reducing the stability of the frequency signal output by the phase-locked loop circuit. Summary of the Invention

[0004] In view of the above problems, embodiments of this application provide a frequency generation circuit, chip, and electronic device to solve the above technical problems.

[0005] In a first aspect, embodiments of this application provide a frequency generating circuit, including: The comparison module is used to receive a reference clock signal and a feedback signal to generate a charge / discharge control signal; A voltage generation module, which is used to receive the charge / discharge control signal to generate a target voltage; A gain filtering module is used to connect a calibration voltage when in calibration mode to calibrate the offset voltage when gain is applied, thereby obtaining a calibration status signal. When the calibration status signal indicates that calibration is complete, the module switches to a filtering mode to filter the target voltage, thereby obtaining a filtered signal. An oscillation module is used to receive the filtered signal to generate a target frequency signal.

[0006] Secondly, embodiments of this application also provide a chip including the frequency generation circuit described above.

[0007] Thirdly, embodiments of this application also provide an electronic device, including a device body and a frequency generating circuit as described above disposed on the device body, or including a device body and a chip as described above disposed on the device body.

[0008] The frequency generation circuit, chip, and electronic device provided in this application introduce a calibration mode to the gain filtering module. When in calibration mode, a calibration voltage is applied to calibrate the offset voltage during gain, resulting in a calibration status signal. This calibration status signal can intuitively indicate whether calibration is complete. When the calibration status signal indicates that calibration is complete, the error caused by the offset voltage can be suppressed, making the calibrated gain filtering module more stable. Therefore, when the gain filtering module switches to filtering mode to filter the target voltage, the phenomenon of integral leakage can be effectively reduced, thereby improving the stability of the target frequency signal generated by the subsequent oscillation module.

[0009] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a loop filter in related technologies is shown.

[0012] Figure 2 A schematic diagram of a frequency generation circuit provided in an embodiment of this application is shown.

[0013] Figure 3 Another schematic diagram of the frequency generation circuit provided in an embodiment of this application is shown.

[0014] Figure 4 Another schematic diagram of the frequency generation circuit provided in an embodiment of this application is shown.

[0015] Figure 5 Another schematic diagram of the frequency generation circuit provided in an embodiment of this application is shown.

[0016] Figure 6 Another schematic diagram of the frequency generation circuit provided in an embodiment of this application is shown.

[0017] Figure 7 Another schematic diagram of the frequency generation circuit provided in an embodiment of this application is shown.

[0018] Figure 8 This diagram illustrates the switching state of the gain filtering module 130 in calibration mode provided in an embodiment of this application.

[0019] Figure 9This paper shows a schematic diagram of the switching state of the gain filtering module 130 in the filtering mode provided in the embodiment of this application.

[0020] Figure 10 Another schematic diagram of the frequency generation circuit provided in an embodiment of this application is shown.

[0021] Figure 11 This paper shows a schematic diagram of an operational amplifier subunit (OP) provided in an embodiment of this application.

[0022] Figure 12 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application.

[0023] Figure 13 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application.

[0024] Figure 14 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application.

[0025] Figure 15 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application.

[0026] Figure 16 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application.

[0027] Figure 17 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application.

[0028] Figure 18 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application.

[0029] Figure 19 This paper illustrates another schematic diagram of the operational amplifier subunit (OP) provided in an embodiment of this application. Figure 20 A schematic diagram of the switching state of the operational amplifier subunit OP in calibration mode provided in an embodiment of this application is shown.

[0030] Figure 21 This paper illustrates the switching state of the operational amplifier subunit (OP) in the filtering mode provided in an embodiment of this application.

[0031] Figure 22 A flowchart of the frequency generation method provided in an embodiment of this application is shown.

[0032] Figure 23 A flowchart of a calibration mode and a filtering mode provided in an embodiment of this application is shown. Detailed Implementation

[0033] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0034] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0035] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0036] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0037] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0038] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0039] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0040] In the embodiments of this application, the first terminal / first end of each transistor is one of the source and the drain, and the second terminal / second end of each transistor is the other of the source and the drain. Since the source and drain of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first terminal / first end and the second terminal / second end of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal / first end is the source, and the second terminal / second end is the drain; for example, when the transistor is an N-type transistor, the first terminal / first end is the drain, and the second terminal / second end is the source.

[0041] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0042] A phase-locked loop (PLL) circuit is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a frequency signal. A loop filter is usually set in the PLL circuit for filtering.

[0043] For example, refer to Figure 1 , Figure 1 A schematic diagram of a loop filter in related technology is shown, in which the loop filter reduces the capacitance C through a resistor Ry and a unity-gain buffer. The offset voltage of the unity-gain buffer causes integral leakage. Figure 1 The offset voltage of the structure causes Vx and Vy to be unequal. The voltage difference generates a current that continuously interferes with the voltage across capacitor C, resulting in V... lpf The voltage changes continuously, which reduces the stability of the frequency signal output by the phase-locked loop circuit.

[0044] Therefore, this application provides a frequency generation circuit, a chip, and an electronic device, which will be described in detail below.

[0045] First, refer to Figure 2 , Figure 2A schematic diagram of a frequency generation circuit provided in an embodiment of this application is shown. The frequency generation circuit includes a comparison module 110, a voltage generation module 120, a gain filtering module 130, and an oscillation module 140.

[0046] The comparison module 110 is used to receive the reference clock signal CLK_REF and the feedback signal to generate the charge / discharge control signal Vc. Specifically, the comparison module 110 can compare the phase and frequency of the reference clock signal CLK_REF with the feedback signal to determine whether the phase and frequency of the feedback signal and the reference clock signal CLK_REF satisfy the corresponding relationship, and then output the charge / discharge control signal Vc. The feedback signal can refer to the target frequency signal CLK_T output by the oscillation module 140, that is, the comparison module 110 can directly compare the target frequency signal CLK_T with the reference clock signal CLK_REF to determine whether the frequency and phase of the target frequency signal CLK_T and the reference clock signal CLK_REF are locked.

[0047] For example, the comparison module 110 can be a frequency and phase detector, which determines whether the phase and frequency of the feedback signal and the reference clock signal CLK_REF satisfy the corresponding relationship by comparing the transition edges (falling edge and / or rising edge) of the reference clock signal CLK_REF and the feedback signal.

[0048] In some embodiments, refer to Figure 3 , Figure 3 The diagram shows another schematic of the frequency generation circuit provided in the embodiment of this application. The frequency generation circuit may also include a feedback module 150. The feedback module 150 may be a frequency divider. That is, the target frequency signal CLK_T output by the oscillation module 140 is first input to the feedback module 150 for frequency division and then outputs the frequency division signal CLK_NDIV. The frequency division signal CLK_NDIV is then input to the comparison module 110 as a feedback signal for comparison.

[0049] The voltage generation module 120 is used to receive the charge / discharge control signal Vc to generate the target voltage Vr. The voltage generation module 120 can control the magnitude of the target voltage Vr through the charge / discharge control signal Vc. For example, the voltage generation module 120 can be a charge pump.

[0050] The gain filtering module 130 is used to connect the calibration voltage Vca when in calibration mode to calibrate the offset voltage during gain, obtain the calibration status signal FL, and switch to the filtering mode when the calibration status signal FL indicates that the calibration is complete, to filter the target voltage Vr and obtain the filtered signal Vlpf.

[0051] For example, the gain filter module 130 can implement the filtering function using resistors and capacitors. Furthermore, the gain filter module 130 can employ a unity-gain buffer to reduce the capacitance value. Therefore, the gain filter module 130 will have an offset voltage during operation. The unity-gain buffer is a buffer with an output gain of 1. The gain filter module 130 can switch between calibration mode and filtering mode using a switch.

[0052] The calibration status signal FL can be output by a unity-gain buffer. The calibration status signal FL is used to indicate whether the calibration is complete. For example, the calibration status signal FL can indicate that the calibration is complete when it flips, and that the calibration is not complete when it remains unchanged.

[0053] The oscillation module 140 can change the oscillation frequency according to the filtered signal Vlpf, thereby changing the frequency of the target frequency signal CLK_T. For example, the oscillation module 140 may include a voltage-controlled oscillator (VCO), with the control terminal of the VCO connected to the filtered signal Vlpf. Under the control of the filtered signal Vlpf, the oscillation frequency of the VCO can be changed. Exemplarily, the VCO can be a capacitor-tuned VCO or an inductor-tuned VCO. It is understood that the oscillation module 140 of this application is not limited to a voltage-controlled oscillator, and the oscillation module 140 may also include other oscillation circuits that can change the oscillation frequency and output a clock signal, such as a crystal oscillator.

[0054] By introducing a calibration mode into the gain filter module 130, a calibration voltage Vca is applied when it is in calibration mode to calibrate the offset voltage during gain, resulting in a calibration status signal FL. The calibration status signal FL can intuitively indicate whether the calibration is complete. When the calibration status signal FL indicates that the calibration is complete, the error caused by the offset voltage can be suppressed, making the calibrated gain filter module 130 more stable. Therefore, when the gain filter module 130 switches to the filtering mode to filter the target voltage Vr, the phenomenon of integral leakage can be effectively reduced, thereby improving the stability of the target frequency signal CLK_T generated by the subsequent oscillation module 140.

[0055] In some embodiments, refer to Figure 4 , Figure 4 This illustration shows another schematic diagram of the frequency generation circuit provided in an embodiment of the present application. The gain filtering module 130 includes a gain filtering unit 131, a first signal selection unit 132, and a second signal selection unit 133.

[0056] The first signal selection unit 132 can select one of the target voltage Vr and the calibration voltage Vca for output according to the control signal, thereby controlling the gain filtering unit 131 to connect to either the target voltage Vr or the calibration voltage Vca. Similarly, the second signal selection unit 133 can select one of the filter signal Vlpf and the calibration status signal FL for output according to the control signal, thereby controlling the gain filtering module 130 to output either the filter signal Vlpf or the calibration status signal FL.

[0057] When the first signal selection unit 132 controls the gain filtering module 130 to connect the calibration voltage Vca, and the second signal selection unit 133 controls the gain filtering module 130 to output the calibration status signal FL, the gain filtering module 130 is in calibration mode. When the first signal selection unit 132 controls the gain filtering module 130 to connect to the target voltage Vr, and the second signal selection unit 133 controls the gain filtering module 130 to output the filtered signal Vlpf, the gain filtering module 130 is in filtering mode.

[0058] As can be seen, by setting the first signal selection unit 132 and the second signal selection unit 133, the gain filtering module 130 does not affect each other when it is in calibration mode and filtering mode, and does not affect the subsequent normal filtering process after offset voltage calibration, thereby improving the stability of the gain filtering module 130.

[0059] In some embodiments, the gain filtering unit 131 includes an operational amplifier subunit OP. In calibration mode, the operational amplifier subunit OP is converted to a comparator form to output a calibration status signal FL, thereby quickly calibrating the offset voltage based on the calibration voltage Vca. In filtering mode, the operational amplifier subunit OP is converted to a unity-gain buffer form to achieve unity gain, thereby reducing the capacitance value of the first capacitor C1.

[0060] In some embodiments, refer to Figure 5 , Figure 5 This illustration shows another schematic diagram of the frequency generation circuit provided in an embodiment of this application. The gain filtering unit 131 includes a first resistor R1, a second resistor R2, a first capacitor C1, an operational amplifier subunit OP, a first switch S1, a second switch S2, and a third switch S3. Exemplarily, the first switch S1, the second switch S2, and the third switch S3 can be transistors.

[0061] Specifically, the first end of the first resistor R1 is connected to the first end of the first signal selection unit 132 to receive the target voltage Vr, and the second end of the first resistor R1 is connected to the second end of the first signal selection unit 132 to receive the calibration voltage Vca; the first plate of the first capacitor C1 is connected to the second end of the first signal selection unit 132 and the first input terminal (i.e., the non-inverting input terminal) of the operational amplifier subunit OP, and the second plate of the first capacitor C1 is connected to the ground terminal; the first end of the first switch S1 is connected to the first input terminal of the operational amplifier subunit OP, and the second end of the first switch S1 is connected to the second input terminal (i.e., the inverting input terminal) of the operational amplifier subunit OP. Connections are made as follows: The first terminal of the second switch S2 is connected to the second input terminal of the operational amplifier subunit OP, and the second terminal of the second switch S2 is connected to the output terminal of the operational amplifier subunit OP and the first terminal of the second signal selection unit 133. The output terminal of the operational amplifier subunit OP is used to output the calibration status signal FL. The first terminal of the third switch S3 is connected to the output terminal of the operational amplifier subunit OP, and the second terminal of the third switch S3 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the first terminal of the first resistor R1 and the second terminal of the second signal selection unit 133. The second terminal of the second resistor R2 is used to output the filter signal Vlpf.

[0062] Specifically, the network consisting of the first resistor R1, the second resistor R2, the first capacitor C1, and the operational amplifier subunit OP can reduce the capacitance value of the first capacitor C1 while filtering. Furthermore, by setting the first switch S1, which is connected to the first and second input terminals of the operational amplifier subunit OP, and the second switch S2, which is connected to the second input and output terminals of the operational amplifier subunit OP, the operational amplifier subunit OP can transform into a comparator when the first switch S1 is on, the second switch S2 is off, and the third switch S3 is off, thereby quickly calibrating the offset voltage based on the calibration voltage Vca. When the first switch S1 is off, the second switch S2 is on, and the third switch S3 is on, negative feedback is formed between the second input and output terminals of the operational amplifier subunit OP, and the operational amplifier subunit OP can transform into a unity-gain buffer, reducing the capacitance value of the first capacitor C1.

[0063] It is understandable that when the operational amplifier subunit OP is converted into a comparator, offset voltage calibration can be performed by adjusting the voltage of the first input terminal and / or the second input terminal of the operational amplifier subunit OP according to the calibration voltage Vca, so that the voltage of the first input terminal and the second input terminal of the operational amplifier subunit OP are consistent, thus completing the offset voltage calibration.

[0064] As can be seen, by introducing the first switch S1, the second switch S2 and the third switch S3, the gain filter unit 131 can support both calibration mode and filtering mode based on a simple structural improvement.

[0065] In some embodiments, refer to Figure 6 , Figure 6 This illustration shows another schematic diagram of a frequency generation circuit provided in an embodiment of this application. The first signal selection unit 132 includes a fourth switch S4 and a fifth switch S5. Exemplarily, the fourth switch S4 and the fifth switch S5 can be transistors.

[0066] The first end of the fourth switch S4 is used to connect to the target voltage Vr, and the second end of the fourth switch S4 is connected to the first end of the first signal selection unit 132 as the first end of the first resistor R1; the first end of the fifth switch S5 is used to connect to the calibration voltage Vca, and the second end of the fifth switch S5 is connected to the second end of the first resistor R1 as the second end of the first signal selection unit 132.

[0067] Specifically, when the fourth switch S4 is on and the fifth switch S5 is off, the gain filter module 130 is connected to the target voltage Vr; when the fourth switch S4 is off and the fifth switch S5 is on, the gain filter module 130 is connected to the calibration voltage Vca. It can be seen that by setting the fourth switch S4 and the fifth switch S5 to control the gain filter module 130 to connect to either the target voltage Vr or the calibration voltage Vca, independent control of the connection of the target voltage Vr and the calibration voltage Vca is achieved, which has the advantages of simple structure and stability.

[0068] In some embodiments, refer to Figure 7 , Figure 7 This illustration shows another schematic diagram of a frequency generation circuit provided in an embodiment of this application. The second signal selection unit 133 includes a sixth switch S6 and a seventh switch S7. Exemplarily, the sixth switch S6 and the seventh switch S7 can be transistors.

[0069] Among them, the first end of the sixth switch S6 is connected to the output end of the operational amplifier subunit OP as the first end of the second signal selection unit 133, and the second end of the sixth switch S6 is used to output the calibration status signal FL; the first end of the seventh switch S7 is connected to the first end of the second resistor R2 as the second end of the second signal selection unit 133, and the second end of the seventh switch S7 is used to output the filter signal Vlpf.

[0070] Specifically, when the sixth switch S6 is on and the seventh switch S7 is off, the gain filter module 130 outputs a calibration status signal FL; when the sixth switch S6 is off and the seventh switch S7 is on, the gain filter module 130 outputs a filter signal Vlpf. It can be seen that by setting the sixth switch S6 and the seventh switch S7 to control the output of the calibration status signal FL or the filter signal Vlpf of the gain filter module 130 respectively, independent control of the output of the calibration status signal FL and the filter signal Vlpf is achieved, which has the advantages of simple structure and stability.

[0071] The working principle of the gain filtering module 130 in calibration mode and filtering mode in the embodiments of this application is described in detail below.

[0072] Reference Figure 8 , Figure 8 The diagram shows the switching state of the gain filter module 130 in calibration mode according to an embodiment of this application. When the first switch S1, the fifth switch S5 and the sixth switch S6 are turned on, and the second switch S2, the third switch S3, the fourth switch S4 and the seventh switch S7 are turned off, the gain filter module 130 is in calibration mode. At this time, the gain filter unit 131 is disconnected from the voltage generation module 120 and the oscillation module 140. The operational amplifier subunit OP is converted into a comparator, and the calibration voltage Vca is connected to calibrate the offset voltage. The calibration status signal FL is output at the second terminal of the sixth switch S6.

[0073] Reference Figure 9 , Figure 9 The diagram shows the switching state of the gain filtering module 130 in the filtering mode provided in this application embodiment. When the first switch S1, the fifth switch S5, and the sixth switch S6 are closed, and the second switch S2, the third switch S3, the fourth switch S4, and the seventh switch S7 are open, the gain filtering module 130 is in the filtering mode. At this time, the gain filtering unit 131 is connected to the voltage generation module 120 and the oscillation module 140, and the calibration voltage Vca is not connected. Filtering is performed through the first resistor R1 and the first capacitor C1 of the gain filtering unit 131. At the same time, the operational amplifier subunit OP is transformed into a unity-gain buffer (voltage follower) to realize the capacitance multiplication function, thereby reducing the capacitance value of the first capacitor C1.

[0074] In some embodiments, refer to Figure 10 , Figure 10 Another schematic diagram of the frequency generation circuit provided in the embodiment of this application is shown. The frequency generation circuit further includes a multi-level voltage output module 160, which is used to output a corresponding calibration voltage Vca according to the voltage of the filtered signal Vlpf.

[0075] For example, assuming the voltage of the filter signal Vlpf is 500mV, the output calibration voltage Vca can also be 500mV, or around 500mV, thereby improving the calibration effect.

[0076] Furthermore, the multi-level voltage output module 160 can output calibration voltages Vca of different magnitudes, thereby adapting to the voltage of the filter signal Vlpf in different application scenarios.

[0077] For example, the multi-level voltage output module 160 can use a resistor divider to output different levels of calibration voltage Vca. The number and value of the required resistors can be determined according to actual needs.

[0078] In some embodiments, refer to Figure 11 , Figure 11 The diagram shows a schematic of an operational amplifier subunit OP provided in an embodiment of this application. The operational amplifier subunit OP includes an input stage amplifier component 1110, a first current digital-to-analog converter component 1120, a second current digital-to-analog converter component 1130, an intermediate stage amplifier component 1140, and an output stage amplifier component 1150.

[0079] In this configuration, the first input terminal VINP of the input stage amplifier component 1110 serves as the first input terminal of the operational amplifier subunit OP; the first output terminal of the input stage amplifier component 1110 is connected to the first terminal of the second current digital-to-analog converter component 1130; the second input terminal VINN of the input stage amplifier component 1110 serves as the second input terminal of the operational amplifier subunit OP; the second output terminal of the input stage amplifier component 1110 is connected to the first terminal of the first current digital-to-analog converter component 1120; the second terminal of the first current digital-to-analog converter component 1120 is connected to the ground terminal; the second terminal of the second current digital-to-analog converter component 1130 is connected to the ground terminal; the first current... The digital-to-analog converter 1120 is used to receive the first calibration code value in calibration mode, and the second current digital-to-analog converter 1130 is used to receive the second calibration code value in calibration mode to calibrate the offset voltage; the first output terminal of the input stage amplifier 1110 is connected to the first input terminal of the intermediate stage amplifier 1140, the second output terminal of the input stage amplifier 1110 is connected to the second input terminal of the intermediate stage amplifier 1140, the output terminal of the intermediate stage amplifier 1140 is connected to the input terminal of the output stage amplifier 1150, and the output terminal OUT of the output stage amplifier 1150 serves as the output terminal of the operational amplifier subunit OP.

[0080] Specifically, after receiving the first calibration code value, the first current digital-to-analog converter 1120 can provide a corresponding bias current to the second input terminal of the operational amplifier subunit OP. When the bias current provided by the first current digital-to-analog converter 1120 is greater than 0, it is equivalent to increasing the voltage of the second input terminal of the operational amplifier subunit OP. Therefore, the voltage applied to the second input terminal of the operational amplifier subunit OP can be controlled by controlling the first calibration code value, so that the voltages of the first input terminal and the second input terminal of the operational amplifier subunit OP are consistent, that is, the offset voltage calibration is completed.

[0081] Similarly, after receiving the second calibration code value, the second current digital-to-analog converter 1130 can provide a corresponding bias current to the first input terminal of the operational amplifier subunit OP. When the bias current provided by the second current digital-to-analog converter 1130 is greater than 0, it is equivalent to increasing the voltage of the first input terminal of the operational amplifier subunit OP. Therefore, the voltage applied to the first input terminal of the operational amplifier subunit OP can be controlled by controlling the second calibration code value, so that the voltage of the first input terminal of the operational amplifier subunit OP is consistent with that of the second input terminal, that is, the offset voltage calibration is completed.

[0082] For example, the first current digital-to-analog converter 1120 can be a switching type current digital-to-analog converter, see reference. Figure 12 , Figure 12 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The first current digital-to-analog converter component 1120 includes a plurality of first current sources IB1 and a thirteenth switch S13 corresponding to each first current source IB1. The first ends of each thirteenth switch S13 are interconnected as the first end of the first current digital-to-analog converter component 1120, and the second ends of each thirteenth switch S13 are respectively connected to the first ends of the corresponding first current sources IB1. The second ends of each first current source IB1 are interconnected as the second end of the first current digital-to-analog converter component 1120.

[0083] Similarly, the second current digital-to-analog converter 1130 can also be a switching type current digital-to-analog converter, see reference. Figure 13 , Figure 13 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The second current digital-to-analog converter component 1130 includes a plurality of second current sources IB2 and a fourteenth switch S14 corresponding to each second current source IB2. The first terminals of each fourteenth switch S14 are interconnected as the first terminal of the second current digital-to-analog converter component 1130, and the second terminals of each fourteenth switch S14 are respectively connected to the first terminals of the corresponding second current sources IB2. The second terminals of each second current source IB2 are interconnected as the second terminal of the second current digital-to-analog converter component 1130.

[0084] In some embodiments, when the calibration status signal FL indicates that calibration is complete, the first current digital-to-analog converter 1120 locks the first calibration code value, the second current digital-to-analog converter 1130 locks the second calibration code value, and the gain filtering module 130 switches to the filtering mode. If the calibration status signal FL indicates that the calibration is not complete, the first current digital-to-analog converter 1120 continues to receive the adjusted first calibration code value, or the second current digital-to-analog converter 1130 continues to receive the adjusted second calibration code value, until the calibration status signal FL indicates that the calibration is complete.

[0085] by Figure 13 The circuit shown is used as an example for explanation. In calibration mode, calibration can be performed using a successive approximation method. In the initial stage, the first calibration code value can be an all-zero code value, corresponding to the connection of multiple first current sources IB1 (which can be achieved using inverters). For example, assuming that there are four thirteenth switches S13, the initial first calibration code value is 0000.

[0086] Accordingly, the second calibration code value is an all-one code value, corresponding to the complete shutdown of multiple second current sources IB2 (which can be achieved using an inverter). For example, assuming that there are four fourteenth switches S14, the initial second calibration code value is 1111.

[0087] At this initial stage, a significant additional voltage is applied to the second input terminal of the operational amplifier unit (OP). Since the OP is switched to comparator mode in calibration mode, its output is low. Next, by increasing the first calibration code value, multiple thirteenth switches S13 are sequentially turned off until all thirteenth switches S13 are closed. If the output of the OP still does not change from low to high, the second calibration code value is then decreased, and multiple fourteenth switches S14 are sequentially turned on until the output of the OP changes from low to high. This indicates that the voltage at the first input terminal and the voltage at the second input terminal of the OP are approaching consistency, signifying calibration completion. After calibration, locking the first and second calibration code values ​​allows switching to filtering mode.

[0088] Continuing with the example above, the first calibration code value after the initial adjustment can be 0001. If the output of the operational amplifier subunit (OP) changes from low to high at this time, the locked first calibration code value is 0001, and the second calibration code value is 1111. This pattern continues, and will not be elaborated further here.

[0089] In addition, when all the first current sources IB1 are connected in the initial stage, the first calibration code value can also be an all-one code value (in the case of not using an inverter). Correspondingly, the second calibration code value can also be an all-zero code value. In this case, the adjustment method of the first calibration code value during the calibration process is to decrease the first calibration code value, and the adjustment method of the second calibration code value is to increase the second calibration code value.

[0090] Understandably, the initial stage of the above calibration method involves adding a larger voltage to the second input terminal of the operational amplifier subunit OP. Alternatively, a larger voltage can be added to the first input terminal of the operational amplifier subunit OP in the initial stage. Correspondingly, the first calibration code value in the initial stage can also be an all-one value, corresponding to the complete shutdown of all first current sources IB1 (achieved using an inverter). For example, assuming there are four thirteenth switches S13, the first calibration code value in the initial stage would be 1111.

[0091] Accordingly, the second calibration code value can be an all-zero value, corresponding to the connection of multiple second current sources IB2 (which can be achieved using an inverter). For example, assuming that there are four fourteenth switches S14, the initial second calibration code value is 0000.

[0092] At this initial stage, a significant additional voltage is applied to the first input terminal of the operational amplifier unit (OP). Since the OP switches to comparator mode in calibration mode, its output is high. Next, by increasing the second calibration code value, multiple fourteenth switches S14 are sequentially turned off until all fourteenth switches S14 are closed. If the output of the OP still does not change from high to low, the first calibration code value is then decreased, and multiple thirteenth switches S13 are sequentially turned on until the output of the OP changes from high to low. This indicates that the voltage at the first input terminal and the voltage at the second input terminal of the OP are approaching consistency, signifying that calibration is complete.

[0093] Continuing with the example above, the second calibration code value after the initial adjustment can be 0001. If the output of the operational amplifier subunit OP changes from high to low at this time, the locked first calibration code value is 1111, and the second calibration code value is 0001. This pattern continues, and will not be elaborated further here.

[0094] In addition, when all the second current sources IB2 are connected in the initial stage, the second calibration code value can also be an all-one code value (in the case of not using an inverter). Correspondingly, the first calibration code value can also be an all-zero code value. In this case, the adjustment method of the second calibration code value during the calibration process is to decrease the second calibration code value, and the adjustment method of the first calibration code value is to increase the first calibration code value.

[0095] The above-mentioned calibration method, by adjusting the first calibration code value and the second calibration code value, can improve the precision of offset voltage calibration.

[0096] For example, refer to Figure 14 , Figure 14This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The input stage amplifier component 1110 includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. Exemplarily, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can all be PMOS transistors.

[0097] Among them, the first terminal of the fifth transistor M5 is connected to the power supply terminal VDD, the control terminal of the fifth transistor M5 is used to connect the bias voltage VBP, and the second terminal of the fifth transistor M5 is connected to the first terminal of the sixth transistor M6. The control terminal of the sixth transistor M6 serves as the first input terminal VINP (i.e., the first input terminal of the operational amplifier subunit OP) of the input stage amplifier component 1110. The first terminal of the sixth transistor M6 is connected to the first terminal of the seventh transistor M7. The second terminal of the sixth transistor M6 serves as the first output terminal of the input stage amplifier component 1110. The control terminal of the seventh transistor M7 serves as the second input terminal VINN (i.e., the second input terminal of the operational amplifier subunit OP) of the input stage amplifier component 1110, and the second terminal of the seventh transistor M7 serves as the second output terminal of the input stage amplifier component 1110.

[0098] For example, refer to Figure 15 , Figure 15 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The intermediate stage amplifier component 1140 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. Exemplarily, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, and the eleventh transistor M11 can be PMOS transistors, and the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 can be NMOS transistors.

[0099] The first terminal of the eighth transistor M8 is connected to the power supply terminal VDD and the first terminal of the ninth transistor M9. The control terminal of the eighth transistor M8 is connected to the control terminal of the ninth transistor M9. The second terminal of the eighth transistor M8 is connected to the first terminal of the tenth transistor M10. The control terminal of the eighth transistor M8 is used to apply the bias voltage VBP. The second terminal of the ninth transistor M9 is connected to the first terminal of the eleventh transistor M11. The control terminal of the tenth transistor M10 is connected to the control terminal of the eleventh transistor M11. The second terminal of the tenth transistor M10 is connected to the first terminal of the twelfth transistor M12. The control terminal of the tenth transistor M10 is used to apply the bias voltage VBPC. The second terminal of the eleventh transistor M11 is connected to the first terminal of the twelfth transistor M12. The first terminal of transistor 13 is connected to the ground terminal. The control terminal of transistor 12 is connected to the control terminal of transistor 13. The control terminal of transistor 12 is used to apply a bias voltage. The second terminal of transistor 12 is connected to the first terminal of transistor 14. The second terminal of transistor 13 is connected to the first terminal of transistor 15. The control terminal of transistor 14 is connected to the second terminal of transistor 10 and the control terminal of transistor 15. The second terminal of transistor 14 is connected to ground. The control terminal of transistor 14 is used to apply a bias voltage VBN. The second terminal of transistor 15 is connected to ground. The first terminal of transistor 15 serves as the first input terminal of intermediate stage amplifier component 1140. The first terminal of transistor 14 serves as the second input terminal of intermediate stage amplifier component 1140. The first terminal of transistor 13 serves as the output terminal of intermediate stage amplifier component 1140.

[0100] In some embodiments, refer to Figure 16 , Figure 16 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The output stage amplifier component 1150 includes a first amplification branch 1151 and a second amplification branch 1152.

[0101] The input terminal of the first amplification branch 1151 is used to connect to the output terminal of the intermediate stage amplification component 1140 in the filtering mode, and the output terminal of the first amplification branch 1151 is used as the output terminal OUT of the output stage amplification component 1150 in the filtering mode. The input terminal of the second amplification branch 1152 is used to connect to the output terminal of the intermediate stage amplification component 1140 in calibration mode, and the output terminal of the second amplification branch 1152 is used as the output terminal OUT of the output stage amplification component 1150 in filtering mode.

[0102] For example, one of the input terminals of the first amplification branch 1151 and the second amplification branch 1152 can be connected to the output terminal of the intermediate stage amplification component 1140 by a switch. Similarly, one of the output terminals of the first amplification branch 1151 and the second amplification branch 1152 can be used as the output terminal OUT of the output stage amplification component 1150 by a switch. By dividing the output stage amplification component 1150 into the independent first amplification branch 1151 and the second amplification branch 1152, it can output in calibration mode and filtering mode respectively, avoiding mutual interference when outputting in calibration mode and filtering mode, thereby improving the stability of calibration and filtering.

[0103] In some embodiments, refer to Figure 17 , Figure 17 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The first amplification branch 1151 includes a first transistor M1, a second transistor M2, an eighth switch S8, and a ninth switch S9.

[0104] In this circuit, the first terminal of the eighth switch S8 serves as the input terminal of the first amplification branch 1151, and the second terminal of the eighth switch S8 is connected to the control terminal of the first transistor M1. The first terminal of the first transistor M1 is connected to the second terminal of the second transistor M2, and the second terminal of the first transistor M1 is connected to the ground terminal. The control terminal of the second transistor M2 is used to connect the bias voltage VBP, the first terminal of the second transistor M2 is connected to the power supply terminal VDD, and the second terminal of the second transistor M2 is connected to the first terminal of the ninth switch S9. The second terminal of the ninth switch S9 serves as the output terminal of the first amplification branch 1151.

[0105] When the eighth switch S8 and the ninth switch S9 are turned on, the first amplification branch 1151 can be connected to the second resistor R2 for gain filtering. In addition, the first transistor M1 and the second transistor M2 act as output buffers, making the output of the operational amplifier subunit OP more stable.

[0106] In some embodiments, refer to Figure 18 , Figure 18 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The second amplification branch 1152 includes a third transistor M3, a fourth transistor M4, a tenth switch S10, an eleventh switch S11, and a twelfth switch S12.

[0107] In this circuit, the first terminal of the tenth switch S10 serves as the input terminal of the second amplification branch 1152, and the second terminal of the tenth switch S10 is connected to the control terminal of the third transistor M3; the first terminal of the eleventh switch S11 is connected to the second terminal of the tenth switch S10, and the second terminal of the eleventh switch S11 is connected to the ground terminal; the first terminal of the third transistor M3 is connected to the second terminal of the fourth transistor M4, and the second terminal of the third transistor M3 is connected to the ground terminal; the control terminal of the fourth transistor M4 is used to connect the bias voltage VBP, the first terminal of the fourth transistor M4 is connected to the power supply terminal VDD, and the second terminal of the fourth transistor M4 is connected to the first terminal of the twelfth switch S12; the second terminal of the twelfth switch S12 serves as the output terminal of the second amplification branch 1152.

[0108] When the tenth switch S10 and the twelfth switch S12 are turned on, and the eleventh switch S11 is turned off, the second amplification branch 1152 can output the calibration status signal FL. Furthermore, the third transistor M3 and the fourth transistor M4 act as output buffers, making the output of the operational amplifier subunit OP more stable. Also, by setting the eleventh switch S11, it can be turned on in filtering mode. When the eleventh switch S11 is turned on, the control terminal of the third transistor M3 is connected to the ground terminal, ensuring that the output of the intermediate stage amplification component 1140 does not affect the third transistor M3 in filtering mode. This improves the stability of the third transistor M3 and makes the calibration status signal FL more accurate.

[0109] In some embodiments, refer to Figure 19 , Figure 19 This illustration shows another schematic diagram of the operational amplifier subunit OP provided in an embodiment of this application. The operational amplifier subunit OP may also include a third resistor R3, a fifteenth switch S15, and a second capacitor C2.

[0110] Among them, the first end of the third resistor R3 is connected to the second end of the eleventh transistor M11, the second end of the third resistor R3 is connected to the first end of the fifteenth switch S15, the second end of the fifteenth switch S15 is connected to the first plate of the second capacitor C2, and the second plate of the second capacitor C2 is connected to the first end of the ninth switch S9.

[0111] When the fifteenth switch S15 is turned on, the third resistor R3 and the second capacitor C2 can realize the loop compensation function, which can improve the stability of the operational amplifier subunit OP when it is used as a unity-gain buffer.

[0112] In some embodiments, the size of the transistor in the second amplification branch 1152 is smaller than the size of the transistor in the first amplification branch 1151, which can improve the speed of the operational amplification subunit OP in calibration mode and shorten the calibration time.

[0113] The working principle of the operational amplifier subunit OP in calibration mode and filtering mode in the embodiments of this application is explained in detail below.

[0114] Reference Figure 20 , Figure 20 The diagram shows the switching state of the operational amplifier subunit OP in calibration mode provided in this application embodiment. When the eighth switch S8, the ninth switch S9, the eleventh switch S11 and the fifteenth switch S15 are closed, and the tenth switch S10 and the twelfth switch S12 are open, the first amplification branch 1151 is disconnected from the intermediate stage amplification component 1140, the second amplification branch 1152 is connected to the intermediate stage amplification component 1140, and finally the calibration status signal FL is output at the second end of the twelfth switch S12.

[0115] Reference Figure 21 , Figure 21 The diagram shows the switching state of the operational amplifier subunit OP in the filtering mode provided in this application embodiment. When the eighth switch S8, the ninth switch S9, the eleventh switch S11 and the fifteenth switch S15 are turned on, and the tenth switch S10 and the twelfth switch S12 are turned off, the first amplification branch 1151 is connected to the intermediate stage amplification component 1140, the second amplification branch 1152 is disconnected from the intermediate stage amplification component 1140, and the second terminal of the ninth switch S9 is connected to the first terminal of the second resistor R2 for gain filtering.

[0116] In some embodiments, refer to Figure 22 , Figure 22 A flowchart of a frequency generation method provided in an embodiment of this application is shown. Taking a frequency generation chip as the execution subject, the frequency generation method includes, but is not limited to, the following steps 2201 to 2203.

[0117] Step 2201: When it is detected that the offset voltage has not been calibrated, enter the calibration mode to calibrate the offset voltage and obtain the calibration status signal FL; Step 2202: When the calibration status signal FL indicates that the calibration is complete, switch to the filtering mode to filter the target voltage Vr and obtain the filtered signal Vlpf; Step 2203: Generate the target frequency signal CLK_T based on the filtered signal Vlpf.

[0118] For example, steps 2201 and 2202 can be performed by the gain filtering module 130, and step 2203 can be performed by the oscillation module 140. By simultaneously introducing calibration mode and filtering mode, the offset voltage is calibrated in calibration mode to obtain a calibration status signal FL. The calibration status signal FL can intuitively indicate whether the calibration is complete. When the calibration status signal FL indicates that the calibration is complete, the error caused by the offset voltage can be suppressed, resulting in higher working stability after calibration. Therefore, when switching to filtering mode to filter the target voltage Vr, the phenomenon of integral leakage can be effectively reduced, thereby improving the stability of the target frequency signal CLK_T generated by the subsequent oscillation module 140.

[0119] In some embodiments, the offset voltage is calibrated using a calibration code value. When switching to the filtering mode when the calibration status signal FL indicates that calibration is complete, specifically, when the calibration status signal FL indicates that calibration is complete, the calibration code value is locked and the filtering mode is switched; when the calibration status signal FL indicates that calibration is not complete, the calibration code value is adjusted until the calibration status signal FL indicates that calibration is complete.

[0120] Specifically, refer to Figure 23 , Figure 23 This document illustrates a flowchart of a calibration mode and a filtering mode provided in an embodiment of this application. In calibration mode, a control switch converts the operational amplifier subunit OP into a comparator form. Then, the calibration status signal FL is determined. If the calibration status signal FL indicates calibration is complete, the calibration code value is locked. The control switch then converts the operational amplifier subunit OP into a unity-gain buffer form and switches to filtering mode to filter the target voltage Vr. If the calibration status signal FL indicates calibration is incomplete, the calibration code value is adjusted, specifically by increasing or decreasing the calibration code value, until the calibration status signal FL indicates calibration is complete.

[0121] Furthermore, this application also provides a chip, wherein the chip includes the frequency generation circuit described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System-on-Chip (SoC) chip or a System-in-Package (SIP) chip. Since the chip of this application possesses the frequency generation circuit of the above embodiments, it has all the beneficial effects of the frequency generation circuit in the above embodiments, and will not be repeated here.

[0122] In addition, this application also provides an electronic device, which includes a device body and a frequency generating circuit or chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. Since the electronic device of this application possesses the frequency generating circuit or chip of the above embodiments, it has all the beneficial effects of the frequency generating circuit or chip in the above embodiments, which will not be repeated here.

[0123] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different beneficial effects.

[0124] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any indirect modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A frequency generation circuit, characterized in that, include: The comparison module is used to receive a reference clock signal and a feedback signal to generate a charge / discharge control signal; A voltage generation module, which is used to receive the charge / discharge control signal to generate a target voltage; A gain filtering module is used to connect a calibration voltage when in calibration mode to calibrate the offset voltage when gain is applied, thereby obtaining a calibration status signal. When the calibration status signal indicates that calibration is complete, the module switches to a filtering mode to filter the target voltage, thereby obtaining a filtered signal. An oscillation module is used to receive the filtered signal to generate a target frequency signal.

2. The frequency generating circuit according to claim 1, characterized in that, The gain filtering module includes a gain filtering unit, a first signal selection unit, and a second signal selection unit. The first signal selection unit is used to control the gain filtering unit to connect to either the target voltage or the calibration voltage. The second signal selection unit is used to control the gain filtering module to output either the filtered signal or the calibration status signal. When the first signal selection unit controls the gain filtering module to connect to the calibration voltage, and the second signal selection unit controls the gain filtering module to output the calibration status signal, the gain filtering module is in the calibration mode. When the first signal selection unit controls the gain filtering module to connect to the target voltage, and the second signal selection unit controls the gain filtering module to output the filtered signal, the gain filtering module is in the filtering mode.

3. The frequency generating circuit according to claim 2, characterized in that, The gain filtering unit includes an operational amplifier subunit. In the calibration mode, the operational amplifier subunit is converted into a comparator to output the calibration status signal. In the filtering mode, the operational amplifier subunit is converted into a unity-gain buffer to achieve unity gain.

4. The frequency generating circuit according to claim 2, characterized in that, The gain filtering unit includes a first resistor, a second resistor, a first capacitor, an operational amplifier subunit, a first switch, a second switch, and a third switch; The first end of the first resistor is connected to the first end of the first signal selection unit to receive the target voltage, and the second end of the first resistor is connected to the second end of the first signal selection unit to receive the calibration voltage. The first plate of the first capacitor is connected to the second terminal of the first signal selection unit and the first input terminal of the operational amplifier subunit, and the second plate of the first capacitor is connected to the ground terminal. The first end of the first switch is connected to the first input end of the operational amplifier subunit, and the second end of the first switch is connected to the second input end of the operational amplifier subunit; The first end of the second switch is connected to the second input end of the operational amplifier subunit, and the second end of the second switch is connected to the output end of the operational amplifier subunit and the first end of the second signal selection unit. The output end of the operational amplifier subunit is used to output the calibration status signal. The first terminal of the third switch is connected to the output terminal of the operational amplifier subunit, and the second terminal of the third switch is connected to the first terminal of the second resistor; The second end of the second resistor is connected to the first end of the first resistor and the second end of the second signal selection unit, and the second end of the second resistor is used to output the filtered signal.

5. The frequency generating circuit according to claim 4, characterized in that, The first signal selection unit includes a fourth switch and a fifth switch; The first end of the fourth switch is used to connect to the target voltage, and the second end of the fourth switch is connected to the first end of the first signal selection unit as the first end of the first resistor. The first end of the fifth switch is used to connect to the calibration voltage, and the second end of the fifth switch is connected to the second end of the first resistor as the second end of the first signal selection unit.

6. The frequency generating circuit according to claim 4, characterized in that, The second signal selection unit includes a sixth switch and a seventh switch; The first end of the sixth switch is connected to the output end of the operational amplifier subunit as the first end of the second signal selection unit, and the second end of the sixth switch is used to output the calibration status signal. The first terminal of the seventh switch is connected to the first terminal of the second resistor as the second terminal of the second signal selection unit, and the second terminal of the seventh switch is used to output the filtered target voltage.

7. The frequency generating circuit according to claim 4, characterized in that, The operational amplifier subunit includes an input stage amplifier component, a first current digital-to-analog converter component, a second current digital-to-analog converter component, an intermediate stage amplifier component, and an output stage amplifier component; The first input terminal of the input stage amplifier component serves as the first input terminal of the operational amplifier subunit, the first output terminal of the input stage amplifier component is connected to the first terminal of the first current digital-to-analog converter component, the second input terminal of the input stage amplifier component serves as the second input terminal of the operational amplifier subunit, and the second output terminal of the input stage amplifier component is connected to the first terminal of the second current digital-to-analog converter component. The second terminal of the first current digital-to-analog converter is connected to the ground terminal; The second terminal of the second current digital-to-analog converter is connected to the ground terminal; The first current digital-to-analog converter is used to receive a first calibration code value in the calibration mode, and the second current digital-to-analog converter is used to receive a second calibration code value in the calibration mode to calibrate the offset voltage. The first output terminal of the input stage amplifier is connected to the first input terminal of the intermediate stage amplifier, the second output terminal of the input stage amplifier is connected to the second input terminal of the intermediate stage amplifier, the output terminal of the intermediate stage amplifier is connected to the input terminal of the output stage amplifier, and the output terminal of the output stage amplifier serves as the output terminal of the operational amplifier subunit.

8. The frequency generating circuit according to claim 7, characterized in that: When the calibration status signal indicates that calibration is complete, the first current digital-to-analog converter locks the first calibration code value, the second current digital-to-analog converter locks the second calibration code value, and the gain filtering module switches to filtering mode. If the calibration status signal indicates that calibration is not complete, the first current digital-to-analog converter continues to receive the adjusted first calibration code value, or the second current digital-to-analog converter continues to receive the adjusted second calibration code value, until the calibration status signal indicates that calibration is complete.

9. The frequency generating circuit according to claim 7, characterized in that, The output stage amplification component includes a first amplification branch and a second amplification branch; The input terminal of the first amplification branch is used to connect to the output terminal of the intermediate stage amplification component in the filtering mode, and the output terminal of the first amplification branch is used as the output terminal of the output stage amplification component in the filtering mode. The input terminal of the second amplification branch is used to connect to the output terminal of the intermediate stage amplification component in the calibration mode, and the output terminal of the second amplification branch is used as the output terminal of the output stage amplification component in the filtering mode.

10. The frequency generating circuit according to claim 9, characterized in that, The size of the transistor in the second amplification branch is smaller than the size of the transistor in the first amplification branch.

11. A frequency generation method, characterized in that, include: When it is detected that the offset voltage has not been calibrated, the calibration mode is entered to calibrate the offset voltage and obtain a calibration status signal. When the calibration status signal indicates that calibration is complete, switch to filtering mode to filter the target voltage and obtain a filtered signal; The target frequency signal is generated based on the filtered signal.

12. The frequency generation method according to claim 11, characterized in that, The offset voltage is calibrated using a calibration code value, and the step of switching to filtering mode when the calibration status signal indicates that calibration is complete includes: When the calibration status signal indicates that calibration is complete, the calibration code value is locked and the system switches to filtering mode; If the calibration status signal indicates that calibration is not complete, adjust the calibration code value until the calibration status signal indicates that calibration is complete.

13. A chip, characterized in that, Includes the frequency generation circuit as described in any one of claims 1 to 10.

14. An electronic device, characterized in that, It includes a device body and a frequency generation circuit as described in any one of claims 1 to 10 disposed on the device body, or it includes a device body and a chip as described in claim 13 disposed on the device body.

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