Communication system of improved parallel cascade LDPC (Low Density Parity Check) code structure based on single encoder

Abstract

The invention discloses a communication system of an improved parallel cascade LDPC code structure based on a single encoder, and belongs to the technical field of aviation platform laser communication. Aiming at the bottlenecks that the traditional PCGC depends on double encoders, the hardware overhead is large, the decoding delay is high and the complementarity requirement on component codes is harsh, the system adopts a single encoder architecture design: firstly, a basic verification sequence is generated through a single LDPC encoder, and differential verification constraints are constructed through interleaving and repeating operations; meanwhile, a zero syndrome and non-zero syndrome dual-check sequence design is introduced, so that the minimum distance of a code word is increased; a decoding end fuses a normalized minimum sum algorithm and a hierarchical message updating and dynamic early stop mechanism, combines channel sensing soft information construction and a self-adaptive interleaving and redundancy allocation strategy, and adapts to composite channel characteristics of an aviation platform.

Description

Technical Field

[0001] This invention relates to the field of channel coding and error correction technology, and in particular to a low-complexity parallel cascaded LDPC construction system suitable for laser communication on airborne platforms (including the combined effects of turbulence, pointing error and atmospheric attenuation). Background Technology

[0002] Since the introduction of parallel concatenated Gallager codes in the 1990s, they have become an important coding scheme for long code length, high-reliability communication scenarios. By integrating the iterative Turbo coding concept with the sparse parity-checking characteristics of LDPC codes, they decompose the encoding and decoding complexity of long codes into low-complexity sub-module operations while maintaining information exchange between component decoders, effectively reducing decoding information loss. They are widely used in fields with stringent error correction performance requirements, such as laser communication on aerospace platforms and deep space transmission. The core advantage of PCGC lies in reducing the implementation complexity of long LDPC codes without significantly sacrificing error correction performance through parallel concatenation and cooperative decoding of multi-component codes, making it particularly suitable for communication systems that need to balance performance and resource consumption.

[0003] However, as the requirements for channel coding in scenarios such as laser communication on aviation platforms evolve towards "low complexity, high robustness, and resource efficiency," traditional PCGC schemes have gradually exposed a series of engineering application bottlenecks, making it difficult to adapt to the multiple interference characteristics of aviation composite channels and the SWaP (Size, Weight, Power) constraints of aviation payloads. The multi-encoder architecture in parallel concatenated Gallager codes requires the deployment of multiple independent LDPC encoders, resulting in long component code complementarity selection cycles, high hardware overhead, and difficulty in meeting miniaturization requirements. The nested decoding process suffers from high latency, extrinsic information is prone to confidence saturation, and iterative gain is insufficient. Based on the AWGN channel assumption, it cannot adapt to combined aviation interference, and error layering is easily observed under high signal-to-noise ratios. Furthermore, the multi-component architecture incurs high storage and computational overhead, leading to low hardware resource utilization. These issues make it difficult to balance performance and complexity, necessitating an improved solution that integrates single encoders and channel-aware strategies to overcome these bottlenecks. Summary of the Invention

[0004] To address the engineering application bottlenecks of traditional parallel concatenated LDPC (PCGC) schemes, such as multi-encoder dependency, high hardware overhead, high decoding latency, poor adaptability to complex time-varying channels, and low hardware implementation efficiency, this application proposes a communication system based on an improved parallel concatenated LDPC code structure with a single encoder. This system combines a single-encoder architecture, differentiated parallel check sequence construction, hierarchical low-complexity decoding, and channel-aware soft-information correction, supplemented by closed-loop simulation optimization and engineering output. This achieves a coordinated optimization of complexity, latency, and robustness without significantly sacrificing error correction performance, making it suitable for high-reliability communication scenarios with limited resources and time-varying channels, such as laser communication on aerospace platforms and UAV swarms. Specifically, it includes: S1. Single encoder verification sequence generation module; S2. A multi-path transformation module for at least two transformations of the basic parity sequence to generate a dual parity sequence; S3. Parallel concatenation and substream scheduling transmission module for dual-verification sequences; S4. The receiver integrates hierarchical iterative decoding with a low-complexity approximation algorithm, and the channel-aware LLR scaling correction and closed-loop simulation optimization module. S5. Control unit module that performs hierarchical iterative scheduling, early stop determination and feedback management.

[0005] The preferred implementation details for each module are given below to support the claims and reflect feasibility and engineering considerations.

[0006] Preferably, S1 includes: S1.1 Single Encoder Selection and Interface: A single high-error-correction-performance encoder is used as the source of verification information. This encoder can be any commonly used LDPC encoder or equivalent error-correction encoder, implemented as a reusable hardware or software module, and provides standardized frame / metadata interfaces (such as frame ID, transform strategy ID, priority flag, etc.) to support subsequent transformation and alignment.

[0007] S1.2 Output Format and Synchronization: The basic parity sequence is output in a frame / subframe format that is easy to transform and align, with the necessary synchronization information and transform identifier (or transform seed) attached to the frame so that the receiver can correctly reverse process or utilize the transform metadata during decoding.

[0008] S1.3 Engineering considerations: The single encoder implementation should support pipeline / multiplexing mode to balance throughput and resource consumption; the encoded output should provide optional error detection fields (such as CRC) for the receiver to quickly determine frame synchronization and integrity.

[0009] Preferably, S2 includes: S2.1 Interleaving Transformation: Pseudo-random or segmented deterministic interleaving is performed on the basic parity sequence to break up low-weight error concentrations; the interleaver supports configurable depth and runtime switching, and the interleaving strategy can be specified by the sender in the frame header or the seed can be pre-negotiated between the two parties.

[0010] S2.2 Repetition and Differentiated Coverage: Apply limited repetition (e.g., 1–2 times) or selective enhancement to critical information segments to form redundant protection for important bit segments. The repeated positions can be remapped in different substreams to disperse the impact of errors.

[0011] S2.3 Bit / Byte Level Remapping and Permutation: Bit or byte level permutation and remapping are performed on the parity bits to change the distribution of the parity bits in the substream, thereby enhancing the minimum distance and low-weight error propagation capabilities; the transformation information is reliably transmitted to the receiving end through metadata or negotiation seed.

[0012] S2.4 Double-check sequence classification: Based on the purpose of differentiation, the transformed sequence is divided into types such as "zero corrector" (covering all information bits) and "non-zero corrector" (focusing on highly sensitive information segments) so that different processing strategies or different confidence levels can be applied in decoding.

[0013] Preferably, S3 includes: S3.1 Substream concatenation and multiplexing strategy: The dual-check sequence is concatenated in parallel into multiple transmission substreams, and resources are allocated according to time multiplexing, frequency multiplexing or time-frequency joint scheme; the scheduler supports redundancy trade-offs under substream priority and bandwidth constraints.

[0014] S3.2 Scheduling Decision and Feedback Interaction: The scheduler can dynamically adjust the allocation of substream resources based on static priority or channel quality indications fed back by the receiver (such as requests to increase redundancy); in scenarios without feedback, a preset adaptive strategy can be adopted to take into account real-time performance.

[0015] S3.3 Alignment and Timing Marking: To ensure that the receiver correctly merges substreams and performs layered decoding, each substream is accompanied by a timestamp, frame ID, and transform description or seed to support asynchronous arrival and reordering processing.

[0016] Preferably, S4 includes: S4.1 Low-complexity approximate decoding algorithm: NMS or its variants (such as Offset-NMS, threshold reduction NMS) are used in the inner iteration to significantly reduce the computational load of the check node; the normalization factor is dynamically adjusted according to the channel estimation during runtime to balance convergence and numerical stability.

[0017] S4.2 Hierarchical Message Update and Storage Optimization: The parity check matrix is ​​divided into sub-blocks and message updates are performed in block order or priority to reduce parallel access conflicts and bus bandwidth pressure; in the hardware implementation, local cache (BRAM) and fixed-point quantization are used to reduce resource consumption.

[0018] S4.3 Channel-aware soft information construction: The receiver estimates channel quality indicators (such as instantaneous gain, scintillation index, pointing error statistics, etc.) in real time and uses them as driving factors for LLR scaling and bias mapping to improve the confidence matching of soft inputs.

[0019] S4.4 Scale correction is implemented by using linear lookup tables or polynomial fitting to obtain and map the data, or by using nonlinear mapping (such as sigmoid type) to limit extreme values; the mapping table can be calibrated through offline simulation and fine-tuned during operation.

[0020] S4.5 Closed-loop simulation and parameter optimization: Simulation is carried out based on the target channel model, and closed-loop optimization is performed on key indicators (such as BER / FER, average number of iterations, decoding delay). If the preset target is not met, the interleaving / repetition strategy, normalization factor or early stopping threshold is adjusted and the simulation is repeated until the target is met.

[0021] Preferably, S5 includes: S5.1 Layered Iterative Framework: The layered decoding process adopts "inner layer (within sub-stream) local iteration + outer layer (between sub-streams) global interactive iteration". The inner layer first removes obvious errors within the sub-stream, and the outer layer performs joint correction after aggregating cross-sub-stream information to improve convergence speed and reduce overall latency.

[0022] S5.2 Dynamic Iterative Control and Early Stopping: Design local and global early stopping criteria (e.g., several consecutive local checksums are zero, error change is below a threshold, no continuous improvement in the outer layer) and set minimum / maximum iteration constraints to achieve an engineering trade-off between error performance and decoding delay.

[0023] S5.3 Statistical Recording and Online Adaptation: Records statistics such as BER, average number of iterations, and frame delay during runtime, and implements long-term adaptive parameter adjustment based on statistical results and feedback channels to cope with long-term channel changes.

[0024] Preferred examples of performance verification and engineering results (used to illustrate creativity and beneficial effects). To verify the technical effects of this invention, the traditional multi-encoder PCGC scheme and the present invention scheme can be compared in simulation and prototype testing. Preferred verification indicators include BER / FER, average (super) iterations, decoding delay, etc. Exemplary engineering effects (as an explanation of preferred implementation effects, not limiting values) include: under the target signal-to-noise ratio condition, the bit error rate is significantly reduced, the average number of super iterations is greatly reduced and accompanied by a reduction in hardware resource consumption, thereby demonstrating the synergistic advantages of single encoder architecture and channel-aware hierarchical decoding.

[0025] This invention achieves the following beneficial effects by combining single encoder and double check sequence construction, hierarchical low-complexity decoding, and channel-aware LLR correction with closed-loop optimization: (1) Significantly reduces the complexity of the encoding end and overall hardware implementation and simplifies system integration; (2) By using inner and outer layer collaborative iteration and dynamic early stopping, the average number of iterations and decoding delay are significantly reduced, thereby enhancing real-time performance and energy efficiency; (3) Improve the robustness and emergency recovery capability of composite time-varying channels through channel-aware soft information correction and adaptive interleaving / redundancy strategies; (4) The solution is engineering-friendly, with configurable parameters, easy to implement on FPGA / ASIC platforms, and supports multi-mode operation and expansion to different code length / code rate scenarios.

[0026] This application achieves synergistic optimization of the PCGC scheme in terms of performance, complexity, and robustness through the integration of a single encoder architecture and a channel-aware strategy. First, the single encoder + dual-check sequence design completely eliminates the dependence of traditional PCGC on multiple encoders, combined with interleaving and repetitive operations. Second, the integration of the NMS algorithm, hierarchical updates, and dynamic early stopping. Third, the construction of channel-aware soft information and adaptive strategies significantly improve the robustness of the scheme under complex channels in aviation platforms, effectively addressing the coupled interference of turbulence, attenuation, and pointing errors. Simultaneously, the single encoder architecture supports efficient hardware implementation, meeting the miniaturization and low-power consumption requirements of aviation platforms. Furthermore, the scheme possesses good scalability, adapting to different code lengths and code rates through parameter adjustments, making it suitable for resource-constrained, high-reliability communication applications such as laser communication in aviation platforms and UAV swarm coordination. Attached Figure Description

[0027] Figure 1 This is a diagram of the PCGC conventional encoder and concatenated codeword structure in an embodiment of this application; Figure 2 This is a PCGC conventional decoder as described in this application embodiment; Figure 3 This is a structural diagram of a single encoder PCGC with concatenated codewords and an encoder, according to an embodiment of this application. Figure 4This is a PCGC decoder with a single encoder, as described in an embodiment of this application. Figure 5 This is a diagram of an improved PCGC structure using concatenated codewords and an encoder, as described in an embodiment of this application. Figure 6 This is a comparison chart of the error performance of conventional PCGC and improved PCGC in embodiments of this application; Figure 7 This is a comparison chart of the complexity of conventional PCGC and improved PCGC in an embodiment of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0029] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] 1. Regular PCGC Parallel Concatenated Galager Codes (PCGC) are a type of concatenated code. They allow two LDPC encoders to be concatenated in parallel without the need for an interleaver between them. (Appendix) Figure 1 This demonstrates a traditional PCGC with a concatenated codeword and encoder structure. The idea behind developing PCGC is to incorporate the principle of Turbo Coding into LDPC codes. In long LDPC codes, the complexity of decoding and encoding is divided into steps of lower complexity. Simultaneously, information flow between decoding components is maintained, reducing information loss during decoding steps. Component codes are selected based on the average column weight (MCW) of the parity check matrix. MCW is the average column weight across all columns in the parity check matrix. It has been found that performance can be improved by selecting a low MCW code as the first component code and a high MCW code as the second component code.

[0031] The decoding process of PCGC is very similar to that of Turbo code decoding, with no interleaving between decoding components. A traditional PCGC decoder is shown in the attached image. Figure 2As shown. During decoding, each component of the LDPC decoder uses an improved sum-product algorithm to calculate the posterior probability. LDPC code decoding is an iterative process in which information is exchanged between decoder components. An LDPC decoder component performs the sum-product algorithm within a complete cycle, which is called local iteration. Any information passed between decoder components must be iterated by the decoder component, a process called super iteration. The information exchange process between decoder components remains unchanged until both decoders converge to valid codewords. In the latter case, the output of the second component decoder is declared as the best estimate of the transmission sequence.

[0032] Traditional PCGC systems have been reported to have several limitations. In each decoder component after performing a fixed number of local iterations, the reliability of the system message bits, i.e., the log-likelihood ratio, is increased, making it difficult to correct the maximum number of errors for the next decoder component. Therefore, the coding gain provided by code concatenation cannot be achieved. Furthermore, local iterations are performed by one decoder component while other decoder components remain idle. Information exchange can occur after a fixed number of local iterations. Therefore, there is significant latency in conventional PCGC decoding. Selecting component codes with different MCWs requires an "extensive computer search." Therefore, the effectiveness of this scheme largely depends on the complementary behavior of the individual LDPC codes.

[0033] 1.1 PCGC Structure Studies have shown that randomly constructed LDPC codes can achieve excellent bit error rate performance with large block lengths. However, in hardware implementation, the storage space required to represent the non-zero elements of the random matrix becomes more challenging. A simpler implementation is provided for encoding and decoding structured LDPC codes. The effectiveness of the LDPC code decoding algorithm is characterized by a parameter called the perimeter, which modulates the number of independent iterations. In the Tanner graph, the shortest cycle length is the parity check matrix or perimeter of the LDPC code. Since iterative decoding affects the exchange of external information, the performance of the LDPC decoder degrades in the Tanner graph due to short cycles with low perimeters. Therefore, the design of large perimeter LDPC codes has received considerable attention. A structured LDPC code construction system is developed, with the main goal of maintaining a high perimeter during LDPC code design. Based on graphical models and Cayley graphs, the performance of half-rate, two structured, and parallel concatenated LDPC codes is evaluated. Performance is obtained through a well-structured process of two concatenated LDPC codes and compared with two randomly generated LDPC components of the same length in a traditional PCGC. This system is less attractive for long block lengths because the SNR value that the parallel concatenated codes surpass increases with the length of each code. Therefore, it can be concluded that this system is only a very good choice for short block lengths and high signal-to-noise ratios. Furthermore, it can replace a single LDPC code of the same length.

[0034] 2. Improve PCGC A composite channel model for laser communication on airborne platforms is presented, which simultaneously incorporates multiplicative turbulence, visibility-based atmospheric attenuation (Kim), instantaneous power shift due to pointing errors, and additive Gaussian noise at the receiver. Key characteristics of this type of composite channel include: rapid time-varying channel gain, heavy-tailed and strongly correlated bit error statistics, and frequent short-duration bursts of large block errors. Traditional parallel cascaded LDPC schemes are mostly based on independent identically distributed (IOD) or AWGN assumptions in their design and analysis, and usually rely on fixed interleaving and static decoding scheduling. They have obvious shortcomings in the following aspects: First, they are sensitive to multiplicative deep fading and long-tailed distribution. Conventional AWGN-based channel LLR approximation will produce confidence mismatch, leading to misdirected message transmission. Second, in the case of burst errors caused by pointing jitter or obstruction, if the interleaving depth is limited, it is difficult for external parallel subcodes to effectively share and correct concentrated errors, resulting in local error accumulation and high retransmission rate. Third, for error floors in high SNR intervals, traditional PCGC may still have residual errors that are difficult to eliminate due to structural correlation and low-weight events. Fourth, simplifications made to pursue low complexity (such as extreme sub-decoding approximations, fixed puncturing strategies, or single scheduling) have poor performance robustness in non-stationary composite channels, making it difficult to achieve the optimal trade-off between performance and complexity under the constraints of SWaP in actual airborne payloads.

[0035] To address the aforementioned issues, this section proposes an improved PCGC, which makes targeted enhancements to the structure and decoding strategy to improve robustness and engineering feasibility in composite channels. The main advantages include: First, channel-aware soft information construction and scale normalization—integrating instantaneous gain estimation, scintillation index (SI), and pointing error statistics into LLR calculation and posterior scale correction significantly reduces the adverse effects of LLR mismatch on BP / parallel decoding; Second, adaptive interleaving and redundancy allocation—dynamically adjusting the interleaving depth based on real-time channel quality (turbulence intensity, pointing jitter variance, visibility). The improvements include: 1) Redundancy allocation between degrees and subcodes to achieve an online trade-off between latency and error correction capability; 2) Low-complexity joint / cooperative decoding scheduling—emphasizing layered / windowed decoding, early stopping mechanisms, and more refined soft information reconstruction (e.g., path metric → LLR reconstruction or probability weighting) for key sub-decoders, improving error recovery capability while maintaining low latency and energy consumption; 3) Error level suppression and burst recovery capability—reducing the contribution of low-weight events to the overall FER through information complementarity and interleaving diffusion between parallel subcodes, and faster recovery after short-term blockage or instantaneous power drops, reducing HARQ retransmission requirements. In summary, the improved PCGC aims to achieve stronger robustness and better system-level performance for composite channels on aviation platforms without significantly increasing hardware resources and latency, through improvements in channel awareness, parameter adaptation, and decoding coordination.

[0036] 2.1 Single Encoder PCGC In a single encoder PCGC, only single-component LDPC codes with MCW > 2.5 are used. Message bits corresponding to the same parity bit are transmitted twice. (Appendix) Figure 3 A single encoder PCGC structure consisting of a codeword and an encoder cascaded is shown. In this structure, the encoding complexity is significantly reduced and much smaller compared to other parallel cascade techniques.

[0037] Appendix Figure 4 The diagram illustrates PCGC decoding with a single encoder. On one side of the decoding process, the two component decoders are connected in parallel via check nodes called interconnect check nodes. Each interconnect check node corresponds to a parity check equation in the corresponding parity check matrix, and if a specific bit of each component decoder relates to the corresponding parity check equation, an edge connects the interconnect check node to the bit node of each component decoder. In the first step of the super iteration, the two component decoders independently and simultaneously perform a local iteration of the iterative decoding, where intrinsic information from the bit node is passed to the check node of the corresponding decoder, and the bit node is updated based on extrinsic information from the check node.

[0038] Next, in the next step of the decoder component, each bit is first updated using the intrinsic information of the decoder component (i.e., the corrected likelihood ratio). Similarly, in the decoder component, each bit is updated using the intrinsic information of the first decoder component. This process continues until one of the decoders converges to a valid codeword, or the maximum number of super-iterations is reached.

[0039] 2.2 Improved PCGC System Implementation 2.2.1 Improve PCGC system modules S1 module: Single encoder generates basic check sequence In this approach, the transmitting end uses a single LDPC encoder to generate a basic parity sequence (hereinafter referred to as the "basic sequence") to ensure the standardization and reusability of the encoder hardware / software implementation. The input consists of a bitstream of information frames (or corresponding soft inputs) and control signals (frame boundaries, priority flags, etc.), while the output consists of standardized codewords and parity bits (soft bit representations can be output simultaneously). To support subsequent transformations and correct alignment at the receiving end, the basic sequence should be encapsulated into a frame format at the transmitting end. The frame header should contain at least the following metadata fields: Frame ID (16 bits), timestamp or sequence number (Seq, 32 bits), transform / interleaving identifier (TransformID, 8 bits), interleaving seed (InterleaverSeed, 16 bits, optional), operating mode (Mode, 2 bits, e.g., high throughput / low latency / ultra-robust), priority (Priority, 2 bits), and parity / CRC (CRC16). The encoder implementation can employ pipelined or partially parallelized matrix operations (G·u) and allows the exposure of encoding delays and codeword boundary signals so that the transformation module can perform frame-by-frame alignment. After generating the basic sequence, the transmitter passes the sequence to the multiplexing module and fills the frame header with a transform identifier or seed so that the receiver can perform the reverse transform.

[0040] S2 module: At least two-way transformation of the basic parity sequence → generation of double parity sequence The transmitting end generates two sets of parity sequences (called zero-correction and non-zero-correction) from the basic sequence through at least two different transformations, for parallel concatenated transmission. The transformation can be a preprocessing of the information bits before encoding or a post-processing of the parity bits after encoding. Formally, let the basic parity vector be... Then the two sets of outputs can be expressed as in A reversible or identifiable transformation (modulo-2 linear transformation or position mapping) defined for the sender. The sender identifies this transformation in the frame header as TransformID / InterleaverSeed. The specific parameters or mapping table number should be provided so that the receiving end can interpret them correctly.

[0041] S3 Module: Scheduling and Transmission of Parallel Cascaded Substreams The sending end will and The data is concatenated into several substreams and transmitted according to a scheduling strategy (time multiplexing, frequency multiplexing, or a combination of both). The scheduler selects the transmission strategy based on frame priority, link bandwidth, and receiver feedback. Typical scheduling logic is as follows: key frames (high priority) can be... Allocate to more reliable subcarriers or earlier transmission time slots; dynamically reduce repetition rate or postpone transmission when bandwidth is limited. Part of it is used to ensure basic throughput.

[0042] S4 Receiver Module: Layered Iterative Decoding Process (Implementation Details) The receiver employs a layered iterative decoding architecture: first, local iterations are performed on each substream in the inner layer (using NMS or its variants to reduce computational load), and then the soft information of each substream is fused and joint correction is performed across substreams by a global coordination unit in the outer layer. The receiver processing flow should include: frame header parsing → restoring mapping / deinterleaving by TransformID → generating LLR vectors corresponding to substreams → inner-layer local iteration (InnerIter) → deriving substream messages → global fusion and outer-layer iteration (OuterIter) → early stop detection and output.

[0043] In the inner iteration, the Normalized Minimum Sum (NMS) approximation is used, and the check node update adopts the minimum / second smallest absolute value method multiplied by a dynamic normalization factor. To avoid due to Shaking Dramatic changes, it is recommended to Perform exponential smoothing: Among the suggestions Use values ​​of 0.05–0.2 (typical value 0.1).

[0044] S4 Receiver Module: Hierarchical Updates, Parallel Collision Mitigation, and Scale Correction The receiver needs to estimate the instantaneous channel quality in real time. The LLR scaling and correction parameters are adjusted accordingly. An engineering-based estimation system and mapping example are provided below to clearly support this as a preferred embodiment in the specification.

[0045] 1) Estimate Pilot-based estimation: If the frame contains pilot symbols Instantaneous SNR (linear scale) is calculated using received pilot energy and noise estimation: in The pilot window size, This is for noise power estimation.

[0046] Sliding window energy estimation (blind / semi-blind): In pilot-free scenarios, the received signal energy is estimated using a sliding window and the noise baseline is subtracted. .

[0047] Scintillation index (SI) estimation: used to quantify turbulence intensity, defined as... (I represents the received light intensity), which can be used in conjunction with SNR for decision-making.

[0048] Pointing error statistics: The receiver can estimate the angular offset variance. And used as an auxiliary indicator.

[0049] LLR correction formula (linear form): This is a scaling function (usually > 0) used to adjust the LLR amplitude.

[0050] This is the bias function used to correct the system offset.

[0051] 3) Smoothing and Quantization Quantization to 8-bit fixed point Quantize to 8 bits or lower precision. To avoid extreme... This leads to instability, and the output of the mapping function should be limited to the range [0.6, 1.2].

[0052] S5 Module: Early Stop Criteria, Output and Closed-Loop Control This invention employs a multi-level early stopping strategy and triggers redundancy enhancement when the channel deteriorates. The following provides a clear and directly implementable quantization threshold and decision logic.

[0053] 1) Localized early stop (within sub-current) If a certain sub-decoding unit is in continuous If all checksums in the next inner iteration are zero, then the sub-decoding unit is marked as converged. Or if continuous... In the next inner iteration, the average LLR change (average absolute increment) is below the threshold. If this occurs, it is considered a local convergence and triggers a local early stop.

[0054] 2) Global (outer layer) early stop If at the end of an outer iteration, the proportion of converged subcurrents to the total number of subcurrents... Greater than the threshold And the number of outer iterations is no less than If the condition is met, then global convergence is determined and iteration stops.

[0055] If continuous The outermost iteration did not significantly improve the frame error rate (FER) (e.g., the reduction in the number of outermost error frames was less than...). If ), then a global early stop will be triggered.

[0056] 3) Redundancy-enhanced triggering (fast response and slow feedback) like If the threshold is suddenly exceeded within a short time window, or if the SI increases beyond the threshold, the receiver performs local rapid enhancement: temporarily increasing the soft information confidence processing strategy (e.g., increasing the weight of substream B, extending the iteration count to the upper limit), and sending a redundancy request (containing suggested interleaving depth / repetition rate) in the background through the feedback channel. The feedback channel periodically / on-demand announces the operating mode switching request between the receiver and the transmitter (this feedback is not real-time and is subject to latency limitations; the transmitter should perform adjustments in subsequent frames based on the receiver's suggestions).

[0057] The improved PCGC process implemented according to the above modules is as follows: The transmitting end generates the basic sequence through a single LDPC encoder and specifies the transform parameters in the frame header. After two (or more) lightweight transforms, a double-checked substream is generated and concatenated for transmission; the receiving end parses the frame header to recover the transform and uses the NMS approximation algorithm and a layered decoding structure based on... The LLR correction is fused and decoded; the early stop criterion and redundancy enhancement strategy ensure low-latency termination under good channel conditions and improve recovery capability under sudden fading.

[0058] 2.2.2 Improved PCGC Structure In the improved parallel cascaded LDPC (PCGC) structure described in this invention, two different sets of parity bits (i.e., two types of check sequences) are sent for the same information block. One set of check sequences satisfies the so-called "zero corrector" criterion, and the other set satisfies the so-called "non-zero corrector" criterion. Preferably, the transmitting end uses only a single LDPC encoder to encode the information bits and output the basic check sequence; then, two complementary check sequences are constructed by performing different preprocessing or postprocessing transformations on the encoder output or encoder input, thus eliminating the need to deploy multiple independent encoders at the transmitting end. The preprocessing or postprocessing transformations include, but are not limited to: inserting predefined bits (e.g., fixed "1" or other control characters) at the beginning of the message block before encoding, performing subset selection / permutation on the check bits output by the encoder, modulo-2 linear combination, pseudo-random or segmented deterministic interleaving, bit / byte-level remapping, selective repetition or hole punching of key information segments, and any combination of the above systems. The two sets of check sequences obtained after the above transformation differ in their positional distribution or linear relationship, and can therefore be used to implement overall constraints covering all information bits (zero corrector) and enhanced protection for sensitive information segments (non-zero corrector), respectively. The transmitting end carries the identifier or seed of the transformation used (or a pre-agreed transformation table and version number) in the frame header of each frame, so that the receiving end can recover the corresponding mapping relationship during decoding or directly apply the transformation relationship during the soft information fusion stage. Since both sets of checks originate from the output of the same encoder and are generated only through lightweight linear or permutation transformations, the core operators of the decoder at the receiving end (such as hierarchical iterative structures and approximation algorithms like Normalized Minimum and NMS) do not require substantial modification; the decoder only maps or weights the checks from different substreams according to the known transformation relationship during the input processing and global message fusion stages. Therefore, by carefully designing a check transformation to select linearly independent check vectors that differ significantly in the Hamming space, the effective minimum distance of substream combinations can be improved without increasing the core complexity of the decoder, thereby improving the bit error rate under the same resource conditions (see the simulation section of this manual for relevant simulations and examples). A schematic diagram of the improved codeword and encoder connection is attached. Figure 5 As shown.

[0059] In the improved PCGC structure of this invention, the decoder adopts a soft-decision-based message passing system (preferably Normalized Minimum and NMS or its numerically stable variants), without using any hard-decision bit-flipping strategies. Decoding uses a "super-iteration" as the loop unit, with each super-iteration comprising three steps: First, performing an inner-layer NMS local iteration on substreams satisfying the zero-correction criterion; second, performing an inner-layer NMS local iteration on substreams satisfying the non-zero-correction criterion (if the transmitter has interleaved or cyclically shifted the second path, the receiver must first perform an inverse mapping according to the TransformID / Seed in the frame header to align the system order); third, mapping back and aggregating the heterodyne information output from each substream according to the transformation rules, and then applying channel-aware scale correction and damping coefficients. Weighted summation is performed to update the prior LLR of each variable node. Completing these three steps constitutes one super iteration. This process is repeated until any subflow is successfully identified through its parity check matrix (syndrome all zeros), or the preset maximum number of super iterations is reached, or a global early stop is triggered (e.g., no significant improvement in the number of erroneous frames after m consecutive outer layer iterations or a change in the global average LLR below a threshold). For stability in engineering implementation, the aforementioned inner / outer layer iteration limits, early stop threshold, and damping parameters are configurable preferred parameters. Specific recommended values ​​are given in the embodiments for reproduction.

[0060] 3. Simulation Verification The error rate performance and average number of iterations (complexity) of conventional PCGC and improved PCGC are compared as shown in the appendix. Figure 6 and 7 As shown.

[0061] Using PEG-LDPC (N=1024, R=1 / 2, average column weight wc=3) as a benchmark, a comparison was made between conventional PCGC and improved PCGC (single encoder repetition + fixed information bit interleaving + component decoding using normalized minimum sum NMS + external information damping and feedback). Simulation results show that the improved PCGC achieves a stable improvement in bit error rate in the waterfall region (approximately 2.0–3.5dB). For example, at 2.5dB, the BER of the conventional / improved PCGC is 9.20 × 10⁻⁶. −2 With 3.17×10 −2 After the improvement, the bit error rate was reduced to 34% of the original (a reduction of approximately 66%, equivalent to a performance improvement of approximately 2.9 times); at 3.0dB, it decreased from 4.73×10 −3 Reduced to 2.34×10 −3 It decreased to 49% of its original value (a reduction of approximately 51%, equivalent to an improvement of approximately 2 times); at 3.5 dB, it decreased from 1.03 × 10⁻⁶. −4 Reduced to 2.23×10 −5This represents a decrease to 22% of the original bit error rate (a reduction of approximately 78%, equivalent to an improvement of approximately 4.6 times). Overall, the typical reduction in the cascade region is "the bit error rate becomes 20%–50% of its original value," which can be roughly considered a reduction of 2–4 times, with a typical value of approximately 3 times. For BER=10... −5 The SNR gain in the vicinity is estimated by linear interpolation of the logarithmic BER with respect to Eb / N0 at the nearest neighbor point: the conventional scheme requires approximately 3.77dB in this BER, while the improved scheme requires approximately 3.59dB. Therefore, the improved scheme brings an SNR gain of approximately 0.18–0.20dB in this bit error rate range (estimated value, based on two-point interpolation, which fluctuates slightly with codebook and randomness).

[0062] In terms of complexity, due to the adoption of NMS (the computational power of a single local iteration is lower than that of SPA) and the introduction of precise early stopping based on the relative change of external LLR, the average number of super iterations in the waterfall region of the improved model is significantly reduced (approaching 1 as SNR increases), thereby significantly reducing the total computational power per bit (ops-per-info-bit) and energy consumption.

[0063] In summary, the improved PCGC achieves a net benefit of "reduced bit error rate + reduced complexity" in composite channels on aviation platforms, and significantly reduces the hardware implementation complexity at the transmitter, making it suitable for resource-constrained scenarios.

[0064] The embodiments described above are merely preferred embodiments of this application and are not intended to limit the scope of this application. Any modifications and improvements made by those skilled in the art to the technical solutions of this application without departing from the spirit of this application should fall within the protection scope defined by the claims of this application.

Claims

1. A communication system based on a single-encoder improved parallel concatenated LDPC code structure, characterized by include: S1. Single encoder module, used to encode the input information bits and output the basic check sequence; S2. A multi-path transformation module, coupled to the single encoder module, is used to apply at least two-path transformations to the basic verification sequence to generate a double verification sequence. The transformations include, but are not limited to, interleaving, repetition, bit / byte remapping, or modulo 2 linear combination. S3. Substream scheduling and transmission module, used to concatenate the dual-verification sequences in parallel into several transmission substreams and send them to the channel according to a predetermined scheduling strategy; S4. Receiver module, including: several parallel sub-decoding units, a global coordination unit and a channel estimation module; wherein: each parallel sub-decoding unit receives the LLR of the substream in systematic order and performs local inner-layer iteration; The global coordination unit is used to collect heterodyne information from each parallel sub-decoding unit, reflect back and fuse the heterodyne information according to the inverse mapping rule of the transformation, perform scale correction and confidence recalibration on the LLR according to the receiver channel estimation, and update the prior of the variable nodes according to the damping coefficient; the channel estimation module is used to estimate the instantaneous channel quality in real time and provide driving parameters to the global coordination unit. S5. Control unit module, used to perform hierarchical iterative scheduling, early stop determination and feedback management; the control unit terminates decoding and outputs decoded data according to the early stop criterion or when the maximum number of iterations is reached.

2. The communication system of claim 1, wherein the improved parallel concatenated LDPC code structure based on a single encoder is characterized by The interleaver described in S2 is a pseudo-random or segmented deterministic interleaver, and the interleaving depth is adaptively adjusted within a first to a second range according to the estimated channel quality.

3. The communication system based on the improved parallel concatenated LDPC code structure with a single encoder as described in claim 1 or 2, characterized in that, The normalization factor described in S4 varies in the range of 0.6-1.2 and is updated according to the instantaneous signal-to-noise ratio or channel quality index using continuous or segmented rules.

4. The communication system based on the improved parallel concatenated LDPC code structure with a single encoder as described in claim 1, characterized in that, The hierarchical iteration in S4 includes inner-layer local iteration and outer-layer global coordination iteration. The inner-layer iteration is completed first to reduce latency, while the outer-layer iteration is used for cross-substream error correction information fusion.

5. The communication system of claim 1, wherein the improved parallel concatenated LDPC code structure based on a single encoder is characterized by The LLR scaling correction described in S4 takes the form of: wherein With are scaling and bias functions computed based on instantaneous channel estimates respectively.

6. The communication system based on the improved parallel concatenated LDPC code structure with a single encoder as described in claim 1, characterized in that, When a sudden bit error or a sharp decline in channel quality is detected, a redundancy enhancement mechanism is triggered, which increases substream repetition or adjusts interleaving parameters according to a preset strategy.

7. The communication system based on the improved parallel concatenated LDPC code structure using a single encoder as described in claim 1, characterized in that, The early stopping criterion includes either "no improvement after m consecutive outer layer iterations" or "the number of erroneous frames reaches n", where m and n are positive integers.

8. The communication system of claim 1, wherein the improved parallel concatenated LDPC code structure based on a single encoder is characterized by The NMS algorithm in S4 uses minimum value substitution and approximation, and incorporates threshold reduction during message update to reduce numerical overflow and computational complexity.

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