Semiconductor element with protruding contact and preparation method thereof

Abstract

The invention provides a semiconductor element with a protruding contact and a preparation method thereof. The semiconductor element comprises a substrate; a bit line structure on the substrate; a capacitor contact structure beside the bit line structure; and a landing pad covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 916,364 (i.e., priority date "October 15, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor element and a method for fabricating the same. In particular, it relates to a semiconductor element having a protruding contact and a method for fabricating the semiconductor element having the protruding contact. Background Technology

[0003] Semiconductor components are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. To meet the ever-increasing demand for computing power, the size of semiconductor components continues to shrink. However, the risks associated with this shrinkage are becoming more frequent and have a greater impact. Therefore, improving quality, yield, performance, and reliability while reducing complexity remains a challenge.

[0004] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0005] One embodiment of this disclosure provides a semiconductor device including a substrate; a shallow trench isolation (STI) structure disposed in the substrate; a capacitor contact structure protruding from the substrate; and a landing pad covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure. The substrate includes a lower semiconductor layer; an upper semiconductor layer disposed above the lower semiconductor layer; and a buried insulating layer disposed between the upper semiconductor layer and the lower semiconductor layer.

[0006] In some embodiments, the shallow trench isolation (STI) structure penetrates the upper semiconductor layer and the buried insulating layer and extends into the lower semiconductor layer.

[0007] In some embodiments, the shallow trench isolation (STI) structure includes a first pad disposed in the substrate; a second pad disposed above the first pad; a third pad disposed above the second pad; and a trench filler layer disposed above the third pad and spaced apart from the second pad by the third pad.

[0008] In some embodiments, the first pad includes a first portion and a second portion covering opposite sidewalls of the embedded insulating layer; and a third portion separating the second pad from the lower semiconductor layer.

[0009] In some embodiments, the first part, the second part, and the third part are spaced apart from each other.

[0010] In some embodiments, the first pad, the second pad, and the third pad comprise different materials.

[0011] In some embodiments, the lower semiconductor layer and the upper semiconductor layer comprise silicon, and the buried insulating layer comprises nitride.

[0012] In some embodiments, the capacitor contact structure includes a pad layer disposed on and extending into the substrate; a capacitor conductive structure disposed above and surrounded by the pad layer; and a spacer structure surrounding the capacitor conductive structure and spaced apart from it by the pad layer.

[0013] In some embodiments, a lower surface of the solder pad is lower than an upper surface of the substrate, and the lower surface of the solder pad is higher than a lower surface of the embedded insulating layer.

[0014] In some embodiments, the angle between one sidewall of the solder pad and the lower surface of the solder pad is greater than 90 degrees.

[0015] In some embodiments, the capacitor conductive structure extends into the substrate and has a tapered profile.

[0016] In some embodiments, the capacitor conductive structure includes a barrier layer conformally disposed above and surrounded by the pad layer; a metal layer disposed above and surrounded by the barrier layer; and a metal filler portion disposed above and surrounded by the metal layer.

[0017] In some embodiments, the metal filler portion has an upper width and a lower width, wherein the upper width is greater than the lower width.

[0018] In some embodiments, the gap substructure includes an L-shaped pad and a porous low-k dielectric layer disposed above the L-shaped pad.

[0019] In some embodiments, the porous low-k dielectric layer is surrounded by the pad layer and the L-shaped pad.

[0020] Another embodiment of this disclosure provides a semiconductor device including a substrate in which a plurality of shallow trench isolation (STI) structures are disposed; a capacitor contact structure disposed in the substrate and protruding from the substrate; a bit line structure disposed on the substrate and adjacent to the capacitor contact structure; a bit line contact member disposed below the bit line structure; and a landing pad covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0021] In some embodiments, the substrate includes a lower semiconductor layer; an upper semiconductor layer disposed above the lower semiconductor layer; and a buried insulating layer disposed between the upper semiconductor layer and the lower semiconductor layer.

[0022] In some embodiments, the shallow trench isolation (STI) structure defines an active region in which a plurality of source / drain regions are disposed.

[0023] In some embodiments, the shallow trench isolation (STI) structure penetrates the upper semiconductor layer and the buried insulating layer and extends into the lower semiconductor layer.

[0024] In some embodiments, the shallow trench isolation (STI) structure includes a first pad disposed in the substrate; a second pad disposed above the first pad; a third pad disposed above the second pad; and a trench filler layer disposed above the third pad and spaced apart from the second pad by the third pad.

[0025] In some embodiments, the first pad includes a first portion and a second portion covering opposite sidewalls of the embedded insulating layer; and a third portion separating the second pad from the lower semiconductor layer.

[0026] In some embodiments, the first part, the second part, and the third part are spaced apart from each other.

[0027] In some embodiments, the first pad, the second pad, and the third pad comprise different materials.

[0028] In some embodiments, the capacitor contact structure includes a pad layer disposed on the substrate and extending into the substrate; a capacitor conductive structure disposed above and surrounded by the pad layer; and a spacer substructure surrounding the capacitor conductive structure and spaced apart from the capacitor conductive structure by the pad layer.

[0029] In some embodiments, a lower surface of the solder pad layer is lower than an upper surface of the substrate, wherein the lower surface of the solder pad layer is higher than a lower surface of the embedded insulating layer.

[0030] In some embodiments, the capacitor conductive structure extends into the substrate and has a tapered profile.

[0031] In some embodiments, the capacitor conductive structure includes a barrier layer conformally disposed above and surrounded by the pad layer; a metal layer disposed above and surrounded by the barrier layer; and a metal filler portion disposed above and surrounded by the metal layer.

[0032] In some embodiments, the metal filler portion has an upper width and a lower width, wherein the upper width is greater than the lower width.

[0033] In some embodiments, the gap substructure includes an L-shaped pad and a porous low-k dielectric layer disposed above the L-shaped pad.

[0034] In some embodiments, the porous low-k dielectric layer is surrounded by the pad layer and the L-shaped pad.

[0035] In some embodiments, an upper surface of the bit line structure is located at a vertical bit plane, which is lower than a vertical bit plane of an upper surface of the capacitor contact structure.

[0036] In some embodiments, the semiconductor element further includes a bit line spacer disposed between the capacitor contact structure and the bit line structure.

[0037] In some embodiments, an upper surface of the bit line gap sublayer is substantially coplanar with the upper surface of the bit line structure.

[0038] In some embodiments, the bitline structure includes a bitline under-conductive layer disposed on the substrate; a bitline intermediate conductive layer disposed on the bitline under-conductive layer; a bitline above-conductive layer disposed on the bitline intermediate conductive layer; and a bitline cover layer disposed on the bitline above-conductive layer.

[0039] In some embodiments, an upper surface of the bit line contact is substantially coplanar with an upper surface of the substrate.

[0040] Another embodiment of this disclosure provides a method for fabricating a semiconductor element, including providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing an upper surface of the bit line structure; and forming a landing pad layer covering a portion of the upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0041] In some embodiments, forming the bitline structure includes forming a bitline under conductive layer on the substrate; forming a bitline intermediate conductive layer on the bitline under conductive layer; forming a bitline above conductive layer on the bitline intermediate conductive layer; and forming a bitline capping layer on the bitline above conductive layer.

[0042] In some embodiments, forming the capacitor contact structure includes forming a spacer substructure on the substrate; forming a pad layer on the substrate and extending into the substrate, wherein the pad layer is surrounded by the spacer substructure; and forming a capacitor conductive structure above and surrounded by the pad layer, wherein the capacitor conductive structure includes a barrier layer conformally disposed above and surrounded by the pad layer; a metal layer disposed above and surrounded by the barrier layer; and a metal filler portion disposed above and surrounded by the metal layer.

[0043] In some embodiments, the fabrication method further includes forming a bit line spacer between the capacitor contact structure and the bit line structure, wherein an upper surface of the bit line spacer layer is substantially coplanar with the upper surface of the bit line structure.

[0044] In some embodiments, the fabrication method further includes forming a bit line contact below the bit line structure.

[0045] In some embodiments, the fabrication method further includes forming source / drain regions beneath the bit line contact and the capacitor contact structure.

[0046] In some embodiments, the preparation method further includes forming a shallow trench isolation (STI) structure in the substrate.

[0047] In some embodiments, forming the shallow trench isolation (STI) structure includes forming a first pad in the substrate; forming a second pad disposed on the first pad; forming a third pad disposed above the second pad; and forming a trench filler layer disposed above the third pad, wherein the trench filler layer is separated from the second pad by the third pad.

[0048] Due to the design of the semiconductor device disclosed herein, a contact surface between a landing pad layer and a capacitor contact structure can be increased. Therefore, the resistance between the landing pad layer and the capacitor contact structure can be reduced. As a result, the power consumption of the semiconductor device can be reduced. Furthermore, the protruding capacitor contact structure can provide sufficient support for the landing pad layer.

[0049] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0050] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with element numbers in the drawings, which represent similar elements throughout the description.

[0051] Figure 1 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0052] Figure 2 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0053] Figure 3 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 2 The cross section along the midline A-A'.

[0054] Figure 4 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 2 The cross section along the midline B-B'.

[0055] Figure 5 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0056] Figure 6 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 5 The cross section along the midline B-B'.

[0057] Figure 7 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0058] Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 7 The cross section along the midline B-B'.

[0059] Figure 9 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0060] Figure 10 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 9 The cross section along the midline A-A'.

[0061] Figure 11 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 9 The cross section along the midline B-B'.

[0062] Figure 12 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0063] Figure 13 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 12 The cross section along the midline A-A'.

[0064] Figure 14 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 12 The cross section along the midline B-B'.

[0065] Figure 15 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 12 The cross section along the midline A-A'.

[0066] Figure 16 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 12 The cross section along the midline B-B'.

[0067] Figure 17 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0068] Figure 18 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 17 The cross section along the midline A-A'.

[0069] Figure 19 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 17 The cross section along the midline B-B'.

[0070] Figure 20 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 17 The cross section along the midline A-A'.

[0071] Figure 21 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 17 The cross section along the midline B-B'.

[0072] Figure 22 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0073] Figure 23 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 22 The cross section along the midline A-A'.

[0074] Figure 24 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 22 The cross section along the midline B-B'.

[0075] Figure 25This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 22 The cross section along the midline A-A'.

[0076] Figure 26 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 22 The cross section along the midline B-B'.

[0077] Figure 27 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 22 The cross section along the midline A-A'.

[0078] Figure 28 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure.

[0079] Figure 29 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 28 The cross section along the midline A-A'.

[0080] Figures 30 to 36 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 12 The section A-A' in the diagram represents a part of the process for manufacturing semiconductor devices.

[0081] Figures 37 to 44 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 17 The section A-A' in the diagram represents a part of the process for manufacturing semiconductor devices.

[0082] Figures 45 to 48 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 17 The section A-A' in the diagram represents a part of the process for manufacturing semiconductor devices.

[0083] The reference numerals in the attached figures are explained as follows:

[0084] 1A: Semiconductor components

[0085] 1B: Semiconductor components

[0086] 1C: Semiconductor components

[0087] 1D: Semiconductor components

[0088] 1E: Semiconductor components

[0089] 1F: Semiconductor components

[0090] 1G: Semiconductor components

[0091] 10: Preparation method

[0092] 101: Base

[0093] 101-1: Lower semiconductor layer

[0094] 101-3: Embedding the insulation layer

[0095] 101-5: Upper semiconductor layer

[0096] 103: Isolation layer

[0097] 105: Active Region (Silicon Layer)

[0098] 107-1: Source Region

[0099] 107-3: Drain region

[0100] 109: First dielectric layer

[0101] 109TS: Top surface

[0102] 123: First solder pad

[0103] 123a: Part

[0104] 123b: Part

[0105] 123c: Part

[0106] 125: Second solder pad

[0107] 127: Third solder pad

[0108] 129: Trench filling layer

[0109] 150a: Shallow Trench Isolation (STI) Structure

[0110] 201: Character Line Structure

[0111] 203: Character line dielectric layer

[0112] 205: Conductive layer below the character line

[0113] 207: Conductive layer on character lines

[0114] 209: Character Line Overlay

[0115] 301: Bitline Structure

[0116] 303: Conductive layer below the bit line

[0117] 305: Intermediate conductive layer of bit line

[0118] 307: Conductive layer on bit line

[0119] 309: Bit line capping layer

[0120] 309TS: Top surface

[0121] 311: Bit line contact

[0122] 311BS: Lower surface

[0123] 313: Bit line gap

[0124] 313BS: Lower surface

[0125] 313TS: Top surface

[0126] 315: Sacrificing a Gap

[0127] 317: Adjustment Layer

[0128] 317SW: Sidewall

[0129] 317TS: Top surface

[0130] 323': L-shaped solder pad

[0131] 325: Porous low-k dielectric layer

[0132] 327: Spacer Structure

[0133] 333: Weld pad layer

[0134] 335: Barrier Layer

[0135] 337: Metallic layer

[0136] 339: Metal filler portion

[0137] 341: Conductive structure of capacitor

[0138] 401: Capacitor contact structure

[0139] 401P1: Partial

[0140] 401P2: Upper part

[0141] 401SW: Sidewall

[0142] 401TS: Top surface

[0143] 403: Conductive layer under capacitor contact

[0144] 403BS: Lower surface

[0145] 403SW: Sidewall

[0146] 403TS: Top surface

[0147] 405: Intermediate conductive layer of capacitor contact

[0148] 407: Conductive layer on capacitor contact

[0149] 407SW: Sidewall

[0150] 407TS: Top surface

[0151] 501: Landing cushion layer

[0152] 601: Insulation Structure

[0153] 603: First insulating layer

[0154] 603B: Bottom

[0155] 603S: Side

[0156] 605: Second insulating layer

[0157] 607: Air gap

[0158] 701: Character line structure groove

[0159] 703: Capacitor contact opening

[0160] 705: First trench

[0161] 801: First conductive material

[0162] 803: Second conductive material

[0163] 805: First insulating material

[0164] 807: Second Insulation Material

[0165] 809: Third conductive material

[0166] 811: The Fourth Conductive Material

[0167] B1: Lower surface

[0168] B2: Lower surface

[0169] D1: First Direction

[0170] S1: Sidewall

[0171] S2: Sidewall

[0172] S7: Sidewall

[0173] S8: Sidewall

[0174] S11: Steps

[0175] S13: Steps

[0176] S15: Steps

[0177] S17: Steps

[0178] S19: Steps

[0179] S21: Steps

[0180] S23: Steps

[0181] T1: Upper surface

[0182] T2: Upper surface

[0183] W1: Top width

[0184] W2: Bottom width

[0185] X: First axis

[0186] Y: Second axis

[0187] Z: Axis

[0188] θ1: Angle

[0189] θ2: Angle Detailed Implementation

[0190] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0191] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass not only the orientations shown in the figures but also different orientations of the elements during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0192] It should be understood that when a component is referred to as "connected to" or "coupled to" another component, the initial component may be directly connected to or coupled to the other component or other intermediate components.

[0193] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0194] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0195] In this disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the scope of semiconductor devices.

[0196] It should be understood that in the description of this disclosure, "above" corresponds to the direction of the Z-direction arrow, while "below" corresponds to the opposite direction of the Z-direction arrow.

[0197] Figure 1 This is a flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to some embodiments of this disclosure. Figure 2 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 3 and Figure 4 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 2 Partial process of manufacturing semiconductor device 1A using the center section lines A-A' and B-B'.

[0198] Please refer to Figures 1 to 4 In step S11, a substrate 101 is provided, and an isolation layer 103 may be formed in the substrate 101, which may define a plurality of active regions 105.

[0199] Please refer to Figures 2 to 4 The substrate 101 may include organic semiconductors or layered semiconductors, such as silicon / silicon-germanium, silicon-on-insulator, or silicon-germanium-on-insulator. When the substrate 101 includes silicon-on-insulator, the substrate 101 may include an upper semiconductor layer and a lower semiconductor layer comprising silicon, and a buried insulating layer that can separate the upper semiconductor layer from the lower semiconductor layer. For example, the buried insulating layer may include crystalline oxides, amorphous oxides, nitrides, or combinations thereof.

[0200] Please refer to Figures 2 to 4 An insulating layer 103 may be formed in the substrate 101. In some embodiments, an upper surface of the insulating layer 103 may be substantially coplanar with an upper surface of the substrate 101. For example, the insulating layer 103 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a fluorine-doped silicate. It should be understood that silicon oxynitride in this disclosure refers to a substance containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance containing silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0201] Please refer to Figures 2 to 4 An isolation layer 103 may surround a portion of the substrate 101. The surrounded portion of the substrate 101 may be referred to as an active region 105. From a top view, the active region 105 may be strip-shaped. Each active region 105 may extend along a first direction D1. The active regions 105 may be arranged along a first axis X and a second axis Y. The active regions 105 may be spaced apart from each other in the first direction D1. The first axis X and the second axis Y are perpendicular to each other. The first direction D1 may be inclined relative to the first axis X and the second axis Y.

[0202] Figure 5 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 6 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 5 Partial process of manufacturing semiconductor device 1A by mid-section line B-B'. Figure 7 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 7 Partial process of manufacturing semiconductor device 1A by mid-section line B-B'.

[0203] Please refer to Figure 1 as well as Figures 5 to 8In step S13, multiple character line structures 201 can be formed in the substrate 101.

[0204] Please refer to Figure 5 and Figure 6 Multiple character line structure trenches 701 can be formed in the substrate 101. From a top view, the character line structure trenches 701 can extend along a first axis X and are parallel to each other. The character line structure trenches 701 can be arranged along a second axis Y. Each active region 105 can intersect with two character line structure trenches 701. In some embodiments, two character line structure trenches 701 can divide a corresponding active region 105 into three segments. In some embodiments, from a cross-sectional view, the lower surface of the character line structure trenches 701 can be flat. In some embodiments, during the fabrication of the semiconductor device 1A, the lower surface of the character line structure trenches 701 can be rounded to reduce defect density and electric field concentration. The rounded lower surface can reduce the corner effect of the character line structure trenches 701.

[0205] It should be noted that in this disclosure, the term "segment" may be used interchangeably with the term "part".

[0206] Please refer to Figure 7 and Figure 8 Multiple character line dielectric layers 203 can be conformally formed in the character line structure trench 701. The character line dielectric layer 203 may have a U-shaped cross-sectional profile. In some embodiments, the fabrication technique of the character line dielectric layer 203 may include a thermal oxidation process. For example, the fabrication technique of the character line dielectric layer 203 may include oxidizing the lower surface and sidewalls of the character line structure trench 701.

[0207] In some embodiments, the fabrication technique for the word line dielectric layer 203 may include a deposition process, such as chemical vapor deposition or atomic layer deposition. The word line dielectric layer 203 may include a high-k material, an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), or a combination thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may, for example, be hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, for example, the high-k material may be lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, aluminum oxide, or a combination thereof.

[0208] Please refer to Figure 7 and Figure 8 Multiple conductive layers 205 below the character line can be formed on the character line dielectric layer 203 and in the character line structure trench 701, respectively. In some embodiments, multiple conductive layers 207 above the character line can be formed on the conductive layers 205 below the character line and in the character line structure trench 701, respectively. Figure 8As shown, the upper surface of the conductive layer 207 on the character line can be located in a vertical plane, which is lower than a vertical plane of the upper surface of the substrate 101.

[0209] For example, the conductive layer 205 below the character line may include polysilicon, polysilicon germanium, polysilicon germanium, the like, or combinations thereof. In some embodiments, the conductive layer 205 below the character line may be doped with dopants such as phosphorus, arsenic, antimony, or boron. For example, the conductive layer 207 above the character line may include tungsten, aluminum, titanium, copper, titanium nitride, the like, or combinations thereof.

[0210] Please refer to Figure 7 and Figure 8 Multiple character line cover layers 209 may be formed on the character line conductive layer 207. In some embodiments, the upper surface of the character line cover layer 209 may be substantially coplanar with the upper surface of the substrate 101. For example, the character line cover layer 209 may include silicon oxide, silicon nitride, silicon oxynitride, other semiconductor oxides, other semiconductor nitrides, or combinations thereof.

[0211] Please refer to Figure 7 and Figure 8 The character line dielectric layer 203, the character line lower conductive layer 205, the character line upper conductive layer 207, and the character line capping layer 209 together form the character line structure 201. From a top view, the character line structures 201 can extend along a first axis X and are parallel to each other. The character line structures 201 can be arranged along a second axis Y. Each active region 105 can intersect with two character line structures 201.

[0212] Please refer to Figure 7 and Figure 8 An implantation process can be performed on substrate 101. From a cross-sectional view, after the implantation process, source / drain regions 107-1 and 107-3 can be formed in the upper part of active region 105 (for ease of understanding, source region 107-1 and drain region 107-3 are used as examples). From a top view, for each active region 105, source region 107-1 can be formed between two word line structures 201 intersecting with active region 105. Drain region 107-3 can be formed at both ends of active region 105. Source / drain regions 107-1 and 107-3 can be doped with dopants such as phosphorus, arsenic, antimony, or boron.

[0213] Figure 9 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 10 and Figure 11 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 9 Partial process of manufacturing semiconductor device 1A with cross-sections A-A' and B-B'. Figure 12This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 13 and Figure 14 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 12 Partial process of manufacturing semiconductor device 1A with cross-sections A-A' and B-B'. Figure 15 and Figure 16 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 12 Partial process of manufacturing semiconductor device 1A with cross-sections A-A' and B-B'.

[0214] Please refer to Figure 1 and Figures 9 to 16 In step S15, a plurality of bit line contacts 311 may be formed in the substrate 101, and a plurality of bit line structures 301 and a plurality of bit line spacers 313 may be formed on the substrate 101.

[0215] Please refer to Figures 9 to 11 Bit line contacts 311 may be formed in the source region 107-1. In some embodiments, an upper surface of the bit line contact 311 may be substantially coplanar with the upper surface of the substrate 101. For example, the bit line contact 311 may include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The bit line contact 311 may be electrically connected to the source region 107-1.

[0216] Please refer to Figures 12 to 14 A series of deposition processes can be sequentially performed to deposit a bottom-line conductive layer 303, a middle-line conductive layer 305, a top-line conductive layer 307, and a top-line capping layer 309 on the substrate 101. Subsequently, a photolithography process and an etching process can be used to pattern the above layers. These patterned layers can collectively form the bitline structure 301.

[0217] From the cross-sectional view, the bitline structure 301 can be formed on the bitline contact 311. In some embodiments, an upper surface 309TS of the bitline cover layer 309 can be considered as an upper surface of the bitline structure 301. In some embodiments, such as Figure 13 As shown, a portion of the bitline contact 311 can be removed during the etching process. From a top view, the bitline structures 301 can extend along the second axis Y and can be parallel to each other. The bitline structures 301 can be arranged along the first axis X. In some embodiments, the bitline structures 301 can intersect with the wordline structure 201. The bitline structures 301 can be electrically connected to the source region 107-1 via the bitline contact 311.

[0218] For example, the bit-line conductive layer 303 may include polycrystalline silicon, polycrystalline germanium, polycrystalline silicon germanium, titanium, tantalum, tungsten, copper, aluminum, tungsten silicide, cobalt silicide, or titanium silicide. For example, the bit-line intermediate conductive layer 305 may include titanium nitride or tantalum nitride. For example, the bit-line conductive layer 307 may include tungsten, tantalum, titanium, copper, or aluminum. The bit-line intermediate conductive layer 305 may reduce or potentially prevent the diffusion of conductive material in the bit-line conductive layer 307 to the bit-line conductive layer 303. For example, the bit-line capping layer 309 may include silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, boron silicon nitride, boron phosphorus nitride, or boron nitride silicon carbide.

[0219] Please refer to Figures 12 to 14 A spacer material layer can be formed to cover the bitline structure 301 and the substrate 101. For example, the spacer material may include silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon nitride oxide. An etching process (e.g., an isotropic dry etching process) can be performed to remove portions of the spacer material layer and simultaneously form bitline spacers 313 on the sidewalls of the bitline structure 301. In some embodiments, such as... Figure 13 As shown, portions of the lower surface 313BS of the bit line spacer 313 can be substantially coplanar with the lower surface 311BS of the bit line contact member 311.

[0220] In some embodiments, after the bit line contact 311 is formed, an intermediate layer may be formed on the substrate 101. The bit line structure 301 may be formed on the intermediate layer. For example, the intermediate layer may include a carbon-doped oxide, a carbon-doped silicon oxide, or a nitrogen-doped silicon carbide.

[0221] Please refer to Figure 15 and Figure 16 A first dielectric layer 109 can be formed to cover the substrate 101 and the bit line structure 301. A planarization process, such as chemical mechanical polishing, can be performed until the upper surface 309TS of the bit line capping layer 309 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. For example, the first dielectric layer 109 may include silicon oxide, undoped silicate glass, fluorosilicate glass, borosilicate glass, low-k dielectric material, or a combination thereof. The low-k dielectric material may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material may have a dielectric constant of less than 2.0.

[0222] Figure 17 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 18 and Figure 19 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 17Partial process of manufacturing semiconductor device 1A with cross-sections A-A' and B-B'.

[0223] Please refer to Figure 1 and Figures 17 to 19 In step S17, a plurality of capacitor contact openings 703 may be formed in the first dielectric layer 109 and extend to the substrate 101.

[0224] Please refer to Figures 17 to 19 A lithography process and a subsequent etching process can be performed to form capacitor contact openings 703 in the first dielectric layer 109 and extend to the upper portions of the substrate 101. In some embodiments, a portion of the drain regions 107-3 may be exposed through the capacitor contact openings 703. From a top view, the capacitor contact openings 703 may be located at the ends of the active regions 105.

[0225] Figure 20 and Figure 21 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 17 Partial process of manufacturing semiconductor device 1A with cross-sections A-A' and B-B'. Figure 21 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 17 The cross section along the midline B-B'. Figure 22 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 23 and Figure 24 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 22 Partial process of manufacturing semiconductor device 1A with cross-sections A-A' and B-B'.

[0226] Please refer to Figure 1 and Figures 20 to 24 In step S19, a capacitor contact structure 401 may be formed in each capacitor contact opening 703.

[0227] Please refer to Figure 20 and Figure 21 A conductive layer 403 can be formed in the capacitor contact opening 703. In some embodiments, such as Figure 21As shown, a vertical plane of a lower surface 403BS of the capacitor contact lower conductive layer 403 may be lower than a vertical plane of the lower surface 313BS of the bit line spacer 313. For example, the capacitor contact lower conductive layer 403 may include polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium. In some embodiments, the capacitor contact lower conductive layer 403 may be doped with dopants such as phosphorus, arsenic, antimony, or boron. In some embodiments, a capacitor contact intermediate conductive layer 405 may be formed on the capacitor contact lower conductive layer 403 and in the capacitor contact opening 703. For example, the capacitor contact intermediate conductive layer 405 may include cobalt silicide, titanium silicide, nickel silicide, nickel-platinum silicide, or tantalum silicide. In some embodiments, an upper surface of the capacitor contact intermediate conductive layer 405 may be at a vertical plane that is lower than a vertical plane of the upper surface 309TS of the bit line capping layer 309.

[0228] A first conductive material 801 can be formed to completely fill the capacitor contact opening 703 and cover the first dielectric layer 109 and the bit line capping layer 309. For example, the first conductive material 801 can be titanium nitride or tantalum nitride. The intermediate conductive layer 405 of the capacitor contact can reduce the contact resistance between the first conductive material 801 and the lower conductive layer 403 of the capacitor contact.

[0229] Please refer to Figures 22 to 24 A planarization process, such as chemical mechanical polishing, can be performed until the upper surface 309TS of the bit line capping layer 309 is exposed to remove excess material, providing a substantially flat surface for subsequent processing steps, and simultaneously forming a capacitor contact conductive layer 407 on the intermediate conductive layer 405 of each capacitor contact. At this stage, the upper surface 407TS of the capacitor contact conductive layer 407 can be substantially coplanar with the upper surface 309TS of the bit line capping layer 309.

[0230] The lower conductive layer 403, the middle conductive layer 405, and the upper conductive layer 407 of the capacitor contact can together form the capacitor contact structure 401. The upper surface 407TS of the upper conductive layer 407 can be referred to as the upper surface of the capacitor contact structure 401. The capacitor contact structure 401 can be electrically connected to the drain region 107-3.

[0231] Figure 25 and Figure 26 These are cross-sectional schematic diagrams illustrating the various embodiments of this disclosure. Figure 22 Partial process of manufacturing semiconductor device 1A with cross-sections A-A' and B-B'.

[0232] Please refer to Figure 1 , Figure 25 and Figure 26In step S21, the upper surface 309TS of the bit line structure 301 (i.e., the upper surface 309TS of the bit line cover layer 309) can be recessed.

[0233] Please refer to Figure 25 and Figure 26 A recess process can be performed to remove portions of the bit line capping layer 309, the first dielectric layer 109, and the bit line spacers 313. For example, the recess process can be isotropic dry etching, anisotropic dry etching, or wet etching. During the recess process, the ratio of the etch rate of the bit line capping layer 309 to the etch rate of the conductive layer 407 on the capacitor contact can be between about 100:1 and about 10:1, or between about 20:1 and about 10:1. During the recess process, the ratio of the etch rate of the first dielectric layer 109 to the etch rate of the conductive layer 407 on the capacitor contact can be between about 100:1 and about 10:1, or between about 20:1 and about 10:1. During the recess process, the ratio of the etching rate of the bit line spacer 313 to the etching rate of the conductive layer 407 on the capacitor contact can be between about 100:1 and about 10:1, or between about 20:1 and about 10:1.

[0234] After performing the recess process, the upper surface 309TS of the bit line cover layer 309 can be recessed. In other words, the conductive layer 407 of the capacitor contact can protrude from a plane formed by the upper surface 309TS of the bit line cover layer 309. A vertical plane of the upper surface 407TS of the conductive layer 407 of the capacitor contact can be higher than a vertical plane of the upper surface 309TS of the bit line cover layer 309, the upper surface 313TS of the bit line spacer 313, and the upper surface 109TS of the first dielectric layer 109. In some embodiments, the upper surface 309TS of the bit line cover layer 309, the upper surface 313TS of the bit line spacer 313, and the upper surface of the first dielectric layer 109 can be substantially coplanar.

[0235] It should be understood that, in the description of this disclosure, the term "about" as used to describe the quantity of ingredients, components, or reactants of this disclosure refers to variations in quantity that may occur, for example, through typical measurements used to prepare concentrates or solutions and liquid handling procedures. Furthermore, variations may occur due to negligence in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to manufacture the composition or carry out the method. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0236] Figure 27This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 22 Partial process of manufacturing semiconductor device 1A with the mid-section A-A'. Figure 28 This is a top view schematic diagram illustrating intermediate semiconductor elements in some embodiments of this disclosure. Figure 29 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 28 Partial process of manufacturing semiconductor device 1A with the mid-section A-A'.

[0237] Please refer to Figure 1 and Figures 27 to 29 In step S23, multiple landing pads 501 may be formed to partially cover the capacitor contact structure 401.

[0238] Please refer to Figure 27 A second conductive material 803 may be formed to cover the capacitor contact conductive layer 407, the bit line cover layer 309, and the bit line spacer 313. In some embodiments, the second conductive material 803 may include a material that is etch-selective to the capacitor contact conductive layer 407. In some embodiments, for example, the second conductive material 803 may be tungsten, copper, or aluminum.

[0239] Please refer to Figure 28 and Figure 29 A lithography process and a subsequent etching process can be performed to remove some portions of the second conductive material 803 and transform the second conductive material 803 into a landing pad layer 501. During the etching process, the ratio of the etching rate of the second conductive material 803 to the etching rate of the conductive layer 407 on the capacitor contact can be between about 100:1 and about 10:1, or between about 20:1 and about 10:1.

[0240] For ease of description, only a landing pad 501 and a capacitor contact conductive layer 407 are described. In cross-sectional view, the landing pad 501 may cover a portion of the upper surface 407TS of the capacitor contact conductive layer 407 and an upper portion of one sidewall 407SW of the capacitor contact conductive layer 407. In other words, the landing pad 501 may partially cover the capacitor contact conductive layer 407. In top view, the landing pad 501 may be offset from the capacitor contact conductive layer 407.

[0241] By partially covering the conductive layer 407 on the capacitor contact with the landing pad layer 501, the contact surface between the landing pad layer 501 and the conductive layer 407 on the capacitor contact can be increased. Therefore, the resistance between the landing pad layer 501 and the conductive layer 407 on the capacitor contact can be reduced. As a result, the power consumption of the semiconductor device 1A can be reduced. Furthermore, the protruding conductive layer 407 on the capacitor contact can provide sufficient support for the landing pad layer 501.

[0242] Figures 30 to 34 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 12 The process of manufacturing semiconductor device 1B by section A-A'.

[0243] Please refer to Figure 30 It can provide with Figure 13 Similar intermediate semiconductor elements are shown. The fabrication techniques for multiple sacrificial spacers 315 can include those used in conjunction with... Figure 13 The formation of the bit-line spacer 313 shown is similar to the procedure. In some embodiments, the sacrificial spacer 315 may comprise a material having etch selectivity for the bit-line capping layer 309 and the first dielectric layer 109. In some embodiments, for example, the sacrificial spacer 315 may comprise an energy-removable material, such as a thermally degradable material, a photodegradable material, an electron beam degradable material, or a combination thereof. The fabrication technique of the first dielectric layer 109 may include techniques similar to those used in fabrication of the bit-line capping layer 309 and the first dielectric layer 109. Figure 15 A similar procedure to the one shown.

[0244] Please refer to Figure 31 In some embodiments, it is possible to Figure 30 The intermediate semiconductor element shown undergoes another planarization process to expose the upper surface of the sacrificial spacer 315. In some embodiments, a planarization process of the first dielectric layer 109 may be performed until the upper surface of the sacrificial spacer 315 is exposed. Subsequently, a removal process may be performed to remove the sacrificial spacer 315. After performing the removal process, a first trench 705 may be formed at the location previously occupied by the sacrificial spacer 315.

[0245] In some embodiments, the removal process can be an etching process, such as dry etching or wet etching. During the etching process, the ratio of the etch rate of the sacrificial spacer 315 to the etch rate of the first dielectric layer 109 can be between about 100:1 and about 10:1, or between about 20:1 and about 10:1. During the etching process, the ratio of the etch rate of the sacrificial spacer 315 to the etch rate of the bit line capping layer 309 can be between about 100:1 and about 10:1, or between about 20:1 and about 10:1.

[0246] In some embodiments, an energy treatment can be applied to remove the sacrificial spacer 315, which comprises an energy-removable material. This can be achieved by applying an energy source to... Figure 30 Energy processing is performed on the intermediate semiconductor element shown. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, the energy processing temperature can be between approximately 800°C and approximately 900°C. When light is used as the energy source, ultraviolet light can be applied.

[0247] Please refer to Figure 32A first insulating material 805 may be conformally formed in the first trench 705 and may cover the first dielectric layer 109 and the bit line cover layer 309. A second insulating material 807 may be formed on the first insulating material 805 and may completely fill the first trench 705.

[0248] In some embodiments, for example, the first insulating material 805 may be silicon nitride, boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbide silicon nitride. In some embodiments, for example, the second insulating material 807 may be silicon oxide.

[0249] Please refer to Figure 33 A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the bit line capping layer 309 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. After the planarization process, the first insulating material 805 can be transformed into a plurality of first insulating layers 603. The second insulating material 807 can be transformed into a plurality of second insulating layers 605. The first insulating layers 603 and the second insulating layers 605 together form an insulating structure 601.

[0250] For ease of description, only one insulating structure 601 is described. The first insulating layer 603 may have a U-shaped cross-sectional profile. The first insulating layer 603 may include a bottom 603B and two side portions 603S. The bottom 603B may be linear and may be horizontally disposed on the substrate 101, particularly on the drain region 107-3. The two side portions 603S may be linear and may be respectively connected to one end of the bottom 603B. Figure 34 As shown, one of the two side portions 603S can be attached to one side wall of the bit line structure 301, and the other of the two side portions 603S can be attached to one side wall of the capacitor contact structure 401. A second insulating layer 605 can be disposed within a space formed by the bottom 603B and the two side portions 603S. In some embodiments, the bottom 603B can be horizontally disposed in the substrate 101 and on the source region 107-1. One of the two side portions 603S can be attached to one side wall of the capacitor contact structure 401, and the other of the two side portions can be attached to one side wall of the bit line contact 311.

[0251] Please refer to Figure 34 The fabrication technology of capacitor contact structure 401 may include... Figures 17 to 24 A similar procedure is shown. The denting process can be achieved through... Figure 25 The procedure is similar to that shown. The manufacturing technology of landing pad 501 may include... Figures 27 to 29 A similar procedure is shown. Some landing pads 501 may cover one of the insulation structures 601.

[0252] Figure 35 and Figure 36 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure. Figure 12 The process of manufacturing semiconductor device 1C by cutting line A-A' in the middle.

[0253] Please refer to Figure 35 It can provide Figure 33 The intermediate semiconductor device is shown. A removal process can be performed to remove the second insulating layer 605. Multiple air gaps 607 can be formed simultaneously at locations previously occupied by the second insulating layer 605. In some embodiments, each air gap 607 may include a space formed by a bottom portion 603B and two side portions 603S. The first insulating layer 603 and the air gaps 607 can together form an insulating structure 601. The air gaps 607 can reduce the parasitic capacitance between the capacitor contact structure 401 and the bit line structure 301. As a result, the performance of the semiconductor device 1C can be improved.

[0254] In some embodiments, the second insulating layer 605 may include a material that is etch-selective towards the first insulating layer 603. The removal process may be an etching process, such as dry etching or wet etching. During the etching process, the ratio of the etch rate of the second insulating layer 605 to the etch rate of the first insulating layer 603 may be between about 100:1 and about 10:1, or between about 20:1 and about 10:1. During the etching process, the ratio of the etch rate of the second insulating layer 605 to the etch rate of the first dielectric layer 109 may be between about 100:1 and about 10:1, or between about 20:1 and about 10:1. During the etching process, the ratio of the etch rate of the second insulating layer 605 to the etch rate of the bit line capping layer 309 may be between about 100:1 and about 10:1, or between about 20:1 and about 10:1.

[0255] In some embodiments, for example, the second insulating layer 605 may include an energy-removable material, such as a thermally decomposable material, a photodecomposable material, an electron beam decomposable material, or a combination thereof. The removal process may employ energy processing to remove the second insulating layer 605. Energy processing can be performed by applying an energy source to the second insulating layer 605. The energy source may include heat, light, or a combination thereof. When heat is used as the energy source, the temperature of the energy processing may be between about 800°C and about 900°C. When light is used as the energy source, ultraviolet light may be applied.

[0256] Please refer to Figure 36 The fabrication technology of multiple capacitor contact structures 401 may include... Figures 17 to 24 A similar procedure is shown. It can be performed using... Figure 25 A similar procedure is used to perform a depression process. The fabrication techniques for multiple landing pads 501 can include those shown. Figures 17 to 29A similar procedure is shown. The landing pad 501 may cover some of the insulation structure 601.

[0257] Figures 37 to 39 This is a cross-sectional schematic diagram illustrating other embodiments of the present disclosure. Figure 17 The section A-A' in the process of manufacturing semiconductor device 1D.

[0258] Please refer to Figure 37 It can provide Figure 18 The intermediate semiconductor element shown may have a third conductive material 809 formed to completely fill the capacitor contact opening 703 and cover the bit line structure 301 and the first dielectric layer 109. For example, the third conductive material 809 may be polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon-germanium.

[0259] Please refer to Figure 38 It is possible to perform operations on the third conductive material 809 in this layer. Figures 22 to 25 A similar procedure is shown. The third conductive material 809 can be transformed into multiple capacitor contact structures 401. Each capacitor contact structure 401 may include a capacitor contact under-conductive layer 403 comprising polysilicon, polysilicon germanium, or polysilicon germanium. The capacitor contact under-conductive layer 403 may protrude from a plane formed by the upper surface 309TS of the bit line capping layer 309.

[0260] Please refer to Figure 39 The manufacturing technology for multiple landing pads 501 can include... Figures 27 to 29 A similar procedure is shown. The landing pad 501 may partially cover the capacitor contact lower conductive layer 403. In some embodiments, the landing pad 501 may cover a portion of an upper surface 403TS of the capacitor contact lower conductive layer 403 and an upper portion of a sidewall 403SW of the capacitor contact lower conductive layer 403.

[0261] Figure 40 and Figure 41 This is a cross-sectional schematic diagram illustrating other embodiments of the present disclosure. Figure 17 The process of manufacturing semiconductor device 1E by cutting line A-A' in the middle.

[0262] Please refer to Figure 40 It can provide Figure 38The intermediate semiconductor element is shown. Subsequently, a conductive material layer can be formed on top of the intermediate semiconductor element. For example, the conductive material may include titanium, nickel, platinum, tantalum, or cobalt. In some embodiments, a heat treatment may be performed. During the heat treatment, the metal atoms of the conductive material layer may chemically react with the silicon atoms of the conductive layer 403 under the capacitor contact to form a conditioning layer 317. The conditioning layer 317 may include titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. In some embodiments, the heat treatment may be a dynamic surface annealing process. After performing the heat treatment, a cleaning process may be performed to remove unreacted conductive material. The cleaning process may use an etchant, such as hydrogen peroxide and SC-1 solution.

[0263] The adjustment layer 317 may have a thickness between approximately 2 nm and approximately 20 nm. Each adjustment layer 317 may cover an upper surface 403TS of the capacitor contact lower conductive layer 403 and the upper portions of each sidewall 403SW of the capacitor contact lower conductive layer 403.

[0264] Please refer to Figure 41 The manufacturing technology for multiple landing pads 501 can include... Figures 27 to 29 A similar procedure is shown. Landing pad 501 may partially cover adjustment layer 317. In some embodiments, landing pad 501 may cover a portion of the upper surface 317TS of adjustment layer 317 and one of the sidewalls 317SW of adjustment layer 317.

[0265] Figures 42 to 44 This is a cross-sectional schematic diagram illustrating other embodiments of the present disclosure. Figure 17 The process of manufacturing semiconductor device 1F by cutting line A-A' in the middle.

[0266] Please refer to Figure 42 It can provide Figure 18 The intermediate semiconductor element shown can be formed with a fourth conductive material 811 to completely fill the capacitor contact opening 703 and cover the bit line structure 301 and the first dielectric layer 109. For example, the fourth conductive material 811 can be titanium nitride or tantalum nitride.

[0267] Please refer to Figure 43 It is possible to perform operations on the fourth conductive material 811 in this layer. Figures 22 to 25 A similar procedure is shown. The fourth conductive material 811 can be transformed into multiple capacitor contact structures 401. Each capacitor contact structure 401 may include a capacitor contact under-conductive layer 403 comprising titanium nitride or tantalum nitride. The capacitor contact under-conductive layer 403 may protrude from a plane formed by the upper surface 309TS of the bit line capping layer 309.

[0268] Please refer to Figure 44The manufacturing technology for multiple landing pads 501 can include... Figures 27 to 29 A similar procedure is shown. The landing pad 501 may partially cover the capacitor contact lower conductive layer 403. In some embodiments, the landing pad 501 may cover a portion of an upper surface 403TS of the capacitor contact lower conductive layer 403 and an upper portion of a sidewall 403SW of the capacitor contact lower conductive layer 403.

[0269] Figures 45 to 48 This is a cross-sectional schematic diagram illustrating other embodiments of the present disclosure. Figure 17 The section A-A' in the process of manufacturing semiconductor device 1G.

[0270] Please refer to Figure 45 In some embodiments, a substrate 101 may be provided. Figure 45 The substrate 101 in the middle can be with Figures 2 to 4 The substrate 101 in the middle is the same or similar, the difference is that Figure 45 The substrate 101 may be an insulator-on-silicon substrate and may contain multiple shallow trench isolation (STI) structures 150a. From along... Figure 2 As shown in the cross-sectional view along line A-A', as described above, when the substrate 101 includes silicon over an insulator, the substrate 101 may include an upper semiconductor layer 101-5 and a lower semiconductor layer 101-1 containing silicon, and a buried insulating layer 101-3 that can separate the upper semiconductor layer 101-5 from the lower semiconductor layer 101-1. For example, the buried insulating layer 101-3 may include crystalline oxides, amorphous oxides, nitrides, or combinations thereof.

[0271] STI structure 150a may include a first pad 123, a second pad 125 disposed above the first pad 123, a third pad 127 disposed above the second pad 125, and a trench filler layer 129 disposed above the third pad 127 and spaced apart from the second pad 125 by the third pad 127. The first pad 123 may contact the upper semiconductor layer 101-5 and the lower semiconductor layer 101-1. The second pad 125 may cover the first pad 123 and may contact the buried insulating layer 101-3. The third pad 127 may cover the second pad 125. In particular, in some embodiments, the first pad 123 has portions 123a and 123c covering opposing sidewalls of the upper semiconductor layer 101-5, and a portion 123b separating the second pad 125 from the lower semiconductor layer 101-1 of the semiconductor substrate 101.

[0272] It should be understood that portions 123a, 123b and 123c of the first pad 123 are spaced apart from each other.

[0273] In some embodiments, the first pad 123, the second pad 125, and the third pad 127 of the STI structure 150a comprise different materials. For example, the first pad 123 comprises silicon oxide, the second pad 125 is silicon nitride, and the third pad 127 is silicon oxynitride. In some embodiments, the STI structure 150a may penetrate the upper semiconductor layer 101-5 and the buried insulating layer 101-3 and extend to the lower semiconductor layer 101-1.

[0274] like Figure 45 As shown, after forming the STI structure 150a, the source / drain regions 107-1 and 107-3 can be adopted with... Figure 7 and Figure 8 The process of forming source / drain regions 107-1 and 107-3 shown is similar to that of forming the active region 105, and will not be described in detail here.

[0275] Please refer to Figure 46 The fabrication techniques for the multiple bit line structures 301, multiple bit line contacts 311, multiple bit line spacers 313, and multiple capacitor contact openings 703 may include those related to... Figures 9 to 18 The same procedure is shown for the bit line structure 301, bit line contact 311, bit line spacer 313, and capacitor contact opening 703, and will not be described again here.

[0276] Please refer to Figure 47 Multiple capacitor contact structures 401 may be formed next to the bit line structure 301. The capacitor contact structures 401 may be disposed in the substrate 101 and may protrude from the substrate. In some embodiments, the capacitor contact structure 401 may include a pad layer 333 disposed on and extending into the substrate 101, a capacitor conductive structure 341 disposed above and surrounded by the pad layer 333, and a spacer substructure 327 surrounding the capacitor conductive structure 341 and spaced apart from the capacitor conductive structure 341 by the pad layer 333.

[0277] In some embodiments, the capacitor conductive structure 341 includes a barrier layer 335 conformally disposed above and surrounded by the solder pad layer 333, a metal layer 337 disposed above and surrounded by the barrier layer 335, and a metal filler portion 339 disposed above and surrounded by the metal layer 337. In some embodiments, the capacitor conductive structure 341 is surrounded by a spacer structure 327.

[0278] In some embodiments, the metal filling portion 339 of the capacitor conductive structure 341 has a tapered profile, wherein a bottom of the metal filling portion 339 is relatively narrower than a top of the metal filling portion 339. For example, the metal filling portion 339 has an upper width W1 and a lower width W2, wherein the upper width W1 is greater than the lower width W2. In some embodiments, the capacitor conductive structure 341 has a tapered profile, wherein a bottom of the capacitor conductive structure 341 is relatively narrower than a top of the capacitor conductive structure 341.

[0279] Furthermore, in some embodiments, the capacitor conductive structure 341 extends through the capacitor contact opening 703 and extends to an upper portion of the substrate 101 (i.e., the upper semiconductor layer 101-5) and a portion of one of the STI structures 150a. In some embodiments, the capacitor conductive structure 341 is spaced apart from the substrate 101 and the spacer substructure 327 by a pad layer 333. In some embodiments, the metal layer 337 of the capacitor conductive structure 341 comprises a copper-manganese (Cu-Mn) alloy, and the metal filler portion 339 of the capacitor conductive structure 341 comprises copper (Cu).

[0280] In some embodiments, the gap substructure 327 may be disposed in the capacitor contact opening 703. In some embodiments, the gap substructure 327 is disposed above an upper surface T1 of the substrate 101 and in direct contact with the upper surface T1 of the substrate 101. In some embodiments, the gap substructure 327 includes an L-shaped pad 323' and a porous low-k dielectric layer 325 disposed above the L-shaped pad 323'. In some embodiments, an upper portion of the L-shaped pad 323' protrudes from an upper surface T2 of the conductive layer 307 on the bit line.

[0281] In some embodiments, the solder pad layer 333 may cover the spacer substructure 327. In some embodiments, the solder pad layer 333 is disposed within the capacitor contact opening 703 and extends into the substrate 101 and one of the STI structures 150a. In some embodiments, the vertical sidewalls S7 and S8 of the solder pad layer 333 are in direct contact with the first dielectric layer 109. Furthermore, in some embodiments, the solder pad layer 333 is in direct contact with the spacer substructure 327. Figure 47 As shown, in some embodiments, the lower surface B2 of the solder pad layer 333 is lower than the upper surface T1 of the substrate 101, and the lower surface B2 of the solder pad layer 333 is higher than the lower surface B1 of the embedded insulating layer 101-3.

[0282] Furthermore, in some embodiments, the pad layer 333 has tapered sidewalls S1 and S2 that are in direct contact with the substrate 101 (i.e., the upper semiconductor layer 101-5) and one of the STI structures 150a. For example... Figure 47As shown, the pad layer 333 includes an angle θ1 between the sidewall S1 and the lower surface B2, and another angle θ2 between the sidewall S2 and the lower surface B2. In some embodiments, both angles θ1 and θ2 are greater than 90 degrees. In some embodiments, the porous low-k dielectric layer 325 is surrounded by the pad layer 333 and the L-shaped pads 323' of the spacer substructure 327.

[0283] Please refer to Figure 48 It can recess the upper surface 309TS of the bit line structure 301 and form multiple landing pad layers 501. It can be connected with... Figure 25 A similar procedure is used to perform a recess process. This can be achieved through... Figures 27 to 29 The landing pad 501 is formed by a similar process as shown. The landing pad 501 can be formed to cover a portion 401P1 of an upper surface 401TS of the capacitor contact structure 401 and an upper portion 401P2 of a side wall 401SW of the capacitor contact structure 401.

[0284] One embodiment of this disclosure provides a semiconductor device including a substrate; a shallow trench isolation (STI) structure disposed in the substrate; a capacitor contact structure protruding from the substrate; and a landing pad covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure. The substrate includes a lower semiconductor layer; an upper semiconductor layer disposed above the lower semiconductor layer; and a buried insulating layer disposed between the upper semiconductor layer and the lower semiconductor layer.

[0285] In some embodiments, the shallow trench isolation (STI) structure penetrates the upper semiconductor layer and the buried insulating layer and extends into the lower semiconductor layer.

[0286] In some embodiments, the shallow trench isolation (STI) structure includes a first pad disposed in the substrate; a second pad disposed above the first pad; a third pad disposed above the second pad; and a trench filler layer disposed above the third pad and spaced apart from the second pad by the third pad.

[0287] In some embodiments, the first pad includes a first portion and a second portion covering opposite sidewalls of the embedded insulating layer; and a third portion separating the second pad from the lower semiconductor layer.

[0288] In some embodiments, the first part, the second part, and the third part are spaced apart from each other.

[0289] In some embodiments, the first pad, the second pad, and the third pad comprise different materials.

[0290] In some embodiments, the lower semiconductor layer and the upper semiconductor layer comprise silicon, and the buried insulating layer comprises nitride.

[0291] In some embodiments, the capacitor contact structure includes a pad layer disposed on and extending into the substrate; a capacitor conductive structure disposed above and surrounded by the pad layer; and a spacer structure surrounding the capacitor conductive structure and spaced apart from it by the pad layer.

[0292] In some embodiments, a lower surface of the solder pad is lower than an upper surface of the substrate, and the lower surface of the solder pad is higher than a lower surface of the embedded insulating layer.

[0293] In some embodiments, the angle between one sidewall of the solder pad and the lower surface of the solder pad is greater than 90 degrees.

[0294] In some embodiments, the capacitor conductive structure extends into the substrate and has a tapered profile.

[0295] In some embodiments, the capacitor conductive structure includes a barrier layer conformally disposed above and surrounded by the pad layer; a metal layer disposed above and surrounded by the barrier layer; and a metal filler portion disposed above and surrounded by the metal layer.

[0296] In some embodiments, the metal filler portion has an upper width and a lower width, wherein the upper width is greater than the lower width.

[0297] In some embodiments, the gap substructure includes an L-shaped pad and a porous low-k dielectric layer disposed above the L-shaped pad.

[0298] In some embodiments, the porous low-k dielectric layer is surrounded by the pad layer and the L-shaped pad.

[0299] Another embodiment of this disclosure provides a semiconductor device including a substrate in which a plurality of shallow trench isolation (STI) structures are disposed; a capacitor contact structure disposed in the substrate and protruding from the substrate; a bit line structure disposed on the substrate and adjacent to the capacitor contact structure; a bit line contact member disposed below the bit line structure; and a landing pad covering a portion of an upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0300] In some embodiments, the substrate includes a lower semiconductor layer; an upper semiconductor layer disposed above the lower semiconductor layer; and a buried insulating layer disposed between the upper semiconductor layer and the lower semiconductor layer.

[0301] In some embodiments, the shallow trench isolation (STI) structure defines an active region in which a plurality of source / drain regions are disposed.

[0302] In some embodiments, the shallow trench isolation (STI) structure penetrates the upper semiconductor layer and the buried insulating layer and extends into the lower semiconductor layer.

[0303] In some embodiments, the shallow trench isolation (STI) structure includes a first pad disposed in the substrate; a second pad disposed above the first pad; a third pad disposed above the second pad; and a trench filler layer disposed above the third pad and spaced apart from the second pad by the third pad.

[0304] In some embodiments, the first pad includes a first portion and a second portion covering opposite sidewalls of the embedded insulating layer; and a third portion separating the second pad from the lower semiconductor layer.

[0305] In some embodiments, the first part, the second part, and the third part are spaced apart from each other.

[0306] In some embodiments, the first pad, the second pad, and the third pad comprise different materials.

[0307] In some embodiments, the capacitor contact structure includes a pad layer disposed on the substrate and extending into the substrate; a capacitor conductive structure disposed above and surrounded by the pad layer; and a spacer substructure surrounding the capacitor conductive structure and spaced apart from the capacitor conductive structure by the pad layer.

[0308] In some embodiments, a lower surface of the solder pad layer is lower than an upper surface of the substrate, wherein the lower surface of the solder pad layer is higher than a lower surface of the embedded insulating layer.

[0309] In some embodiments, the capacitor conductive structure extends into the substrate and has a tapered profile.

[0310] In some embodiments, the capacitor conductive structure includes a barrier layer conformally disposed above and surrounded by the pad layer; a metal layer disposed above and surrounded by the barrier layer; and a metal filler portion disposed above and surrounded by the metal layer.

[0311] In some embodiments, the metal filler portion has an upper width and a lower width, wherein the upper width is greater than the lower width.

[0312] In some embodiments, the gap substructure includes an L-shaped pad and a porous low-k dielectric layer disposed above the L-shaped pad.

[0313] In some embodiments, the porous low-k dielectric layer is surrounded by the pad layer and the L-shaped pad.

[0314] In some embodiments, an upper surface of the bit line structure is located at a vertical bit plane, which is lower than a vertical bit plane of an upper surface of the capacitor contact structure.

[0315] In some embodiments, the semiconductor element further includes a bit line spacer disposed between the capacitor contact structure and the bit line structure.

[0316] In some embodiments, an upper surface of the bit line gap sublayer is substantially coplanar with the upper surface of the bit line structure.

[0317] In some embodiments, the bitline structure includes a bitline under-conductive layer disposed on the substrate; a bitline intermediate conductive layer disposed on the bitline under-conductive layer; a bitline above-conductive layer disposed on the bitline intermediate conductive layer; and a bitline cover layer disposed on the bitline above-conductive layer.

[0318] In some embodiments, an upper surface of the bit line contact is substantially coplanar with an upper surface of the substrate.

[0319] Another embodiment of this disclosure provides a method for fabricating a semiconductor element, including providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing an upper surface of the bit line structure; and forming a landing pad layer covering a portion of the upper surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

[0320] In some embodiments, forming the bitline structure includes forming a bitline under conductive layer on the substrate; forming a bitline intermediate conductive layer on the bitline under conductive layer; forming a bitline above conductive layer on the bitline intermediate conductive layer; and forming a bitline capping layer on the bitline above conductive layer.

[0321] In some embodiments, forming the capacitor contact structure includes forming a spacer substructure on the substrate; forming a pad layer on the substrate and extending into the substrate, wherein the pad layer is surrounded by the spacer substructure; and forming a capacitor conductive structure above and surrounded by the pad layer, wherein the capacitor conductive structure includes a barrier layer conformally disposed above and surrounded by the pad layer; a metal layer disposed above and surrounded by the barrier layer; and a metal filler portion disposed above and surrounded by the metal layer.

[0322] In some embodiments, the fabrication method further includes forming a bit line spacer between the capacitor contact structure and the bit line structure, wherein an upper surface of the bit line spacer layer is substantially coplanar with the upper surface of the bit line structure.

[0323] In some embodiments, the fabrication method further includes forming a bit line contact below the bit line structure.

[0324] In some embodiments, the fabrication method further includes forming source / drain regions beneath the bit line contact and the capacitor contact structure.

[0325] In some embodiments, the preparation method further includes forming a shallow trench isolation (STI) structure in the substrate.

[0326] In some embodiments, forming the shallow trench isolation (STI) structure includes forming a first pad in the substrate; forming a second pad disposed on the first pad; forming a third pad disposed above the second pad; and forming a trench filler layer disposed above the third pad, wherein the trench filler layer is separated from the second pad by the third pad.

[0327] Due to the design of the semiconductor device disclosed herein, a contact surface between a landing pad layer and a capacitor contact structure can be increased. Therefore, the resistance between the landing pad layer and the capacitor contact structure can be reduced. As a result, the power consumption of the semiconductor device can be reduced. Furthermore, the protruding capacitor contact structure can provide sufficient support for the landing pad layer.

[0328] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0329] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A base, comprising: The next semiconductor layer; An upper semiconductor layer is disposed above the lower semiconductor layer; and An insulating layer is embedded between the upper semiconductor layer and the lower semiconductor layer; A shallow trench isolation structure is set in the substrate; A capacitor contact structure protrudes from the substrate; and A landing pad covers a portion of the top surface of an upper surface of the capacitor contact structure and the upper part of a side wall of the capacitor contact structure.

2. The semiconductor device of claim 1, wherein the shallow trench isolation structure penetrates the upper semiconductor layer and the buried insulating layer and extends into the lower semiconductor layer.

3. The semiconductor device of claim 2, wherein the shallow trench isolation structure comprises: A first bonding pad is disposed in the substrate; A second solder pad is disposed above the first solder pad; A third solder pad is positioned above the second solder pad; as well as A trench filler layer is disposed above the third solder pad and separated from the second solder pad by the third solder pad.

4. The semiconductor device of claim 3, wherein the first bonding pad comprises: A first part and a second part cover the opposite sidewalls of the embedded insulation layer; as well as The third part separates the second pad from the lower semiconductor layer.

5. The semiconductor element of claim 4, wherein the first portion, the second portion, and the third portion are spaced apart from each other.

6. The semiconductor device of claim 5, wherein the first pad, the second pad, and the third pad comprise different materials.

7. The semiconductor device of claim 1, wherein the lower semiconductor layer and the upper semiconductor layer comprise silicon, and the buried insulating layer comprises nitride.

8. The semiconductor element of claim 1, wherein the capacitor contact structure comprises: A bonding pad is disposed on the substrate and extends into the substrate; A capacitor conductive structure is disposed above and surrounded by the solder pad layer; as well as A spacer structure surrounds the conductive structure of the capacitor and is separated from the conductive structure of the capacitor by the pad layer.

9. The semiconductor device of claim 8, wherein a lower surface of the pad layer is lower than an upper surface of the substrate, and a lower surface of the pad layer is higher than a lower surface of the embedded insulating layer.

10. The semiconductor device of claim 9, wherein the included angle between one sidewall of the pad layer and the lower surface of the pad layer is greater than 90 degrees.

11. The semiconductor element of claim 8, wherein the capacitor conductive structure extends into the substrate and has a tapered profile.

12. The semiconductor element of claim 11, wherein the capacitor conductive structure comprises: A barrier layer is conformally disposed above and surrounded by the solder pad layer; A metal layer is disposed above and surrounded by the barrier layer; and A metal filling portion is disposed above and surrounded by the metal layer.

13. The semiconductor element of claim 12, wherein the metal filling portion has an upper width and a lower width, and the upper width is greater than the lower width.

14. The semiconductor device of claim 8, wherein the spacer substructure includes an L-shaped pad and a porous low-k dielectric layer disposed above the L-shaped pad.

15. The semiconductor device of claim 14, wherein the porous low-k dielectric layer is surrounded by the pad layer and the L-shaped pad.

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