Read-only memory device and manufacturing method thereof

Abstract

A read-only memory (ROM) device includes: an active region extending in a first direction; and a plurality of gates extending across the active region in a second direction transverse to the first direction and located above the active region. The plurality of gates and the active regions correspondingly configure the plurality of transistors. Each of the plurality of transistors is configured to store data. The active region continuously extends across and over more than four conductive gates of the plurality of gates. The embodiment of the invention also discloses a method for manufacturing the read-only memory (ROM) device.

Description

Technical Field

[0001] Embodiments of this application relate to read-only memory devices and methods of manufacturing the same. Background Technology

[0002] Integrated circuit (“IC”) devices include one or more semiconductor devices represented in an IC layout diagram (also known as a “layout diagram,” “IC layout,” or “layout”). A layout diagram is hierarchical and includes modules that perform higher-level functions according to the design specifications of the IC device. Modules are typically constructed from combinations of cells, each cell representing one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layout diagrams (sometimes called standard cells) are stored in a standard cell library (hereinafter referred to as a “library” or “cell library” for simplicity) and are accessible by various tools, such as electronic design automation (EDA) tools, to generate, optimize, and verify IC designs. Examples of IC devices and cells accordingly include memory devices and memory cells. Summary of the Invention

[0003] According to one aspect of the present application, a read-only memory (ROM) device is provided, comprising: an active region extending along a first direction; and a plurality of gates extending across the active region and above the active region along a second direction laterally to the first direction, wherein the plurality of gates are configured with a plurality of transistors together with the active region, each of the plurality of transistors being configured to store data, and the active region continuously extending across more than four of the plurality of gates and above the conductive gates.

[0004] According to another aspect of the embodiments of this application, a read-only memory (ROM) device is provided, comprising: a plurality of instances of a circuit region, wherein the circuit region includes: a plurality of active regions extending continuously along a first direction; and a plurality of gates extending across the plurality of active regions along a second direction transverse to the first direction, the plurality of gates and the plurality of active regions being configured together as a plurality of transistors for storing data, the plurality of instances of the circuit region including a first instance and a second instance that are adjacent to each other and share a source / drain group.

[0005] According to another aspect of the present application, a method for manufacturing a read-only memory (ROM) device is provided, the method comprising: forming a plurality of active regions extending continuously along a first direction on a substrate; forming a plurality of gates extending along a second direction transverse to the first direction above the plurality of active regions, the plurality of gates being configured together with the plurality of active regions as a plurality of transistors for storing data; and forming one or more vias above one or more sources / drains of the plurality of active regions according to data to be stored in the ROM device, wherein the plurality of active regions, the plurality of gates, and the plurality of transistors are arranged in a plurality of instances of a circuit region, the circuit region including at least four adjacent transistors in the first direction, and forming at least one of the plurality of active regions including at least one active region between adjacent instances of the plurality of instances without forming an isolation structure. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a schematic block diagram of a memory device according to some embodiments.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G These are schematic circuit diagrams of various memory cells according to some embodiments.

[0009] Figure 3A This is a circuit diagram of the circuit area of ​​a memory device according to some embodiments.

[0010] Figure 3B This is a schematic diagram of the layout of the circuit area of ​​a memory device according to some embodiments.

[0011] Figure 3C This is a schematic cross-sectional view of the circuit area of ​​a memory device according to some embodiments.

[0012] Figure 4 This is a schematic diagram of the layout of the circuit area of ​​a memory device according to some embodiments.

[0013] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5EEach includes circuit diagrams and schematic diagrams showing the layout of circuit regions of memory devices, according to some embodiments.

[0014] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F Each includes circuit diagrams and schematic diagrams showing the layout of circuit regions of memory devices, according to some embodiments.

[0015] Figure 7A , Figure 7B , Figure 7C , Figure 7D These are flowcharts of various methods according to some embodiments.

[0016] Figure 8 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Figure 9 This is a block diagram of an IC device manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, arrangements, etc., may be considered. For example, in the following description, forming a first component on or above a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0020] In some embodiments, a read-only memory (ROM) device or its layout includes a plurality of instances of circuit regions or ROM cells arranged adjacent to each other. The ROM device or layout includes an active region extending continuously over the plurality of adjacent instances of circuit regions or ROM cells without being interrupted or discontinuous by one or more isolation structures within or between the plurality of instances.

[0021] Compared to other methods that utilize such isolation structures within and / or between adjacent instances of circuit regions or ROM cells, the size of the ROM device is advantageously reduced in one or more embodiments. In a non-limiting example, a 4×4 ROM cell according to some embodiments has a width of 4 gate pitches (sometimes referred to as "CPP"), while a 4×4 ROM cell according to other methods has a larger width of 5 CPP or 6 CPP. As a result, according to one or more embodiments, a ROM device comprising a 4×4 ROM cell with 4 CPP can achieve an area reduction of approximately 16.7% compared to a ROM device comprising a 4×4 ROM cell with 5 CPP, or an area reduction of approximately 33.3% compared to a ROM device comprising a 4×4 ROM cell with 6 CPP according to other methods. In some embodiments, one or more further advantages can be achieved, including but not limited to reduced bit line length, reduced variable bit line leakage, reduced polyextension effect (PXE), etc.

[0022] Figure 1 This is a schematic block diagram of a memory device 100 according to some embodiments. A memory device is a type of IC device. In at least one embodiment, the memory device is a single IC device. In some embodiments, the memory device is included as part of a larger IC device that includes circuitry other than the memory device for other functions. In one or more embodiments, the memory device 100 is a read-only memory (ROM) device.

[0023] Memory device 100 includes a memory array 101 of multiple memory cells MC and a memory controller 102 (sometimes referred to as "memory control circuitry") coupled to control the operation of the memory cells MC. In a ROM device according to some embodiments, each memory cell MC is configured to store a bit, sometimes referred to as a bit cell, and the memory array 101 is referred to as a ROM array. In memory array 101, the memory cells MC are arranged in multiple columns and multiple rows. The number of columns in memory array 101 may be the same as or different from the number of rows. Columns and rows in a memory array are sometimes referred to as memory columns and memory rows. Memory columns extend along a column direction, designated as the C-axis in the description. Memory rows extend along a row direction laterally to the column direction, designated as the R-axis in the description.

[0024] The memory device 100 also includes a plurality of word lines WL0, WL1, ... WLn extending along the rows of the memory array 101, and a plurality of bit lines BL0, BL1, ... BLm extending along the columns of the memory array 101. Here, the label WL is typically used to refer to word lines, and the label BL is used to refer to bit lines. Word lines are configured to transmit the address of a memory cell MC to be read from. Word lines are sometimes referred to as “address lines.” Bit lines are configured to transmit data read from the memory cell MC indicated by the address on the corresponding word line. Bit lines are sometimes referred to as “data lines.” Various numbers of word lines and / or bit lines in the memory device 100 are within the range of various embodiments. Memory cells MC in each memory row are electrically coupled to the memory controller 102 via a corresponding word line, while memory cells MC in each memory column are electrically coupled to the memory controller 102 via a corresponding bit line. For example, memory cell 111 in the memory array 101 is coupled to the memory controller 102 via a corresponding word line WL1 and a corresponding bit line BL1.

[0025] exist Figure 1 In the example configuration, the memory controller 102 includes word line driver circuitry 103 (sometimes referred to as a row decoder or row decoder circuit), bit line driver circuitry 104 (sometimes referred to as a column decoder or column decoder circuit), and control circuitry 106. Various numbers of word line driver circuits and / or bit line driver circuits are found throughout the various embodiments.

[0026] Word line driver circuit 103 is configured to decode the row address of one or more memory cells MC selected for access during a read operation. For example, word line driver circuit 103 includes multiple word line drivers, each coupled to one or more word lines of memory array 101. Word line driver circuit 103 is configured to provide a set of access voltages to the selected word line corresponding to the decoded row address via the respective word line driver, and to provide a different set of voltages (e.g., zero) to other unselected word lines.

[0027] Bit line driving circuit 104 is configured to decode the column address of one or more memory cells MC selected for access during a read operation. In some embodiments, bit line driving circuit 104 includes one or more bit line multiplexers, each bit line multiplexer coupled to one or more bit lines of memory array 101. In some embodiments, bit line driving circuit 104 is configured to provide a set of voltages to the selected bit line corresponding to the selected memory cell MC to be accessed via the bit line multiplexers, and to provide a different set of voltages to other unselected bit lines. In at least one embodiment, the unselected bit lines remain floating. For example, bit line driving circuit 104 includes one or more precharge circuits configured to precharge the selected bit line to a precharge voltage during a read operation. In some embodiments, the selected bit line is not precharged. Bit line driving circuit 104 is configured to couple the selected bit line corresponding to the selected memory cell MC to an output circuit (not shown), a sense amplifier (not shown), etc., in memory controller 102 to read data stored in the selected memory cell MC.

[0028] In the example read operation, the memory cell 111 to be accessed is selected. As a result, the corresponding word line WL1 is the selected word line, and the corresponding bit line BL1 is the selected bit line. Word line driver circuitry 103 is configured to provide an access voltage (e.g., VDD) to the selected word line WL1 and to provide different voltages (e.g., zero or VSS) to the other unselected word lines. Bit line driver circuitry 104 is configured to provide a precharge voltage (e.g., VDD) to the selected bit line BL1 and couple the selected bit line BL1 to an output circuit or a sense amplifier. When an access voltage is applied to the memory cell 111 through word line WL1, the precharge voltage on bit line BL1 remains constant, or is pulled to VSS depending on the data or bit stored in the memory cell 111. The voltage on bit line BL1 is provided to the output circuitry or sense amplifier, thereby reading the data or bit stored in the memory cell 111.

[0029] Control circuitry 106 is configured to control the operation of word line drive circuitry 103, bit line drive circuitry 104, output circuitry, sense amplifier, and / or other components in memory controller 102. In at least one embodiment, memory controller 102 further includes one or more clock generators for providing clock signals to various components of memory device 100, one or more input / output (I / O) circuits for exchanging data, clock, and / or control with external devices or circuits, and / or one or more sub-controllers for controlling various operations within memory device 100. The described memory device configuration is an example, and other memory device configurations are within the scope of various embodiments.

[0030] Figures 2A-2GThis is a circuit diagram of various memory cells 200A-200G according to some embodiments. In some embodiments, one or more of the memory cells 200A-200G correspond to... Figure 1 The memory cells MC described are one or more of the following. For simplicity, Figures 2A-2G The corresponding components are specified by the same reference numerals.

[0031] Memory cells 200A-200B are examples of memory cells configured to store a first logic value, and memory cells 200C-200G are examples of memory cells configured to store a second logic value different from the first logic value. In the specific examples described herein, the first logic value is logic "1" and the second logic value is "0". Other configurations where the first logic value is logic "0" and the second logic value is logic "1" are within the scope of various embodiments. Memory cells 200A-200G are sometimes referred to as NOR (Non-Negative) type ROM bit cells, and ROM devices including one or more of memory cells 200A-200G are sometimes referred to as NOR type ROM devices.

[0032] exist Figure 2A In the memory cell 200A, a transistor T is included, the transistor T having a gate 211, a first source / drain 212, and a second source / drain 213. The gate 211 is electrically coupled to a word line WL, the first source / drain 212 is electrically coupled to a power rail 215, and the second source / drain 213 is electrically coupled to a bit line BL. In at least one embodiment, the word line WL corresponds to one or more word lines, while the bit line BL corresponds to... Figure 1 One or more bit lines are described. Power rail 215 is configured to carry the power supply voltage for read operations of memory cell 200A. Figures 2A-2GIn the example configuration, transistor T is an N-type transistor, and power rail 215 carries a supply voltage that is ground or VSS. Power rail 215 configured to carry VSS is referred to herein as the VSS power rail. Other configurations are within the scope of various embodiments. For example, when transistor T is a P-type transistor, power rail 215 is configured to carry a positive voltage, such as VDD, etc. Examples of transistor T include, but are not limited to, MOSFETs, CMOS transistors, P-channel MOSFETs, N-channel MOSFETs, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, or similar elements. In one or more non-limiting embodiments specifically described herein, all transistors in the ROM array are N-type transistors, such as NMOS transistors.

[0033] In an example read operation of memory cell 200A according to some embodiments, an access voltage (e.g., VDD) is supplied to the gate 211 of transistor T via word line WL, and bit line BL is precharged to a precharge voltage (e.g., VDD). The access voltage turns on transistor T, and the turned-on transistor T electrically couples bit line BL to the VSS power rail. As a result, the voltage on bit line BL is pulled down from the precharge voltage (e.g., VDD) to VSS. The voltage on bit line BL pulled down to VSS is output or detected by a sense amplifier to indicate that a logic "1" is stored in memory cell 200A.

[0034] The configuration of memory cell 200A, configured to store logic "1", is referred to herein as the ON configuration. The ON configuration indicates that when transistor T is turned on, the turned-on transistor T electrically couples the bit line BL to the VSS power rail. Memory cell 200B is another example of a memory cell having an ON configuration and configured to store logic "1". Conversely, as described herein, memory cells 200C-200G are examples of memory cells having an OFF configuration and configured to store logic "0". The OFF configuration indicates that when transistor T is turned on, the turned-on transistor T does not electrically couple the bit line BL to the VSS power rail.

[0035] The ON configuration of memory cell 200A, in which the first source / drain 212 is electrically coupled to the VSS power rail and the second source / drain 213 is electrically coupled to the bit line BL, is referred to herein as ON configuration 1g.

[0036] exist Figure 2BIn this embodiment, memory cell 200B is configured to store logic "1" and has an ON configuration. In memory cell 200B, a first source / drain 212 is electrically coupled to bit line BL, a second source / drain 213 is electrically coupled to the VSS power rail, and the ON configuration of memory cell 200B is referred to herein as ON configuration 1h. In some embodiments, the read operation of memory cell 200B is similar to the operation described with respect to memory cell 200A, i.e., when transistor T is turned on, the turned-on transistor T electrically couples bit line BL to the VSS power rail, and the voltage on bit line BL is pulled down from the precharge voltage to VSS to indicate that logic "1" is stored in memory cell 200B.

[0037] exist Figure 2C In this document, memory cell 200C is configured to store logic "0" and has an OFF configuration. In memory cell 200C, the first source / drain 212 and the second source / drain 213 are electrically coupled to the VSS power rail, and the OFF configuration of memory cell 200C is referred to herein as OFF configuration OFF.

[0038] In an example read operation of memory cell 200C according to some embodiments, an access voltage (e.g., VDD) is supplied to the gate 211 of transistor T via word line WL, and bit line BL is precharged to a precharge voltage (e.g., VDD). The access voltage turns on transistor T. However, since both the first source / drain 212 and the second source / drain 213 are electrically coupled to the VSS power rail, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail. As a result, the voltage on bit line BL remains at the precharge voltage (e.g., VDD). The voltage on bit line BL, which remains at the precharge voltage, is output or detected by a sense amplifier to indicate that logic "0" is stored in memory cell 200C.

[0039] exist Figure 2D In this embodiment, memory cell 200D is configured to store logic "0" and has an OFF configuration. In memory cell 200D, both the first source / drain 212 and the second source / drain 213 are electrically coupled to bit line BL, and the OFF configuration of memory cell 200D is referred to herein as OFF configuration 0i. In some embodiments, the read operation of memory cell 200D is similar to the read operation described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail, and the voltage on bit line BL is maintained at the pre-charge voltage to indicate that logic "0" is stored in memory cell 200D.

[0040] exist Figure 2EIn this embodiment, memory cell 200E is configured to store logic "0" and has an OFF configuration. In memory cell 200E, the first source / drain 212 and the second source / drain 213 are not electrically coupled to either bit line BL or the VSS power rail. In at least one embodiment, the first source / drain 212 and the second source / drain 213 are electrically floating. In some embodiments, a read operation of memory cell 200E is similar to the read operation described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail, and the voltage on bit line BL is maintained at a pre-charge voltage to indicate that logic "0" is stored in memory cell 200E.

[0041] exist Figure 2F In this embodiment, memory cell 200F is configured to store logic "0" and has an OFF configuration. In memory cell 200F, a first source / drain 212 is electrically coupled to the VSS power rail, but a second source / drain 213 is not electrically coupled to either bit line BL or the VSS power rail. In at least one embodiment, the second source / drain 213 is electrically floating. In some embodiments, a read operation of memory cell 200F is similar to the read operation described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail, and the voltage on bit line BL is maintained at a pre-charge voltage to indicate that logic "0" is stored in memory cell 200F.

[0042] exist Figure 2G In this embodiment, memory cell 200G is configured to store logic "0" and has an OFF configuration. In memory cell 200G, a second source / drain 213 is electrically coupled to bit line BL, but a first source / drain 212 is not electrically coupled to either bit line BL or the VSS power rail. In at least one embodiment, the first source / drain 212 is electrically floating. In some embodiments, a read operation of memory cell 200G is similar to the operation described with respect to memory cell 200C, i.e., when transistor T is turned on, the turned-on transistor T does not electrically couple bit line BL to the VSS power rail, and the voltage on bit line BL remains at a pre-charge voltage to indicate that logic "0" is stored in memory cell 200G. The OFF configuration of memory cells 200E-200G is generally referred to herein as OFF configuration 0a.

[0043] In some embodiments, during the design phase, a blank or unprogrammed ROM array corresponding to memory array 101 is developed. In such an unprogrammed ROM array, each memory cell or bit cell has information about... Figure 2EThe described configuration, in which the electrical connections of the first source / drain 212 and the second source / drain 213 to the bit lines BL and VSS power rails are not yet determined. In the subsequent programming phase, the unprogrammed ROM array is programmed according to data to be stored in the ROM array. For example, by determining the data or bit or logic value to be stored in the bit cells, and according to... Figures 2A-2G One of the described configurations involves adding or not adding one or more electrical connections to program each bit cell in an unprogrammed ROM array.

[0044] In some embodiments, use about Figures 2A-2D The described configuration uses code mode 1 to program an unprogrammed ROM array, without using anything about... Figures 2E-2G The configuration is described. About Figures 5A-5E This describes a non-restrictive example of ROM programming using code mode 1.

[0045] In some embodiments, use about Figures 2A-2G All the configurations described use code mode 2 to program the unprogrammed ROM array. About Figures 6A-6F It describes a non-restrictive example of ROM programming using code mode 2.

[0046] Figure 3A This is a circuit diagram of circuit region 301 of memory device 300A according to some embodiments. In at least one embodiment, memory device 300A corresponds to memory device 100 and / or circuit region 301 corresponds to a region in memory array 101. For simplicity, Figure 1 , Figures 2A-2G , Figure 3A The corresponding components are specified by the same reference numerals.

[0047] exist Figure 3A In the circuit region 301, four consecutive bit units are included, each bit unit corresponding to about Figure 1 The memory cell MC described and / or about Figures 2A-2G One of the memory cells 200A-200G is described. The four bit cells correspondingly include transistors T0-T3. The gates of transistors T0-T3 are electrically coupled to word lines WL0-WL3. Transistors T0-T3 are series coupled such that a pair of directly adjacent transistors share a common source / drain. Two transistors are considered directly adjacent (or adjacent to each other) if there are no other transistors between them. In some embodiments, as described herein, two directly adjacent transistors have corresponding gates physically separated by one gate pitch (CPP). Figure 3AIn the example configuration, transistors T0 and T1 are directly adjacent and share a common source / drain (unnumbered) electrically coupled to electrical connector 311, and transistors T1 and T2 are directly adjacent and share a common source / drain (unnumbered) electrically coupled to electrical connector 312.

[0048] Another transistor TK outside circuit region 301 is directly adjacent to transistor T0 and shares a common source / drain with it (unnumbered). Another transistor TL outside circuit region 301 is directly adjacent to transistor T3 and shares a common source / drain with it (unnumbered). In some embodiments, another instance of circuit region 301 is arranged below circuit region 301 (in...). Figure 3A (in the middle), and adjacent to circuit region 301. Transistor TK corresponds to transistor T3 in this other instance of circuit region 301, and has a gate (not shown) electrically coupled to the word line. In some embodiments, another instance of circuit region 301 is arranged on top of circuit region 301 (in the middle). Figure 3A (middle) and adjacent to circuit region 301. Transistor TL corresponds to transistor T0 in this other instance of circuit region 301 and has a gate (not shown) electrically coupled to the word line. In some embodiments, for example when circuit region 301 is located at the edge of the ROM array, one of transistors TK and TL is omitted.

[0049] According to Figures 2A-2G In one of the described configurations, each transistor T0-T3 (or corresponding bit unit) is configured to store a predetermined data or bit or logic value. For example, transistor T0 is configured to store logic "0". Since one source / drain of transistor T0 is electrically coupled to bit line BL via electrical connector 311, the other source / drain in transistor T0 is... Figure 2D The OFF configuration 0i is electrically coupled to the line BL or according to Figure 2G The OFF configuration 0a is electrically floating. Transistor T1 is configured to store logic "1", and according to... Figure 2A ON configuration 1g and Figure 2B One of the ON configurations 1h has one source / drain electrically coupled to line BL via electrical connector 311, and another source / drain electrically coupled to the VSS power rail via electrical connector 312. Transistor T2 is configured to store logic "1", and according to Figure 2A ON configuration 1g and Figure 2B The transistor T3 is configured to store logic "0". It has one source / drain electrically coupled to the VSS power rail via electrical connector 312, and another source / drain electrically coupled to bit line BL via electrical connector 313. Since one source / drain of transistor T3 is electrically coupled to bit line BL via electrical connector 313, the other source / drain in transistor T3 is configured to store logic "0". Figure 2D The OFF configuration 0i is electrically coupled to the line BL or according to Figure 2G The OFF configuration 0a is electrically floating. In some embodiments, each of the transistors TK and TL outside the circuit region 301 is also configured according to the information provided. Figures 2A-2G One of the described configurations stores logical values.

[0050] Figure 3B This is a schematic diagram of the layout of circuit region 302 of memory device 300B according to some embodiments. In at least one embodiment, memory device 300B corresponds to memory device 300A and / or circuit region 302 corresponds to circuit region 301. For simplicity, Figure 1 , Figures 2A-2G , Figures 3A-3B The corresponding components are designated by the same reference numerals.

[0051] like Figure 3B As shown in the layout, the memory device 300B includes an active region OD extending along a first direction (e.g., the X-axis) and a plurality of gates GK, G0-G3, GL extending on the active region OD along a second direction laterally to the first direction (e.g., the Y-axis). Gates GK, G0-G3, GL are configured with transistors correspondingly to the active region OD, each transistor configured to store data. In some embodiments, Figure 3B The gates GK, G0-G3, and GL in the diagram correspond to... Figure 3A The gates of transistors TK, T0-T3, and TL, and Figure 3B The transistors with gates GK, G0-G3, and GL correspond to Figure 3A Transistors TK, T0-T3, and TL are shown. Gates GK, G0-G3, and GL are arranged along the X-axis with gate pitch (CPP), which is the distance along the X-axis between the center lines of directly adjacent gates, as shown in gates G2 and G3. If there are no other gates between two gates, they are considered to be directly adjacent (or directly next to each other).

[0052] The active region OD spans more than four gates (GK, G0-G3, GL) along the X-axis and extends continuously below them. Figure 3BIn the example configuration, the active region OD continuously spans and lies below six gates GK, G0-G3, GL. In at least one embodiment, one of the gates GK, GL is omitted (e.g., when circuit region 302 is located at the edge of the ROM array), and the active region OD spans at least five gates and extends continuously below them. Other numbers (greater than 6) of gates extending continuously below the active region OD are within the range of various embodiments. In some embodiments, the memory device 300B includes multiple instances of circuit region 302 arranged adjacent to each other along the X-axis. For example, another instance of circuit region 302 is arranged below circuit region 302 (in... Figure 3B (in the middle) and adjacent to circuit area 302, and / or another instance of circuit area 302 is arranged above circuit area 302 (in Figure 3B (middle) and adjacent to circuit region 302. In at least one embodiment, the active region OD extends continuously along the X-axis below the gates of multiple instances of the adjacently arranged circuit regions 302. In some embodiments, all gates crossed by the continuous extension of the active region OD below it belong to transistors configured to store data, e.g., regarding Figure 3A The transistors TK, T0-T3, TL and / or related to are described. Figures 2A-2G The transistor T is described.

[0053] The active region OD extends continuously along the X-axis, passing through more than four gates of transistors configured to store data, and is not interrupted or discontinuous by isolation structures. In some embodiments, the memory device 300B does not have isolation structures that divide the active region OD into electrically isolated portions. This distinguishes it from other methods that include isolation structures within and / or at the edges of circuit regions. For example, according to other methods, there will be isolation structures below gates GL and GK, extending along the Y-axis, to divide the active region OD into three electrically isolated portions. Alternatively, according to other methods, gates GL and GK will be dummy gates, comprising non-conductive material and / or not forming transistors configured to store data. For example, according to other methods, gates GL and GK will be dummy gates not electrically coupled to word lines. Instead, in one or more embodiments, each of a plurality of gates that the active region OD continuously spans and extends below is electrically coupled to a word line, and the transistors formed by such gates and the active region OD are configured to store data. Compared to other methods that have isolation structures dividing the active region into electrically isolated portions, the size of the memory device 300B with the active region OD extending continuously is advantageously reduced.

[0054] The memory device 300B also includes contact structures MD0-MD4, which are respectively located on the source / drain of the transistor configured by the gate GK, G0-G3, GL, and active region OD. For simplicity, not all contact structures are shown. Figure 3BIn the circuit diagram, contact structures MD0-MD4 are arranged along the X-axis with a gate pitch (CPP), which is the distance along the X-axis between the centerlines of directly adjacent contact structures, as shown in contact structures MD1 and MD2. If there are no other contact structures between two contact structures, they are considered directly adjacent (or immediately adjacent). Contact structures MD0 and MD4 are arranged on the edge of circuit region 302 and are shared with other instances of circuit region 302 adjacent to it. This further distinguishes them from other methods where isolation structures and / or dummy gates are arranged on the edge of the circuit region.

[0055] The memory device 300B further includes a bit line BL and a VSS power rail that overlap the active region OD and extend continuously along the X-axis across multiple gates. Figure 3B In the example configuration, the bit lines BL and VSS power rails are conductive patterns in the same metal layer on the contact structures MD0-MD4 and gates GK, G0-G3, GL. In some embodiments, the bit lines BL and VSS power rails extend continuously across the same number of gates as the active region OD.

[0056] The memory device 300B also includes vias VD1-VD3, each via contacting a corresponding electrically coupled bit line BL or VSS power rail in the structures MD0-MD4 to program or configure a corresponding transistor to store predetermined data. In at least one embodiment, vias VD1-VD3 correspond to electrical connections 311-313.

[0057] In at least one embodiment, compared to other methods with isolation structures that divide the active region into electrically isolated portions, the length of the bit line BL along the X-axis is advantageously reduced because the size of the memory device 300B, in which the active region OD extends continuously, is advantageously reduced. In at least one embodiment, the reduced length of the bit line BL provides one or more further advantages, including, but not limited to, reduced parasitic capacitance, reduced drive strength and / or size requirements of the bit line drive circuitry, etc.

[0058] Figure 3C This is a schematic cross-sectional view of the circuit area of ​​memory device 300C according to some embodiments. In at least one embodiment, memory device 300C corresponds to one or more of memory devices 100, 300A, and 300B. For simplicity, Figure 1 , Figures 2A-2G , Figures 3A-3C The corresponding components are designated by the same reference numerals.

[0059] The memory device 300C includes a substrate 320 and at least one transistor 321 on the substrate 320. In at least one embodiment, the transistor 321 corresponds to one or more of the memory cells MC, 200A-200G, transistors TK, T0-T3, TL, and transistors having gates GK, G0-G3, GL in the memory device 100.

[0060] In some embodiments, substrate 320 is a semiconductor substrate. N-type and P-type dopants are added to the substrate to form N-wells 322, 323 and P-wells (not shown) respectively. In some embodiments, an isolation structure is formed between adjacent P-wells and N-wells. For simplicity, from Figure 3C Several features, such as the P-well and isolation structure, are omitted.

[0061] Transistor 321 includes a gate stack and source / drain electrodes. N-wells 322 and 323 define the source / drain of transistor 321. A portion of the substrate 320 between the source / drain electrodes 322 and 323, or a P-well (not shown), corresponds to the channel of transistor 321. The channel and the source / drain electrodes 322 and 323 together correspond to the active region, for example, regarding... Figure 3B The active region OD is described. The gate stack of transistor 321 includes a gate dielectric layer 324 and a gate 325. In at least one embodiment, transistor 321 includes multiple gate dielectric layers. Example materials for the gate dielectric layers include HfO2, ZrO2, etc. Example materials for the gate 325 include polysilicon (poly), metal, etc. The described configuration of transistor 321 is one example. Various other transistor configurations are within the scope of various embodiments.

[0062] The memory device 300C also includes conductive components configured to electrically couple transistor 321 to other circuitry within the memory device 300C. The conductive components include source / drain (metal-to-device, or MD) contact structures 326, 327, correspondingly located on and electrically contacting source / drain terminals 322, 323. The conductive components also include various vias. For example, a via-to-gate (VG) via 330 is located on and electrically contacts gate 325. Vias-to-device (VD) vias 328, 329 are correspondingly located on and electrically contacting MD contact structures 326, 327. As described herein, the VG via 330 and / or the VD vias 328, 329 are configured to couple transistor 321 to various patterns in the MO layer of the redistribution structure 350.

[0063] The redistribution structure 350 includes multiple metal layers M0, M1, ... and multiple via layers V0, V1, ..., arranged alternately in the thickness direction of the substrate 320 (i.e., along the Z-axis). The redistribution structure 350 further includes various interlayer dielectric (ILD) layers (not shown) embedded with the metal layers and via layers. The M0 layer, also known as the metal zero (M0) layer, is the lowest metal layer immediately adjacent to and electrically in contact with the VD and VG vias, and is schematically shown under the label "M0". The M1 layer is the metal layer immediately adjacent to the M0 layer and is schematically shown under the label "M1". The redistribution structure 350 further includes other metal layers sequentially stacked on the M1 layer. The redistribution structure 350 also includes via layers disposed between and electrically coupling the consecutive metal layers. A via layer Vn is disposed between and electrically coupling the Mn and Mn+1 layers, where n is an integer starting from zero. For example, the via zero (V0) layer is the bottommost via layer disposed between and electrically coupling the M0 and M1 layers, and is schematically shown with the label "V0". The metal layers and via layers of the redistribution structure 350 are configured to form interconnects that electrically couple various components or circuits of the memory device 300C to each other and to external circuits.

[0064] exist Figure 3C In the example configuration, the M0 layer includes M0 conductive patterns 331, 332, and 333, correspondingly above and electrically contacting VD vias 328, 329, and 330. In at least one embodiment, M0 conductive pattern 331 corresponds to one of the bit line BL and the VSS power rail, while M0 conductive pattern 332 corresponds to the other of the bit line BL and the VSS power rail. For example, M0 conductive pattern 331 corresponds to the bit line BL, while M0 conductive pattern 332 corresponds to the VSS power rail. (See also: Regarding...) Figure 3B The M0 conductive patterns 331 and 332 extend along the X-axis. The M0 conductive pattern 333 corresponds to the word line pattern of the M1 conductive pattern 335 electrically coupled to the M1 layer through the V0 via 334. The M1 conductive pattern 335 corresponds to the word line and extends along the Y-axis.

[0065] Figure 3C The configuration in the example, where MD contact structures 326 and 327 are correspondingly coupled to bit line BL (M0 conductive pattern 331) and VSS power rail (M0 conductive pattern 332), is an example, and corresponds to, for example Figure 2A ON configuration 1g.

[0066] When transistor 321 is configured to have Figure 2B When the ON configuration is 1h, the MD contact structures 326 and 327 are correspondingly coupled to the VSS power rail (M0 conductive pattern 332) and the bit line BL (M0 conductive pattern 331).

[0067] When transistor 321 is configured to have Figure 2C When the OFF configuration is 0f, the MD contact structures 326 and 327 are both coupled to the VSS power rail (M0 conductive pattern 332).

[0068] When transistor 321 is configured to have Figure 2D When the OFF configuration is 0i, both MD contact structures 326 and 327 are coupled to the local line BL (M0 conductive pattern 331).

[0069] When transistor 321 is configured to have Figure 2E In OFF configuration 0a, MD contact structures 326 and 327 are not coupled to the VSS power rail (M0 conductive pattern 332) and bit line BL (M0 conductive pattern 331). For example, VD vias 328 and 329 are omitted.

[0070] When transistor 321 is configured to have Figure 2F When configured OFF 0a, the MD contact structure 326 is not coupled to the bit line BL (M0 conductive pattern 331). For example, the VD via 328 is omitted.

[0071] When transistor 321 is configured as Figure 2G When configured OFF 0a, the MD contact structure 327 is not coupled to the VSS power rail (M0 conductive pattern 332). For example, the VD via 329 is omitted. According to some embodiments, one or more of the advantages described herein can be achieved by the memory device 300C.

[0072] Figure 4 This is a schematic diagram of the layout of the circuit regions of a memory device 400 according to some embodiments. In some embodiments, the memory device 400 corresponds to one or more of memory devices 100, 300A, 300B, and 300C. For simplicity, Figure 1 , Figures 2A-2G , Figures 3A-3C , Figure 4 The corresponding components are specified by the same reference numerals.

[0073] The memory device 400 includes multiple instances of circuit regions, and these instances are arranged adjacent to each other along the X and Y axes. Some instances of the circuit regions are, for example, in... Figure 4 The elements are labeled as Unit 0, Unit 1, Unit 2, and Unit 3. For simplicity, in... Figure 4 Other instances of circuit regions are omitted. For example... Figure 4 As shown, elements 0, 1, 2, and 3 are arranged adjacent to each other along their corresponding boundaries. Each of elements 0, 1, 2, and 3 corresponds to having Figure 4The ROM unit 405 is arranged as shown. In at least one embodiment, the ROM unit 405 is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium. Figure 4 In the example configuration, ROM unit 405 is a 4×4 ROM unit comprising 16-bit units arranged in four rows along the X-axis and four columns along the Y-axis. Other dimensions and / or sizes of the ROM unit are within the range of various embodiments.

[0074] ROM cell 405 includes a boundary 410 (i.e., cell boundary, also referred to as pr boundary) through which multiple instances of ROM cell 405 are placed adjacent to each other, as described herein. For example, boundary 410 corresponds to the boundary of each of cells 0, 1, 2, and 3. Boundary 410 includes edges 411, 412, 413, and 414. Edges 411 and 412 extend along the X-axis, and edges 413 and 414 extend along the Y-axis. In some embodiments, the X-axis is an example of one of a first direction and a second direction, and the Y-axis is an example of the other of the first direction and the second direction. Edges 411, 412, 413, and 414 are joined together to form a closed boundary 410. In the placement and routing operations described herein (also referred to as “Automatic Placement and Routing (APR)”), in the layout of memory device 400 or its ROM array, multiple instances of ROM cell 405 are placed adjacent to each other at their respective boundaries. The rectangle or square of boundary 410 is merely an example.

[0075] ROM cell 405 includes active regions OD0-OD3 and gates G0-G3. The active regions OD0-OD3 are spaced apart from each other along the Y-axis. The active regions OD0-OD3 extend continuously along the X-axis within boundary 410 and also extend beyond boundary 410 into further instances of ROM cells 405 arranged adjacent to each other along the X-axis. For example, when ROM cell 405 corresponds to cell_0, the active regions OD0-OD3 extend continuously through at least cell_0 and cell_1. ROM cell 405 does not have an isolation structure that divides any of the active regions OD0-OD3 into electrically isolated portions. Active regions are sometimes referred to as oxide-defined (OD) regions and are schematically shown with the label "OD". Figure 4 In the example configuration, all active regions OD0-OD3 are N-type or NMOS, i.e., configured to form N-type or NMOS transistors. In at least one embodiment, each active region OD0-OD3 corresponds to about Figure 3B The active region (OD) is described.

[0076] Gates G0-G3 extend along the Y-axis across active regions OD0-OD3. As described herein, gates G0-G3 are spaced apart from each other by gate pitch (CPP) along the X-axis. Each of gates G0-G3 is a conductive gate comprising a conductive material (e.g., polysilicon) and is schematically shown with the label “PO”. Other conductive materials for the gates (e.g., metals) are available in various embodiments. Gates G0-G3, together with each active region OD0-OD3, are configured as transistors coupled in series, as per [reference to...]. Figure 3B All gates G0-G3 are functional gates, which, together with the active regions OD0-OD3, are configured as transistors for storing data. The transistors in ROM cell 405 correspond to the transistors related to... Figure 5A The transistors T1-T16 are described. ROM cell 405 does not contain non-conductive material and / or does not form dummy gates for transistors configured for storing data.

[0077] ROM cell 405 further includes cleaved gate (or cleaved polysilicon) regions CPO11, CPO12, CPO21, CPO22, CPO31, and CPO32 extending along the X-axis across gates G0-G3. The cleaved gate regions are schematically shown under the label "CPO". The cleaved gate regions correspond to areas where no gate is formed.

[0078] For example, the lengths of gates G0 and G1 along the Y-axis are defined by diced gate regions CPO11 and CPO31, which correspondingly define the opposite ends of each gate G0 and G1. Dictated gate regions CPO21 and CPO22 are aligned along the X-axis and spaced apart from each other. Gates G0 and G1 extend continuously along the Y-axis, passing through the space between diced gate regions CPO21 and CPO22.

[0079] The gate region CPO22 cuts or separates the gate G2 into two physically disconnected gate portions 421 and 422, and also cuts or separates the gate G3 into two physically disconnected gate portions 431 and 432. However, the physically disconnected gate portions 421 and 422 are electrically coupled to each other through, for example, word lines WL2 in the M1 layer, and the physically disconnected gate portions 431 and 432 are still electrically coupled to each other through, for example, word lines WL3 in the M1 layer.

[0080] The cut gate regions CPO11 and CPO12 are aligned along the X-axis and spaced apart from each other. In some embodiments, the center lines of the cut gate regions CPO11 and CPO12 coincide with the edge 412 of the boundary 410. The gate portions 421 and 431 of the corresponding gates G2 and G3 extend continuously along the Y-axis, passing through the space between the cut gate regions CPO11 and CPO12, and entering another instance of the ROM cell 405 adjacent to the ROM cell 405 along the edge 412. For example, when the ROM cell 405 corresponds to cell_0, the gate portions 421 and 431 of the corresponding gates G2 and G3 extend continuously from cell_0 to cell_2. The lengths of the gate portions 421 and 431 of the corresponding gates G2 and G3 (including portions in cell_0 and cell_2) are the same as or substantially the same as the lengths of the gates G0 and G1.

[0081] The diced gate regions CPO31 and CPO32 are aligned along the X-axis and spaced apart from each other. In some embodiments, the center lines of the diced gate regions CPO31 and CPO32 coincide with the edge 411 of the boundary 410. The gate portions 422 and 432 of the corresponding gates G2 and G3 extend continuously along the Y-axis across the space between the diced gate regions CPO31 and CPO32, entering another instance of the ROM cell 405 adjacent to the ROM cell 405 along the edge 411. For example, when the ROM cell 405 corresponds to cell_2, the gate portions 422 and 432 of the corresponding gates G2 and G3 extend continuously from cell_2 to cell_0. The lengths of the gate portions 422 and 432 of the corresponding gates G2 and G3 (including portions in cell_0 and cell_2) are the same or substantially the same as the lengths of the gates G0 and G1. In some embodiments, the staggered arrangement of the described diced gate regions results in the gate portions having the same or substantially the same length, and / or reduces the polysilicon extension effect (PXE).

[0082] ROM unit 405 further includes an MD contact structure. Figure 4 For simplicity, the MD contact structures on active regions OD0 are designated as MD0-MD4, while the MD contact structures on active regions OD1-OD3 are not specified. In at least one embodiment, the MD contact structure on each active region OD0-OD3 corresponds to the structure with respect to... Figure 3B The described contact structures are MD0-MD4. The MD contact structures are spaced apart from each other along the X-axis by the gate pitch (CPP) and are arranged alternately with gates G0-G3 along the X-axis. The MD contact structures are schematically shown with the label "MD".

[0083] A first set of MD contact structures, including MD contact structure MD0 (and the underlying source / drain), is arranged along edge 413 of boundary 410 and configured to be shared with another instance of ROM cell 455 adjacent to ROM cell 405 along edge 413. For example, when ROM cell 405 corresponds to cell_0, the first set of MD contact structures along edge 413 is shared by cell_0 and cell_1. In other words, cell_0 and cell_1 are directly adjacent without a gate or dummy gate between them. In at least one embodiment, the MD contact structures in the first set have a centerline coinciding with edge 413. A second set of MD contact structures, including MD contact structure MD4 (and the underlying source / drain), is arranged along edge 414 of boundary 410 and configured to be shared with another instance of ROM cell 455 adjacent to ROM cell 405 along edge 414. In at least one embodiment, the MD contact structures in the second set have a centerline coinciding with edge 414.

[0084] exist Figure 4 In the example configuration, the ROM cell 405 has a width of 4 CPP along the X-axis. According to other methods, this width is advantageously reduced compared to a 4×4 ROM cell, and this is achieved by configuring the active regions OD0-OD3 as continuous without being interrupted or broken by one or more isolation structures within and / or on the boundary 410 of the ROM cell 405. A 4×4 ROM cell according to another method includes isolation structures on active regions extending along the Y-axis edge and has a width of 5 CPP along the X-axis. A 4×4 ROM cell according to yet another method includes isolation structures not only extending along the Y-axis edge but also on active regions within the ROM cell, and has a width of 6 CPP along the X-axis. A 4CPP 4×4 ROM cell according to one or more embodiments achieves approximately 16.7% area reduction compared to a described 5CPP 4×4 ROM cell, or approximately 33.3% area reduction compared to a 6CPP 4×4 ROM cell according to other methods described herein. As described herein, the reduced width of the ROM cell according to some embodiments further advantageously reduces the bit line lengths of various bit lines.

[0085] ROM cell 405 further includes vias to gate vias VG0-VG3 that are electrically in contact with the corresponding gates G0-G3. The vias to gate vias are schematically shown with the label "VG".

[0086] ROM cell 405 also includes M0 conductive patterns 441-455 in the M0 layer. M0 conductive patterns 442, 447, 449, and 454 are configured with multiple bit lines BL0-BL3, and M0 conductive patterns 443, 446, 450, and 453 are configured with multiple VSS power rails. Bit lines BL0-BL3 and VSS power rails extend continuously along the X-axis through multiple adjacent instances of ROM cell 405. Each pair of bit lines and corresponding VSS power rails extends above the corresponding active region. For example, bit line BL0 and the corresponding VSS power rail (M0 conductive pattern 443) extend above the active region OD0.

[0087] M0 conductive patterns 452, 445, 451, and 444 are correspondingly configured with word line patterns. Word line patterns 444 and 445 are aligned along the X-axis and arranged on the same M0 track. Word line patterns 451 and 452 are aligned along the X-axis and arranged on the same M0 track. Word line patterns 452, 445, 451, and 444 are respectively electrically contacted with VG vias VG0-VG3, thereby electrically coupled to gates G0-G3. Word line patterns 452, 445, 451, and 444 are arranged in a manner similar to that described above. Figure 3C In the described manner, the corresponding word lines WL0-WL3 (not shown) in the M1 layer are electrically coupled through corresponding V0 vias (not shown). In the example where ROM cell 405 corresponds to cell_0, the word line WL0 in the M1 layer extends continuously along the Y-axis above the word line pattern 452 and a similar word line pattern in cell_2, and is electrically coupled through corresponding V0 vias to the word line pattern 452 and the similar word line pattern in cell_2. As a result, all transistors configured by gate G0 in cells_0 and cell_2 are electrically coupled to the word line WL0.

[0088] exist Figure 4 In the example configuration, ROM cell 405 has not yet included a via-to-device (VD) via electrically contacting one or more MD contact structures. This is because, according to some embodiments, ROM cell 405 is a blank or unprogrammed ROM cell. In some embodiments, during the design phase, multiple instances of ROM cell 405 (such as...) are... Figure 4 Cells _0, _1, _2, and _3 (shown in the diagram) are arranged adjacent to each other (e.g., in an APR operation) to develop a blank or unprogrammed ROM array corresponding to memory array 101. In a subsequent programming phase, the unprogrammed ROM array is programmed by configuring each individual bit cell in the ROM array to store logic "0" or logic "1" according to predetermined data to be stored in the ROM array, as shown in the diagram. Figures 2A-2G , Figures 3A-3C The above. Regarding Figures 5A-5E , Figures 6A-6F Further, specific, non-restrictive examples of ROM programming are described.

[0089] According to some embodiments, Figures 5A-5E Each includes a circuit diagram and a schematic diagram of the layout of the circuit area of ​​the memory device. Figures 5A-5E This shows a non-restrictive example of ROM programming using code mode 1, i.e., using about Figures 2A-2D The configuration is described, without using anything about Figures 2E-2G The configuration is described. For simplicity, Figure 1 , Figures 2A-2G , Figures 3A-3C , Figure 4 , Figures 5A-5E The corresponding components are specified by the same reference numerals.

[0090] Figure 5A This includes a circuit diagram of circuit area 500A and a layout diagram of ROM unit 505A corresponding to circuit area 500A. ROM unit 505A is a programmed example of unprogrammed ROM unit 405. ROM unit 505A includes transistors T1-T16, wherein transistors T1, T5, T9, and T13 are configured with gates G0-G3 and active region OD0 respectively; transistors T2, T6, T10, and T14 are configured with gates G10-G3 and active region OD1 respectively; transistors T3, T7, T11, and T15 are configured with gates G20-G3 and active region OD2 respectively; and transistors T4, T8, T12, and T16 are configured with gates G0-G3 and active region OD3 respectively.

[0091] ROM cell 505A is programmed so that transistors T1, T5, T9, and T13 store data or code 501; transistors T2, T6, T10, and T14 store data or code 502; transistors T3, T7, T11, and T15 store data or code 503; and transistors T4, T8, T12, and T16 store data or code 504. In each code 501-504, "0" represents logic "0" and "1" represents logic "1". For example, code 501 is "0000", corresponding to all transistors T1, T5, T9, and T13 storing logic "0". In another example, code 503 is "0010", corresponding to transistor T3 storing logic "0", transistor T7 storing logic "0", transistor T11 storing logic "1", and transistor T15 storing logic "0". Compared to ROM unit 405, ROM unit 505A also includes VD vias. Based on the data to be stored (codes 501-504), each VD via electrically couples the source / drain in the active regions OD0-OD3 to the corresponding bit line or power rail above the active region. VD vias 550-554 are located in... Figure 5AThe codes 501-504 are specified in the diagram, while other VD vias are not labeled for simplicity. In some embodiments, each of the codes 501-504 is programmed into the ROM cell 505A independently of the other codes. In an example ROM programming operation, the codes 501-504 are programmed sequentially, for example, from left to right or from right to left. For example, code 501 is programmed sequentially from right to left, starting with transistor T13.

[0092] Transistor T13 is programmed to store logic "0", corresponding to code mode 1. Figure 2C OFF configuration 0f or Figure 2D The OFF configuration 0i is selected for transistor T13. In at least one embodiment, the selection between OFF configuration 0f and OFF configuration 0i is based on another transistor (not shown) on bit line BL0, which is directly adjacent to the right side of transistor T13 and shares a common source / drain with transistor T13 (below the MD contact structure MD4). This other transistor has been programmed prior to transistor T13. If the programmed other transistor has a common source / drain coupled to the VSS power rail shared with transistor T13, then OFF configuration 0f is selected for transistor T13. If the programmed other transistor is coupled to bit line BL0 with the common source / drain shared with transistor T13, then OFF configuration 0i is selected for transistor T13. Figure 5A In the example configuration, transistor T13 is programmed to have an OFF configuration OFF. For this purpose, VD vias 553 and 554 are generated (e.g., by an EDA tool performing an APR operation) to couple the source / drain of transistor T13 accordingly to the VSS power rail 443 in ROM cell 505A. In at least one embodiment, VD via 554 is generated when another transistor to the right of transistor T13 is programmed, and VD via 553 is generated when transistor T13 is programmed.

[0093] Next, transistor T9 is programmed to store logic "0". Since the common source / drain of transistors T9 and T13 (below the MD contact structure MD3) is already coupled to the VSS power rail 443 via via VD 553, the OFF configuration 0f is selected to program transistor T9. To do this, via VD 552 is created to couple the other source / drain of transistor T9 (below the MD contact structure MD2) to the VSS power rail 443. Similarly, transistor T5 is programmed to store logic "0" by coupling the MD contact structure MD1 to the VSS power rail 443 via VD 551, and transistor T1 is programmed to store logic "0" by coupling the MD contact structure MD0 to the VSS power rail 443 via VD 550.

[0094] Code 502, or "0000", is programmed into transistors T2, T6, T10, and T14, starting with transistor T14, which is programmed to have OFF configuration 0i. As a result, the two source / drain terminals of transistor T14 are coupled to bitline BL1. Since the common source / drain of transistors T10 and T14 is coupled to bitline BL1 when transistor T14 is programmed, the other source / drain terminal of transistor T10 is also coupled to bitline BL1 to program logic "0" into transistor T10 according to OFF configuration 0i. Similarly, based on the programming configuration of transistor T10, transistor T6 is programmed to have OFF configuration 0i, and then transistor T2 is programmed to have OFF configuration 0i based on the programming configuration of transistor T6. The APR tool is configured to generate a set of VD vias (unnumbered) corresponding to OFF configuration 0i at all transistors T2, T6, T10, and T14, as shown in ROM cell 505A.

[0095] Code 503, or "0010", is programmed into transistors T3, T7, T11, and T15, starting with transistor T15, which is programmed to have an OFF configuration of 0i. As a result, the two source / drain terminals of transistor T15 are coupled to bitline BL2. Since the common source / drain of transistors T11 and T15 is coupled to bitline BL2 when transistor T15 is programmed, the other source / drain terminal of transistor T11 is coupled to the VSS power rail, so as to... Figure 2A The ON configuration 1g programs logic "1" into transistor T11. Since the common source / drain of transistors T7 and T11 is coupled to the VSS power rail when transistor T11 is programmed, the other source / drain of transistor T7 is also coupled to the VSS power rail to program logic "0" into transistor T7 according to the OFF configuration 0f. Similarly, based on the programming configuration of transistor T7, transistor T3 is programmed with the OFF configuration 0f. The APR tool is configured to generate a set of VD vias (unnumbered) corresponding to the programming configurations of transistors T3, T7, T11, and T15, as shown in ROM cell 505A.

[0096] Code 504, or "0010", is programmed into transistors T4, T8, T12, and T16, starting with transistor T16, which is programmed to have an OFF configuration of 0f. As a result, both source / drain terminals of transistor T16 are coupled to the VSS power rail. Since the common source / drain of transistors T12 and T16 is coupled to the VSS power rail when transistor T16 is programmed, the other source / drain terminal of transistor T12 is coupled to bitline BL3 to allow for... Figure 2BThe ON configuration 1h programs logic "1" into transistor T12. Since the common source / drain of transistors T8 and T12 is coupled to bitline BL3 when transistor T12 is programmed, the other source / drain of transistor T8 is also coupled to bitline BL3 to program logic "0" into transistor T8 according to the OFF configuration 0i. Similarly, based on the programming configuration of transistor T8, transistor T4 is programmed with the OFF configuration 0i. The APR tool is configured to generate a set of VD vias (unnumbered) corresponding to the programming configurations of transistors T4, T8, T12, and T16, as shown in ROM cell 505A.

[0097] exist Figure 5A In this example, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming the data "0000" by configuring all transistors T1, T5, T9, and T13 with OFF configuration OFF, while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data "0000" by configuring all transistors T2, T6, T10, and T14 with OFF configuration OFF 0i. In at least one embodiment, group programming is performed to program multiple transistors simultaneously, rather than programming one transistor at a time. For example, two configurations (e.g., two sets of VD vias) are pre-developed and stored (e.g., in a library) for the data "0000". One of the pre-developed configurations corresponds to... Figure 5A The programming configuration of transistors T1, T5, T9, and T13 (e.g., VD via group 550-554), and another corresponding pre-developed configuration. Figure 5A Programming configurations for transistors T2, T6, T10, and T14 (e.g., corresponding VD via groups). When the data "0000" is to be programmed to a string of one or four transistors, one of the pre-developed configurations is selected and used to program the string of four transistors simultaneously. Based on previously programmed directly adjacent transistors, one of the pre-developed configurations to be used is selected in a manner similar to that described regarding the programming of transistor T13.

[0098] Similarly, the programming configurations for transistors T3, T7, T11, and T15 include examples of programming data "0010," while the programming configurations for transistors T4, T8, T12, and T16 include examples of programming the same data "0010." In at least one embodiment, for group programming, two configurations (e.g., two sets of VD vias) are pre-developed and stored (e.g., in a library) for the data "0010." One of the pre-developed configurations corresponds to... Figure 5A The programming configurations of transistors T3, T7, T11, and T15, while another pre-developed configuration corresponds to... Figure 3AProgramming configurations for transistors T4, T8, T12, and T16. When the data "0010" is to be programmed to a group or a string of four transistors, one of the pre-developed configurations is selected and used to program the string of four transistors simultaneously. Based on previously programmed directly adjacent transistors, one of the pre-developed configurations to be used is selected in a manner similar to that described regarding the programming of transistor T13. The described example of group programming of four transistors is merely an example. According to some embodiments, any other number of transistors can be used for group programming.

[0099] Figure 5B This includes a circuit diagram of circuit area 500B and a schematic diagram of the layout corresponding to circuit area 500B. This layout includes a portion of ROM units 505A and 505B. Like ROM unit 505A, ROM unit 055B is a programmed instance of an unprogrammed ROM unit 405.

[0100] ROM cell 505B has a boundary 510 corresponding to boundary 410. ROM cell 505B is placed adjacent to ROM cell 505A along the common edge of boundary 510 and boundary 410. The common edge is edge 413 of boundary 410. ROM cells 505A and ROM cell 505B share a common set of MD contact structures, including MD contact structure MD0, and are arranged on edge 413. In other words, ROM cells 505A and ROM cell 505B share a common source / drain below a common set of MD contact structures.

[0101] The ROM unit 505B includes 16 transistors arranged in a 4×4 configuration. Figure 5B Transistors T17-T20 of ROM cell 505B are shown, while other transistors are omitted for simplicity. Transistors T17-T20 of ROM cell 505B correspond to transistors T13-T16 of ROM cell 505A. Transistors T17-T20 of ROM cell 505B and transistors T1-T4 of ROM cell 505A are directly adjacent to each other and share a common source / drain group arranged on edge 413. Transistors T17-T20 are respectively configured with gate GK and active regions OD0-OD3. In some embodiments, Figure 5B The gate GK in the middle corresponds to about Figure 3B The gate GK is described. In the example embodiment, ROM cell 505A corresponds to Figure 4 Unit _0 in the ROM unit 505B corresponds to unit _1. The active regions OD0-OD3, bit lines BL0-BL3, and VSS power rails 443, 446, 450, and 453 extend continuously along the X-axis through ROM units 505A and ROM units 505B.

[0102] ROM cell 505B is programmed to store codes 506-509. For simplicity, the data stored by transistors T17-T20 is shown below. Figure 5B In codes 506-509, the data to be stored by other transistors in ROM cell 505B is omitted. The logic "0" in code 506 is programmed into transistor T17 based on the programming configuration of transistor T1, or based on the electrical connection of the common source / drain of transistor T1 and its directly adjacent transistor T17. Since the common source / drain of transistors T1 and T17 is coupled to the VSS power rail 443 via via VD 550 when transistor T1 is programmed, the other source / drain of transistor T17 is also coupled to the VSS power rail 443 to program the logic "0" into transistor T17 according to the OFF configuration 0f. For this purpose, the APR tool is configured to generate via 55K to electrically couple the MD contact structure MDK above the other source / drain of transistor T17 to the VSS power rail 443.

[0103] Similarly, based on the programming configuration of transistor T2, transistor T18 is programmed with OFF configuration 0i, and based on the programming configuration of transistor T3, transistor T19 is programmed with OFF configuration 0f. The APR tool is configured to generate corresponding VD vias corresponding to the programming configurations of transistors T18 and T19, as shown in ROM cell 505B.

[0104] Based on the programming configuration of transistor T4, the logic "1" in code 509 is programmed into transistor T20. Since the common source / drain of transistors T4 and T20 is coupled to bit line BL3 when transistor T4 is programmed, another source / drain in transistor T20 is coupled to VSS power rail 453 to program the logic "1" into transistor T20 according to ON configuration 1g. For this purpose, the APR tool is configured to generate a VD via 559, which electrically couples the MD contact structure 558 above the other source / drain of transistor T20 to VSS power rail 453. In some embodiments, operations are performed on ROM cells 505B and / or other ROM cells in the ROM array regarding... Figure 5A Described group programming.

[0105] Figure 5C This includes a circuit diagram of circuit area 500C and a layout diagram of ROM cell 505C corresponding to circuit area 500C. ROM cell 505C is a programmed example of unprogrammed ROM cell 405.

[0106] Codes 581-584 are similar to Figures 5A-5BThe programming is performed in the manner described in transistors T1-T16 of ROM cell 505C. For example, to store code 581, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to have OFF configuration 0i, OFF configuration 0i, ON configuration 1g, and OFF configuration 0f, respectively. The APR tool is configured to generate a set of VD vias 564, 563, 562, 551, and 550 to correspond to the programming configurations of transistors T13, T9, T5, and T1, as shown in ROM cell 505C.

[0107] exist Figure 5C In this document, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming data “0100”, while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data “0100”. In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13 (or VD via groups 550, 551, 562, 563, and 564) and the programming settings of transistors T2, T6, T10, and T14 (or the corresponding VD via groups) are pre-developed and stored, for example, stored in a library, for group programming of data “0100”, as described herein.

[0108] Similarly, the programming configurations of transistors T3, T7, T11, and T15 include an example of programming data "0110", while the programming configurations of transistors T4, T8, T12, and T16 include another example of programming the same data "0110". In at least one embodiment, as described herein, the programming configurations (or corresponding VD via groups) of transistors T3, T7, T11, and T15 and the programming configurations (or corresponding VD via groups) of transistors T4, T8, T12, and T16 are pre-developed and stored, for example, in a library, for group programming of data "0110".

[0109] Figure 5D This includes a circuit diagram of circuit area 500D and a layout diagram of ROM cell 505D corresponding to circuit area 500D. ROM cell 505D is a programmed example of unprogrammed ROM cell 405.

[0110] Codes 586-589 are similar to Figures 5A-5B The programming is performed in the manner described in transistors T1-T16 of ROM cell 505D. For example, to store code 586, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to have OFF configuration 0i, OFF configuration 0i, OFF configuration 0i, and ON configuration 1g, respectively. The APR tool is configured to generate a set of VD vias 564, 563, 562, 571, and 550 to correspond to the programming configurations of transistors T13, T9, T5, and T1, as shown in ROM cell 505D.

[0111] exist Figure 5D In this document, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming data "1000", while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data "1000". In at least one embodiment, the programming configurations of transistors T1, T5, T9, and T13 (or VD via groups 550, 571, 562, 563, and 564) and the programming settings of transistors T2, T6, T10, and T14 (or their respective VD via groups) are pre-developed and stored, for example, in a library, for group programming of data "1000", as described herein.

[0112] Similarly, the programming configurations of transistors T3, T7, T11, and T15 include an example of programming data "1010", while the programming configurations of transistors T4, T8, T12, and T16 include another example of programming the same data "1010". In at least one embodiment, as described herein, the programming configurations (or corresponding VD via groups) of transistors T3, T7, T11, and T15 and the programming configurations (or corresponding VD via groups) of transistors T4, T8, T12, and T16 are pre-developed and stored, for example, in a library, for group programming of data "1010".

[0113] Figure 5E This includes a circuit diagram of circuit area 500E and a layout diagram of ROM cell 505E corresponding to circuit area 500E. ROM cell 505E is a programmed example of unprogrammed ROM cell 405.

[0114] Codes 591-594 are similar to Figures 5A-5B The programming is performed in the manner described in transistors T1-T16 of ROM cell 505E. For example, to store code 591, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to have OFF configuration 0f, OFF configuration 0f, ON configuration 1h, and ON configuration 1g, respectively. The APR tool is configured to generate a set of VD vias 554, 553, 552, 571, and 550 to correspond to the programming configurations of transistors T13, T9, T5, and T1, as shown in ROM cell 505E.

[0115] exist Figure 5EIn this document, the programming configurations of transistors T1, T5, T9, and T13 include an example of programming data "1100", while the programming configurations of transistors T2, T6, T10, and T14 include another example of programming the same data "1100". In at least one embodiment, as described herein, the programming configurations of transistors T1, T5, T9, and T13 (or VD via groups 550, 571, 552, 553, and 554) and the programming configurations of transistors T2, T6, T10, and T14 (or their corresponding VD via groups) are pre-developed and stored, for example, in a library, for group programming of data "1100".

[0116] Similarly, the programming configurations of transistors T3, T7, T11, and T15 include an example of programming data "1110", while the programming configurations of transistors T4, T8, T12, and T16 include another example of programming the same data "1110". In at least one embodiment, as described herein, the programming configurations (or corresponding VD via groups) of transistors T3, T7, T11, and T15 and the programming configurations (or corresponding VD via groups) of transistors T4, T8, T12, and T16 are pre-developed and stored, for example, in a library, for group programming of data "1110".

[0117] According to some embodiments, Figures 6A-6F Each includes a circuit diagram and a schematic diagram of the layout of the circuit area of ​​the memory device. Figures 6A-6F This shows a non-restrictive example of ROM programming using code mode 2, i.e., using about Figures 2A-2G The configuration is described. For simplicity, Figure 1 , Figures 2A-2G , Figures 3A-3C , Figure 4 , Figures 5A-5E , Figures 6A-6F The corresponding components are specified by the same reference numerals.

[0118] Figure 6A This includes a circuit diagram of circuit area 600A and a layout diagram of ROM unit 605A corresponding to circuit area 600A. ROM unit 605A is a programmed example of unprogrammed ROM unit 405.

[0119] Codes 601-604 are similar to Figures 5A-5B The method described above programs the transistors T1-T16 of the ROM unit 605A. For example, to store code 601, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to all have... Figure 2EOFF configuration 0a. Since all sources / drains of transistors T1, T5, T9, and T13 are electrically floating, the APR tool is configured to generate a set of five “zero” VD vias, i.e., no VD vias, for the five corresponding MD contact structures MD0-MD4 according to the programming configuration of transistors T1, T5, T9, and T13, as shown in ROM cell 605A.

[0120] To store code 602, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have corresponding... Figure 2E OFF configuration 0a in Figure 2E OFF configuration 0a, Figure 2G The OFF structure 0a and OFF configuration 0i are shown in the ROM cell 605A. The APR tool is configured to generate a set of VD vias for the three corresponding MD contact structures based on the programming configurations of transistors T2, T6, T10, and T14. These vias include VD vias 606 and 607 and three “zero” VD vias, i.e., no VD vias, as shown in the ROM cell 605A.

[0121] To store code 603, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have corresponding functions. Figure 2E OFF configuration 0a in Figure 2E OFF configuration 10a Figure 2F The OFF structure 0a and OFF configuration 0f are shown in the ROM cell 605A. The APR tool is configured to generate a set of VD vias for the three corresponding MD contact structures based on the programming configurations of transistors T3, T7, T11, and T15. These vias include VD vias 608 and 609 and three “zero” VD vias, i.e., no VD vias, as shown in the ROM cell 605A.

[0122] Code 604 is programmed into transistors T4, T8, T12, and T16 in the same way as transistors T1, T5, T9, and T13.

[0123] exist Figure 6A In the example, the programming configurations of transistors T1, T5, T9, and T13 include a first example with the programming data "0000"; the programming configurations of transistors T2, T6, T10, and T14 include a second example with the same data "0000"; and the programming configurations of transistors T3, T7, T11, and T15 include a third example with the same data "0000". According to... Figures 2C-2GThe various OFF configurations described, and other examples of programming the same data "0000" according to the configurations available in code mode 2, are within the scope of various embodiments. In at least one embodiment, as described herein, programming configurations for transistors T1, T5, T9, T13, programming configurations for transistors T2, T6, T10, T14, programming configurations for transistors T3, T7, T11, T15, and / or one or more further examples of programming data "0000" are pre-developed and stored (e.g., stored in a library) for group programming of data "000".

[0124] In some embodiments, code mode 2 provides more options for programming the same data or code compared to code mode 1, which advantageously increases the flexibility of circuit design. In at least one embodiment, code mode 2 sometimes requires fewer VD vias than code mode 1 to program the same data or code, which advantageously reduces the requirements for wiring resources and / or reduces parasitic capacitance, which in turn improves performance.

[0125] Figure 6B This includes a circuit diagram of circuit area 600B and a layout diagram of ROM unit 605B corresponding to circuit area 600B. ROM unit 605B is a programmed example of unprogrammed ROM unit 405.

[0126] Codes 611-614 are similar to Figures 5A-5B The method described is programmed into transistors T1-T16 of ROM unit 605B. For example, code 611 is related to... Figure 6A The code 601 described is programmed into transistors T1, T5, T9, and T13 in the same way.

[0127] To store code 612, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have corresponding... Figure 2F The OFF configuration is 0a, ON configuration is 1h, OFF configuration is 0i, and OFF configuration is 0i. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T2, T6, T10, and T14, as shown in ROM cell 605B.

[0128] To store code 613, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have corresponding... Figure 2G The OFF configuration is 0a, ON configuration is 1g, OFF configuration is 0f, and OFF configuration is 0f. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T3, T7, T11, and T15, as shown in ROM cell 605B.

[0129] To store code 614, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have corresponding... Figure 2G OFF configuration 0a, ON configuration 1g, Figure 2F OFF configuration 0a in Figure 2E The OFF configuration is 0a. The APR tool is configured to generate a set of VD vias based on the programming configurations of transistors T4, T8, T12, and T16, including two "zero" VD vias, two VD vias, and another "zero" VD via, as shown in ROM cell 605B.

[0130] exist Figure 6B In this embodiment, the programming configurations of transistors T2, T6, T10, and T14 include a first example of programming data "0010"; the programming configurations of transistors T3, T7, T11, and T15 include a second example of programming the same data "0010"; and the programming configurations of transistors T4, T8, T12, and T16 include a third example of programming the same data "0010". Other examples of programming the same data "0010" are within the scope of various embodiments. In at least one embodiment, as described herein, one or more further examples of programming configurations of transistors T2, T6, T10, and T14, programming configurations of transistors T3, T7, T11, and T15, programming configurations of transistors T4, T8, T12, and T16, and / or programming data "0010" are pre-developed and stored (e.g., stored in a library) for group programming of data "0010".

[0131] Figure 6C This includes a circuit diagram of circuit area 600C and a layout diagram of ROM cell 605C corresponding to circuit area 600C. ROM cell 605C is a programmed example of unprogrammed ROM cell 405.

[0132] Codes 621-624 are similar to Figures 5A-5B The method described is programmed into transistors T1-T16 of ROM cell 605C. For example, code 621 is related to... Figure 6A The code 601 described is programmed into transistors T1, T5, T9, and T13 in the same way.

[0133] To store code 622, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have corresponding... Figure 2E OFF configuration 0a in Figure 2F The OFF configuration is 0a, the ON configuration is 1h, and the OFF configuration is 0i. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, based on the programming configurations of transistors T2, T6, T10, and T14, as shown in ROM cell 605C.

[0134] To store code 623, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have corresponding... Figure 2E OFF configuration 0a in Figure 2G The OFF configuration is 0a, the ON configuration is 1g, and the OFF configuration is 0f. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, based on the programming configurations of transistors T3, T7, T11, and T15, as shown in ROM cell 605C.

[0135] To store code 624, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have corresponding... Figure 2E OFF configuration 0a in Figure 2G OFF configuration 0a, ON configuration 1g, Figure 2F The OFF configuration is 0a. The APR tool is configured to generate a set of VD vias based on the programming configurations of transistors T4, T8, T12, and T16, including a "zero" VD via, two VD vias, and two additional "zero" VD vias, as shown in ROM cell 605C.

[0136] exist Figure 6C In this embodiment, the programming configurations of transistors T2, T6, T10, and T14 include a first example of programming data "0100"; the programming configurations of transistors T3, T7, T11, and T15 include a second example of programming the same data "0100"; and the programming configurations of transistors T4, T8, T12, and T16 include a third example of programming the same data "0100". Other examples of programming the same data "0100" are within the scope of various embodiments. In at least one embodiment, as described herein, one or more further examples of programming configurations of transistors T2, T6, T10, and T14, programming configurations of transistors T3, T7, T11, and T15, programming configurations of transistors T4, T8, T12, and T16, and / or programming data "0100" are pre-developed and stored (e.g., stored in a library) for group programming of data "0100".

[0137] Figure 6D This includes a circuit diagram of circuit area 600D and a layout diagram of ROM cell 605D corresponding to circuit area 600D. ROM cell 605D is a programmed example of unprogrammed ROM cell 405.

[0138] Codes 631-634 are similar to Figures 5A-5B The method described is programmed into transistors T1-T16 of ROM cell 605D. For example, code 631 is related to... Figure 6AThe code 601 described is programmed into transistors T1, T5, T9, and T13 in the same way.

[0139] To store code 632, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have corresponding... Figure 2G The OFF configuration is 0a, ON configuration is 1g, ON configuration is 1h, and OFF configuration is 0i. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T2, T6, T10, and T14, as shown in ROM cell 605D.

[0140] To store code 633, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have corresponding... Figure 2F The OFF configuration is 0a, ON configuration is 1h, ON configuration is 1g, and OFF configuration is 0f. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T3, T7, T11, and T15, as shown in ROM cell 605D.

[0141] To store code 634, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have corresponding... Figure 2F The OFF configuration is 0a, ON configuration is 1h, ON configuration is 1g, and OFF configuration is 0a. The APR tool is configured to generate a set of VD vias based on the programming configurations of transistors T4, T8, T12, and T16, including a "zero" VD via, three VD vias, and another "zero" VD via, as shown in ROM cell 605D.

[0142] exist Figure 6D In this embodiment, the programming configurations of transistors T2, T6, T10, and T14 include a first example of programming data "0110"; the programming configurations of transistors T3, T7, T11, and T15 include a second example of programming the same data "0110"; and the programming configurations of transistors T4, T8, T12, and T16 include a third example of programming the same data "0110". Other examples of programming the same data "0110" are within the scope of various embodiments. In at least one embodiment, as described herein, one or more further examples of programming configurations of transistors T2, T6, T10, and T14, programming configurations of transistors T3, T7, T11, and T15, programming configurations of transistors T4, T8, T12, and T16, and / or programming data "0110" are pre-developed and stored (e.g., stored in a library) for group programming of data "0110".

[0143] Figure 6EThis includes a circuit diagram of circuit area 600E and a layout diagram of ROM cell 605E corresponding to circuit area 600E. ROM cell 605E is a programmed example of unprogrammed ROM cell 405.

[0144] Codes 641-644 are similar to Figures 5A-5B The described method is used to program the transistors T1-T16 of ROM cell 605E. For example, to store code 641, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to have corresponding values. Figure 2E OFF configuration 0a in Figure 2E OFF configuration 0a, Figure 2G The OFF configuration is 0a, and the ON configuration is 1g. The APR tool is configured to generate a set of VD vias, including two VD vias and three "zero" VD vias, based on the programming configurations of transistors T1, T5, T9, and T13, as shown in ROM cell 605E.

[0145] To store code 642, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have corresponding... Figure 2E OFF configuration 0a in Figure 2E OFF configuration 10a Figure 2F The OFF configuration is 0a, and the ON configuration is 1h. The APR tool is configured to generate a set of VD vias, including two VD vias and three "zero" VD vias, based on the programming configurations of transistors T2, T6, T10, and T14, as shown in ROM cell 605E.

[0146] The programming configurations of transistors T1, T5, T9, and T13 include a first example of programming data "1000", and the programming configurations of transistors T2, T6, T10, and T14 include a second example of programming the same data "1000". Other examples of programming the same data "1000" are within the scope of various embodiments. In at least one embodiment, as described herein, programming configurations of transistors T1, T5, T9, and T13, programming configurations of transistors T2, T6, T10, and T14, and / or one or more further examples of programming data "1000" are pre-developed and stored (e.g., stored in a library) for group programming of data "1000".

[0147] To store code 643, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have corresponding... Figure 2F The OFF configuration is 0a, the ON configuration is 1h, the OFF configuration is 0i, and the ON configuration is 1g. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T3, T7, T11, and T15, as shown in ROM cell 605E.

[0148] To store code 644, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have corresponding... Figure 2F The OFF configuration is 0a, the ON configuration is 1g, the OFF configuration is 0f, and the ON configuration is 1h. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T4, T8, T12, and T16, as shown in ROM cell 605E.

[0149] The programming configurations of transistors T3, T7, T11, and T15 include a first example of programming data "1010", and the programming configurations of transistors T4, T8, T12, and T16 include a second example of programming the same data "1010". Other examples of programming the same data "1010" are within the scope of various embodiments. In at least one embodiment, as described herein, programming configurations of transistors T3, T7, T11, and T15, programming configurations of transistors T4, T8, T12, and T16, and / or one or more further examples of programming data "1010" are pre-developed and stored (e.g., stored in a library) for group programming of data "1010".

[0150] Figure 6F This includes a circuit diagram of circuit area 600F and a layout diagram of ROM cell 605F corresponding to circuit area 600F. ROM cell 605F is a programmed example of unprogrammed ROM cell 405.

[0151] Codes 651-654 are similar to Figures 5A-5B The programming is performed in the manner described in transistors T1-T16 of ROM cell 605F. For example, to store code 651, transistors T13, T9, T5, and T1 are programmed sequentially from right to left to correspondingly have Figure 2E OFF configuration 0a in Figure 2F The OFF structure is 0a, the ON configuration is 1h, and the ON configuration is 1g. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, based on the programming configurations of transistors T1, T5, T9, and T13, as shown in ROM cell 605F.

[0152] To store code 652, transistors T14, T10, T6, and T2 are programmed sequentially from right to left to have corresponding... Figure 2E OFF configuration 0a in Figure 2GThe OFF configuration is 0a, the ON configuration is 1g, and the ON configuration is 1h. The APR tool is configured to generate a set of VD vias, including three VD vias and two "zero" VD vias, based on the programming configurations of transistors T2, T6, T10, and T14, as shown in ROM cell 605F.

[0153] The programming configurations of transistors T1, T5, T9, and T13 include a first example of programming data "1100", and the programming configurations of transistors T2, T6, T10, and T14 include a second example of programming the same data "1100". Other examples of programming the same data "1100" are within the scope of various embodiments. In at least one embodiment, as described herein, programming configurations of transistors T1, T5, T9, and T13, programming configurations of transistors T2, T6, T10, and T14, and / or one or more further examples of programming data "1100" are pre-developed and stored (e.g., stored in a library) for group programming of data "1100".

[0154] To store code 653, transistors T15, T11, T7, and T3 are programmed sequentially from right to left to have corresponding... Figure 2G The OFF configuration is 0a, the ON configuration is 1g, the ON configuration is 1h, and the ON configuration is 1g. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T3, T7, T11, and T15, as shown in ROM cell 605F.

[0155] To store code 654, transistors T16, T12, T8, and T4 are programmed sequentially from right to left to have corresponding... Figure 2F The OFF configuration is 0a, the ON configuration is 1h, the ON configuration is 1g, and the ON configuration is 1h. The APR tool is configured to generate a set of VD vias, including four VD vias and a "zero" VD via, based on the programming configurations of transistors T4, T8, T12, and T16, as shown in ROM cell 605F.

[0156] The programming configurations of transistors T3, T7, T11, and T15 include a first example of programming data "1110", and the programming configurations of transistors T4, T8, T12, and T16 include a second example of programming the same data "1110". Other examples of programming the same data "1110" are within the scope of various embodiments. In at least one embodiment, as described herein, programming configurations of transistors T3, T7, T11, and T15, programming configurations of transistors T4, T8, T12, and T16, and / or one or more further examples of programming data "1110" are pre-developed and stored (e.g., stored in a library) for group programming of data "1110".

[0157] Figure 7A This is a flowchart of a method 700A for generating a layout and manufacturing an IC device using the layout, according to some embodiments. According to some embodiments, method 700A can be implemented, for example, using the EDA system and / or integrated circuit (IC) manufacturing system described herein. Examples of layouts for method 700A include the layouts disclosed herein. Examples of IC devices manufactured according to method 700A include one or more memory devices disclosed herein, such as ROM devices. Method 700A includes operations 702 and 704.

[0158] In operation 702, a layout is generated, including at least one ROM cell having at least one active region continuously extending through the ROM cell, as described herein. Regarding Figures 7B-7C An example of operation 702 is described.

[0159] In operation 704, based on the layout, at least one of (A) one or more photolithographic exposures, (B) the fabrication of one or more semiconductor masks, or (C) the fabrication of one or more components in an IC device layer is performed. Regarding Figure 7D Example describing operation 704.

[0160] Figure 7B This is a flowchart of a method 700B for generating the layout of read-only memory (ROM) cells. Method 700B is executed at least in part by a processor. In some embodiments, method 700B is executed to generate ROM cells corresponding to ROM cells 405. Method 700B includes operations 710, 712, 714, 716, 718, and 720.

[0161] In operation 710, multiple active regions and multiple gates are arranged within the boundary of the ROM cell, wherein the multiple active regions extend continuously from inside the boundary across the boundary to the outside of the boundary. For example, as per [reference to...] Figure 4 The plurality of active regions OD0-OD3 and the plurality of gates G0-G3 are arranged in the boundary 410 of the ROM cell 405. The active regions OD0-OD3 extend continuously from inside the boundary 410 through the boundary 410 and extend to the outside of the boundary 410.

[0162] In operation 712, multiple contact structures are arranged above multiple active regions, wherein the multiple contact structures include at least one set of contact structures on the boundary edges. For example, as per [reference to...] Figure 4 The aforementioned method involves arranging multiple MD contact structures above the active regions OD0-OD3. The multiple MD contact structures include at least one set of MD contact structures on the edges of boundary 410 (e.g., edge 413 or edge 414).

[0163] In operation 714, a plurality of first vias are arranged above a plurality of gates. For example, as per [reference to...] Figure 4As described above, a plurality of VG vias VG0-VG3 are correspondingly arranged on the plurality of gates G0-G3.

[0164] In operation 716, a pair of bit lines and power rails are arranged in a metal layer and located on each of the multiple active regions. For example, as per [reference to...] Figure 4 As described above, in the M0 layer, pairs of bit lines BL0 and VSS power rails 443 are arranged above the active region OD0, and pairs of bit lines BL1 and VSS power rails 446 are arranged above the active region OD1, etc.

[0165] In operation 718, multiple word line patterns overlapping with multiple first vias are arranged in the metal layer and between adjacent active regions in the multiple active regions. For example, as per [reference to...] Figure 4 In the M0 layer, word line patterns 444 and 445 are arranged between adjacent active regions OD0 and OD1 to overlap with VG vias VG3 and VG1 respectively, and word line patterns 451 and 452 are arranged between adjacent active regions OD2 and OD3 to overlap with VG vias VG2 and VG0 respectively.

[0166] At operation 720, the layout of the obtained ROM cells is stored in a library or on a non-transitory computer-readable recording medium, for example, for subsequent retrieval and for generating the layout of the ROM array, as per [reference to...]. Figure 7C In some embodiments, the stored ROM cell 405 does not have a VD via, which, as described herein, will be added in a later ROM programming operation. According to some embodiments, one or more of the advantages described herein can be achieved through the ROM cell generated by method 700B.

[0167] Figure 7C This is a flowchart of a method 700C for generating a layout of a read-only memory (ROM) device. Method 700C is executed at least in part by a processor. In some embodiments, method 700C is executed to generate a layout of a ROM device corresponding to one or more memory devices and / or ROM devices described herein. Method 700C includes operations 730, 732, and 734.

[0168] In operation 730, multiple instances of ROM cells are repeatedly placed adjacent to each other to obtain the layout of the ROM device. Each ROM cell includes an active region extending continuously from one edge of the ROM cell to the opposite edge of the ROM cell without being interrupted or discontinuous by an isolation structure. For example, as per [reference to...] Figure 4The ROM cells 405 are arranged adjacent to each other in a repeating manner to obtain the layout of the memory device 400. The ROM cells 405 include active regions (e.g., any one of active regions OD0-OD3) that extend continuously from edge 413 of the ROM cells 405 to opposite edge 414 of the ROM cells 405 without being interrupted or discontinuous by isolation structures.

[0169] In operation 732, vias are generated in multiple instances of the ROM cell according to the data to be stored in the ROM device. For example, as per [reference to...] Figures 5A-5E , Figures 6A-6F As described in one or more of the above, VD vias are added to various bit cells of the instance of ROM cell 405 according to the data to be stored. To program the bit cell to store logic "1", two VD vias are added to couple one source / drain of the transistor in the bit cell to bit line BL, and to connect the other source / drain of the transistor to the VSS power rail, as per [reference to...]. Figure 2A , Figure 2B As described above. To program a bit cell to store logic "0", two VD vias are added to couple the source / drain of the transistor in the bit cell to the bit line BL, or to couple the source / drain of the transistor to the VSS power rail, as per [reference needed]. Figure 2C , Figure 2D As stated above. Alternatively, in order to program bit cells to store logic "0", as regarding Figure 2E The method described above involves either not adding a VD via, or adding only one VD via to couple one source / drain of the transistor in the bit cell to the bit line BL or VSS power rail, as per the appendix. Figure 2F , Figure 2G In some embodiments, bit cells are programmed sequentially along bit lines, or group programming is performed to program multiple bit cells simultaneously.

[0170] In operation 734, the layout of the obtained programmable ROM device is stored on a non-transitory computer-readable recording medium, for example, for subsequent retrieval and use in the manufacture of the ROM device, as per [reference to...]. Figure 7D According to some embodiments, one or more advantages described herein can be achieved through the layout of the ROM device generated by method 700C.

[0171] Figure 7D This is a flowchart of a method 700D for manufacturing a ROM device according to some embodiments. In some embodiments, method 700D is performed to manufacture a ROM device corresponding to one or more memory devices and / or ROM devices described herein. Method 700D includes operations 740, 742, and 744.

[0172] In operation 740, a plurality of active regions extending continuously along a first direction are formed on the substrate. For example, as per [reference to...] Figure 3C The example active region is formed along the X-axis on substrate 320, corresponding to the source / drain 322, 323 and the channel therebetween. In some embodiments, the active region comprises one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.), a dopant material (e.g., boron (B), phosphorus (P), arsenic (As), gallium (Ga), or other suitable materials). In some embodiments, the active region comprises a nanosheet structure, for example, a continuous volume of one or more layers of one or more semiconductor materials. In various embodiments, a single nanosheet layer comprises a single monolayer or multiple monolayers of a given semiconductor material.

[0173] In operation 742, a plurality of gates are formed above a plurality of active regions, extending in a second direction transverse to the first direction. The plurality of gates, together with the plurality of active regions, are configured to store data in a plurality of transistors. For example, as per [reference to...] Figure 3C The example gate 325 extends along the Y-axis and is formed above the active region to configure transistor 321. In some embodiments, the gate is part of a gate structure and includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials. The gate structure also includes a gate dielectric layer comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials with a k value less than 3.8, or high-k materials with a k value greater than 3.8, such as alumina (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium dioxide (TiO2).

[0174] Multiple active regions, multiple gates, and multiple transistors are arranged in multiple instances of a circuit region, which includes at least four adjacent transistors in a first direction. For example, as per [reference to...] Figure 4 The circuit region comprises various active regions, gates, and transistors arranged in multiple instance cells_0 to_3 (e.g., ROM cell 405). ROM cell 405 includes four transistors adjacent to each other along the X-axis (e.g., regarding...). Figure 5A The transistors described are T1, T5, T9, and T13.

[0175] At least one active region is formed among multiple active regions, including at least one active region between adjacent instances in multiple instances where no isolation structure is formed. For example, as regarding Figure 5B As stated above, no isolation structure is formed in any active region OD0-OD3 between adjacent instances 505A and 505B of ROM unit 405.

[0176] In operation 744, one or more vias are formed on one or more sources / drains in multiple active regions, based on the data to be stored in the ROM device. For example, as per [reference to...] Figure 3C The aforementioned, one or more of the VD vias 328 and 329 are formed to couple the corresponding source / drain 322 and 323 to bit lines BL or VSS power rails, for example, in the M0 layer. Regarding Figures 5A-5E , Figures 6A-6F Various examples of VD vias formed according to the data to be stored are described. Therefore, the ROM device is programmed. In at least one embodiment, one or more advantages described herein can be achieved by a ROM device manufactured according to method 700D.

[0177] The described methods include example operations, but they do not necessarily need to be performed in the order shown. Operations may be added, substituted, altered in order, and / or eliminated as appropriate, within the spirit and scope of embodiments of the invention. Embodiments combining different features and / or different embodiments are within the scope of the invention and will be apparent to those skilled in the art upon review of this application.

[0178] In some embodiments, at least one of the methods discussed above is performed, in whole or in part, by at least one EDA system. In some embodiments, the EDA system may be used as part of the design room of the IC manufacturing system discussed below.

[0179] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0180] In some embodiments, EDA system 800 includes an APR system. The design layout methods described herein represent wiring arrangements according to one or more embodiments, which, according to some embodiments, can be implemented, for example, using EDA system 800.

[0181] In some embodiments, the EDA system 800 is a general-purpose computing device including a hardware processor 802 and a non-transitory computer-readable recording medium 804. Among other things, the recording medium 804 is encoded with stored computer program code 806, i.e., a set of executable instructions. The instructions 806, executed by the hardware processor 802, represent (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter, the processes and / or methods) according to one or more embodiments.

[0182] Processor 802 is electrically coupled to computer-readable recording medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is also electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and computer-readable recording medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 encoded in computer-readable recording medium 804, so that system 800 can be used to perform part or all of the process and / or method. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0183] In one or more embodiments, the computer-readable recording medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable recording medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable recording medium 804 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0184] In one or more embodiments, recording medium 804 stores computer program code 806 configured to enable system 800 (where such execution representation (at least partially) EDA tools) to perform part or all of the process and / or method. In one or more embodiments, recording medium 804 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, recording medium 804 stores a standard cell library 807 comprising the standard cells disclosed herein.

[0185] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for communicating information and commands to processor 802.

[0186] EDA system 800 also includes a network interface 812 coupled to processor 802. Network interface 812 allows system 800 to communicate with a network 814 connected to one or more other computer systems. Network interface 812 includes a wireless network interface such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more systems 800.

[0187] System 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 802. This information is transmitted to processor 802 via bus 808. EDA system 800 is configured to receive UI-related information via I / O interface 810. This information is stored as a user interface (UI) 842 in computer-readable recording medium 804.

[0188] In some embodiments, part or all of the process and / or method is implemented as a standalone software application for execution by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 800. In some embodiments, software such as that provided by CADENCE DESIGN SYSTEMS Ltd. is used. Use tools or another suitable layout generation tool to generate layouts that include standard cells.

[0189] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0190] Figure 9This is a block diagram of an integrated circuit (IC) manufacturing system 900 according to some embodiments, and the associated IC manufacturing process. In some embodiments, based on layout, the manufacturing system 900 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one element in a semiconductor integrated circuit layer.

[0191] exist Figure 9 In this IC manufacturing system 900, entities such as design studio 920, mask room 930, and IC manufacturing plant / manufacturer (“Fab”) 950 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC devices 960. The entities in system 900 are connected via a communication network. In some embodiments, the communication network is a single network. In some implementations, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 920, mask room 930, and IC manufacturing plant 950 are owned by a single, larger company. In some embodiments, two or more of the design studio 920, mask room 930, and IC manufacturing plant 950 coexist in a common facility and use common resources.

[0192] Design studio (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC device 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 960 to be manufactured. The layers combine to form various IC features. For example, a portion of IC design layout 922 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 920 implements appropriate design procedures to form IC design layout 922. The design process includes one or more of logic design, physical design, or location and routing operations. IC design layout 922 is presented in one or more data files containing geometric pattern information. For example, IC design layout 922 may be represented in GDSII or DFII file format.

[0193] Mask chamber 930 includes data preparation 932 and mask fabrication 944. Mask chamber 930 uses IC design layout 922 to fabricate one or more masks 945 for fabricating various layers of IC device 960 according to IC design layout 922. Mask chamber 930 performs mask data preparation 932, where IC design layout 922 is converted into a representative data file (“RDF”). Mask data preparation 932 provides the RDF for mask fabrication 944. Mask fabrication 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mesh) 945 or a semiconductor wafer 953. Design layout 922 is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication plant 950. Figure 9 In this embodiment, mask data preparation 932 and mask manufacturing 944 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 944 may be collectively referred to as mask data preparation.

[0194] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution assistance, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0195] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that uses a set of mask creation rules that include certain geometric and / or connectivity constraints to check the IC design layout 922 that has undergone the process in OPC to ensure sufficient margin to account for variability in the semiconductor manufacturing process, etc. In some embodiments, the MRC modifies the IC design layout 922 to compensate for constraints during mask fabrication 944, which can undo some modifications performed by OPC to satisfy the mask creation rules.

[0196] In some embodiments, mask data preparation 932 includes a lithography process check (LPC), which simulates the process to be implemented by an IC manufacturing plant 950 to manufacture an IC device 960. The LPC simulates this process based on an IC design layout 922 to create a simulated manufacturing apparatus, such as the IC device 960. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, coefficients associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, focal length (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after the LPC has created the simulated manufacturing apparatus, if the shape of the simulated device is not close enough to meet design rules, the OPC and / or MRC are repeated to further refine the IC design layout 922.

[0197] It should be understood that, for clarity, the above description of mask data preparation 932 has been simplified. In some embodiments, data preparation 932 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 922 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0198] After mask data preparation 932 and during mask fabrication 944, a mask 945 or a set of masks 945 is fabricated based on a modified IC design layout 922. In some embodiments, mask fabrication 944 includes performing one or more photolithographic exposures based on the IC design layout 922. In some embodiments, based on the modified IC design layout 922, an electron beam (electron beam) or a mechanism of multiple electron beams is used to form a pattern on the mask (photomask or crosshair) 945. The mask 945 can be formed in various techniques. In some embodiments, a binary technique is used to form the mask 945. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask version of the mask 945 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, a phase-shifting technique is used to form the mask 945. In the phase-shift mask (PSM) version of mask 945, various features in the pattern formed on the phase-shift mask are configured with appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask can be attenuated PSM or alternating PSM. The mask produced by mask fabrication 944 is used in various processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 953, in etching processes to form various etched regions in semiconductor wafer 953, and / or in other suitable processes.

[0199] IC manufacturing plant 950 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 950 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility that can provide back-end manufacturing (back-end process (BEOL) fabrication) for interconnecting and packaging of IC products, and a third manufacturing facility that can provide additional services for the foundry operations.

[0200] IC manufacturing plant 950 includes manufacturing tooling 952 configured to perform various manufacturing operations on semiconductor wafer 953, such that IC device 960 is manufactured according to a mask (e.g., mask 945). In various embodiments, manufacturing tooling 952 includes one or more of the following: wafer stepper, ion implanter, photoresist coater, process chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes discussed herein.

[0201] IC manufacturing plant 950 uses a mask 945, fabricated in mask chamber 930, to manufacture IC device 960. Therefore, IC manufacturing plant 950 uses IC design layout 922 at least indirectly to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is fabricated by IC manufacturing plant 950 using mask 945 to form IC device 960. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 922. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 953 also includes one or more various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0202] In some embodiments, a read-only memory (ROM) device includes: an active region extending along a first direction; and a plurality of gates extending across the active region and located above the active region along a second direction laterally to the first direction. The plurality of gates, together with the active region, correspondingly configure a plurality of transistors. Each of the plurality of transistors is configured to store data. The active region extends continuously across more than four of the plurality of gates and is located above the conductive gates.

[0203] In some embodiments, the ROM device further includes: bit lines; power rails; and a plurality of word lines, correspondingly electrically coupled to a plurality of gates.

[0204] In some embodiments, the plurality of transistors includes: a first transistor configured to store a first logic value, the first transistor having a first source / drain electrically coupled to a bitline and a second source / drain electrically coupled to a power rail; a second transistor configured to store a second logic value different from the first logic value, the second transistor having a first source / drain and a second source / drain electrically coupled to a bitline; and a third transistor configured to store the second logic value, the third transistor having a first source / drain and a second source / drain electrically coupled to a power rail.

[0205] In some embodiments, each pair of adjacent transistors in a plurality of transistors shares a common source / drain.

[0206] In some embodiments, the plurality of transistors further includes at least one of the following: a fourth transistor configured to store a second logic value, the fourth transistor having an electrically floating first source / drain and a second source / drain; a fifth transistor configured to store a second logic value, the fifth transistor having a first source / drain electrically coupled to a power rail and an electrically floating second source / drain; or a sixth transistor configured to store a second logic value, the sixth transistor having a first source / drain electrically coupled to a power rail and an electrically floating second source / drain.

[0207] In some embodiments, each pair of adjacent transistors in a plurality of transistors shares a common source / drain.

[0208] In some embodiments, bit lines and power rails overlap with the active region and extend continuously across a plurality of gates along a first direction.

[0209] In some embodiments, each of more than four conductive gates is electrically coupled to a corresponding word line in a plurality of word lines, and the active region extends continuously across more than four conductive gates and is located below more than four conductive gates.

[0210] In some embodiments, all gates that extend continuously across and are located below the active region belong to transistors configured to store data.

[0211] In some embodiments, the ROM device does not have an isolation structure that divides the active region into electrically isolated portions.

[0212] In some embodiments, the read-only memory (ROM) device includes multiple instances of a circuit region. The circuit region includes: multiple active regions extending continuously along a first direction; and multiple gates extending across the multiple active regions along a second direction transverse to the first direction, the multiple gates and the multiple active regions being configured together as multiple transistors for storing data. The multiple instances of the circuit region include a first instance and a second instance that are adjacent to each other and share a source / drain pair.

[0213] In some embodiments, multiple active regions extend continuously from a first instance to a second instance.

[0214] In some embodiments, in a first instance, the plurality of gates includes a first gate, which is configured together with a plurality of active regions to form a first group of transistors; in a second instance, the plurality of gates includes a second gate, which is configured together with a plurality of active regions to form a second group of transistors; and each source / drain in a source / drain group shared by the first and second instances is a common source / drain of a transistor in the first group of transistors and a corresponding transistor in the second group of transistors.

[0215] In some embodiments, the plurality of gates includes a first gate to a fourth gate spaced apart from each other by a gate pitch along a first direction, and the size of the circuit region along the first direction is four times the gate pitch.

[0216] In some embodiments, the plurality of active regions include a first active region to a fourth active region spaced apart from each other along a second direction, the plurality of gates include a first gate to a fourth gate spaced apart from each other along a first direction, and the circuit region further includes a first group of source / drains to a fifth group of source / drains, the first group of source / drains to the fifth group of source / drains and the first active region to the fourth active region are alternately arranged along the first direction, and each group of the first group of source / drains to the fifth group of source / drains includes four source / drains corresponding to the first active region to the fourth active region.

[0217] In some embodiments, the source / drain group shared by the first instance and the second instance is one of the first group of source / drain to the fifth group of source / drain in the first instance, and one of the first group of source / drain to the fifth group of source / drain in the second instance.

[0218] In some embodiments, the circuit region further includes: a plurality of bit lines and a plurality of power rails extending continuously along a first direction, wherein each of the plurality of bit lines and the corresponding power rail of the plurality of power rails is located above a corresponding active region among the plurality of active regions, a plurality of word line patterns electrically coupled to corresponding plurality of gates, and one or more vias, wherein the source / drain of one of the plurality of active regions is electrically coupled to a bit line or power rail above an active region according to data stored in the circuit region.

[0219] In some embodiments, the plurality of gates includes: at least one first gate extending continuously along a second direction across the entirety of the plurality of active regions, and at least one second gate physically divided into a first gate portion and a second gate portion, the first gate portion extending continuously along the second direction across some of the plurality of active regions, and the second gate portion extending continuously along the second direction across some other of the plurality of active regions.

[0220] A method of manufacturing a read-only memory (ROM) device according to some embodiments includes: forming a plurality of active regions extending continuously along a first direction on a substrate; forming a plurality of gates extending along a second direction transverse to the first direction above the plurality of active regions, the plurality of gates being configured together with the plurality of active regions as a plurality of transistors for storing data; and forming one or more vias above one or more sources / drains of the plurality of active regions according to data to be stored in the ROM device, wherein the plurality of active regions, the plurality of gates, and the plurality of transistors are arranged in a plurality of instances of a circuit region, the circuit region including at least four adjacent transistors in the first direction, and forming at least one of the plurality of active regions including at least one active region between adjacent instances of the plurality of instances where no isolation structure is formed.

[0221] In some embodiments, the method further includes: depositing and patterning a metal layer to form: a plurality of word line patterns, correspondingly electrically coupled to a plurality of gates, and a plurality of bit lines and a plurality of power rails extending continuously along a first direction, wherein each of the plurality of bit lines and a corresponding power rail of the plurality of power rails is located above a corresponding active region of a plurality of active regions, wherein each of one or more vias electrically couples a corresponding source / drain of one or more source / drains to a bit line of the plurality of bit lines or a power rail of the plurality of power rails.

[0222] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A read-only memory device, comprising: The active region extends along the first direction; as well as Multiple gates extend across the active region along a second direction laterally to the first direction and are located above the active region. in The plurality of gates, together with the active region, are correspondingly configured with a plurality of transistors. Each of the plurality of transistors is configured to store data, and The active region extends continuously across more than four of the plurality of gates and is located above the conductive gates.

2. The read-only memory device according to claim 1, further comprising: Bit line; Power rail; as well as Multiple word lines are electrically coupled to the multiple gates.

3. The read-only memory device according to claim 2, wherein, The plurality of transistors includes: A first transistor, configured to store a first logic value, has a first source / drain electrically coupled to the bit line and a second source / drain electrically coupled to the power rail. A second transistor, configured to store a second logic value different from the first logic value, the second transistor having a first source / drain and a second source / drain electrically coupled to the bit line, and A third transistor is configured to store the second logic value, the third transistor having a first source / drain and a second source / drain electrically coupled to the power rail.

4. The read-only memory device according to claim 3, wherein, The plurality of transistors further includes at least one of the following: A fourth transistor, configured to store a second logic value, has electrically floating first source / drain and second source / drain. A fifth transistor, configured to store a second logic value, has a first source / drain electrically coupled to the bit line and an electrically floating second source / drain, or A sixth transistor, configured to store a second logic value, has a first source / drain electrically coupled to the power rail and a second source / drain electrically floating.

5. The read-only memory device according to claim 2, wherein, The bit lines and the power rails overlap with the active region and extend continuously across the plurality of gates along the first direction.

6. The read-only memory device according to claim 2, wherein, Each of the more than four conductive gates is electrically coupled to a corresponding word line in the plurality of word lines, and the active region extends continuously across the more than four conductive gates and is located below the more than four conductive gates.

7. The read-only memory device according to claim 1, wherein, The read-only memory device does not have an isolation structure that divides the active region into electrically isolated portions.

8. A read-only memory device, comprising: Multiple instances of the circuit region, among which The circuit region includes: Multiple active regions, extending continuously along the first direction; and A plurality of gates extend across the plurality of active regions along a second direction transverse to the first direction, the plurality of gates and the plurality of active regions being configured together as a plurality of transistors for storing data. The plurality of instances of the circuit region include a first instance and a second instance that are adjacent to each other and share a source / drain pair.

9. The read-only memory device according to claim 8, wherein, The plurality of gates includes a first gate to a fourth gate spaced apart from each other along the first direction by a gate pitch, and The dimension of the circuit region along the first direction is four times the gate pitch.

10. A method for manufacturing a read-only memory device, the method comprising: Multiple active regions are formed on the substrate, extending continuously along a first direction; A plurality of gates are formed above the plurality of active regions, extending in a second direction transverse to the first direction, and the plurality of gates together with the plurality of active regions are configured as a plurality of transistors for storing data; as well as Based on the data to be stored in the read-only memory device, one or more vias are formed above one or more sources / drains in one or more of the plurality of active regions. in The plurality of active regions, the plurality of gates, and the plurality of transistors are arranged in multiple instances of a circuit region, wherein the circuit region includes at least four adjacent transistors in the first direction, and The formation of at least one of the plurality of active regions includes the formation of no isolation structure in the at least one active region between adjacent instances of the plurality of instances.

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