Ion sensitive field effect transistor

Abstract

An ion sensitive field effect transistor (ISFET) for testing a medium, the ISFET comprising: a substrate; the active layer is located on the substrate; a source region and a drain region in the active layer; a gate structure over the channel region between the drain region and the source region; a back-end stack comprising a plurality of metal layers wherein the gate structure is directly connected to a top metal layer of the plurality of metal layers and the drain region and the source region are directly connected to one or more other metal layers of the plurality of metal layers; and a sensing layer overlying the top metal layer wherein the sensing layer comprises an anti-reflective coating (ARC) arranged in contact with a medium.

Description

Technical Field

[0001] This invention relates to ion-sensitive field-effect transistors (ISFETs). Background Technology

[0002] ISFET is an ion-sensitive sensor that can be fabricated in a CMOS process using standard MOSFETs. pH-sensitive CMOS ISFETs with a specific H+ ion-sensitive layer are fabricated using expensive and complex processes, rather than standard CMOS process flows. On the other hand, CMOS ISFETs using standard / unmodified CMOS processes are inexpensive to produce and suitable for mass production, making them applicable to a variety of different applications.

[0003] Currently, the ion-sensitive layer of a CMOS ISFET consists of a stack of oxide and nitride passivation layers. However, the sensitivity and signal resolution of these (unmodified) CMOS ISFETs may be too low for some applications, and hydration of the silicon nitride layer can cause drift and reduce the ISFET's lifetime.

[0004] Therefore, there is a need to improve the sensitivity of ISFETs while using only standard CMOS processes to manufacture them. Summary of the Invention

[0005] Various aspects of the present invention provide an ISFET and a method of manufacturing the same as described in the appended claims.

[0006] Specific embodiments are described below with reference to the accompanying drawings. Attached Figure Description

[0007] Figure 1 A schematic cross-sectional view of a conventional ISFET is shown;

[0008] Figure 2 A schematic cross-sectional view of a CMOS ISFET is shown;

[0009] Figure 3 A schematic cross-sectional view of a CMOS ISFET with an ARC layer is shown.

[0010] Figure 4A and Figure 4B Two graphs showing the material content as a function of depth for the silicon nitride ARC layer and the standard nitride layer are presented respectively; and

[0011] Figure 5 A flowchart illustrating the steps of a method for manufacturing an ISFET is shown. Detailed Implementation

[0012] To improve CMOS ISFETs, an anti-reflective coating (ARC) layer is added in contact with a dielectric. The dielectric can be a fluid such as an ionic liquid. By adding the ARC layer, the performance of CMOS ISFET sensors can be significantly improved in terms of sensitivity, resolution, and drift. The deposition of this layer is part of a standard / unmodified CMOS process and therefore remains cost-effective.

[0013] Testing a medium can include characterizing / determining one or more of the parameters, substances, mixtures of substances, or analytes present in the medium. In one example, the medium is a substance or mixture of substances in which ions are present as charge carriers, and their detection can be used to characterize the analytes or their parameters contained in the medium. The medium can exist in different aggregate states, allowing for the analysis of primarily fluid, liquid, and gaseous media.

[0014] The analyte contained in the medium to be detected can be, for example, an ion acting as a charge carrier. The analyte can also be a substance contained in a mixture of substances. In more complex cases, the analyte in the medium can be, for example, a molecular structure (e.g., DNA, antibody, antigen, protein, enzyme, etc.) that contains or generates a charge carrier due to reaction with other biological, chemical, and / or biochemical functional structures. Similarly, the analyte can be a cellular structure that contains or generates a charge carrier due to reaction with other biological, chemical, and / or biochemical functional structures. The medium can also include combinations of such structures.

[0015] Figure 1 A schematic cross-sectional view of a conventional ISFET 2 is shown, including an ion-sensitive gate structure 4 in contact with a fluid 6 to be tested. A reference electrode 8 provides a bias voltage to the fluid 6. A current dI flows between the source region 10 and the drain region 12 of the ISFET. The magnitude of the current depends on the pH value of the fluid 6 in contact with the gate structure 4.

[0016] Figure 2 A schematic cross-sectional view of the CMOS ISFET 2 is shown. The same reference numerals are used in different figures for similar or equivalent features to aid understanding and are not intended to limit the embodiments shown. The CMOS ISFET 2 is similarly arranged to measure the current through the transistor between the source region 10 and the drain region 12. The gate structure 4 is directly connected to the top metal layer 16 of the back-end stack 18 of the CMOS device. A sensing layer 20 sensitive to the ion concentration of the fluid 6 is disposed on the top metal layer 16. The sensing layer includes an oxide layer 22 and a nitride passivation layer 24 in contact with the fluid 6.

[0017] Figure 3A schematic cross-sectional view of a CMOS ISFET 2 with an ARC layer 50 for improved sensitivity is shown. The CMOS ISFET 2 includes a substrate 28 (e.g., bulk silicon) and an active layer 30 (e.g., epitaxial silicon) on the substrate 28. In the active layer 30, a source region 10 and a drain region 12 are present in a doped well 34. For example, the source region 10 and the drain region 12 may be n-doped regions in a p-doped well.

[0018] The CMOS ISFET 2 also includes a gate structure 4 located above a channel region 36 between the drain region 10 and the source region 12. The gate structure 4 includes a gate oxide layer 38 and a conductive gate layer 40 (e.g., a polysilicon layer) isolated from the active layer 30 by the gate oxide layer 38. A gate voltage applied to the conductive gate layer 40 changes the resistance in the channel region 36, thereby causing a measurable change in the transistor current.

[0019] The CMOS ISFET 2 also includes a back-end stack 18 comprising multiple metal layers, wherein the drain region 10 and the source region 12 are directly connected to a first metal layer 42 (metal 1), and the gate structure 4 is directly connected to a top metal layer 16 (metal 4) among the multiple metal layers. The metal layers are separated by interlayer dielectric (ILD) oxide 44. A conductive gate layer 40 is connected to the top metal layer 16 through a via 46 between the metal layers. The metal layers and the via 46 typically comprise copper.

[0020] The CMOS ISFET 2 includes a sensing layer 20 covering a top metal layer 16. The sensing layer 20 includes an oxide layer 22 and a nitride passivation layer 24 (similar to the one described above). Figure 2 (See the related description of ISFET). Additionally, the sensing layer 20 includes an anti-reflective coating (ARC) layer 50 arranged in contact with the fluid 6. In this embodiment, the ARC layer 50 is a silicon nitride (Si3N4) layer (different from the underlying nitride passivation layer). The oxide layer 22 may have a thickness of approximately 700 nm.

[0021] The Si3N4 ARC layer contains more nitrogen than standard Si3N4, thus providing potential binding sites for H+ ion binding, which can result in higher sensitivity compared to standard Si3N4 (e.g., in nitride passivation layer 24). The Si3N4 ARC layer is more compressed than nitride passivation layer 24, and therefore has fewer cracks that ions and charged particles can penetrate. This can lead to reduced drift and noise, thereby improving signal resolution.

[0022] The higher compressive stress and stoichiometric properties of the nitride ARC layer 50 provide a lower refractive index (e.g., RI 1.92) compared to standard Si3N4 (RI 1.96), which has been shown to be beneficial to ISFET performance.

[0023] Table 1 compares some performance metrics of CMOS ISFETs without an ARC layer with those of CMOS ISFETs with a silicon nitride ARC layer. It can be seen that sensitivity, resolution, and drift are all improved.

[0024] Table 1

[0025]

[0026] One reason for the performance improvement is the increased proportion of nitride in ARC silicon nitride compared to the standard (passivated nitride), and especially the increased nitride near the surface of the layer (closer to the fluid interface).

[0027] Figure 4A and Figure 4B The graphs showing the material content as a function of depth (expressed as etch time) for the Si3N4 ARC layer and the Si3N4 passivation layer are presented separately. It can be seen that near the surface (where the etch time is shorter), the ARC layer has a higher nitrogen content and a lower oxygen content compared to the passivation layer.

[0028] In alternative embodiments, other materials may be used for the ARC layer 50. For example, the ARC layer may include SiO2 (RI 1.42-1.46), SiON (RI 1.90-1.94), SiON (RI 1.70-1.74), TiN, Ti, Ti / TiN, or a composition including Ti.

[0029] The ARC module is an existing process module in CMOS technology used to deposit ARC layers. It is typically used to increase light transmittance and improve the efficiency of optical semiconductor devices such as photodiodes, avalanche photodiodes (APDs), and single-photon avalanche diodes (SPADs). Therefore, this process module can be applied to existing CMOS processes without modification for the fabrication of ISFETs.

[0030] Figure 5This is a flowchart illustrating the steps of a method for forming an ISFET. The method includes: setting a substrate (step S1); setting an active layer on the substrate (step S2); forming a source region and a drain region in the active layer (step S3); and setting a gate structure over a channel region between the drain and source regions (step S4). The method further includes: setting a back-end stack comprising multiple metal layers, wherein the drain and source regions are directly connected to a first metal layer among the multiple metal layers, and the gate structure is directly connected to a top metal layer among the multiple metal layers (step S5); and then setting a sensing layer covering the top metal layer, wherein the sensing layer includes an anti-reflective coating (ARC) layer arranged to be in contact with a fluid (step S6).

[0031] The ARC layer can be a silicon nitride layer. The deposition pressure during ARC layer deposition can be lower than that of standard Si3N4, and it can have lower gas flow rate, gas ratio, and RF power.

[0032] Typically, CMOS processes include multiple available process modules that can be combined with certain constraints on their specific combinations and order to create different semiconductor structures. For example, there are shallow trench isolation (STI) modules for creating isolation in the active layer, and MET1 modules for depositing and patterning the lowest metal layer directly connected to the active layer. Importantly, the embodiments described herein can provide improved ISFETs using only standard CMOS process modules. In one example, after a passivation module forms a passivation layer, an ARC module forms an ARC layer on top of the passivation layer.

[0033] In general, according to the first aspect, the embodiments described herein can provide an ion-sensitive field-effect transistor (ISFET) for testing a medium (e.g., measuring the pH of a fluid), the ISFET comprising:

[0034] Substrate;

[0035] The active layer is located on the substrate;

[0036] The source and drain regions are located in the active layer;

[0037] Above the channel region between the drain and source regions in the gate structure;

[0038] The back-end stack includes multiple metal layers, wherein the drain and source regions are directly connected to the first metal layer among the multiple metal layers, and the gate structure is directly connected to the top metal layer among the multiple metal layers; and

[0039] A sensing layer, covering a top metal layer, wherein the sensing layer includes an anti-reflective coating (ARC) layer arranged to be in contact with a medium.

[0040] The ARC layer may comprise silicon nitride and may have a refractive index in the range of 1.9 to 1.94. Alternatively, the ARC layer may comprise titanium or tantalum pentoxide.

[0041] An ARC layer can be one of the following:

[0042] Si3N4 has a refractive index of 1.90-1.94;

[0043] SiO2 with a refractive index of 1.42-1.46;

[0044] SiON with a refractive index of 1.90-1.94; or

[0045] SiON with a refractive index of 1.70-1.74.

[0046] The ARC layer may include a Ti composition. For example, the ARC layer may be a TiN, Ti, or Ti / TiN layer.

[0047] The ARC layer can have a thickness ranging from 10 nm to 150 nm to provide suitable ion sensitivity.

[0048] The sensing layer may also include an oxide layer and a nitride passivation layer, wherein the oxide layer is in direct contact with the top metal layer, and the nitride passivation layer is located between the oxide layer and the ARC layer. The oxide layer and the nitride passivation layer can be formed in conventional CMOS processes. The nitride passivation layer can have a thickness in the range of 650 nm to 1000 nm. For example, the nitride passivation layer can have a thickness of approximately 900 nm. A thinner passivation layer can improve the sensitivity of the ISFET. The oxide layer can have a thickness in the range of 500 nm to 1100 nm (e.g., approximately 700 nm).

[0049] According to the second aspect, the embodiments described herein can provide a method for manufacturing an ion-sensitive field-effect transistor (ISFET), the method comprising:

[0050] Set up a substrate;

[0051] An active layer is provided on the substrate;

[0052] Source and drain regions are formed in the active layer;

[0053] A gate structure is disposed above the channel region between the drain region and the source region;

[0054] The configuration includes a back-end stack of multiple metal layers, wherein the drain and source regions are directly connected to the first metal layer among the multiple metal layers, and the gate structure is directly connected to the top metal layer among the multiple metal layers; and

[0055] A sensing layer is provided that covers the top metal layer, wherein the sensing layer includes an anti-reflective coating (ARC) layer arranged to be in contact with the medium.

[0056] This method can be used to manufacture an ISFET according to the first aspect described above. The method includes forming a transistor and then forming a sensing layer, wherein the sensing layer includes an ARC layer for contact with a dielectric. The sensing layer is connected to the gate of the transistor through metal layers in a back-end stack and through vias between the metal layers.

[0057] The ARC layer may include silicon nitride and may have a refractive index in the range of 1.9 to 1.94. Forming the sensing layer may include depositing silicon nitride to form the ARC layer in a complementary metal-oxide-semiconductor (CMOS) plasma-enhanced chemical vapor deposition (PECVD) process. Deposition may include deposition at a temperature in the range of 300°C to 400°C. Alternatively, the ARC layer may include titanium or tantalum pentoxide.

[0058] The ARC layer can have a thickness ranging from 10nm to 150nm.

[0059] The sensing layer may also include an oxide layer and a nitride passivation layer, wherein the oxide layer is in direct contact with the top metal layer and the nitride passivation layer is located between the oxide layer and the ARC layer.

[0060] According to another aspect, the embodiments described herein can provide a complementary metal-oxide-semiconductor (CMOS) ion-sensitive field-effect transistor (ISFET) for testing a dielectric, the CMOS ISFET including an anti-reflective coating (ARC) layer arranged in contact with the dielectric.

[0061] According to another aspect, the embodiments described herein can provide a method for manufacturing a complementary metal-oxide-semiconductor (CMOS) ion-sensitive field-effect transistor (ISFET) for testing a dielectric, the method comprising depositing an anti-reflective coating (ARC) layer disposed in contact with the dielectric.

[0062] Deposition may include depositing silicon nitride in a complementary metal-oxide-semiconductor (CMOS) plasma-enhanced chemical vapor deposition (PECVD) process. Deposition may include depositing at a temperature in the range of 300°C to 400°C.

[0063] While specific embodiments have been described above, it will be apparent to those skilled in the art that modifications can be made to the embodiments without departing from the scope of the claims. Each feature disclosed or described herein may be incorporated into the embodiments, either alone or in any suitable combination with any other feature disclosed or described herein.

Claims

1. An ion-sensitive field-effect transistor (ISFET) for testing dielectric materials, the ISFET comprising: Substrate; An active layer is located on the substrate; The source and drain regions are located in the active layer; A gate structure is located above the channel region between the drain region and the source region; A back-end stack includes multiple metal layers, wherein the gate structure is directly connected to the top metal layer of the multiple metal layers, and the drain region and the source region are directly connected to one or more other metal layers of the multiple metal layers; and A sensing layer covering the top metal layer, wherein the sensing layer includes an anti-reflective coating (ARC) layer arranged to be in contact with the medium.

2. The ISFET according to claim 1, wherein, The ARC layer comprises silicon nitride.

3. The ISFET according to claim 2, wherein, The ARC layer has a refractive index in the range of 1.90 to 1.

94.

4. The ISFET according to claim 1, wherein, The ARC layer comprises titanium or tantalum pentoxide.

5. The ISFET according to claim 1, wherein, The ARC layer has a thickness ranging from 10 nm to 150 nm.

6. The ISFET according to claim 1, wherein, The ARC layer is in direct contact with the top metal layer.

7. The ISFET according to claim 1, wherein, The sensing layer further includes an oxide layer and a nitride passivation layer, wherein the oxide layer is in direct contact with the top metal layer, and the nitride passivation layer is located between the oxide layer and the ARC layer.

8. The ISFET according to claim 7, wherein, The nitride passivation layer has a thickness in the range of 650 nm to 1000 nm.

9. The ISFET according to claim 7, wherein, The oxide layer has a thickness in the range of 500 nm to 1100 nm.

10. A method for manufacturing an ion-sensitive field-effect transistor (ISFET), the method comprising: Set up a substrate; An active layer is provided on the substrate; Source and drain regions are formed in the active layer; A gate structure is disposed above the channel region between the drain region and the source region; The configuration includes a back-end stack comprising multiple metal layers, wherein the gate structure is directly connected to the top metal layer of the plurality of metal layers, and the drain region and the source region are directly connected to one or more other metal layers of the plurality of metal layers; and A sensing layer is provided to cover the top metal layer, wherein the sensing layer includes an anti-reflective coating (ARC) layer arranged to be in contact with the medium.

11. The method according to claim 10, wherein, The ARC layer comprises silicon nitride.

12. The method according to claim 11, wherein, The ARC layer has a refractive index in the range of 1.90 to 1.

94.

13. The method according to claim 11, wherein, Setting the sensing layer includes depositing silicon nitride in a complementary metal-oxide-semiconductor (CMOS) plasma-enhanced chemical vapor deposition (PECVD) process to form the ARC layer.

14. The method according to claim 13, wherein, Silicon nitride deposition involves deposition at temperatures ranging from 300°C to 400°C.

15. The method according to claim 10, wherein, The ARC layer comprises titanium or tantalum pentoxide.

16. The method of claim 10, wherein, The ARC layer has a thickness ranging from 10 nm to 150 nm.

17. The method according to claim 10, wherein, The sensing layer further includes: an oxide layer and a nitride passivation layer, wherein the oxide layer is in direct contact with the top metal layer, and the nitride passivation layer is located between the oxide layer and the ARC layer.

18. A complementary metal-oxide-semiconductor CMOS ion-sensitive field-effect transistor (ISFET) for testing dielectric materials, the CMOS ISFET comprising: An anti-reflective coating (ARC) layer is arranged to be in contact with the medium.

19. A method for manufacturing a complementary metal-oxide-semiconductor CMOS ion-sensitive field-effect transistor (ISFET) for testing dielectric materials, the method comprising: The deposition is arranged as an anti-reflective coating ARC layer in contact with the medium.

20. The method according to claim 19, wherein, The deposition includes: depositing silicon nitride in a complementary metal-oxide-semiconductor (CMOS) plasma-enhanced chemical vapor deposition (PECVD) process.

21. The method according to claim 20, wherein, The deposition includes deposition at a temperature in the range of 300°C to 400°C.

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