Solar cell and preparation method thereof, laminated cell and photovoltaic module

Abstract

The invention relates to the field of solar cells, in particular to a solar cell piece and a preparation method thereof, a laminated cell and a photovoltaic module, and the prepared solar cell piece comprises a silicon substrate, and an aluminum oxide interface modification layer, a tunneling oxide layer, a heavily doped polycrystalline silicon layer, a back passivation film layer and a back electrode which are sequentially arranged from the back of the silicon substrate from inside to outside, the front emitting electrode, the front passive film layer and the front electrode are sequentially arranged on the front face of the silicon substrate from inside to outside, and the thickness of the aluminum oxide interface modification layer is smaller than that of the tunneling oxide layer. According to the cell, the aluminum oxide interface modification layer is inserted between the back surface of the silicon wafer and the tunneling oxide layer, fixed negative charges and high dielectric constant of aluminum oxide are utilized, interface positive charges are neutralized, the interface state density is reduced, meanwhile, it is ensured that the electron tunneling efficiency is not affected, and the problem of insufficient passivation caused by Si-SiOX interface defects of an existing cell silicon wafer is solved; and finally, the conversion efficiency and the long-term stability of the battery and the manufactured photovoltaic module are improved.

Description

Technical Field

[0001] This invention relates to the field of solar cells, specifically to a solar cell and its preparation method, a tandem cell, and a photovoltaic module. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) cells are a high-efficiency solar cell technology based on the principle of selective charge carriers. Its core lies in the fabrication of an ultrathin tunneling oxide layer (SiO2) on the back of the cell. x The passivation contact structure consists of a silicon wafer and a doped silicon thin layer (such as polycrystalline silicon). This structure aims to significantly reduce recombination losses in the metal contact area, thereby improving the open-circuit voltage (Voc) and conversion efficiency of the battery. The interface quality between the silicon wafer and the tunneling oxide layer is a key bottleneck determining the effectiveness of this passivation structure and even the final performance of the battery.

[0003] In silicon wafers and SiO x At the interface, there are generally three types of core physical defects that restrict the passivation effect: The first type is interface state defects, due to the incomplete bonding between silicon and oxygen atoms, there are SiO and SiO atoms at the interface. 1+ The presence of numerous dangling bonds and oxygen vacancies, among other microscopic defects, typically maintains an interfacial density of states of 10. 11 cm -2 eV -1 The magnitude is significant. These interface states become recombination centers for charge carriers, directly leading to carrier recombination and loss of photocurrent. The second type is charge defects and contamination. After wet chemical treatments such as texturing and cleaning, silicon wafers easily adsorb hydroxyl groups (-OH) or retain positive charges due to incomplete oxidation. In addition, Na introduced during the process... + K + Alkali metal ions may reside in the oxide layer and migrate to the interface during battery operation, further intensifying recombination. The third type is the stability issue of the tunneling oxide layer, particularly in ultrathin SiO₂ layers. x In subsequent high-temperature processes (such as phosphorus doping of polycrystalline silicon layers), the structural integrity and barrier properties of the layer are challenged, and there is a risk that the dopant will diffuse into the silicon substrate, thereby deteriorating the junction characteristics of the PN junction.

[0004] Existing technologies for solving the above problems mainly focus on optimizing SiO2 by controlling the thermal oxidation temperature or plasma parameters. x Regarding the layer growth process, additional SiN may be deposited on top of the polycrystalline silicon layer. x Dielectric passivation layers such as Al2O3 are used. However, these solutions have inherent limitations: the former cannot fundamentally eliminate interface defects; the latter, because it is located above the polycrystalline silicon layer, cannot directly act on the silicon wafer-SiO2. xThis is the most critical initial interface, and an excessively thick additional layer may introduce unfavorable contact resistance.

[0005] It is particularly important to note that the aforementioned interface defects pose a particularly severe and critical challenge to the construction of N-type silicon wafers. First, the residual positive charge at the interface strongly attracts the majority carriers—electrons—in N-type silicon through Coulomb attraction, leading to electron enrichment in the interface region. This drastically increases the probability of interface state defects trapping electrons, significantly enhancing the recombination rate of charge carriers and fatally impacting the open-circuit voltage. Second, unlike P-type silicon, which can utilize fixed charges to form field-effect passivation, the interaction between N-type silicon and positive charges inherently promotes recombination. Therefore, N-type TOPCon cells require extremely stringent control over interface state density (Dit) and charge.

[0006] In summary, current technologies lack a direct and efficient method to improve the initial interface between the silicon wafer and the tunneling oxide layer—especially for N-type silicon wafers—that can effectively passivate interface states while neutralizing or mitigating the effects of harmful charges, and ensuring the stability and low contact resistance of the tunneling oxide layer. This technological bottleneck severely restricts further improvements in the conversion efficiency of cells, particularly high-performance N-TOPCon cells. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention provides solar cells and their preparation methods, tandem cells, and photovoltaic modules.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] The first aspect of the present invention provides a solar cell comprising a silicon substrate, an alumina interface modification layer, a tunneling oxide layer, a heavily doped polycrystalline silicon layer, a back passivation film layer and a back electrode arranged sequentially from the inside to the outside on the back side of the silicon substrate, and a front emitter, a front passivation film layer and a front electrode arranged sequentially from the inside to the outside on the front side of the silicon substrate, wherein the thickness of the alumina interface modification layer is less than the thickness of the tunneling oxide layer.

[0010] This invention achieves multi-dimensional performance enhancements in solar cells by inserting an alumina interface modification layer between the back side of the silicon substrate and the tunneling oxide layer. This alumina interface modification layer utilizes its inherent high density to fix negative charges, effectively neutralizing the Si-SiO₂ layer. x The positive charge at the interface, induced by silicon dangling bonds, significantly reduces the interface state density, thereby greatly improving the chemical passivation effect and suppressing carrier recombination. Simultaneously, the high dielectric constant of alumina optimizes the electric field distribution at the interface, enhancing field-effect passivation. The Al in the alumina layer... 3+Ions can also fill oxygen vacancy defects in the tunneling oxide layer (SiO2), improving the density and stability of the tunneling layer and fundamentally reducing the sources of defects in the tunneling layer. Furthermore, the newly added alumina film on the back can reflect penetrating long-wavelength light that has not been absorbed by the silicon substrate, allowing it to re-enter the battery and improving the battery's absorption and utilization rate of long-wavelength light. All these improvements are achieved while ensuring efficient electron tunneling, ultimately working synergistically to significantly improve the battery's conversion efficiency and long-term operational reliability.

[0011] The alumina interface modification layer of this invention is prepared using conventional alumina layer processing methods, with the difference being in thickness. Conventional aluminum passivation layers are typically 5-30 nm thick. As the main passivation layer, they are dense and continuous, achieving high-efficiency passivation due to their high fixed negative charge. However, conventionally thick alumina layers severely hinder carrier tunneling, especially electron tunneling, and therefore cannot be placed at interfaces requiring carrier tunneling. In contrast, the alumina interface modification layer of this invention uses an ultrathin alumina layer, which functions as an interface modifier rather than an independent main passivation layer. This ultrathin alumina layer design allows it to perform interface modification without creating a significant barrier to electron tunneling.

[0012] Furthermore, the thickness ratio of the alumina interface modification layer to the tunneling oxide layer is (0.2~0.4):1, which enables the "passivation quality" and "carrier tunneling efficiency" to achieve the best balance.

[0013] Preferably, the thickness of the alumina interface modification layer is 0.5~1 nm. Its thickness is precisely controlled within this preferred range. This thickness is not a continuous, dense thin film, but exists in the form of a sub-monolayer, island-like structure, or ultrathin layer. This fills the surface defects of the tunneling oxide layer, reduces the interface state density, and suppresses recombination and leakage, without forming an additional barrier, ensuring carrier tunneling efficiency, thereby improving the minority carrier lifetime, open-circuit voltage, and fill factor of the battery. Simultaneously, this thickness is easily controlled precisely through processes such as atomic layer deposition, and the island-like structure disperses stress, enhancing battery stability.

[0014] Furthermore, the front passivation film layer and the back passivation film layer are at least one of silicon oxide layer, silicon nitride layer, silicon oxynitride layer, and silicon carbide layer.

[0015] A second aspect of the present invention provides a method for preparing the above-mentioned solar cell, comprising the following steps:

[0016] (1) Cleaning and texturing of silicon substrate;

[0017] (2) The silicon substrate is diffused to form a front emitter;

[0018] (3) An alumina interface modification layer is deposited on the back side of the silicon substrate;

[0019] (4) A tunnel oxide layer is grown on the surface of the alumina interface modification layer: ALD deposition process is used, with trimethylaluminum as the aluminum source and deionized water as the oxidant. The deposition temperature is 250~300℃ and the deposition cycle is 4~8 times.

[0020] (5) Heavy doping on the back side, depositing a heavily doped polycrystalline silicon layer;

[0021] (6) A front passivation film is deposited on the front surface of the silicon substrate, and a back passivation film is deposited on the surface of the heavily doped polycrystalline silicon layer;

[0022] (7) Print the front electrode and the back electrode in sequence.

[0023] Furthermore, the total pulse duration of the trimethylaluminum is 5-7 seconds, the pulse switching ratio is 1:2, and the flow rate is 20-24 sccm.

[0024] Furthermore, the total pulse duration of the deionized water is 5-7 seconds, the pulse switching ratio is 1:2, and the flow rate is 20-24 sccm.

[0025] Furthermore, the texturing in step (1) includes texturing the front side of the silicon substrate and preparing the pyramid base on the back side. The front side texturing time is 380~420s, and the prepared pyramid base has a size of 3~4μm. The back side pyramid base preparation time is 200~250s, and the pyramid base has a size of 8~10μm.

[0026] Furthermore, the front texturing process uses an alkaline solution at 80-82°C.

[0027] Furthermore, the back side preparation of the tower base uses an alkaline solution at 64~68℃.

[0028] In some preferred embodiments of the present invention, the silicon substrate is an N-type silicon substrate, and the front emitter diffusion in step (2) is to prepare the front emitter of the PN junction by using BCl3 as the boron source, with a flow rate of 240~300 sccm, a diffusion temperature of 850~900℃, and a diffusion time of 1300~2000s under the protection of a protective gas.

[0029] Furthermore, the protective gas is at least one of N2, O2, H2, and argon.

[0030] Preferably, the protective gas is a mixture of N2 and O2, with an N2 flow rate of 2000 sccm and an O2 flow rate of 800 sccm.

[0031] In some embodiments of the present invention, in step (4), a tunneling oxide layer is prepared by PECVD process at a temperature of 500~550℃, a time of 15~25s, an N2O flow rate of 700~800sccm, a silane flow rate of 9000~11000sccm, an RF power of 10000~15000w, and a pulse switching ratio of 50:1000, to prepare a tunneling oxide layer with a thickness of 1.5~2.5nm.

[0032] Furthermore, in step (5), a heavily doped polycrystalline silicon layer is deposited using a low-pressure chemical vapor deposition (LPCVD) process.

[0033] In some preferred embodiments of the present invention, the silicon substrate is an N-type silicon substrate. In step (5), a low-pressure chemical vapor deposition (LPCVD) process is used. Intrinsic silicon is first deposited using SiH4 as the silicon source. The deposition temperature is 590~600℃, the deposition time is 1400~1600s, the SiH4 flow rate is 1880~2000sccm, and the deposition thickness is 100~120nm. Phosphorus oxychloride is used as the doping source to form a polycrystalline silicon layer by doping phosphorus into the intrinsic silicon. The phosphorus diffusion temperature is 800~1000℃, the phosphorus oxychloride flow rate is 1400~1550sccm, the time is 1000~1200s, the propagation depth is 100~200nm, and the layer reaches the tunneling oxide layer.

[0034] Preferably, the passivation film is SiN. x / SiON x Layering.

[0035] A third aspect of the present invention provides a stacked battery, which includes a base cell unit consisting of a solar cell or a cell prepared by the above-described solar cell preparation method.

[0036] A fourth aspect of the present invention provides a photovoltaic module assembled from the above-described solar cells, or assembled from solar cells prepared by the above-described solar cell preparation method.

[0037] In some embodiments of the present invention, the assembly of the photovoltaic module specifically involves: firstly, screening qualified solar cells by EL detection and classifying them according to performance; then, welding the solder strips to the main grid lines of the solar cells at 350-380°C for 2-5 seconds to achieve series connection; subsequently, stacking the solar cell strings with tempered glass, EVA film, and backsheet according to design specifications, and laminating them for 15-25 minutes at 135-150°C and 0.8-1.2 MPa; after the laminated components have cooled, installing the aluminum alloy frame and sealing it with adhesive, attaching the junction box and welding the busbars, and performing waterproof encapsulation; finally, ensuring that the module power and stability meet the standards through appearance inspection, electrical performance testing, and damp heat reliability testing, thus completing the assembly.

[0038] The beneficial effects of this invention are:

[0039] 1) Achieving atomic-level repair and efficient passivation of interface defects: This invention achieves atomic-level repair and efficient passivation of interface defects through Si-SiO x An ultrathin, atomically level alumina interface modification layer is inserted into the interface, utilizing Al 3+ Ions precisely fill oxygen vacancy defects in the tunneling oxide layer and effectively neutralize the positive charge at the interface by fixing their negative charge, significantly reducing the interface state density. This innovative structure simultaneously improves both chemical passivation and field-effect passivation, fundamentally solving the problem of severe interfacial recombination in conventional TOPCon cells and overcoming a key obstacle to further improving conversion efficiency.

[0040] 2) Enhanced passivation while ensuring efficient carrier tunneling: Unlike conventional thick alumina layers (5-30nm) used as the main passivation layer, this invention thins the alumina layer to a sub-monolayer or island-like atomic scale. This design allows it to perform interface modification and defect repair without significantly hindering electron tunneling, successfully resolving the contradiction between "enhanced passivation" and "maintained tunneling," and ensuring that the selective carrier tunneling function of the battery core remains unaffected.

[0041] 3) Improved long-term battery stability: On the one hand, Al 3+ The filling of oxygen vacancies enhances the structural density and stability of the tunneling oxide layer, improving the long-term reliability of the battery. On the other hand, the newly added aluminum oxide layer on the back can also reflect long-wavelength light that penetrates the battery, causing it to be absorbed again, thus enhancing the battery's spectral response to infrared light. This improves the overall performance of the battery from both stability and light absorption perspectives. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the solar cell structure of the present invention. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the embodiments thereof. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0044] This invention provides a solar cell, such as Figure 1As shown, the solar cell includes an aluminum oxide interface modification layer 2, a tunneling oxide layer 3, a heavily doped polycrystalline silicon layer 4, a back passivation film layer 5, and a back electrode 6 arranged sequentially from the inside to the outside on the back side of the silicon substrate 1, and a front emitter 7, a front passivation film layer 8, and a front electrode 9 arranged sequentially from the inside to the outside on the front side of the silicon substrate.

[0045] Example 1

[0046] This embodiment provides an N-TOPCon battery, which includes an N-type silicon substrate, an alumina interface modification layer with a thickness of 0.7 nm disposed sequentially from the inside to the outside of the back side of the silicon substrate, a tunneling oxide layer with a thickness of 2 nm, a heavily doped polycrystalline silicon layer with a doping depth of 150 nm formed by phosphorus doping, and a SiN layer with a thickness of 75 nm. x / SiO x The stacked passivation layer and back Ag electrode consist of a front passivation film composed of a P-type emitter, a 6nm aluminum oxide film, and an 80nm silicon nitride film, arranged sequentially from the inside to the outside on the front side of the silicon substrate.

[0047] The method for preparing this N-TOPCon battery includes the following steps:

[0048] (1) Silicon substrate cleaning and texturing: N-type silicon substrate cleaning, reacting in sodium hydroxide solution at 80℃ for 380s to prepare a pyramid-shaped textured surface (front side) with a size of 3~4μm.

[0049] (2) Formation of front emitter by diffusion on silicon substrate: The texturized N-type silicon substrate is placed in a quartz boat in a diffusion furnace, heated to 850°C, and 240 sccm of BCl3, 2000 sccm of N2 and 800 sccm of O2 are introduced. Diffusion is carried out for 1500 s. After diffusion, a front emitter is formed on the front side of the N-type silicon substrate. + The emitter is etched with an etchant to create the edge PN junction, followed by rinsing.

[0050] (3) In a sodium hydroxide solution at 65℃, the reaction was carried out for 220s to prepare a square tower base (back side) with a size of 8~10μm.

[0051] (4) Deposition of aluminum oxide interface modification layer on the back of silicon substrate: The polished silicon wafer is placed in an ALD device, with trimethylaluminum (TMA) as aluminum source and deionized water (H2O) as oxidant. The deposition temperature is controlled at 280℃, TMA pulse time is 7s, TMA flow rate is 24sccm, H2O pulse time is 7s, and H2O flow rate is 24sccm. The process is repeated for 6 cycles to deposit a 0.7nm aluminum oxide interface modification layer on the back of the silicon wafer.

[0052] (5) A tunneling oxide layer was grown on the surface of the alumina interface modification layer: The tunneling oxide layer was prepared by PECVD process at a temperature of 550℃, a time of 15s, an N2O flow rate of 700sccm, a silane flow rate of 11000sccm, an RF power of 15000w, and a pulse switching ratio of 50:1000 to prepare a tunneling oxide layer with a thickness of 2.5nm.

[0053] (6) Backside heavy doping, deposition of a heavily doped polycrystalline silicon layer: Using LPCVD process, the silicon wafer is placed in a furnace tube, and intrinsic silicon is deposited first using SiH4 as the silicon source. The temperature is raised to 590℃, and 1880 sccm of SiH4 is introduced. Deposition takes 1500s, and the deposition thickness is 110nm. The temperature is raised to 900℃, and 1400 sccm of POCl3 is introduced to dope phosphorus into the intrinsic silicon. Doping takes 1000s, and phosphorus atoms diffuse into the intrinsic silicon layer to form N. + A polycrystalline silicon layer was doped to a depth of 150 nm, PSG was removed with HF solution, and the layer was rinsed with deionized water.

[0054] (7) Deposition of passivation film: A 6 nm thick Al2O3 layer was deposited on the front side using ALD deposition process, followed by 80 nm SiN deposition on the front side using PECVD process. x Layer; On the surface of the N+ polycrystalline silicon layer, SiON layers with a thickness of 20 nm are sequentially deposited using PECVD. x and 55nm SiN x ;

[0055] (8) Printed electrodes: Silver paste is printed sequentially on the front and back sides using screen printing to form electrodes.

[0056] Example 2

[0057] This embodiment provides a P-TOPCon battery, which includes a P-type silicon substrate, an alumina interface modification layer with a thickness of 1 nm disposed sequentially from the inside to the outside of the back side of the silicon substrate, a tunneling oxide layer with a thickness of 2.5 nm, a heavily doped polycrystalline silicon layer with a doping depth of 200 nm formed by boron doping, and a SiN layer with a thickness of 75 nm. x / SiON x The stacked passivation layer and back Ag electrode consist of an N-type emitter, a 15nm aluminum oxide film, and an 80nm silicon nitride film layer arranged sequentially from the inside to the outside on the front side of the silicon substrate.

[0058] The method for preparing this P-TOPCon battery includes the following steps:

[0059] (1) Silicon substrate cleaning and texturing: P-type silicon substrate cleaning, reaction in sodium hydroxide solution at 85℃ for 420s to prepare a pyramid-shaped textured surface (front side) with a size of 3~5μm.

[0060] (2) Formation of front emitter by diffusion on silicon substrate: The texturized P-type silicon substrate is placed in a quartz boat in a diffusion furnace, heated to 900°C, and POCl3 at 200 sccm, N2 at 2000 sccm, and O2 at 800 sccm are introduced. Diffusion is carried out for 1500 s. After diffusion, a front emitter is formed on the front side of the P-type silicon substrate. + The edge PN junction of the emitter is etched with etching solution, and then rinsed.

[0061] (3) In a sodium hydroxide solution at 65℃, the reaction was carried out for 200s to prepare a square tower base (back side) with a size of 8~10μm.

[0062] (4) Deposition of aluminum oxide interface modification layer on the back of silicon substrate: The polished silicon wafer is placed in an ALD device, with trimethylaluminum (TMA) as aluminum source and deionized water (H2O) as oxidant. The deposition temperature is controlled at 250℃, TMA pulse time is 5s, TMA flow rate is 20sccm, H2O pulse time is 5s, and H2O flow rate is 20sccm. The process is repeated for 8 cycles to deposit a 1nm aluminum oxide interface modification layer on the back of the silicon wafer.

[0063] (5) Growing a tunneling oxide layer on the surface of the alumina interface modification layer: The silicon wafer after the alumina interface modification layer has been deposited is used to prepare a tunneling oxide layer by PECVD process at a temperature of 500℃, a time of 25s, an N2O flow rate of 800sccm, a silane flow rate of 9000sccm, an RF power of 10000w, and a pulse switching ratio of 50:1000 to prepare a tunneling oxide layer with a thickness of 1.5nm.

[0064] (6) Backside heavy doping, deposition of a heavily doped polycrystalline silicon layer: Using LPCVD process, the silicon wafer is placed in a furnace tube and heated to 600℃. First, a 2000 sccm SiH4 silicon source is introduced, and deposition is carried out for 1500s to a thickness of 100nm; then, a 200 sccm BCl3 boron source is introduced for in-situ doping for 600s to form P + Doped polycrystalline silicon layer; driven to a depth of 200nm, rinsed with deionized water;

[0065] (7) Deposition of passivation film: Using PECVD process, a 15nm thick Al2O3 layer and an 80nm thick SiN layer are sequentially deposited on the front side. x Layer; in P + On the surface of the polycrystalline silicon layer, SiON layers with a thickness of 40 nm are sequentially deposited using PECVD. x and 60nm SiN x ;

[0066] (8) Printed electrode: Silver paste is printed on the front side and aluminum paste is printed on the back side in sequence to form the electrode.

[0067] Example 3

[0068] The difference between the N-TOPCon battery in Example 3 and that in Example 1 is that the thickness of the alumina interface modification layer is 0.5 nm, while the rest is the same as in Example 1. The preparation method is basically the same as that in Example 1, except that the pulse on time is 5 s, the cycle is 4 times, and the flow rate is 24 sccm during the preparation of the alumina interface modification layer.

[0069] Example 4

[0070] The N-TOPCon battery in Example 4 differs from that in Example 1 in that the thickness of the alumina interface modification layer is 0.4 nm, while the rest is the same as in Example 1. The preparation method is basically the same as in Example 1, except that the pulse on-time is 4 s, the cycle is 4 times, and the flow rate is 24 sccm during the preparation of the alumina interface modification layer.

[0071] Example 5

[0072] The N-TOPCon battery in Example 5 differs from that in Example 1 in that the thickness of the alumina interface modification layer is 1.1 nm, while the rest is the same as in Example 1. The preparation method is basically the same as in Example 1, except that the pulse on-time is 7 s, the cycle is 8 times, and the flow rate is 24 sccm during the preparation of the alumina interface modification layer.

[0073] Comparative Example 1

[0074] like Figure 1 As shown, the N-TOPCon cell of Comparative Example 1 includes an N-type silicon substrate, a tunneling oxide layer with a thickness of 2 nm disposed sequentially from the inside to the outside of the back side of the silicon substrate, a heavily doped polycrystalline silicon layer with a doping depth of 150 nm formed by phosphorus doping, and a SiN layer with a thickness of 75 nm. x / SiON x The stacked passivation layer and back Ag electrode consist of a front passivation film composed of a P-type emitter, a 6nm aluminum oxide film, and an 80nm silicon nitride film, arranged sequentially from the inside to the outside on the front side of the silicon substrate.

[0075] The battery fabrication method omits the step of depositing an alumina interface modification layer on the back side; the other steps are the same as in Example 1.

[0076] The TOPCon cells prepared in Examples 1-5 and Comparative Example 1 were subjected to performance tests (reflecting passivation quality), with the test indicators being open-circuit voltage, short-circuit current, and photoelectric efficiency.

[0077] The test results are shown in Table 1.

[0078] Table 1 project Open circuit voltage (mV) Short-circuit current (A) Photoelectric efficiency (Eff) Example 1 728.45 13.688 25.72% Example 2 728.54 13.670 25.71% Example 3 728.23 13.687 25.70% Example 4 727.86 13.706 25.68% Example 5 727.77 13.685 25.65% Comparative Example 1 726.78 13.665 25.63%

[0079] Comparative analysis of Examples 1-5 and Comparative Example 1 shows that the battery and its preparation method provided by the present invention, by inserting an ultrathin alumina interface modification layer between the back side of the silicon substrate and the tunneling oxide layer, utilizes the layer to fix negative charges, neutralize positive charges at the interface, and fill oxygen vacancy defects. This achieves enhanced chemical passivation and field effect passivation at the interface while ensuring that electron tunneling efficiency is not affected, thereby significantly improving the conversion efficiency and long-term stability of the battery.

[0080] Comparative analysis of Examples 1-3 and Examples 4-5 shows that when the thickness of the alumina interface modification layer is too thin, the interface modification may be insufficient, and the passivation effect may be limited; when it is too thick, it may introduce a tunneling barrier, affecting carrier transport and causing a slight decrease in efficiency; when the thickness of the alumina interface modification layer is controlled within the preferred range of the present invention, it can effectively play the roles of interface state modification, charge neutralization and defect filling, and will not significantly hinder carrier tunneling, thereby achieving better overall passivation and electrical performance.

[0081] Comparative analysis of Example 1 and Comparative Example 1 shows that the short-circuit current, photoelectric conversion efficiency, and open-circuit voltage of the battery prepared by the present invention are significantly improved. This indicates that the introduction of the alumina interface modification layer in the present invention significantly enhances the interface passivation quality and reduces carrier recombination losses, thereby achieving a significant improvement in current output and ultimately resulting in an overall improvement in conversion efficiency. This also demonstrates that the alumina interface modification layer introduced in the present invention effectively optimizes the interface physical and electrical properties while maintaining tunneling characteristics, providing a reliable technical approach for improving solar cell efficiency.

[0082] The present invention has been further described above with reference to specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the nature and scope of the present invention. Various modifications made to the above embodiments by those skilled in the art after reading this specification are all within the scope of protection of the present invention.

Claims

1. A solar cell, characterized by, The device includes a silicon substrate, and an alumina interface modification layer, a tunneling oxide layer, a heavily doped polycrystalline silicon layer, a back passivation film layer, and a back electrode arranged sequentially from the inside to the outside on the back side of the silicon substrate. A front emitter, a front passivation film layer, and a front electrode are arranged sequentially from the inside to the outside on the front side of the silicon substrate. The thickness of the alumina interface modification layer is less than the thickness of the tunneling oxide layer.

2. The solar cell of claim 1, wherein The thickness ratio of the alumina interface modification layer to the tunneling oxide layer is (0.2~0.4):

1.

3. A solar cell according to claim 1, characterized in that, The thickness of the alumina interface modification layer is 0.5~1nm.

4. The solar cell of claim 1, wherein the first and second electrodes are formed of a material selected from the group consisting of silver, aluminum, and copper. The front passivation film and the back passivation film are at least one of aluminum oxide layer, silicon oxide layer, silicon nitride layer, silicon oxynitride layer, and silicon carbide layer.

5. The method for producing a solar cell according to any one of claims 1 to 4, characterized in that, Includes the following steps: (1) Cleaning and texturing of silicon substrate; (2) The silicon substrate is diffused to form a front emitter; (3) The back side of the silicon substrate is deposited with an alumina interface modification layer: ALD deposition process is adopted, with trimethylaluminum as aluminum source, deionized water as oxidant, deposition temperature of 250~300℃, and deposition cycle of 4~8 times; (4) A tunneling oxide layer is grown on the surface of the alumina interface modification layer; (5) Heavy doping on the back side, depositing a heavily doped polycrystalline silicon layer; (6) A front passivation film is deposited on the front surface of the silicon substrate, and a back passivation film is deposited on the surface of the heavily doped polycrystalline silicon layer; (7) Print the front electrode and the back electrode in sequence.

6. The method of claim 5, wherein the step of forming the first and second electrodes is performed by screen printing. The total pulse duration of the trimethylaluminum is 5-7 seconds, the pulse on / off ratio is 1:2, and the flow rate is 20-24 sccm.

7. The method of claim 6, wherein the method further comprises: The total pulse duration of the deionized water is 5-7 seconds, the pulse on / off ratio is 1:2, and the flow rate is 20-24 sccm.

8. The method of claim 5, wherein the method further comprises: The texturing in step (1) includes texturing the front and back sides of the silicon substrate. The texturing time for the front side is 380~420s, and the size of the prepared pyramid base is 3~4μm. The texturing time for the back side is 200~250s, and the size of the pyramid base is 8~10μm.

9. A stacked battery characterized by comprising: The base cell unit includes a solar cell prepared by any one of claims 1-4 or a solar cell prepared by any one of claims 5-8.

10. A photovoltaic module, characterized by, It is assembled from solar cells according to any one of claims 1-4, or from solar cells prepared by any one of claims 5-8.

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