Wafer and processing method thereof
By integrating an ion beam polishing device with a white light interferometer and closed-loop control, combined with a planarization auxiliary layer, the problem of high-precision planarization in a large wafer-level range was solved, achieving efficient surface topography control and meeting the flatness requirements of three-dimensional integrated circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2025-12-11
- Publication Date
- 2026-04-17
AI Technical Summary
Existing ion beam polishing technology struggles to achieve high-precision global planarization over large wafer-level areas, especially in handling unevenly distributed macroscopic undulations and insufficient stability of morphology transfer at material interfaces.
An ion beam polishing device with an integrated white light interferometer, combined with a planarization auxiliary layer and a closed-loop control process, achieves efficient surface planarization by controlling the ion beam incident angle and etching selectivity through real-time morphology detection and selective polishing.
Achieving global flatness PV value ≤10 nm and surface roughness Ra value ≤1 nm at the wafer level meets the high-precision flatness requirements of three-dimensional integrated circuits, and improves the automation level of the process and the selectivity of material removal.
Smart Images
Figure CN121888933A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing technology, specifically relating to a wafer and its processing method. Background Technology
[0002] In advanced semiconductor manufacturing, as the three-dimensional structure of integrated circuits continues to shrink, extremely high requirements are placed on the atomic-level planarization of the entire wafer surface (i.e., over a large area).
[0003] Chemical mechanical polishing (CMP) technology relies on mechanical contact, which can easily introduce damage when processing hard and brittle materials.
[0004] Ion beam polishing, as a non-contact alternative, typically requires a sacrificial layer on the wafer surface, which is then uniformly etched by an ion beam to achieve surface finishing. However, existing ion beam polishing methods are usually based on a uniform etching mode with fixed process parameters. This uniform etching mode cannot detect or respond to the inherent, spatially uneven macroscopic undulations (such as warpage and local protrusions) on the wafer surface. Because it removes material indiscriminately across all areas, this mode is inefficient at reducing the height difference between "high points" and "low points," and it cannot guarantee the stability of morphology transfer at interfaces between different materials (such as the sacrificial layer and the underlying substrate). Therefore, the surface morphology obtained by existing ion beam polishing methods often fails to achieve the level of uniformity required by advanced processes over a large wafer-level scale. Summary of the Invention
[0005] In view of the above problems, this application provides a wafer and its processing method to solve the problem of difficulty in achieving high-precision overall planarization at a large size range at the wafer level in three-dimensional integrated circuit manufacturing.
[0006] On one hand, the present invention provides a wafer in which, after planarization treatment of at least one functional layer of the wafer, the global flatness PV value is ≤10 nm and the surface roughness Ra value is ≤1 nm.
[0007] This invention achieves high-precision surface topography control at the global wafer scale, which can meet the requirements of advanced processes such as three-dimensional integrated circuits for substrate flatness.
[0008] On the other hand, the present invention provides a method for manufacturing the wafer, comprising the following steps: S1. A wafer is provided, the surface of which includes a material layer to be planarized; S2. A planarization auxiliary layer is formed on the material layer to be planarized; S3. The wafer is polished using an ion beam polishing device with an integrated white light interferometer so that the flatness of the material layer to be planarized meets the preset requirements.
[0009] In one possible implementation, the preset requirements include: a global flatness PV value ≤ 10 nm and a surface roughness Ra value ≤ 1 nm.
[0010] It is worth noting that step S2 can be performed by repeatedly spin-coating a planarization auxiliary layer to pre-reduce the surface smoothness PV value to <20 nm before proceeding to step S3.
[0011] By introducing a planarization auxiliary layer as an intermediate layer for controllable removal and defect filling, and by utilizing polishing equipment with integrated online metering functions, a direct link is established from morphology monitoring to process execution, providing a process foundation for achieving high-precision planarization at the wafer level.
[0012] Furthermore, by repeatedly spin-coating in S2, the thickness uniformity and surface smoothness of the planarization auxiliary layer can be further optimized, providing a more ideal starting morphology for subsequent ion beam polishing, thereby reducing the difficulty of final fine polishing and improving the overall process efficiency.
[0013] Furthermore, step S3 includes a closed-loop control process based on three-dimensional topographic information, comprising: S31. Topography inspection: The three-dimensional topography information of the wafer surface is obtained using the white light interferometer. S32. Selective polishing: Based on the three-dimensional morphology information, the ion beam polishing equipment is controlled to polish the morphological protrusion areas on the wafer surface using polishing parameters different from those for flat areas.
[0014] The aforementioned closed-loop control process directly uses the online measured three-dimensional topography data as the basis for polishing path and parameter adjustment, enabling polishing energy to be applied to the surface protrusion area in a targeted manner, thereby improving the efficiency of correcting macroscopic height differences and reducing material removal from areas that do not require treatment.
[0015] For example, the selective polishing includes: controlling the angle between the incident direction of the ion beam and the normal direction of the wafer surface to 45°~90° and performing scanning polishing on the morphological protrusion area.
[0016] Large-angle incident polishing is employed, taking advantage of the sensitivity of ion beam etching rate to local surface tilt angle. For the sidewalls of raised areas, large-angle incident light can produce a higher effective etching rate, thereby significantly enhancing the selective removal capability of high points and improving planarization efficiency.
[0017] It should be noted that when polishing transitions from the planarization auxiliary layer to the material layer to be planarized, the etching selectivity ratio of the ion beam on the planarization auxiliary layer and the material layer to be planarized is controlled to be 1:1.
[0018] By controlling the etching selectivity ratio at 1:1, the material replacement during the polishing process, which penetrates the auxiliary layer and begins to act on the underlying target material, does not cause a sudden change in the etching rate. This is crucial for maintaining the obtained flat morphology and preventing the formation of new steps or undulations at the material interface, enabling a smooth transfer of the morphology from the auxiliary layer to the target layer.
[0019] Preferably, the closed-loop control process is executed at least twice. Through multiple "detection-polishing" iterations, the optimal flatness can be gradually approximated and ultimately achieved. Each iteration is a further refinement of the previous result, improving the convergence accuracy of the process and the controllability of the final surface quality.
[0020] Specifically, in step S31, the white light interferometer completes the three-dimensional morphology acquisition of the entire wafer in a single scan and generates a three-dimensional morphology map associated with the spatial position; in step S32, the surface morphology protrusion region is automatically identified and located based on the three-dimensional morphology map.
[0021] Global rapid scanning and mapping enable global digital modeling of the wafer surface condition. Automatic identification and positioning based on the mapping allows for accurate and automated selective polishing, improving the automation and reliability of the process.
[0022] Furthermore, the planarization auxiliary layer is a material layer formed by a spin coating process.
[0023] For example, the material of the planarization auxiliary layer includes one or more of spin-coated carbon, spin-coated silicon dioxide, polycrystalline silicon, and silicon nitride.
[0024] Furthermore, the material of the material layer to be planarized includes one or more of tetraethyl orthosilicate, a low dielectric constant material, polycrystalline silicon, or silicon nitride; And / or, the low dielectric constant material includes one or more of carbon-doped oxides, fluorine-doped silicon dioxide, porous silicon dioxide, organosilicon glass, and organic polymer dielectric materials.
[0025] When selecting the specific material combination of the planarization auxiliary layer and the material layer to be planarized, the key lies in adjusting the etching selectivity ratio between the two materials to suit the planarization target by controlling the ion beam polishing process parameters. These process parameters include the physical and chemical interaction conditions of the ion beam, the incident angle, and the gas atmosphere. For example, by adjusting the proportion of reactant gases and the incident angle, the etching selectivity ratio of a specific material pair can be controlled at 1:1, facilitating a smooth transfer of morphology from the auxiliary layer to the target layer. Therefore, the method described in this invention has universality in material selection and is not limited to specific examples; its applicability depends on whether the required interface etching behavior control can be achieved through process adjustments.
[0026] Compared with the prior art, the present invention has at least the following technical effects: This invention provides an ion beam planarization method integrating online topology detection and adaptive control. It combines real-time topology detection, topology-based selective polishing, and interface etching selectivity control to form a closed-loop process. Specifically: First, three-dimensional topology information of the wafer surface is acquired using a white light interferometer; then, based on this information, the ion beam is controlled to selectively polish the protruding areas on the surface; simultaneously, by adjusting process parameters, the etching selectivity ratio of the ion beam for the planarization auxiliary layer and the underlying target material is maintained at 1:1 during the polishing transition phase to promote stable transfer of interface topology.
[0027] By combining and iteratively implementing the above methods, we can improve the convergence efficiency and consistency of wafer-level large-scale surface flatness, thus meeting the semiconductor manufacturing process's demand for high-precision global flatness. Attached Figure Description
[0028] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the cross-sectional structure of the wafer to be planarized in an embodiment of the present invention; Figures 2-4 This is a schematic diagram illustrating the structural state changes during the ion beam polishing process on the wafer surface in an embodiment of the present invention. Figure 5 This is a schematic diagram of the real-time detection results of the three-dimensional morphology of a wafer surface based on a white light interferometer in an embodiment of the present invention.
[0029] Figure label: 100 - Lower process film layer; 200 - First low dielectric constant layer; 201 - Copper interconnect structure; 300 - Doped carbon nitride layer; 400 - Second low dielectric constant layer; 500 - TEOS layer; 600 - Spin-coated carbon layer; h1 - Initial undulation height of the upper surface of the spin-coated carbon layer; h2 - undulation height of the upper surface of the TEOS layer after planarization treatment. Detailed Implementation
[0030] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.
[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.
[0032] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.
[0033] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0034] Existing ion beam planarization technology is limited by its non-selective uniform etching mode and insufficient control over etching behavior across material interfaces. When dealing with the global planarization requirements of large-size wafers, it is difficult to achieve high-precision and high-convergence surface morphology control.
[0035] To address the aforementioned shortcomings, this invention proposes a wafer planarization method integrating online topology detection and adaptive polishing control, along with the resulting wafer: After forming a planarization auxiliary layer on the wafer surface, an ion beam polishing device integrating a white light interferometer is used. This device acquires the three-dimensional topology information of the wafer surface in real time and, based on this information, controls the ion beam to selectively polish the raised areas of the surface topology. By adjusting the ion beam incident angle and controlling the etching selectivity ratio of the polishing transition interface to 1:1, efficient peak reduction and stable topology transfer are achieved synergistically. Ultimately, this invention's method can achieve high-precision global planarization across the entire wafer.
[0036] On one hand, the present invention provides a wafer in which, after planarization treatment of at least one functional layer of the wafer, the global flatness PV value is ≤10 nm and the surface roughness Ra value is ≤1 nm.
[0037] This invention achieves high-precision surface topography control at the global wafer scale, which can meet the requirements of advanced processes such as three-dimensional integrated circuits for substrate flatness.
[0038] On the other hand, the present invention provides a method for manufacturing the wafer, comprising the following steps: S1. A wafer is provided, the surface of which includes a material layer to be planarized; S2. A planarization auxiliary layer is formed on the material layer to be planarized; S3. The wafer is polished using an ion beam polishing device with an integrated white light interferometer so that the flatness of the material layer to be planarized meets the preset requirements.
[0039] It is worth noting that step S2 can be performed by repeatedly spin-coating a planarization auxiliary layer to pre-reduce the surface smoothness PV value to ≤20 nm before proceeding to step S3.
[0040] By introducing a planarization auxiliary layer as an intermediate layer for controllable removal and defect filling, and by utilizing polishing equipment with integrated online metering functions, a direct link is established from morphology monitoring to process execution, providing a process foundation for achieving high-precision planarization at the wafer level.
[0041] Furthermore, by repeatedly spin-coating in S2, the thickness uniformity and surface smoothness of the planarization auxiliary layer can be further optimized, providing a more ideal starting morphology for subsequent ion beam polishing, thereby reducing the difficulty of final fine polishing and improving the overall process efficiency.
[0042] Furthermore, step S3 includes a closed-loop control process based on three-dimensional topographic information, comprising: S31. Topography inspection: The three-dimensional topography information of the wafer surface is obtained using the white light interferometer. S32. Selective polishing: Based on the three-dimensional morphology information, the ion beam polishing equipment is controlled to polish the morphological protrusion areas on the wafer surface using polishing parameters different from those for flat areas.
[0043] The aforementioned closed-loop control process directly uses the online measured three-dimensional topography data as the basis for polishing path and parameter adjustment, enabling polishing energy to be applied to the surface protrusion area in a targeted manner, thereby improving the efficiency of correcting macroscopic height differences and reducing material removal from areas that do not require treatment.
[0044] For example, the selective polishing includes: controlling the angle between the incident direction of the ion beam and the normal direction of the wafer surface to 45°~90° and performing scanning polishing on the morphological protrusion area.
[0045] Preferably, the angle between the incident direction of the ion beam and the normal direction of the wafer surface is controlled to 45°, 50°, 55°, 60°, 65°, 70°, 75°, 80°, 85°, or 90°.
[0046] Large-angle incident polishing is employed, taking advantage of the sensitivity of ion beam etching rate to local surface tilt angle. For the sidewalls of raised areas, large-angle incident light can produce a higher effective etching rate, thereby significantly enhancing the selective removal capability of high points and improving planarization efficiency.
[0047] It should be noted that when polishing transitions from the planarization auxiliary layer to the material layer to be planarized, the etching selectivity ratio of the ion beam on the planarization auxiliary layer and the material layer to be planarized is controlled to be 1:1.
[0048] By controlling the etching selectivity ratio at 1:1, the material replacement during the polishing process, which penetrates the auxiliary layer and begins to act on the underlying target material, does not cause a sudden change in the etching rate. This is crucial for maintaining the obtained flat morphology and preventing the formation of new steps or undulations at the material interface, enabling a smooth transfer of the morphology from the auxiliary layer to the target layer.
[0049] Preferably, the closed-loop control process is executed at least twice. Through multiple "detection-polishing" iterations, the optimal flatness can be gradually approximated and ultimately achieved. Each iteration is a further refinement of the previous result, improving the convergence accuracy of the process and the controllability of the final surface quality.
[0050] Specifically, in step S31, the white light interferometer completes the three-dimensional morphology acquisition of the entire wafer in a single scan and generates a three-dimensional morphology map associated with the spatial position; in step S32, the surface morphology protrusion region is automatically identified and located based on the three-dimensional morphology map.
[0051] Global rapid scanning and mapping enable global digital modeling of the wafer surface condition. Automatic identification and positioning based on the mapping allows for accurate and automated selective polishing, improving the automation and reliability of the process.
[0052] Furthermore, the planarization auxiliary layer is a material layer formed by a spin coating process.
[0053] For example, the material of the planarization auxiliary layer includes one or more of spin-coated carbon, spin-coated silicon dioxide, polycrystalline silicon, and silicon nitride.
[0054] Furthermore, the material of the material layer to be planarized includes one or more of tetraethyl orthosilicate, a low dielectric constant material, polycrystalline silicon, or silicon nitride; And / or, the low dielectric constant material includes one or more of carbon-doped oxides, fluorine-doped silicon dioxide, porous silicon dioxide, organosilicon glass, and organic polymer dielectric materials.
[0055] When selecting the specific material combination of the planarization auxiliary layer and the material layer to be planarized, the key lies in adjusting the etching selectivity ratio between the two materials to suit the planarization target by controlling the ion beam polishing process parameters. These process parameters include the physical and chemical interaction conditions of the ion beam, the incident angle, and the gas atmosphere. For example, by adjusting the proportion of reactant gases and the incident angle, the etching selectivity ratio of a specific material pair can be controlled at 1:1, facilitating a smooth transfer of morphology from the auxiliary layer to the target layer. Therefore, the method described in this invention has universality in material selection and is not limited to specific examples; its applicability depends on whether the required interface etching behavior control can be achieved through process adjustments.
[0056] Example Figures 2-4 This is a schematic diagram illustrating the structural state changes during the ion beam polishing process on the wafer surface in an embodiment of the present invention. Figure 5 This is a schematic diagram of the real-time detection results of the three-dimensional morphology of a wafer surface based on a white light interferometer.
[0057] The wafer fabrication method includes the following steps: Step S1: Provide the wafer to be planarized, such as... Figure 1 As shown.
[0058] like Figure 1 As shown, the wafer to be planarized includes a stacked structure from bottom to top (from substrate upwards): Lower process film layer 100: serves as a base layer or substrate for which previous processes have been completed; First low dielectric constant layer 200: formed on the lower process film layer 100, and embedded therein with copper interconnect structure 201 distributed according to design; Doped carbon nitride layer 300: As an etch stop layer, it is formed on the first low dielectric constant layer 200; Second low dielectric constant layer 400: As another dielectric layer, it is formed on the doped carbon nitride layer 300; TEOS layer 500: As a material layer to be planarized, it is formed on top of the second low dielectric constant layer 400 by chemical vapor deposition. The surface of TEOS layer 500 has micro-undulations and defects caused by the underlying pattern and deposition process.
[0059] Step S2, as follows Figure 2 As shown, a planarization auxiliary layer is formed on the surface of the TEOS layer 500.
[0060] Specifically, a spin-coated carbon layer 600 is formed on the surface of the TEOS layer 500 using a spin-coating process. The spin-coated carbon layer 600 is used to initially fill the depressions on the surface of the TEOS layer 500, providing a more uniform starting surface for polishing. After repeated spin-coating and curing, the initial undulation height of the upper surface of the spin-coated carbon layer 600 is h1 = 20 nm.
[0061] Step S3: Polish the wafer using an ion beam polishing device with an integrated white light interferometer to make the surface of the TEOS layer 500 meet the preset flatness requirements.
[0062] Includes the following sub-steps: S31. Initial morphology detection and benchmark establishment.
[0063] The wafer with the spin-coated carbon layer is mounted in the ion beam polishing equipment, and the white light interferometer is started to perform the first full-domain scan to obtain the initial three-dimensional topography image, record the surface undulation h1, and use it as the process reference.
[0064] S32. Closed-loop selective ion beam polishing based on morphology information.
[0065] The polishing process is carried out in a controlled argon reaction atmosphere, performing a closed-loop iteration of "detection-polishing". Key process parameters are set as follows: Ion source power: 1000-2000W; Screen gate voltage / accelerating gate voltage: 500-800 V / -100~-300 V; Grid current / neutralizer current: 50-500 mA / 25-400 mA; Working gas and flow rate: The reaction gases are argon and xenon fluoride, with volume fractions of 70% and 30%, respectively; Operating vacuum level: Maintain <1x10 -2 ~5x10 -2 Pa high vacuum state; A single closed-loop iteration includes: Morphology detection: such as Figure 3 As shown, a white light interferometer is used to quickly acquire a full-field three-dimensional topographic map of the current wafer surface, and the system automatically analyzes and marks the topographic protrusion areas.
[0066] Selective polishing: such as Figure 4 As shown, the control system generates an optimized polishing path for the protruding areas based on the three-dimensional topography map. During polishing, the angle between the incident direction of the ion beam and the normal direction of the wafer surface is dynamically controlled to be 45-90°, and the etching selectivity ratio of the ion beam to the spin-coated carbon layer 600 and the underlying TEOS layer 500 is controlled at 1:1 in real time by adjusting the composition of the reactive gas. Subsequently, scanning polishing is performed according to the planned path.
[0067] S33. Process Endpoint Judgment and Effect Verification.
[0068] Repeat the closed-loop iteration described in step S32. When the white light interferometer detects that the spin-coated carbon layer 600 has been completely removed and the surface of the underlying TEOS layer 500 is completely exposed and meets the preset flatness requirement, the process terminates. Measure the surface of the final TEOS layer 500, and the undulation height is reduced to h2 = 10 nm.
[0069] Planarization Effect: After the above process treatment, the global flatness PV value based on global scanning is 10 nm, and the surface roughness Ra value is 1 nm, achieving the convergence goal of h2 < h1.
[0070] Comparative Example 1 The wafer structure is the same as that of the embodiment, and the surface is polished by ion beam. Compared with the embodiment, the difference is that: a white light interferometer is not used for detection and feedback. The entire polishing process uses preset fixed parameters (including a fixed incident angle of 0° and pure argon sputtering), and the entire wafer is polished uniformly over the entire area. The polishing time is set according to the average thickness experience of the spin-coated carbon layer 600.
[0071] Planarization Effect: After the above process treatment, the surface undulation of the final TEOS layer 500 is measured as h2’ (15) nm. The results show that h2’ > h2, and the global flatness convergence is poor, proving that the uniform polishing mode without topography feedback is inefficient.
[0072] Comparative Example 2 The wafer structure is the same as that of the embodiment, and the surface is polished by ion beam. Compared with the embodiment, the difference is that: during the selective polishing process, the etching selectivity ratio is not controlled to be 1:1. A process gas that makes the etching rate of the spin-coated carbon layer 600 significantly higher than that of the TEOS layer 500 is used during the polishing process, resulting in an etching selectivity ratio between the two far greater than 1.
[0073] Planarization Effect: After the above process treatment, the surface undulation of the final TEOS layer 500 is measured as h2’’ (15) nm. The results show that h2’’ > h2. This result indicates that even with selective polishing, if the etching behavior at the interface is mismatched, it will still hinder the optimal convergence of flatness. It should be noted that the above embodiments are only for demonstrating the process flow and effects of the present invention. In the specific implementation process, for the wafer structure and ion beam polishing parameters, those skilled in the art can make conventional selections and optimizations according to the material layer to be planarized.
[0074] In summary, this invention provides an ion beam planarization method integrating online topology detection and adaptive control. It combines real-time topology detection, topology-based selective polishing, and interface etching selectivity control to form a closed-loop process. This achieves high-precision, high-convergence surface topology control at the wafer-level global scale.
Claims
1. A wafer, characterized by, Within the entire wafer, at least one functional layer of the wafer, after planarization, has a global flatness PV value ≤ 10 nm and a surface roughness Ra value ≤ 1 nm.
2. A method for processing the wafer as described in claim 1, characterized in that, Includes the following steps: S1. A wafer is provided, the surface of which includes a material layer to be planarized; S2. A planarization auxiliary layer is formed on the material layer to be planarized; S3. The wafer is polished using an ion beam polishing device with an integrated white light interferometer so that the flatness of the material layer to be planarized meets the preset requirements.
3. The method according to claim 2, characterized in that, Step S3 includes a closed-loop control process based on three-dimensional topography information, including: S31. Topography inspection: The three-dimensional topography information of the wafer surface is obtained using the white light interferometer. S32. Selective polishing: Based on the three-dimensional morphology information, the ion beam polishing equipment is controlled to polish the morphological protrusion areas on the wafer surface using polishing parameters different from those for flat areas.
4. The method according to claim 3, characterized in that, The selective polishing includes controlling the angle between the ion beam incident direction and the normal direction of the wafer surface to 45°~90° and performing scanning polishing on the morphological protrusion area.
5. The method according to claim 3 or 4, characterized in that, When polishing transitions from the planarization auxiliary layer to the material layer to be planarized, the etching selectivity ratio of the ion beam for the planarization auxiliary layer and the material layer to be planarized is controlled to be 1:
1.
6. The method according to claim 3, characterized in that, The closed-loop control process described herein shall be executed at least twice.
7. The method according to claim 3, characterized in that, In step S31, the white light interferometer completes the three-dimensional morphology acquisition of the entire wafer in a single scan and generates a three-dimensional morphology map associated with the spatial position; in step S32, the surface morphology protrusion region is automatically identified and located based on the three-dimensional morphology map.
8. The method according to claim 2, characterized in that, The planarization auxiliary layer is a material layer formed by a spin coating process.
9. The method according to claim 8, characterized in that, The material of the planarization auxiliary layer includes one or more of spin-coated carbon, spin-coated silicon dioxide, polycrystalline silicon, and silicon nitride.
10. The method according to claim 9, characterized in that, The material of the material layer to be planarized includes one or more of tetraethyl orthosilicate, low dielectric constant material, polycrystalline silicon, or silicon nitride. And / or, the low dielectric constant material includes one or more of carbon-doped oxides, fluorine-doped silicon dioxide, porous silicon dioxide, organosilicon glass, and organic polymer dielectric materials.