Method for eliminating small stacking faults of silicon carbide based on high temperature oxidation

Abstract

The application belongs to the technical field of third-generation semiconductor material defect control. A method for eliminating small-scale stacking faults of silicon carbide based on high-temperature oxidation is proposed. The silicon carbide substrate is scanned and characterized by photoluminescence, and the target small-scale stacking fault is accurately identified and positioned. Then, the substrate is cleaned to remove surface impurities, and high-temperature oxidation treatment is carried out in a dry oxygen atmosphere, and an oxidation layer is controlled to grow. The mismatch of the thermal expansion coefficient between the oxidation layer and the substrate and the reaction molar volume expansion are used to construct a composite interface stress field at the interface, drive the directional reconstruction of the atomic arrangement of the target stacking fault, and convert it into the standard sequence of the matrix. Finally, nitric oxide assisted annealing is carried out, and the nitrogen passivation effect is used to solidify the lattice configuration after reconstruction. The application has the advantages of simple process, strong compatibility, efficient and stable elimination of small-scale stacking faults, and significantly improved crystal quality of silicon carbide substrate, which provides a guarantee for the preparation of high-reliability power devices.

Description

Technical Field

[0001] This invention relates to the field of defect control technology for third-generation semiconductor materials, specifically to a method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Silicon carbide (SiC), as a typical third-generation semiconductor material, possesses excellent physicochemical properties such as wide bandgap, high thermal conductivity, and high breakdown field strength. It is irreplaceable in power electronic devices, radio frequency devices, and high-temperature, high-power applications, and is a core material driving the development of new energy, aerospace, and smart grids. As silicon carbide devices evolve towards higher power density, miniaturization, and higher reliability, stringent requirements are placed on the crystal quality of the substrate material. Various crystal defects in the substrate directly disrupt lattice integrity, leading to reduced device breakdown voltage, increased leakage current, and shortened lifespan, severely hindering device performance improvement and industrialization.

[0004] Stacking faults (SFs) are common planar defects in silicon carbide (SiC). Small SFs do not easily propagate spontaneously without external stimulation, but they tend to expand during device operation, leading to forward voltage drift and increased leakage current, severely impacting long-term device reliability. Therefore, effectively controlling and eliminating small SFs in SiC substrates is a key technological bottleneck for improving the core competitiveness of SiC devices. Existing SiC defect elimination technologies mostly rely on process control during epitaxial growth (such as temperature gradient optimization and gas source ratio adjustment) or high-cost modifications to growth equipment. These technologies are difficult to adapt to the post-processing requirements of already fabricated SiC substrates. For existing small SFs, there is a lack of clear, efficient, and repeatable elimination methods, and some technologies suffer from complex processes and poor compatibility with existing device manufacturing processes, failing to meet the demands of industrial mass production. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation. By forming interfacial stress through high-temperature oxidation, stacking faults are eliminated, and subsequent annealing improves the interfacial quality. Under optimized process parameters, no secondary strain damage is introduced, thus improving the controllability and reliability of defect handling.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] This invention provides a method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation, comprising the following steps:

[0008] A silicon carbide substrate containing the target small stacking fault was selected, and the silicon carbide substrate was scanned and characterized by photoluminescence to identify and locate the target small stacking fault.

[0009] The characterized silicon carbide substrate was cleaned to remove surface impurities. The cleaned silicon carbide substrate was then placed in a high-temperature oxidation furnace and subjected to high-temperature oxidation using dry oxygen as the oxidation source. An oxide layer was formed on the surface of the silicon carbide substrate in a controlled manner, causing the target small stacked layer to be misaligned towards the standard stacked sequence of the substrate.

[0010] After the oxide layer is formed, the silicon carbide substrate is subjected to nitric oxide-assisted annealing. The nitrogen passivation effect is used to solidify the interface lattice configuration after directional reconstruction, thereby completing the high-temperature oxidation elimination of small stacking faults.

[0011] As an optional implementation of the present invention, after the high-temperature oxidation elimination of small stacking faults is completed, the following process is also included:

[0012] The silicon carbide substrate after nitrogen passivation curing was re-characterized using a 426nm characteristic emission wavelength to confirm the elimination of the target small stacking fault. If the signal intensity of the 426nm characteristic emission wavelength corresponding to the target small stacking fault region on the silicon carbide substrate is reduced to the background noise level, it is determined that the target small stacking fault has been eliminated.

[0013] As an optional implementation of the present invention, identifying and locating target small stacking faults includes: identifying the spatial distribution, size and defect density of target small stacking faults using a characteristic emission wavelength of 426nm.

[0014] As an optional implementation of the present invention, the target small stacking fault is a continuous linear defect without breaks, the aspect ratio of the linear defect is greater than 5:1, and the length of the linear defect ranges from 0.05mm to 0.5mm.

[0015] As an optional implementation of the present invention, when identifying and locating the target small stacking fault, a fixed-position characteristic defect is selected as a spatial reference benchmark to track the positional change of the target small stacking fault before and after the high-temperature oxidation elimination treatment.

[0016] As an optional implementation of the present invention, the cleaning process includes sequential RCA cleaning and diluted hydrofluoric acid rinsing to remove organic contaminants, metallic impurities and native oxide layer from the surface of the silicon carbide substrate.

[0017] The process parameters for high-temperature oxidation treatment include: oxygen flow rate ranging from 150 sccm to 300 sccm, oxidation temperature ranging from 1250℃ to 1500℃, and oxidation time ranging from 2h to 4h.

[0018] As a further limitation of the present invention, by controlling the process parameters of the high-temperature oxidation treatment, the thickness of the formed oxide layer is controlled within the range of 45nm to 55nm, so as to maintain the interfacial shear stress required to trigger lattice reconstruction.

[0019] As an optional implementation of the present invention, the thermal expansion coefficient mismatch and molar volume expansion between the oxide layer and the silicon carbide substrate generate an interfacial stress field at the interface. The interfacial stress field drives the atomic layer stacking order of the target small stacking fault to undergo directional reconstruction, so that the target small stacking fault transforms from a metastable state to a standard stacking sequence of the matrix.

[0020] As an optional implementation of the present invention, the process parameters for nitric oxide-assisted annealing include: an annealing temperature ranging from 1100°C to 1400°C, and an annealing time ranging from 1 hour to 2 hours.

[0021] As a further limitation of the present invention, the nitric oxide-assisted annealing treatment introduces nitrogen atoms to passivate the silicon dangling bonds at the interface and replace the carbon defect sites at the interface, thereby eliminating the local non-uniform stress concentration caused by defects at the interface, thus solidifying the lattice configuration after directional reconstruction and preventing the interface stability from deteriorating in subsequent thermal processes.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] This invention, through precise control of high-temperature oxidation process parameters, strictly limits the oxide layer thickness to a critical window of 45nm to 55nm, successfully constructing an interfacial stress field at the SiO2 / SiC interface. This invention surpasses the limitations of traditional simple thermal annealing, utilizing the intrinsic compressive stress from molar volume expansion caused by the oxidation reaction, combined with the thermal stress generated during cooling due to the mismatch in thermal expansion coefficients, to generate a composite interfacial stress field at the interface. This elimination method, based on changes in mechanical boundary conditions, uses the composite interfacial stress field containing shear components as a clear physical driving force to directly drive the directional reconstruction of the atomic layer stacking order of the target small stacking faults, forcing them to transform from a metastable state to a more thermodynamically stable matrix standard sequence. After treatment using this method, the originally strong 426nm characteristic luminescence signal in the silicon carbide substrate was completely quenched, confirming that the small stacking faults were completely eliminated. Furthermore, under optimized process parameters, no secondary lattice distortion or new strain damage was introduced, demonstrating extremely high process repeatability and stability.

[0024] This invention establishes a closed-loop precision characterization system based on photoluminescence (PL) technology, using a characteristic emission wavelength of 426 nm as a dedicated fingerprint for identifying small stacking faults. Before implementing the method of this invention, scanning the silicon carbide substrate with this specific wavelength can accurately separate and locate linear defects with an aspect ratio greater than 5:1 from complex background noise. Simultaneously, a fixed-position characteristic defect is selected as a spatial reference benchmark to construct a high-precision defect distribution map. After implementing the method of this invention, a 426 nm wavelength scan is performed again on the same reference area. By comparing the changes in signal intensity before and after processing, the degree of defect elimination is quantitatively evaluated. This characterization strategy not only eliminates interference from other types of defects (such as microtubes and dislocations) but also achieves intuitive and visual verification of the elimination effect of micron-level small stacking faults. This invention significantly improves the controllability of the process, ensuring that the processing quality of each substrate is traceable and quantifiable, and providing reliable feedback data for optimizing process parameters.

[0025] The process flow design of this invention is highly compatible with existing silicon carbide substrate manufacturing lines, possessing strong industrialization capabilities. The core steps only require the use of mature high-temperature dry oxygen oxidation furnaces and nitric oxide-assisted annealing furnaces, eliminating the need to develop dedicated and expensive equipment or make large-scale modifications to existing production lines. The process conditions (such as oxidation at 1250℃~1500℃ and annealing at 1100℃~1400℃) are all within the capabilities of industry standard equipment. Furthermore, the oxygen, nitric oxide, and other gases used are all high-purity reagents commonly used in semiconductors, ensuring a secure supply chain and controllable costs. In addition, the simplified RCA cleaning and diluted hydrofluoric acid rinsing steps of this invention are easy to automate and integrate, significantly reducing human error and making it suitable for large-scale mass production, thus significantly improving the preparation efficiency of high-yield silicon carbide substrates.

[0026] This invention provides a solution to the challenge of small-scale stacking faults that restrict the yield of high-performance silicon carbide devices, and has broad applicability. Whether it's a 4-inch, 6-inch, or 8-inch silicon carbide substrate, as long as there are continuous, unbroken linear stacking faults with a length ranging from 0.05 mm to 0.5 mm, this method can efficiently repair them. By eliminating these metastable defects, the crystal integrity of the substrate is significantly improved, fundamentally blocking the path of stacking faults expanding into large-area stacking faults or causing device breakdown during epitaxial growth. This not only significantly improves the yield of power devices such as high-voltage Schottky diodes (SBDs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), but also significantly enhances the long-term reliability of devices under high-voltage, high-current conditions. This invention provides key material quality assurance for the fabrication of automotive-grade and aerospace-grade high-reliability silicon carbide power modules, and strongly promotes the large-scale application of third-generation semiconductor technology in high-end fields such as new energy vehicles and smart grids.

[0027] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0029] Figure 1 A schematic flowchart of a method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation is provided as an exemplary embodiment of the present invention.

[0030] Figure 2 A two-dimensional mapping of the first field of photoluminescence spectrum of a silicon carbide substrate before processing, provided as an exemplary embodiment of the present invention;

[0031] Figure 3 A two-dimensional mapping of the first field of photoluminescence spectrum of a silicon carbide substrate after processing, provided as an exemplary embodiment of the present invention;

[0032] Figure 4 A two-dimensional mapping of the second field photoluminescence spectrum of a silicon carbide substrate before processing, provided as an exemplary embodiment of the present invention;

[0033] Figure 5 A two-dimensional mapping of the second field of photoluminescence spectrum of a silicon carbide substrate after processing, provided as an exemplary embodiment of the present invention;

[0034] in, Figure 2 and Figure 4 The contrasting areas of light and dark displayed correspond to the luminous signal intensity of stacking fault defects. The target small stacking fault is manifested as a continuous linear bright area. Typical small stacking faults are circled with white dashed lines. Figure 3 and Figure 5 The complete disappearance of the linear bright area in the corresponding region proves that the target defect has been effectively eliminated.

[0035] Figures 2-5 The “CCD cts” marked in the text refers to the photon count of the charge-coupled device, which represents the photon signal count detected and quantified by the CCD sensor at the corresponding point of “specific spatial location” and “specific wavelength within the 426±10nm band” during the scanning process. Its value directly reflects the relative intensity of PL luminescence at that location and wavelength. The numbers 9177 and 9604 are the relative PL luminescence intensity values ​​(unit: CCD cts) at the corresponding micro-area location in the 426±10nm band. Detailed Implementation

[0036] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0037] It should be noted that the following detailed descriptions are exemplary and intended to provide further illustration of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0038] This invention provides a method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation. This method aims to solve the technical problem in existing technologies where small stacking faults within silicon carbide substrates are difficult to remove, severely affecting the quality of subsequent epitaxial growth and device reliability. The core concept of this invention is to abandon the traditional approach of simple high-temperature annealing or chemical etching, and instead utilize the physical and mechanical effects naturally generated at the interface between silicon dioxide and silicon carbide during high-temperature oxidation. Specifically, this invention constructs a composite interfacial stress field of specific intensity at the SiO2 / SiC interface by controlling the growth of an oxide layer of a specific thickness. This interfacial stress field is formed by the combined action of the intrinsic compressive stress caused by the molar volume expansion due to the oxidation reaction and the thermal stress generated during cooling due to the mismatch of the material's thermal expansion coefficients. Using this composite interfacial stress field as a driving force, the atomic layer stacking order of the target small stacking fault region is forced to undergo directional reconstruction, compelling the metastable stacking fault structure to transform into a more thermodynamically stable matrix standard sequence, thereby achieving the physical elimination of defects. Subsequently, nitric oxide-assisted annealing introduces nitrogen atoms to passivate the interfacial silicon dangling bonds and replace the interfacial carbon defect sites, eliminating the local non-uniform stress concentration caused by defects at the interface, thereby solidifying the directionally reconstructed lattice configuration and preventing interface stability degradation during subsequent thermal processes. The technical solution of this invention will be described in detail below with specific process steps, parameter ranges, physical mechanisms, and experimental examples.

[0039] Before implementing the method of this invention, it is necessary to first clarify the characteristics of the object being processed. The target defect of this invention is a small stacking fault in a silicon carbide substrate. This type of defect manifests as a continuous, unbroken linear defect with a distinctive geometric shape, namely, an aspect ratio typically greater than 5:1, and a length ranging from 0.05 mm to 0.5 mm. Although these defects are tiny, they are highly identifiable in photoluminescence (PL) spectra, with their characteristic emission wavelength precisely located around 426 nm. This specific emission wavelength is determined by the local energy level changes caused by the stacking fault and is a unique characteristic of this type of defect. In contrast, silicon carbide substrate defects or other types of defects (such as microtubules, threaded dislocations, etc.) do not produce strong emission signals at this wavelength, or their emission wavelengths are significantly different (for example, the characteristic emission wavelength of rod-shaped stacking faults is approximately 432 nm). Therefore, the 426 nm characteristic emission wavelength becomes the exclusive basis for identifying, locating, and verifying the effectiveness of target defect elimination in this invention.

[0040] In practice, to ensure strict spatial consistency between the pre- and post-process comparisons and to avoid data misjudgment due to sample movement or scanning area deviation, this invention also introduces a spatial reference mechanism. Specifically, a fixed-position, well-defined defect on the substrate (such as the aforementioned rod-shaped stacking fault) or other easily traceable microscopic morphological features is selected as a reference. In each subsequent processing and characterization step, this reference is used as the origin of the coordinate system to precisely track the positional changes and signal intensity evolution of the target small stacking fault, thereby ensuring the accuracy and repeatability of the experimental data.

[0041] like Figure 1 As shown, the specific implementation process of the present invention begins with step S1 (pre-processing characterization stage). In this stage, the operator selects a silicon carbide substrate containing the target small stacking faults as the sample to be processed. The crystal form of the silicon carbide substrate is usually 4H-SiC, which is the most mainstream crystal form in the current power semiconductor device manufacturing, but the present invention is also applicable to other crystal forms of silicon carbide materials.

[0042] The source of the silicon carbide substrate is not specifically limited in this invention; commercially available products well-known to those skilled in the art can be used, as long as the surface or near-surface of the substrate contains target small stacking faults that meet the above-mentioned geometric characteristics (aspect ratio greater than 5:1, length 0.05~0.5mm) and have a defect density greater than zero. After selecting a suitable silicon carbide substrate, a comprehensive scanning characterization is performed using photoluminescence technology. Photoluminescence technology is a non-destructive optical detection method. Its basic principle is to use a laser of a specific wavelength to excite the semiconductor material, causing electrons to jump from the valence band to the conduction band. Subsequently, when the electrons fall back to a lower energy level, they release photons. Since different defects in the material correspond to different energy level structures, the wavelengths of the photons released during radiative recombination also differ. Therefore, by analyzing the emission spectrum, the type and distribution of defects can be accurately identified.

[0043] In the specific execution of step S1, a preliminary large-scale scan of the entire substrate is first required to determine the approximate distribution area of ​​the target defects. This process typically employs a large scan step size, such as 100 μm, to quickly cover the entire wafer surface and obtain a global overview of the defect distribution. Once the region of interest containing the target small stacking fault is identified, the process switches to fine scanning mode. In fine scanning mode, the scan step size is significantly reduced to 5 μm or even smaller to ensure that minute linear defects with a length of only 0.05 mm can be clearly distinguished. Simultaneously, to obtain images with a high signal-to-noise ratio, the integration time for each scan point is set to 0.01 seconds or optimized according to the device sensitivity. After data acquisition, the crucial data processing stage begins. By filtering the acquired full-spectrum data, the emission peak intensity in the 426 nm band and its adjacent range is specifically extracted for integration. Through this processing, the originally complex spectral data, which was mixed with matrix emission and emission from other defects, is transformed into a clear two-dimensional mapping image (PL Mapping). In a two-dimensional mapping image, the brightness level directly corresponds to the strength of the 426nm characteristic emission signal, which in turn reflects the spatial distribution density and size of the target's small stacking faults.

[0044] To further quantify the defect state and establish a reliable comparison benchmark, step S1 requires the selection and recording of the reference benchmark. As previously mentioned, this invention preferably uses rod-shaped stacking faults with a characteristic emission wavelength of approximately 432 nm as a spatial location reference. These rod-shaped stacking faults typically have a relatively stable morphology, and during subsequent high-temperature oxidation, their emission characteristics change differently from the target small stacking faults, or their positions are extremely fixed, making them very suitable as a benchmark. The operator will select two typical fields of view in the photoluminescence mapping map for detailed recording. The first field of view was selected as a 1500 μm × 1500 μm square region containing a distinct rod-shaped stacking fault. Within this region, multiple linear defects (0.05 to 0.4 mm in length) confirmed by spectral analysis to be small stacking faults were distributed. The second field of view was selected as an adjacent 1050 μm × 1500 μm rectangular region containing another distinct rod-shaped stacking fault. Within this region, multiple linear defects (0.05 to 0.3 mm in length) confirmed by spectral analysis to be small stacking faults were distributed. The PL mapping images of these two fields of view before processing (e.g., ...) were recorded. Figure 2 and Figure 4 As shown in the diagram, numerous continuous linear bright lines can be clearly observed distributed around the rod-shaped stacking faults. These bright lines represent the target small stacking faults to be eliminated, and their defect density is significantly greater than zero. This step not only clarifies the initial defect state but also provides irrefutable raw data support for subsequent process effect verification.

[0045] After completing the characterization in step S1, the process proceeds to step S2 (cleaning and high-temperature oxidation). This step is the core of the defect elimination process in this invention, and it comprises two closely linked sub-processes: surface cleaning and controlled high-temperature oxidation. A rigorous cleaning process is essential first, as any residual organic contaminants, metallic impurities, or natural oxide layers on the substrate surface will severely interfere with the growth quality of the subsequent oxide layer, leading to uneven distribution of the interfacial stress field and even inducing new defects. The cleaning process employed in this invention is a combination of RCA cleaning and diluted hydrofluoric acid rinsing.

[0046] RCA cleaning (Radio Corporation of America cleaning) is a standard wet cleaning process in the semiconductor industry, typically consisting of two steps: SC-1 (a mixture of ammonia, hydrogen peroxide, and deionized water) and SC-2 (a mixture of hydrochloric acid, hydrogen peroxide, and deionized water). SC-1 utilizes the oxidizing power of hydrogen peroxide to decompose organic contaminants, while the alkaline environment causes both the substrate surface and particles to become negatively charged, removing surface particles through electrostatic repulsion. SC-2 primarily removes metal ion impurities, using the acidic environment of hydrochloric acid to dissolve metal oxides and form soluble complexes. After RCA cleaning, although most contaminants are removed from the substrate surface, a new thin native oxide layer often forms, and the surface may adsorb polar groups such as hydroxyl groups. Therefore, a diluted hydrofluoric acid (HF) rinsing is required immediately afterward. Hydrofluoric acid has a strong ability to etch silicon dioxide. By controlling the concentration of hydrofluoric acid (typically 1%~5%) and the rinsing time, the native oxide layer on the surface can be precisely stripped away, exposing a fresh, clean, and hydrophobic hydrogen-terminated surface to the silicon carbide substrate. After cleaning, to prevent watermarks or re-oxidation caused by deionized water residue, the substrate surface must be dried immediately with high-purity nitrogen. The purity of the high-purity nitrogen is typically required to be above 99.999%, and the drying process must be carried out in a dust-free environment to ensure that there is no moisture or impurities remaining on the substrate surface, creating perfect initial conditions for subsequent high-temperature oxidation.

[0047] After cleaning and drying, the substrate is immediately placed in a high-temperature oxidation furnace for controlled high-temperature oxidation. This step is preferably performed in a high-temperature oxidation furnace. High-purity dry oxygen is used as the oxidation gas source, and the presence of moisture or other reducing gases is strictly prohibited to prevent runaway oxidation or the formation of non-stoichiometric oxides. During the high-temperature oxidation process, oxygen molecules diffuse through the formed oxide layer to the SiC surface, reacting with silicon atoms to form silicon dioxide (SiO2). This reaction process is accompanied by significant volume expansion because the molar volume of silicon dioxide is much larger than the molar volume of silicon atoms in silicon carbide (actually, it compares the volume of SiC consumed with the volume of SiO2 generated; typically, the volume of SiO2 generated is more than twice the volume of SiC consumed. Furthermore, considering the expulsion of C atoms from SiC, a large compressive stress is generated at the interface). In addition, there is a significant difference in the coefficients of thermal expansion between silicon dioxide and silicon carbide (the coefficient of thermal expansion of SiC is approximately 4.3 × 10⁻⁶). -6 / K, while the coefficient of thermal expansion of SiO2 is approximately 0.5×10. -6 During the cooling process after high-temperature oxidation, the two components shrink at different rates, resulting in additional thermal mismatch stress at the interface. These two stresses (intrinsic compressive stress and thermal mismatch stress) work together at the interface to form a composite interfacial stress field.

[0048] This invention ensures that the generated interfacial stress field is sufficient to drive lattice reconstruction without causing oxide layer cracking or plastic relaxation through precise control of oxidation process parameters. The specific process parameter window was determined through extensive experimental optimization: oxygen flow rate controlled between 150 and 300 sccm, oxidation temperature set between 1250 and 1500°C, and oxidation time lasting 2 to 4 hours. Under these parameters, a uniform SiO2 oxide layer with a thickness strictly controlled between 45 and 55 nm can be formed on the surface of a silicon carbide substrate. This thickness range is one of the key innovations of this invention, representing a balance between effective accumulation of interfacial strain energy and avoiding excessive thermal stress that could damage the substrate. If the oxide layer is too thin (less than 45 nm), the accumulated strain energy is insufficient to generate the critical shear stress required to trigger lattice reconstruction, resulting in incomplete defect elimination; conversely, if the oxide layer is too thick (greater than 55 nm), the stress gradient at the interface will be unevenly distributed, or excessive thermal stress will be generated during the cooling stage, leading to the risk of substrate cracking. Only by locking the thickness within a narrow window of 45~55nm can we ensure that the interfacial shear stress is always maintained at the optimal level, which not only guarantees the effectiveness of the driving force, but also avoids substrate cracking or the generation of new defects caused by excessive stress.

[0049] During high-temperature oxidation, the interfacial stress field acts by physically altering the energy state of the defect region. The target small-scale stacking fault is essentially an error in the atomic stacking order of a crystal, existing in a high-energy metastable state. Under the influence of the shear component in the strong composite interfacial stress field, the atomic layers in the stacking fault region are driven by directional mechanical forces, forced to overcome energy barriers, and undergo displacement and rearrangement. This rearrangement is not random but occurs along the most thermodynamically favorable direction, transforming the incorrect stacking sequence into the correct matrix standard sequence. As the reconstruction of the atomic stacking sequence is completed, the original stacking fault structure disintegrates, and the defect disappears. This process is entirely driven by changes in mechanical boundary conditions, possessing a clear physical mechanism, unlike traditional thermal annealing which relies solely on thermal energy to induce atomic diffusion; therefore, it is more efficient and targeted.

[0050] After step S2, the substrate surface is covered with a stress-rich silicon dioxide layer, and there may be a large number of dangling bonds and incompletely reacted carbon clusters at the interface. To solidify the lattice reconstruction achieved in step S2 and further improve the interface quality, step S3 (NO-assisted annealing stage) is then performed. This step is crucial to prevent defect regeneration. After high-temperature oxidation, although the stacking faults are reconstructed under stress, this new lattice configuration may still be thermodynamically unstable, especially in subsequent high-temperature processes. Dangling bonds and carbon clusters at the interface may form localized non-uniform stress concentration points, providing a potential driving force for lattice distortion near the interface, which is detrimental to the long-term stability of the reconstructed lattice configuration. To address this issue, this invention introduces nitric oxide (NO) gas as the annealing atmosphere.

[0051] Nitric oxide (NO)-assisted annealing is performed in a dedicated annealing furnace with rigorously optimized process parameters: the annealing temperature is set between 1100 and 1400°C, and the annealing time lasts 1 to 2 hours. Under this high-temperature environment, NO gas molecules decompose, releasing reactive nitrogen atoms. These nitrogen atoms have extremely small atomic radii and high chemical reactivity, enabling them to rapidly diffuse to the SiO2 / SiC interface. The role of nitrogen atoms at the interface is mainly twofold: First, they passivate interfacial silicon dangling bonds. During the oxidation process, silicon carbide surfaces retain a large number of silicon dangling bonds, which are the main source of interface states and the root cause of device instability. Nitrogen atoms preferentially combine with these silicon dangling bonds to form stable Si-N bonds, effectively passivating the interface and significantly reducing the interface state density. Second, they eliminate interfacial carbon defects. During oxidation, some carbon atoms may not completely escape, forming carbon defects at the interface. These carbon defects are a potential cause of high interface state defects. Nitrogen atoms can replace or fix these carbon defect sites, purifying the interface structure and thus further reducing defect density and improving channel carrier mobility.

[0052] By using nitric oxide (NO)-assisted annealing, the lattice configuration at the interface is stabilized in the reconstructed state. The introduction of nitrogen atoms not only eliminates dangling bonds that cause instability but also avoids lattice distortion caused by localized non-uniform stress concentration at the interface due to defects, ensuring that it does not degrade further during subsequent epitaxial growth or high-temperature device fabrication processes. Experiments show that the samples treated with NO-assisted annealing exhibit significantly improved structural stability of the oxide layer, bias temperature stress reliability, and a significant reduction in interfacial charge density. This lays a solid material foundation for the fabrication of high-performance silicon carbide MOSFETs and other devices.

[0053] After completing step S3, the entire defect elimination and interface optimization process is basically finished, and the process proceeds to step S4 (post-processing verification stage). The purpose of this step is to quantitatively and qualitatively confirm whether the target small stacking faults have been completely eliminated and whether the process has introduced new defects. The verification method is completely consistent with step S1, using the same photoluminescence technique to characterize the processed substrate. To ensure the rigor of the comparison, the scanning area must be strictly aligned with the first and second fields of view recorded in step S1, that is, using the previously selected rod-shaped stacking fault or other spatial reference as the positioning point to ensure that the scanned area is exactly the same physical region.

[0054] In post-processing characterization, the 426nm characteristic emission wavelength is also used as the detection basis. The system performs a fine scan on the processed substrate to acquire a new PL two-dimensional mapping image. The newly acquired image is compared point by point with the original image recorded in step S1. If the process of this invention is successfully implemented, the expected result should be that, in the first and second fields of view, the intensity of the 426nm characteristic emission signal corresponding to the target small stacking fault is reduced to the background noise level, that is, the original bright fringes disappear on the PL mapping image, and the emission intensity of this area is no different from that of the surrounding perfect substrate area. At the same time, the position and shape of the rod-shaped stacking fault (432nm emission) or other characteristic defects, which serve as a spatial reference, should remain unchanged. This proves the accuracy of the scanning positioning and eliminates misjudgment caused by sample movement.

[0055] In addition to confirming the disappearance of the target defect, step S4 also needs to check whether new defects have been introduced. A full-spectrum scan is used to observe whether new abnormal emission peaks appear or whether the emission uniformity of the substrate is compromised. Ideally, the result should be: the target small stacking fault signal completely disappears without introducing any secondary strain damage or other types of defects, and the overall emission uniformity of the substrate is improved. Experimental data (e.g.) Figure 3 and Figure 5 As shown in the figure, this is fully demonstrated: after the cleaning, high-temperature oxidation and NO-assisted annealing treatment of the present invention, the small stacking faults of the target under different fields of view are stably and completely eliminated, the 426nm signal is completely invisible, while the reference is still clearly visible, which confirms the efficiency and reliability of the method.

[0056] To illustrate the implementation details and effects of the present invention more specifically, a detailed description is provided below with reference to specific examples. It should be noted that the following examples are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0057] Example 1: This example demonstrates a specific operational procedure for eliminating small stacking faults in silicon carbide based on high-temperature oxidation, which strictly follows the step logic of steps S1 to S4 mentioned above.

[0058] In step S1 (preprocessing characterization), a 6-inch 4H-SiC substrate was selected as the experimental sample. This substrate was double-sided polished, but exhibited a certain density of small stacking faults in the near-surface region. First, the substrate was scanned using a photoluminescence spectrometer. The initial scan used a 100μm step size to quickly survey the entire wafer, locating several areas with high defect density. Subsequently, two representative fields of view were selected for detailed imaging. The first field of view was a 1500μm × 1500μm square region containing a distinct rod-shaped stacking fault. Its emission wavelength was confirmed by spectral analysis to be 432nm, and this was marked as spatial reference point A. Within this region, multiple linear defects, confirmed by spectral analysis to be small stacking faults, were distributed, with lengths ranging from 0.05 to 0.4 mm. The second field of view was selected as an adjacent rectangular region of 1050μm×1500μm. This region contains another obvious rod-shaped stacking fault, whose emission wavelength was confirmed to be 432nm by spectral analysis. This region was marked as spatial reference point B. In addition, there are multiple parallel linear defects with lengths between 0.05 and 0.3mm distributed in this region. These defects were confirmed by spectral analysis to be target small stacking faults with a characteristic emission wavelength of 426nm.

[0059] In fine scanning mode, the scan step size was set to 5 μm and the single-point integration time to 0.01 seconds. Integral imaging was performed on the light intensity in the 426±10 nm band. The resulting unprocessed PL mapping (corresponding to...) Figure 2 and Figure 4 The results show that in the first field of view, the reference point rod-shaped stacking fault-A is clearly visible with stable brightness, and multiple bright linear fringes appear in the image. In the second field of view, the reference point rod-shaped stacking fault-B is also clearly visible with stable brightness, and multiple bright linear fringes appear in the image. These fringes appearing in both fields of view represent the target small stacking faults to be eliminated, and their signal intensity is much higher than the background, indicating a defect density significantly greater than zero. This data was completely saved as a benchmark for subsequent effect evaluation.

[0060] In step S2 (cleaning and high-temperature oxidation treatment), the characterized substrate is first subjected to a rigorous wet cleaning process. The substrate is immersed in a standard RCA-1 solution (NH4OH:H2O2:H2O=1:1:5, 75°C) for 10 minutes to remove organic contaminants and particles from the surface. It is then rinsed with deionized water and immersed in an RCA-2 solution (HCl:H2O2:H2O=1:1:6, 75°C) for 10 minutes to remove metal ions. Next, the substrate is transferred to a diluted hydrofluoric acid solution (HF:H2O=1:50) and rinsed for 30 seconds to thoroughly remove the natural oxide layer on the surface, making the surface hydrophobic. After cleaning, the substrate surface is immediately dried using a high-purity nitrogen gun with a flow rate of 20 slm to ensure no watermarks remain.

[0061] The dried substrate was quickly placed into a preheated high-temperature oxidation furnace. The furnace temperature was set to 1250°C, and after the temperature stabilized, high-purity dry oxygen was introduced at a flow rate of 200 sccm. Timing was started to initiate the high-temperature oxidation reaction. The oxidation process lasted 3.5 hours. During this period, oxygen reacted with the SiC surface to generate SiO2. Based on the pre-defined growth rate, the expected oxide layer thickness was approximately 50 nm, falling precisely within the critical window of 45-55 nm specified in this invention. After oxidation, oxygen supply was stopped, high-purity nitrogen was introduced for protection, and the substrate was cooled to room temperature at a controlled rate (e.g., 5°C / min). This slow cooling process helps to ensure uniform distribution and effective retention of interfacial stress, avoiding microcracks caused by rapid cooling.

[0062] In step S3 (NO-assisted annealing), the oxidized substrate (now covered with a 50nm thick SiO2 layer) is transferred to a NO annealing furnace. Nitric oxide (NO) gas with a purity of 99.999% is introduced into the furnace, with the flow rate controlled within an appropriate range to maintain a normal or slightly positive pressure environment. The furnace temperature is raised to 1250°C and maintained at this temperature for 1 hour. During this process, the active nitrogen atoms generated by the decomposition of NO gas diffuse to the SiO2 / SiC interface, reacting with dangling bonds and carbon clusters at the interface to form stable Si-N bonds and remove carbon impurities. After annealing, the heating power is turned off, and the substrate is allowed to cool naturally to below 600°C under a NO atmosphere, then switched to nitrogen purging for cooling to room temperature. This step effectively solidifies the reconstructed lattice formed in step S2, eliminates localized non-uniform stress concentrations caused by defects at the interface, and ensures the stability of the reconstructed lattice configuration in subsequent high-temperature processes.

[0063] In step S4 (post-processing verification), the processed substrate is removed and placed back into the photoluminescence spectrometer. Strictly following the coordinates recorded in step S1, and using reference points A and B (rod-like stacking faults) as positioning markers, the first and second fields of view are rescanned. The scanning parameters (step size 5 μm, integration time 0.01 s, wavelength 426 nm) are kept completely consistent with those in step S1 to ensure data comparability.

[0064] The obtained processed PL mapping (corresponding to) Figure 3 and Figure 5 The results show that the positions of reference points A and B in both fields of view are essentially the same as before processing, demonstrating the accuracy of the scanning area and the stability of the process. The previously clear and bright linear target small stacking fault signal has completely disappeared, and the original 426nm luminescence intensity has decreased to the background level, resulting in a uniform dark field in the image, indistinguishable from the luminescence intensity of a perfect lattice region. Comparing the images before and after processing, it can be clearly concluded that under the process conditions of this example (oxidation at 1250℃ for 3.5 hours to generate a 50nm oxide layer, followed by NO annealing at 1250℃ for 1 hour), the target small stacking faults in the substrate are completely eliminated, and no new defects or residual defects are observed.

[0065] Example 2: To verify the robustness of the process parameter window of the present invention, this example is conducted under process parameters different from those in Example 1, using another 4H-SiC substrate with a similar defect density.

[0066] In step S1, the characterization results confirmed the presence of a target small stacking fault with a length of 0.1 mm.

[0067] In step S2, the high-temperature oxidation parameters are adjusted: the oxygen flow rate is set to 300 sccm (upper limit), the oxidation temperature is increased to 1400℃, and the oxidation time is shortened to 2.5 hours. Under these conditions, the thickness of the generated oxide layer is still within the effective window of 45~55nm.

[0068] In step S3, the NO annealing parameters are adjusted: the annealing temperature is increased to 1350℃ and the annealing time is extended to 1.5 hours to enhance the diffusion depth of nitrogen atoms and the passivation effect.

[0069] The characterization results of step S4 show that the 426nm characteristic emission signal was also completely quenched, and the defect elimination rate reached 100%. This indicates that the parameter range provided by the present invention (oxygen flow rate 150~300sccm, temperature 1250~1500℃, time 2~4h; annealing temperature 1100~1400℃, time 1~2h) has good process tolerance. As long as the thickness of the final oxide layer falls within the critical window of 45~55nm and sufficient NO passivation time can be guaranteed, excellent defect elimination effect can be achieved.

[0070] Example 3: This example aims to illustrate the impact of oxide layer thickness on defect elimination, demonstrating the importance of the 45-55nm equilibrium window. Three substrates with similar initial defect states were selected and subjected to oxidation treatments for different durations, while other conditions (cleaning, annealing) remained consistent.

[0071] Sample A: Oxidation time 1 hour, resulting in an oxide layer thickness of approximately 20 nm;

[0072] Sample B: Oxidation time 3 hours, resulting in an oxide layer thickness of approximately 50 nm (in line with the window of this invention);

[0073] Sample C: Oxidation time 8 hours, resulting in an oxide layer thickness of approximately 120 nm (outside the window of this invention).

[0074] The characterization results of step S4 are as follows:

[0075] Sample A (20nm): The PL mapping shows that although the signal at 426nm is weakened, it is still clearly visible, indicating that the interfacial stress is insufficient to drive complete lattice reconstruction and the defect elimination is incomplete.

[0076] Sample B (50nm): The PL mapping diagram shows that the 426nm signal completely disappeared, the defect was completely eliminated, and the effect was the best.

[0077] Sample C (120nm): The PL mapping shows that the 426nm signal remains, and there are slight signs of warping on the substrate surface.

[0078] Analysis suggests that an excessively thick oxide layer generates excessive thermal stress during cooling due to thermal mismatch, leading to uneven distribution of the interfacial stress gradient. This, in turn, causes slight warping of the substrate surface, impairing the integrity of the interfacial structure and making it impossible to effectively maintain the shear component in the composite interfacial stress field required for drive reconstruction. This comparative experiment strongly demonstrates that controlling the oxide layer thickness within the range of 45–55 nm is crucial for achieving efficient and stable defect elimination; deviations from this window will result in process failure.

[0079] In summary, this invention provides a method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation. Through a scientifically designed three-step strategy of cleaning, controlled oxidation, and NO annealing, it cleverly utilizes the intrinsic physical and mechanical properties of the material interface. Step S1, precise photoluminescence characterization, provides a clear target and verification benchmark for the process. Step S2, by precisely controlling the oxide layer thickness within a balance window of 45-55 nm, constructs an interfacial stress field sufficient to drive atomic-oriented reconstruction, fundamentally eliminating the structural basis of small stacking faults. Step S3 utilizes NO-assisted annealing to achieve chemical passivation and structural solidification of the interface, preventing defect regeneration. The entire method requires no expensive specialized equipment, has a simple process flow, controllable parameters, and is highly compatible with existing silicon carbide production lines. Experimental results show that this invention can stably and completely eliminate small stacking faults in the length range of 0.05-0.5 mm, completely quenching the 426 nm characteristic emission signal, and without introducing secondary damage under optimized process parameters. This not only significantly improves the crystal quality of silicon carbide substrates, but also provides crucial material assurance for the subsequent fabrication of high-yield, high-reliability silicon carbide power devices (such as MOSFETs and SBDs), demonstrating extremely high engineering application value and broad market prospects. Whether for scientific research or large-scale industrial production, this invention provides a set of effective, theoretically sound, and rigorously standardized technical solutions.

[0080] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation, characterized in that, Includes the following steps: A silicon carbide substrate containing the target small stacking fault is selected, and the silicon carbide substrate is scanned and characterized by photoluminescence to identify and locate the target small stacking fault. The characterized silicon carbide substrate is cleaned to remove surface impurities. The cleaned silicon carbide substrate is then placed in a high-temperature oxidation furnace and subjected to high-temperature oxidation using dry oxygen as the oxidation source. An oxide layer is formed on the surface of the silicon carbide substrate in a controlled manner, causing the target small stacked fault to transform from a metastable state to a standard stacked sequence of the substrate. The process parameters for the high-temperature oxidation treatment include: an oxygen flow rate ranging from 150 sccm to 300 sccm, an oxidation temperature ranging from 1250°C to 1500°C, and an oxidation time ranging from 2 h to 4 h. By controlling the process parameters of the high-temperature oxidation treatment, the thickness of the formed oxide layer is controlled within the range of 45 nm to 55 nm to maintain the interfacial shear stress required to trigger lattice reconstruction. The thermal expansion coefficient mismatch and molar volume expansion between the oxide layer and the silicon carbide substrate generate an interfacial stress field at the interface. This interfacial stress field drives the atomic layer stacking sequence of the target small stacking fault to undergo directional reconstruction, causing the target small stacking fault to transform from a metastable state to a standard stacking sequence of the matrix. After the oxide layer is formed, the silicon carbide substrate is subjected to nitric oxide-assisted annealing. The nitrogen passivation effect is used to solidify the oriented reconstructed interface lattice configuration, thereby completing the high-temperature oxidation elimination of small stacking faults. The process parameters of the nitric oxide-assisted annealing include: an annealing temperature ranging from 1100°C to 1400°C and an annealing time ranging from 1 hour to 2 hours. The nitric oxide-assisted annealing introduces nitrogen atoms to passivate the silicon dangling bonds at the interface and replace the carbon defect sites at the interface, thereby eliminating the local non-uniform stress concentration caused by defects at the interface, thus solidifying the oriented reconstructed lattice configuration and preventing the interface stability from deteriorating in subsequent thermal processes. After completing the high-temperature oxidation elimination of small stacking faults, the following processes are also included: The silicon carbide substrate after nitrogen passivation curing was re-characterized using a 426nm characteristic emission wavelength to confirm the elimination of the target small stacking fault. If the signal intensity of the 426nm characteristic emission wavelength corresponding to the target small stacking fault region on the silicon carbide substrate is reduced to the background noise level, it is determined that the target small stacking fault has been eliminated.

2. The method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation as described in claim 1, characterized in that, Identifying and locating the target small stacking fault includes: identifying the spatial distribution, size, and defect density of the target small stacking fault using a characteristic emission wavelength of 426 nm.

3. The method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation as described in claim 1, characterized in that, The target small stacking fault is a continuous, unbroken linear defect with an aspect ratio greater than 5:1 and a length range of 0.05 mm to 0.5 mm.

4. The method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation as described in claim 1, characterized in that, When identifying and locating the target small stacking fault, a fixed-position characteristic defect is selected as a spatial reference benchmark to track the positional changes of the target small stacking fault before and after the high-temperature oxidation elimination treatment.

5. The method for eliminating small stacking faults in silicon carbide based on high-temperature oxidation as described in claim 1, characterized in that, The cleaning process includes sequential RCA cleaning and diluted hydrofluoric acid rinsing to remove organic contaminants, metallic impurities, and the natural oxide layer from the surface of the silicon carbide substrate.

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