Entropy source, quantum random number generator and electronic circuit

Abstract

A monolithically integrated entropy source comprising a photon source and a photon detector wherein the photon source is designed to emit photons wherein the photon source comprises a first housing wherein the first housing is formed by a first bottom surface, a first top surface and at least one first side surface interconnecting the first bottom surface and the first top surface, the photon detector is designed to detect photons emitted by the photon source, wherein the first bottom surface of the photon source is arranged towards the photon detector.

Description

Technical Field

[0001] This disclosure primarily relates to an entropy source, a quantum random number generator, and an electronic circuit having an entropy source and / or a quantum random number generator. Background Technology

[0002] In numerous scientific and technological fields, the determination of random events and probabilities plays a crucial role. For example, Monte Carlo simulations, the personalization of transmitters and / or components, bus addressing methods, and secure encryption methods all rely heavily on providing random numbers. In this regard, a distinction is generally made between pseudo-random numbers and true random numbers.

[0003] Pseudo-random numbers are generated by pseudo-random number generators (PRNGs) using deterministic formulas, meaning they are not absolutely random. True random number generators (TRNGs), used to provide truly random numbers, are generally based on real, unpredictable processes, such as thermal or atmospheric noise, rather than on artificially generated deterministic algorithmic patterns. However, such non-deterministic random number generators based on extrinsic parameters exhibit weak correlations due to the underlying random elements they rely on, and their results may still tend, for example, slightly towards larger or even numbers, thus making the generated random numbers at least somewhat predictable. Furthermore, such true random number generators (TRNGs), for example, when using thermal entropy sources for random numbers, may be manipulated externally if poorly constructed.

[0004] In contrast, the so-called quantum random number generator (QRNG), as a special subclass of true random number generator (TRNG), is based on the fundamental quantum random number generation process and is at least theoretically independent of any other external factors and effects that affect statistics. Therefore, there is no so-called side channel that affects the random number generation process.

[0005] Quantum random number generators can be implemented using the random properties of photons (as photonic quantum random number generators). A traditional concept of random number generation is based on utilizing the random arrival times of photons at a photon detector. This distribution effect is based on the inherent statistical properties of photons from a relevant photon source (which, in principle, cannot be calculated deterministically) and can be used to provide truly random numbers. The arrival times of photons at a single-photon detector typically follow an exponential distribution.

[0006] Patent document EP3529694 relates to a (quantum) random number generator comprising a photon source, one or more photon detectors configured to detect at least one photon belonging to a stream of detected photons generated by the photon source, and an electronic sampling mechanism functionally connected to the photon detectors (configured to perform a logical method for extracting a binary sequence based on the arrival time of each detected photon). In this random number generator, the photon source and photon detectors are juxtaposed and integrated into a single semiconductor substrate.

[0007] Patent document WO2016 / 016741A1 relates to a (quantum) random number generator comprising a photon source and one or more SPAD-type photon detectors (configured to detect a photon flux equal to λ), wherein photons are generated by the photon source. The random number generator also includes electronic sampling mechanisms. These electronic sampling mechanisms are configured to record the arrival time t of photons incident on each SPAD-type photon detector for each observation window Tw, and are further configured to convert the arrival time t into a binary sequence. The photon source and electronic sampling mechanisms are configured such that the product λ*Tw is less than or equal to 0.01. Summary of the Invention

[0008] The optional technical objective of this disclosure is to provide an apparatus and / or method suitable for improving the prior art.

[0009] One possible specific objective is to propose an entropy source or quantum random number generator with high security. Alternatively, another possible specific objective is to propose an entropy source or quantum random number generator with a small footprint.

[0010] The solutions disclosed herein for achieving the above objectives are characterized by the features of each independent claim. Optional improvements to this disclosure are described in the dependent claims.

[0011] Accordingly, the present invention achieves the above-mentioned objective through a monolithically integrated entropy source, optionally used for a quantum random number generator. The entropy source includes a nondeterministic photon source designed to emit photons. The photon source includes a first housing, wherein the first housing is formed by a first bottom surface, a first top surface, and at least one first side surface connecting the first bottom surface and the first top surface. The entropy source includes a photon detector designed to detect photons emitted by the photon source. The first bottom surface of the photon source is arranged facing the photon detector.

[0012] The photon detector may include a second housing, wherein the second housing is formed by a second bottom surface, a second top surface, and at least one second side surface connecting the first bottom surface and the first top surface. The first bottom surface of the photon source may be arranged facing the second bottom surface of the photon detector.

[0013] Additionally or alternatively, to achieve the above objectives, this disclosure also proposes a monolithically integrated entropy source, optionally an entropy source for a quantum random number generator, wherein the entropy source includes a photon source designed to emit photons. The entropy source includes a photon detector designed to detect photons emitted by the photon source. The photon detector includes a second housing formed by a second bottom surface, a second top surface, and at least one second side surface connecting the second bottom surface and the second top surface. The second bottom surface of the photon detector is arranged facing the photon source.

[0014] That is, an entropy source integrally constructed on a semiconductor substrate having a surface can be provided. This entropy source can be a vertical entropy source having at least one photon source and at least one photon detector. Here, the surface of the semiconductor substrate can be defined as a horizontal plane having a first planar direction (first planar vector) and a second planar direction (second planar vector) different from the first planar direction. Regarding the first and second directions of the horizontal plane of the semiconductor substrate surface, the photon source and photon detector can be arranged in the semiconductor substrate along a vertical direction relative to the first and second planar directions. That is, the photon source can be arranged between the surface and the photon detector. Alternatively, the photon detector can be arranged between the surface and the photon source. It is conceivable that the entropy source is part of a (random number) generator that generates truly random numbers based on quantum processes, configured to generate one or more random bits depending on the output signal of the entropy source.

[0015] A monolithically integrated entropy source can be understood as an entropy source in which a photon source and a photon detector are constructed in a semiconductor substrate, which optionally has one, two or more inseparable interconnect layers.

[0016] An entropy source can be understood as a source of physical information that outputs random or nondeterministic signals. This can be mainly achieved by including nondeterministic photon sources as entropy sources. That is, an entropy source with nondeterministic output signals is proposed.

[0017] It can be conceived that the entropy source of the nondeterministic output signal can be understood as an entropy source that meets the tests (approximately 15 items) listed in the NIST SP800-22 version 1 guide published by the National Institute of Standards and Technology (NIST) in April 2010. These tests can be used to determine whether the entropy source and / or the random number generator including the entropy source have sufficient entropy (or not sufficient entropy), that is, whether it is nondeterministic.

[0018] A photon source can be understood as a physical unit designed to emit photons during its operation.

[0019] A nondeterministic photon source can be understood as a photon source whose timing of emitting one (or more) photons cannot be predicted or precisely predicted. In other words, the exact moment of photon emission is random. However, it is still conceivable that, for example, depending on environmental influences (such as temperature), the probability of the number of photons emitted within a predetermined time period can be estimated.

[0020] A photon detector can be understood as a physical unit designed to detect or measurably collect photons during its operation.

[0021] The housing of a photon detector or photon source can be understood as the surface that is in contact with the environment of the photon detector or photon source (i.e., a semiconductor substrate).

[0022] Photon detectors and / or photon sources can be substantially cylindrical in shape. The cylinder has a circular base and a circular top surface, which are arranged opposite each other. Side surfaces or lateral faces extend along the entire height of the cylinder, thus connecting the top and bottom surfaces to form a closed structure. The height of the cylinder is equal to the (vertical) distance from the top to the bottom surface. The radius of the base can be greater than the height of the cylinder.

[0023] Photon detectors and / or photon sources can be substantially cuboid in shape. The cuboid has a rectangular base and a rectangular top face, which are arranged opposite each other. The sides consist of multiple (four in total) sides and extend along the entire height of the cuboid, thus connecting the top and bottom faces to form a closed structure. The height of the cuboid is equal to the (vertical) distance from the top to the bottom face. The base diagonal of the cuboid can be greater than its height.

[0024] A photon source can be designed to emit photons through its bottom surface. A photon detector can be designed to detect photons that strike its bottom surface.

[0025] As described above, the bottom surface of the photon source can face the photon detector. That is, regardless of the three-dimensional shape of the photon source, the bottom surface of the photon source can be essentially constructed on a two-dimensional plane, wherein the normal vector perpendicular to this plane, and thus perpendicular to the bottom surface, points in the direction of the photon detector. In the case of a cuboid shape, the bottom surface can be the surface with the largest area of ​​the photon source, or the surface with the second largest area after the top surface.

[0026] As described above, the bottom surface of the photon detector can face the photon source. That is, regardless of the three-dimensional shape of the photon detector, the bottom surface of the photon detector can be essentially constructed on a two-dimensional plane, wherein the normal vector perpendicular to this plane, and thus perpendicular to the bottom surface, points in the direction of the photon source. When the photon source is cuboid in shape, the bottom surface can be the surface with the largest area of ​​the photon source, or the surface with the second largest area after the top surface.

[0027] Therefore, the two bottom surfaces can also be arranged facing each other.

[0028] According to the design of the entropy source, that is, the bottom surface of the photon source is arranged facing the photon detector, its advantage is that the photons emitted through the bottom surface of the photon source will be directed towards the photon source, so they are likely to collide with the photon detector and be detected by it.

[0029] According to the design of the entropy source, that is, the bottom surface of the photon detector is arranged facing the photon source, the advantage is that the photons emitted by the photon source are likely to collide with the photon detector (especially the bottom surface of the photon detector) and be detected by it.

[0030] If the two bases are arranged facing each other, the two effects mentioned above will occur in combination.

[0031] Therefore, under any circumstances, the photon detector can detect a large number of emitted photons, and thus obtain a high entropy value of the entropy source output signal.

[0032] A photon source can be a single-photon source.

[0033] A single-photon source can be a light source or photon source that essentially never emits two or more photons simultaneously. Alternatively, a single-photon source can be a photon source that emits only a small number of photons at the same time.

[0034] The photon source can be an avalanche Zener diode. An avalanche Zener diode can have a breakdown voltage of less than or equal to 10V, optionally less than or equal to 8V, or optionally less than or equal to 7V. Avalanche Zener diodes allow for high single-photon rates at relatively low operating voltages (even below and within the (Zener) breakdown voltage range). Avalanche Zener diodes also allow for construction, or can be designed, such that photons emitted by the photon source are highly likely to be emitted or transmitted via the bottom surface of the photon source, because the area of ​​the bottom surface is larger than the area of ​​the side surfaces.

[0035] Photon detectors may include single-photon detectors, optionally single-photon avalanche diodes (SPADs).

[0036] A single-photon detector can be understood as a detector designed to collect or detect photons emitted individually from a single-photon source.

[0037] A single-photon avalanche diode may include a first PN junction formed by a first P-type layer and a first N-type layer, wherein the first P-type layer and the first N-type layer are in contact with each other.

[0038] Both P-type and N-type layers can be obtained through doping. In semiconductor technology, doping refers to introducing foreign atoms into a layer or substrate of an integrated circuit. For P-type doped substrates (P represents freely moving positive holes), trivalent elements (i.e., acceptors) can be introduced into the silicon lattice and replace tetravalent silicon atoms. For N-type doping (N represents freely moving negative charges), pentavalent elements (i.e., donors) can be introduced into the silicon lattice and replace tetravalent silicon atoms.

[0039] A single-photon avalanche diode may include an absorption region designed to absorb photons emitted by a photon source, such that the absorption region generates an electron-hole pair for each photon, optionally exactly one electron-hole pair. The absorption region may be in contact with a first PN junction, and the first PN junction may be designed to generate charge avalanche due to the generated electron-hole pairs.

[0040] Photon detectors can be designed to detect the corresponding photons emitted by a photon source based on the resulting charge avalanche.

[0041] In other words, if a single-photon avalanche diode is excited by a single photon, each excitation photon can generate (optionally individually) electron-hole pairs in the sensing active region or absorption region. The excited electrons are attracted to the cathode by the electric field, while the excited holes are attracted to the anode. Here, in a single-photon avalanche diode, charge carriers can drift through the so-called avalanche region formed by the PN junction, where collisional ionization generates charge avalanches. Thus, a single-photon avalanche diode can be a highly sensitive photon receiving element that, when activated by a photon, can provide a large amount of charge (approximately 10⁵–10⁶ electrons) with high time resolution.

[0042] Single-photon avalanche diodes can operate in Geiger mode above their breakdown voltage, where a single photon can be detected via the generated charge avalanche and subsequently recorded as a single event. To reduce the dead time that occurs during recording, further charge carrier multiplication can be actively or passively suppressed or quenched immediately after avalanche formation begins.

[0043] An integrated circuit can be provided that includes a single-photon counting unit or single-photon counter (SPC) in addition to a single-photon avalanche diode. This allows for real-time statistical evaluation of the temporal distribution of each detected single-photon event, rather than directly outputting a single pulse from the detector.

[0044] The absorption region may have a P-type doped substrate or be composed of a P-type doped substrate that completely covers the surface of the first PN junction facing the photon source direction.

[0045] The absorption region may have a P-type doped substrate that only partially covers the surface of the first PN junction facing the photon source and forms a channel extending from the surface of the first PN junction toward the photon source, the channel being laterally defined by an N-type doped substrate.

[0046] The absorption region may have an N-type doped substrate or be composed of an N-type doped substrate that completely covers the surface of the first PN junction facing the photon source direction.

[0047] The absorption region can be in contact with the photon source, and optionally with the p-type doped substrate of the photon source.

[0048] A single-photon avalanche diode may include a second PN junction formed by a second P-type layer and a first N-type layer, wherein the second P-type layer and the first N-type layer are in contact with each other.

[0049] It is conceivable that the second PN junction could be used as an additional photon detector to monitor for external attacks. The additional PN junction could, for example, be used to detect photons introduced into an entropy source from the outside or external sources, thus enabling the identification of external attacks.

[0050] It can be envisioned that the second PN junction is arranged between the first PN junction and the back side of the semiconductor substrate, which is opposite to the surface of the semiconductor substrate as defined above, thus enabling the detection of attacks from the back side of the semiconductor substrate.

[0051] The entropy source may have a metal layer (optionally provided together with an internal silicide layer) which shields the entropy source from the outside.

[0052] This metal layer can be used to shield external photons (“shield”) and / or improve efficiency by reflecting photons generated by a relevant photon source.

[0053] The entropy source may have at least two anodes for photon source and photon detector, which are electrically connected to each other via a metal layer.

[0054] The photon source and / or photon detector (optionally an entropy source as a whole) can be configured to be rotationally symmetric along an axis perpendicular to the first and / or second base surfaces.

[0055] It can be envisioned that the axis is perpendicular to the semiconductor substrate surface as defined above and / or perpendicular to the opposite back surface.

[0056] Entropy sources can be constructed using bipolar CMOS-DMOS technology (BCD technology) or manufactured using BCD technology.

[0057] Bipolar CMOS technology is a semiconductor manufacturing method that combines two originally independent circuit technologies (i.e., circuits based on bipolar transistors (BJTs) and complementary metal-oxide-semiconductor (CMOS) logic gates based on metal-oxide-semiconductor field-effect transistors (MOSFETs)) into a single integrated circuit.

[0058] BCD technology allows for efficient and optimized integration of SPADs, optionally with other functional groups such as digital and / or analog circuit components, particularly energy-efficient digital storage and switching elements, general-purpose power and drive electronics, and detector and sensor components.

[0059] The entropy source may include a substrate having a carrier substrate and an epitaxial layer, wherein the epitaxial layer may have a first PN junction and the carrier substrate may have a second PN junction.

[0060] It can be envisioned that the epitaxial layer is an epitaxial layer grown on a carrier substrate. The first PN junction can be located in the epitaxial layer (e.g., introduced by diffusion of a dopant introduced from below the epitaxial layer through the surface of the carrier substrate), and it can be a buried PN junction.

[0061] The carrier substrate can be a P-type substrate, but an N-type substrate or an intrinsic substrate can also be used. The (semiconductor) substrate material can be silicon. For example, boron can be used as a dopant to form the P-type region. Phosphorus (P), arsenic (As), and / or antimony (Sb) can be used to form the N-type region. Here, for example in silicon, boron has a significantly greater diffusion rate as a dopant than heavy donors (P, As, or Sb). Furthermore, it can be found that due to the higher doping dose used, the resulting N-type region is essentially dominant; that is, the phosphorus-doped N-type region retains its existing conductivity type even after the additional introduction of boron. To provide a buried PN junction, the additional masking, photolithography, and epitaxial steps in conventional BCD processes can often be omitted.

[0062] The first and second dopant may exhibit different diffusion characteristics in the substrate and / or epitaxial layer. The mobility of the second dopant in the substrate and / or epitaxial layer may be higher than that of the first dopant. The introduction of the first and / or second dopant can be done without a mask or via a mask method. For maskless introduction, direct ion beam writing can be used, for example. In the mask method, the introduction can be accomplished with the aid of a pre-provided mask, which can be done via chemical or physical deposition or via ion beam writing. It is conceivable that after the introduction of the second dopant, the first or second region immediately and completely overlaps with the corresponding other region (viewed from the surface of the substrate as defined above). The first region may be a (buried) N-type layer (NBL layer), and the second region may be a (buried) P-type layer (PBL layer).

[0063] The upper and / or lower sides of the substrate may be mirrored and / or include a light-blocking layer, at least in the region of the photon source and / or photon detector.

[0064] The substrate may have a combined structure on its surface and / or back side or its upper and / or lower side, each consisting of at least one of the following elements: a metal overlay, a sidewall contact, and a through-hole.

[0065] The main advantages of the aforementioned entropy source are that it (and optionally, a quantum random number generator incorporating the entropy source) is resistant to external attacks and possesses high efficiency and low substrate loss. Optionally, the entropy source may include Zener diodes and single-photon avalanche diodes stacked vertically on a common semiconductor substrate to provide a compact and secure entropy source.

[0066] In addition, a method for operating the aforementioned entropy source can also be provided. The method includes emitting photons via a photon source, such that the photons leave the photon source via a first bottom surface of the photon source toward a photon detector, and / or receiving the photons emitted by the photon source on a second bottom surface of the photon detector.

[0067] In addition, a quantum random number generator can be provided. This quantum random number generator includes the aforementioned entropy source and electronic circuitry designed to generate random bits based on the output signal of the entropy source, and optionally output the generated random bits, wherein the characteristics of the output signal of the entropy source depend on the time frequency of the photons detected by the photon detector.

[0068] The generated random bits can be part of a random bit data stream. That is, a quantum random number generator can be designed to continuously generate random bits and optionally output them as a random bit data stream. A random bit data stream is considered random if it passes the following NIST test:

[0069] Smid, Elaine Barker, et al., “A statistical test suite for random and pseudorandom number generators for cryptographic applications” (2010), download link: https: / / www.researchgate.net / profile / Salamlsmaeel / post / Is_there_any_program_or_software_to_check_strength_of_cryptography_algorithm2 / attachment / 59d61de479197b807797be4a / AS%3A273823310516224%401442295972158 / download / NIST.pdf

[0070] The NIST test kit software can be downloaded from the following URL (as of the application date): https: / / csrc.nist.gov / CSRC / media / Projects / Random-Bit-Generation / documents / sts-2_1_2.zip

[0071] A quantum random number generator may include a pseudo-random number generator, which is designed to generate a digital output signal based on an entropy source output signal and a generator polynomial that can be predetermined or adjustable.

[0072] A quantum random number generator may include a random bit generation unit, which is designed to generate random bits based on the digital output signal of a pseudo-random number generator.

[0073] The random bit generation unit can generate random bits by determining a first value and a second value of the digital output signal. Specifically, if the first value of the digital output signal is less than the second value, and the difference between the first and second values ​​is greater than a minimum difference, then the output value of the random bit generation unit is set to a first logic value. Alternatively, if the first value of the digital output signal is greater than the second value, and the difference between the first and second values ​​is greater than a minimum difference, then the random bit generation unit sets its output value to a second logic value.

[0074] The random bit generation unit can be designed such that if the difference between the first value and the second value of the digital output signal is less than a predetermined minimum difference, then the first value and the second value of the digital output signal are discarded.

[0075] A quantum random number generator may include a monitoring unit or watchdog, designed to monitor the output of the random bit generation unit. It is conceivable that if the number of values ​​discarded by the random bit generation unit exceeds a predetermined limit, the monitoring unit can detect a malfunction in the quantum random number generator.

[0076] Furthermore, this disclosure also relates to an integrated electronic circuit, wherein the circuit includes the aforementioned monolithically integrated entropy source and / or quantum random number generator (200). The integrated electronic circuit may be a microelectronic integrated circuit.

[0077] Furthermore, this disclosure also relates to a computer-readable medium. The computer-readable medium contains data defining operational guidelines suitable for controlling a semiconductor manufacturing apparatus to manufacture the aforementioned entropy source, the aforementioned quantum random number generator, and / or the aforementioned integrated electronic circuitry when the data is output to the semiconductor manufacturing apparatus.

[0078] The computer-readable medium is a technical object. The computer-readable medium can primarily be any computer-readable storage medium, such as a digital data storage device, like a USB flash drive, hard disk, CD-ROM, SD card, or SSD card. The computer-readable medium can be a data signal. That is, data does not necessarily have to be stored on a computer-readable storage medium, but can be obtained, for example, via the Internet. The data may contain a computer program configured as a control program or configurable as a control program, which contains instructions that, when executed by a semiconductor manufacturing device, cause the semiconductor manufacturing device to manufacture or produce an entropy source and / or a quantum random number generator and / or integrated electronic circuitry.

[0079] The data contains at least operational guidelines applicable to controlling semiconductor manufacturing equipment, and is therefore intended for use in controlling semiconductor manufacturing equipment to create entropy sources and / or quantum random number generators and / or integrated electronic circuits. Thus, at least a technical purpose of the data is implied.

[0080] It is conceivable that the data contains a digital representation of an entropy source, a quantum random number generator, and / or integrated electronic circuitry, so that when the data is output to a semiconductor manufacturing device, the entropy source, quantum random number generator, and / or integrated electronic circuitry can be fabricated using the digital representation and operating instructions.

[0081] The technical contribution of a digital representation of one or more products lies at least in that the representation defines the technical characteristics of a physical product that has been manufactured or is to be manufactured. It is conceivable that the representation exists independently or as part of an operating instruction, or that the operating instruction comprises the representation, wherein the representation is adapted to derive, based on the representation (using conventional means), a control program suitable for controlling a semiconductor manufacturing equipment, so that when the control program is output to the semiconductor manufacturing equipment, the aforementioned entropy source, the aforementioned quantum random number generator, and / or the aforementioned integrated electronic circuitry can be manufactured by the semiconductor manufacturing equipment. That is, the digital representation inherently contains a control program and thus possesses technical effects. In other words, the digital representation is suitable for controlling a semiconductor manufacturing equipment and is therefore intended to be used to control the semiconductor manufacturing equipment to manufacture products. This represents a technical use of the digital representation, at least an implicit one.

[0082] This number can represent what is known as an IP core (IP-Core, derived from the English terms Intellectual Property Core or IP-Block). In the field of microelectronics, this term refers to a reusable pre-fabricated functional block of chip design (i.e., blueprint or circuit design) in the semiconductor industry. Based on the information contained in the IP core, semiconductor manufacturing equipment can be controlled to create products according to the information contained in the IP core, such as creating entropy sources.

[0083] In principle, IP cores can be categorized into soft IP cores and hard IP cores. Soft IP cores may include source code in a predefined hardware description language (e.g., Verilog or VHDL). Soft IP cores may also be in the form of a manufacturer-synthesized netlist, i.e., a textual description of a circuit diagram. The netlist may also be in encrypted form. Hard IP cores, on the other hand, are blocks with a completed layout and can be used to manufacture products, such as entropy sources, based on the information contained within them. In this disclosure, the IP core may be a hard IP core. For development purposes, a black-box representation of the hard IP core may be provided to the developer. The contents of this black box are known only to the foundry or service provider responsible for completing the chip layout or manufacturing the product (here, for example, an entropy source) commissioned by the developer.

[0084] Fabricating entropy sources, quantum random number generators, and / or integrated electronic circuits may include: in a semiconductor process, optionally in a CMOS semiconductor process, a BiCMOS semiconductor process, or a bipolar device semiconductor process, optionally using bipolar CMOS technology, by means of semiconductor manufacturing equipment, according to operating instructions, fabricating entropy sources, quantum random number generators, and / or integrated electronic circuits on a wafer.

[0085] Furthermore, this disclosure also relates to a computer implementation method for creating the aforementioned computer-readable medium. The method may include defining first data suitable for controlling the operation of a semiconductor manufacturing apparatus, so that when the data is output to the semiconductor manufacturing apparatus, the aforementioned integrated electronic circuit can be manufactured by the semiconductor manufacturing apparatus. The method may include providing second data defining the operation of the semiconductor manufacturing apparatus, so that when the second data is output to the semiconductor manufacturing apparatus, the aforementioned entropy source can be manufactured by the semiconductor manufacturing apparatus. The method may include generating first data based on the provided second data and third data, the third data defining operation instructions suitable for controlling the semiconductor manufacturing apparatus, so that when the third data is output to the semiconductor manufacturing apparatus, the remaining parts of the integrated electronic circuit, excluding the entropy source, can be manufactured by the semiconductor manufacturing apparatus.

[0086] It can be envisioned that the operation guidelines for the first data contain the overall layout of the entire circuit, the operation guidelines for the second data contain the layout of the entropy source or consist of it, and / or the operation guidelines for the third data contain the overall preliminary layout of the entire circuit or consist of it, wherein the overall preliminary layout does not contain the layout of the entropy source.

[0087] Generating the first data may include: using a computer-implemented layout method, or optionally a computer-implemented synthesis method, merging the layout data of the entropy source with the overall preliminary layout data (optionally performing synthesis) to obtain the overall layout data.

[0088] The method may include: providing a netlist of a circuit, wherein the netlist contains blocks of entropy sources, and generating an overall preliminary layout of the circuit based on the provided netlist.

[0089] A netlist can be understood as a textual description of a circuit diagram, such as a textual description of a circuit (with or without entropy sources).

[0090] A circuit layout can be understood as the (real) geometric representation of a circuit. A layout is obtained through what is called layout synthesis. In electrical engineering, this refers to the (optionally automatic) creation of the geometric arrangement of cells and their connections during the layout design process of integrated circuits. Input information can be a netlist created during circuit design, along with optional cell library information and / or technical information. The result of layout synthesis is the layout, which is a graphical, layered mapping of all elements of the circuit (e.g., in GDSII or OASIS file format).

[0091] Furthermore, this disclosure also relates to a method for fabricating the aforementioned entropy source, quantum random number generator, and / or integrated electronic circuit. The method includes fabricating the entropy source, quantum random number generator, and / or integrated electronic circuit using a semiconductor manufacturing apparatus, optionally employing the aforementioned computer-readable medium.

[0092] In the specific design described below as a non-limiting embodiment, the fabrication and optional use of the fabricated entropy source can be accomplished in the following manner:

[0093] a) Provides a dataset of microelectronic integrated circuit netlists;

[0094] b) Wherein, the netlist contains sub-circuit blocks, which are used for entropy sources or for sub-loops containing entropy sources;

[0095] c) Based on the provided netlist and existing layout data of known sub-blocks, generate an overall preliminary layout of the microelectronic integrated circuit, wherein the layout components of the entropy source are not yet included or are only represented to a degree insufficient for manufacturing;

[0096] c) Provide the layout data of the entropy source;

[0097] d) Generate a dataset of the overall layout using a computer-implemented layout method, wherein the computer-implemented layout method integrates the layout data of the entropy source with the layout data of other parts of the microelectronic integrated circuit and the layout data of other layout information and / or structures that may be needed for manufacturing the microelectronic integrated circuit (2) into a dataset of the overall layout through a computer-implemented synthesis method.

[0098] e) In semiconductor processes, especially CMOS, BiCMOS or bipolar device semiconductor processes, microelectronic circuits are fabricated on wafers based on an overall layout dataset.

[0099] f) Separating microelectronic integrated circuits from the wafer complex;

[0100] g) Use the entropy source of microelectronic integrated circuits as a random bit source (especially in quantum random number generators).

[0101] in,

[0102] In the process of synthesizing the overall layout data, the entropy source layout data includes the layout data of photon sources (especially the first SPAD diode or Zener diode or photon source); and

[0103] In the process of synthesizing the overall layout data, the entropy source layout data includes the layout data of the photon detector (especially the second SPAD diode and / or single-photon detector); and in the overall layout and subsequent microelectronic integrated circuits, the photon source and photon detector are stacked one on top of the other, thus...

[0104] After microelectronic integrated circuits are fabricated in and / or on a semiconductor substrate.

[0105] The photon source and photon detector are fabricated in a semiconductor substrate, below the horizontal surface of the semiconductor substrate, and stacked on top of each other in a substantially vertical direction.

[0106] The aforementioned integrated electronic circuits can be manufactured or fabricated using a Quad Flat No Leads Package (QFN package). Attached Figure Description

[0107] The features described herein and those shown in the accompanying drawings are not limited to the explicitly described embodiments and combinations thereof. Therefore, this disclosure also covers other technically feasible combinations and isolated features. The present disclosure is illustrated below with reference to the accompanying drawings, but this disclosure is not limited to the embodiments or examples shown in the description or figures.

[0108] Figure 1 A schematic diagram of a BCD substrate provided by a method for providing a buried PN junction in the BCD process and a TCAD diagram of the resulting dopant distribution are shown.

[0109] Figure 2 A cross-sectional schematic diagram of an exemplary first embodiment of the entropy source is shown;

[0110] Figure 3 A cross-sectional schematic diagram of an exemplary second embodiment of the entropy source is shown;

[0111] Figure 4 A cross-sectional schematic diagram of an exemplary third embodiment of the entropy source is shown;

[0112] Figure 5 It shows Figures 2 to 4 The graphs show the dependence of the SPAD current and the ratio of the SPAD current to the Zener current on the Zener reverse voltage under different SPAD reverse voltages (less than, equal to, and greater than the breakdown voltage) within the entropy source.

[0113] Figure 6 It shows having Figures 2 to 4 A schematic diagram of a quantum random number generator for an entropy source;

[0114] Figure 7 It shows having Figures 2 to 4 The entropy source and / or shown Figure 6 A top view schematic diagram of an exemplary layout of the integrated electronic circuitry of the quantum random number generator shown;

[0115] Figure 8 It shows having Figures 2 to 4 The entropy source and / or shown Figure 6 The quantum random number generator and encryption engine shown (which are optionally at least partially constructed as) Figure 7A schematic diagram of a system (in the form of a microelectronic integrated circuit 500) is shown.

[0116] Figure 9 It shows Figure 7 The flowchart shown is a method for fabricating a microelectronic integrated circuit 500. Detailed Implementation

[0117] The reference numerals in all the figures are used consistently, meaning that the same reference numerals in all the figures refer to the same object.

[0118] Figure 1 A schematic diagram of a (BCD) substrate 110 provided by a method for providing buried PN junctions 50 and 52 using a BCD process is shown, along with a TCAD illustration of the resulting dopant distribution.

[0119] Methods for generating buried PN junctions 50 and 52 in a BCD process may include providing a carrier substrate 49.

[0120] The method may include introducing a first dopant into the surface S of a carrier substrate 49 to form a first region 22 (e.g., NBL) of a first conductivity type (NBL being a negative conductivity type).

[0121] The method may include introducing a second dopant into the surface S of a carrier substrate 49 to form a second region 32 (e.g., PBL) of a second conductivity type (PBL being positively conductive), wherein the first region 22 (NBL) and the second region 32 (PBL) at least partially overlap.

[0122] The method may include: growing an epitaxial layer 48 on the surface S of a carrier substrate 49, wherein a first region 22 (NBL) and a second region 32 (PBL) are extended by diffusion of a first dopant and a second dopant in the epitaxial layer 48 to form a (first) PN junction 50 located in the epitaxial layer 48.

[0123] As shown in the figure, the first zone 22 is a deeply buried NBL layer, while the second zone 32 is a deeply buried PBL layer. However, the order can be reversed, that is, the first zone 22 can also be a deeply buried PBL layer, and the second zone 32 can also be a deeply buried NBL layer.

[0124] By adjusting the diffusion lengths of various dopants accordingly, the layer order of PN junctions 50 and 52 can also be reversed, for example... Figure 1 The NBL and PBL layers at PN junctions 50 and 52 can also be interchanged.

[0125] The advantage of this method is that the first region 22 (NBL) and the second region 32 (PBL) can at least partially overlap. Optionally, after introducing the second dopant, when viewed from the surface S of the carrier substrate 49, the first region 22 or the second region 32 can completely overlap with the corresponding other region 32, 22. Therefore, in the illustrated embodiment, after introducing the second dopant to form the second region 32 (PBL), when viewed from the surface S of the carrier substrate 49, the second region is completely located within the first region 22 (NBL). Here, in order to form the PN junction 50 in the epitaxial layer, the first dopant and the second dopant can exhibit different diffusion characteristics in the carrier substrate 49 and / or the epitaxial layer 48. Optionally, as shown, the diffusion mobility (and diffusion length) exhibited by the second dopant in the second region 32 (PBL) in the carrier substrate 49 and the epitaxial layer 48 can be higher than that of the first dopant in the first region 22 (NBL).

[0126] To enhance diffusion, the carrier substrate 49 may be heated after the introduction of the first dopant and / or the second dopant. The carrier substrate 49 may be heated after the epitaxial layer 48 has grown to enhance dopant diffusion.

[0127] In the method proposed in this disclosure, the introduction of the first dopant and / or the second dopant can be performed either without a mask or via a mask. In the illustrated BCD wafer, it can be assumed that the first region 22 (NBL) and the separate second region 32 (PBL) completely overlap. However, conventionally, the first region 22 and the second region 32 are constructed to be spatially separated from each other. In particular, the distance between them is generally chosen to be at least sufficient to ensure that no overlapping regions are generated even after the various dopants diffuse outward.

[0128] The Technology Computer-Aided Design (TCAD) illustration below the schematic diagram exemplifies the dopant distribution within the contact substrate 110 to simulate a corresponding integrated diode structure. In the bilayer structure shown in this embodiment, the epitaxial layer 48 has an upper PN junction 50, while the carrier substrate 49 has a lower (second) PN junction 52. Therefore, as shown in the side view, the N-type region (NBL) enclosed within the PN junctions 50 and 52 is effectively contracted by two P-type regions (PBL) surrounding it. The two PN junctions 50 and 52 can be configured to provide mutually independent SPADs, with doping density and field strength distributions suitable for generating an avalanche effect.

[0129] Thus, a particularly buried SPAD (“deepSPAD”) can be generated using a corresponding (semiconductor) substrate 110 suitable for BCD technology. Sufficient structural space remains above the provided SPAD to integrate more optoelectronic components. Therefore, the avalanche Zener LED formed above the buried SPAD can be used to realize a particularly compact vertical entropy source 401, wherein a single photon 58 is emitted by the Zener-avLED as a photon source 55 toward the upper PN junction 50, the emission optionally occurring vertically downwards, and thus provided for detection by the SPAD, positioned directly below the Zener-avLED and formed at the upper PN junction 50, as a single-photon detector (see [link to documentation]). Figures 2 to 4 (and related accompanying illustrations).

[0130] Figure 2 A schematic diagram of an exemplary first embodiment of a (vertical) monolithically integrated entropy source 401 is shown.

[0131] Entropy source 401 may include substrate 110 having carrier substrate 49 and epitaxial layer 48. Epitaxial layer 48 may have or include a first PN junction 50 and / or a third PN junction 554. Carrier substrate 49 may have or include a second PN junction 52.

[0132] Entropy source 401 includes photon source 55, designed to emit photons 58. Photon source 55 includes a third PN junction 554 formed by a third P-type layer 46 and a third N-type layer 45, wherein the third P-type layer 46 and the third N-type layer 45 are in contact with each other. Photon source 55 (more precisely, its PN junction 554) includes a first outer shell formed by a first bottom surface 551, a first top surface 552, and at least one first side surface 553 connecting the first bottom surface 551 and the first top surface 552. The first bottom surface 551 may have the same area as the first top surface 552. The area of ​​the first bottom surface 551 may be greater than or less than the area of ​​the first top surface 552. A normal vector perpendicular to the first bottom surface 551 may be parallel to a normal vector perpendicular to the first top surface 552. The third PN junction 554 may be cylindrical. The height of the cylinder may be parallel to the normal vector. The height of the cylinder can be less than the radius of the first bottom surface 551 and / or the first top surface 552, and can be selected to be several times smaller than that radius. The third PN junction 554 can be a thin layer.

[0133] Entropy source 401 includes a photon detector 54 designed to detect photons 58 emitted by photon source 55. The photon detector 54 includes a first PN junction 50 formed by a first P-type layer 32 and a first N-type layer 22, wherein the first P-type layer 32 and the first N-type layer 22 are in contact with each other. The photon detector 54 (more precisely, its first PN junction 50) includes a second housing formed by a second bottom surface 541, a second top surface 542, and at least one second side surface 543 connecting the second bottom surface 541 and the second top surface 542. The second bottom surface 541 may have the same area as the second top surface 542. The area of ​​the second bottom surface 541 may be larger or smaller than the area of ​​the first top surface 542. A normal vector perpendicular to the second bottom surface 541 may be parallel to a normal vector perpendicular to the second top surface 542. The first PN junction 50 may be cylindrical. The height of the cylinder may be parallel to the normal vector. The height of the cylinder can be less than the radius of the second bottom surface 541 and / or the second top surface 542, and can be selected to be several times smaller than that radius. The first PN junction 50 can be a thin layer.

[0134] The first bottom surface 541 of the third PN junction 554 of the photon source 55 is arranged facing the second bottom surface 541 of the first PN junction of the photon detector 55. That is, the normal vector perpendicular to the second bottom surface 541 is parallel to the normal vector perpendicular to the first bottom surface 551. The distance from the first bottom surface 551 to the second bottom surface 541 is shorter than the distance from the first top surface 552 to the second bottom surface 541.

[0135] The photon source 55 can be a silicon light-emitting diode (LED) and / or a single photon source, optionally a SPAD or an avalanche Zener diode, wherein the avalanche Zener diode optionally has a breakdown voltage of less than 10V.

[0136] Photon detector 55 includes absorption regions 10 and 47, designed to absorb photons 58 emitted by photon source 55, such that absorption regions 10 and 47 generate an electron-hole pair for each photon 58, optionally exactly one electron-hole pair. Absorption regions 10 and 47 are in contact with a first PN junction 50 (and a third PN junction 554). The first PN junction 50 is designed to generate charge avalanche due to the generated electron-hole pairs. Photon detector 54 is designed to detect the corresponding photon 58 emitted by photon source 55 based on the generated charge avalanche.

[0137] The photon detector 54 may include a single-photon detector, optionally a single-photon avalanche diode, or optionally a SPAD.

[0138] The absorption regions 10 and 47 include or are composed of a P-type doped substrate, such that the surface of the first PN junction 50 facing the photon source 55 (i.e., its second bottom surface 541) is completely covered.

[0139] Absorption regions 10 and 47 are in contact with photon source 55 (in this case, the P-type doped substrate 46 of the third PN junction 554 of photon source 55).

[0140] The photon detector 54 includes a second PN junction 52 formed by a second P-type layer 32 and a first N-type layer 22, wherein the second P-type layer 32 and the first N-type layer 22 are in contact with each other.

[0141] Entropy source 401 includes a metal layer 53 (optionally together with a silicide layer inside it or a layer facing the O direction of the surface), which shields entropy source 401 from the outside.

[0142] Entropy source 401 may include at least two anodes 124, 134 for photon source 55 and photon detector 54, which may be electrically connected to each other via metal layer 53.

[0143] The photon source 55 and / or photon detector 54 (optionally the entropy source 401 as a whole) can be configured to be rotationally symmetric along an axis. This axis can be parallel to the normal vector perpendicular to the first bottom surface 541 and / or the second bottom surface 551 and / or the surface O.

[0144] Entropy source 401 can be made using BCD technology.

[0145] The upper and / or lower sides of the entropy source 401 may be mirrored and / or include a light-blocking layer, at least in the region of the photon source 55 and / or the photon detector 54.

[0146] During the operation of entropy source 401, photons 58 can be emitted at random time intervals at the third PN junction 554 of photon source 55, so that photons 58 leave from the third PN junction 554 of photon source 55 via its first bottom surface 551 toward the second bottom surface 541 of the first PN junction of photon detector 54, forming electron-hole pairs in absorption regions 10 and 47, and triggering charge avalanche at the first PN junction 50.

[0147] Specifically, in the context of this paper, the vertical entropy source 401 is characterized by the vertical arrangement of the photon source 55 relative to the photon detector 54. Here, the horizontal direction is defined by the surface O of the semiconductor substrate 110 with the epitaxial layer 48. Thus, the centroid line connecting the vertical arrangement of the photon source 55 to the photon detector 54 is vertical relative to the surface O of the substrate 49 with the epitaxial layer 48; here, "vertical" can be understood relatively broadly as the angle between this line and the surface O being greater than 30°, preferably 90°. As shown, the monolithically integrated entropy source 401 includes the photon source 55 and the photon detector 54, which can be stacked vertically on a common substrate 110 made of semiconductor material. Optionally, the photon source 55 is a single-photon source, configured to provide only one or a few photons 58 simultaneously (a so-called single-photon source). Optionally, the photon source 55 is an avalanche Zener LED, which operates at or near its breakdown voltage. Optionally, the photon detector 54 can be a single-photon detector, such as a single-photon avalanche diode.

[0148] Entropy source 401 can be constructed in (BCD) substrate 110 using BCD technology. Substrate 110 may include carrier substrate 49 and epitaxial layer 48 grown on carrier substrate 49. PN junctions 50 and 52 can be constructed according to reference... Figure 1 The arrangement is as described above. The photon detector 55 may include an avalanche region constructed in the region surrounding the upper PN junction 50 of the photon detector 54, and absorption regions 10 and 47 for converting photons into electron-hole pairs. These absorption regions have a high-voltage p-type well 10 and a p-type well 47, wherein the absorption regions 10 and 47 may be adjacent to regions 22 and 32 constituting the buried PN junction 50. Here, the fully formed high-voltage p-type well 10 enables optimal connection between the buried PN junction 50 and the anodes 124 and 134.

[0149] The upper buried PN junction 50 of the photon detector 54 can be constructed between the buried N-type layer 22, which serves as the cathode 132, and the buried P-type layer 32 adjacent to the buried N-type layer 22. The absorption regions 10 and 47 can be adjacent to the buried P-type layer 32 and are substantially P-type regions (optionally including intrinsic regions). The anode 46 (P-type) of the uppermost or third PN junction 554 can be connected to the P+ type region 51 via the P-type region 47, wherein the anode 32 of the middle or second PN junction 50 can also be connected to the P+ type region 51 via the absorption regions 10 and 47.

[0150] In the illustrated embodiment, the anodes 124 and 134 of the photon source 55 and photon detector 54 are merged together. These anodes can be electrically contacted, for example, via a common metallization layer 53 on the surface O of the substrate 110. Shielding from electromagnetic radiation from above can also be achieved through the common continuous metallization layer 53. The associated cathodes 122 and 132 are implemented separately, for example, and can be electrically contacted via a first additional associated metallization layer 141.

[0151] Entropy source 401 can be constructed as a circular structure (corresponding to a spatial rotation of the shown view plane about an imaginary central axis in the vertical direction). However, other constructions of entropy source 401 can also be considered.

[0152] Figure 3 A schematic diagram of an exemplary second embodiment of entropy source 401 is shown. Figure 3 The implementation shown is basically equivalent to Figure 2 The first embodiment is shown and described above. Therefore, the reference numerals and their correspondence with the various features also apply.

[0153] In the second embodiment, the absorption regions 10 and 47 with the P-type doped substrate are configured to only partially cover the surface of the first PN junction 50 facing the photon source 55 or the second bottom surface 541, and form a channel extending from the second bottom surface 541 of the first PN junction 50 toward the photon source 55, the channel being laterally defined by the N-type doped substrate 29.

[0154] That is, compared to the first embodiment, the high-voltage P-type well 10 is structurally tapered and additionally has a (weak) N-type doped region 29. Here, the high-voltage P-type well 10 of the absorption regions 10, 47 is located in the upper P-type well 47 (e.g., Figure 2 A channel is formed between the upper buried PN junction 50 and the (deeply buried) P-type layer 32 of the second PN junction 50. The surrounding environment of this channel is defined by the (weakly) N-type doped region 29. Through this channel, the upper buried PN junction 50 can be electrically connected to the upper PN junctions 45 and 46 without additionally penetrating / through the N-type doped region 29, and is irradiated by photons 58 by the photon source 54.

[0155] Figure 4 A schematic diagram of an exemplary third embodiment of entropy source 401 is shown. The third embodiment shown is essentially equivalent to... Figure 2 and Figure 3 The first and second embodiments are shown and described above. Therefore, the reference numerals and their correspondence with the various features also apply.

[0156] However, absorption regions 10 and 47 have an N-type doped substrate 29 (or consist of it), which completely covers the bottom surface 541 of the first PN junction 50 facing the photon source 55.

[0157] Compared with the second embodiment, in the third embodiment, the channel-shaped high-voltage P-type well 10 is not provided in the absorption regions 10, 47. The weakly N-type doped region 29 formed in the epitaxial layer 48 extends across the entire lower region between the second PN junction 50 and the photon source 54. In this regard, compared with the second embodiment, the high-voltage P-type well 10 in this region is structurally replaced by the (weakly) N-type doped region 29. Thus, the upper buried PN junction 50 can be connected to the photon source 54 only by additionally penetrating / breaking through the weakly N-type doped region 29, which causes decoupling between multiple possibly parallel and juxtaposed entropy sources 401.

[0158] Figure 5 The graph shows the dependencies of: a) the SPAD current and b) the ratio of the SPAD current to the Zener current on the Zener reverse voltage at different SPAD reverse voltages (less than, equal to, greater than the breakdown voltage) within the entropy source 401. Here, Figure 5 The dependency shown in a) clearly shows that within the range of 5.6V to 6.6V, the SPAD current increases exponentially with the Zener diode reverse voltage. This applies to all operating modes of the SPAD, that is, below its own breakdown voltage (<VBD, linear range), close to the breakdown voltage (~VBD, avalanche range), and above the breakdown voltage (>VBD), so it also applies to the Geiger operating mode.

[0159] Figure 5 The lower distribution curve (<VBD) shown in b) shows that for different Zener reverse voltages within the range of 5.8V to 6.6V, the measured current ratio between the SPAD current and the Zener current is approximately 1:4000. Within the breakdown voltage region of the SPAD (~VBD), this current ratio increases to a value of approximately 1:10. This is attributed to the so-called multiplication factor of the SPAD, which deviates from the linear region within the breakdown voltage range. The upper distribution curve finally represents the corresponding current ratio (approximately 1:1) when the SPAD operates under conditions above the relevant breakdown voltage (>VBD). This indicates that when the SPAD operates under conditions above the relevant breakdown voltage (>VBD), the generated photocurrent is approximately equal to the Zener current of the Zener-avLED, and a significant measurement signal can be measured by coupling photons to the SPAD.

[0160] Figure 6 The figure shows a schematic diagram of a quantum random number generator 400 for generating and outputting a digital random number sequence in the form of, for example, a random bit stream ZBS (see also Figure 8 ) and / or optionally generating a random bit data word 418 by means of a finite automaton 404.8.

[0161] The quantum random number generator 400 is further described in detail below.

[0162] The quantum random number generator 400 includes the aforementioned entropy source 401. The entropy source 401 of the quantum random number generator 400 can be connected to a power supply voltage line V that is accessible to the voltage converter 408. ENT The voltage is supplied relative to the reference potential on the reference potential line GND.

[0163] The output signal or voltage signal 405 generated by entropy source 401 can first optionally be transmitted via reference voltage line V. REF The signal is digitized in the powered analog-to-digital converter (ADC) 403 and then transmitted as a digital output signal 407 to the pulse widening circuit 406.

[0164] For example, the output signal 405 of entropy source 401 can be obtained by applying a forward bias (via breakdown voltage) to region 45 relative to region 51, thereby enabling the third PN junction 554 to emit photon 58. Region 22 is applied with a positive potential bias (reverse bias) relative to region 32. If the third PN junction 554 emits photon 58 and this photon 58 is detected by the second PN junction 50, a current pulse can be extracted at the cathode 132, which can then be converted into a voltage pulse. This voltage pulse can correspond to the output signal 405 of entropy source 401.

[0165] The power supply voltage line V can be monitored via voltage monitor 413. ENT and / or reference voltage line V REF The voltage converter 408 and / or voltage monitor 413 can be supplied with voltage via a positive supply voltage line VDD relative to a reference potential on a reference potential line GND. The voltage converter 408 can be connected to the voltage monitor 413 via voltage converter line 421.

[0166] The pulse widening circuit 406 can be a monostable multivibrator (MF). The monostable multivibrator can, depending on a specific predetermined system clock, widen the pulse on the digital output signal 407 line of the ADC 403, for example, to a duration of at least one system clock cycle.

[0167] The pulse widening circuit 406 can output a synchronized voltage signal 415, i.e., a pulse with a specific minimum length, and optionally pass it to the pseudo-random number generator 404.3.

[0168] The pseudo-random number generator 404.3 can be a time-to-pseudo-random-number converter (TPRC). The TPRC can be single-stage or multi-stage. For example, the TPRC may include an analog unit, a time-to-analog converter (TAC), and / or an analog pseudo-random number converter (APRC). The TPRC may include a feedback shift register that, depending on its configuration, shifts its value one bit to the left or right each system clock cycle and feeds back the feedback value of a predetermined feedback polynomial to the vacated bit. This feedback polynomial can be a simple primitive feedback polynomial. The advantage of this type of TPRC is its high speed, small chip area, and difficulty for an attacker to measure its success or failure. In addition to the TPRC, a time-to-digital converter (TDC) can also be used, which is typically a binary start-stop counter started by a first pulse of the synchronization voltage signal 415 and stopped by a second pulse of the synchronization voltage signal 415. The pseudo-random number generator 404.3 can be connected to the internal data bus 419 (optionally directly). The output signal 410 of the pseudo-random number generator 404.3 can be further supplied to the entropy extractor 404.4.

[0169] In order to generate the output signal 410 of the pseudo-random number generator 404.3, starting from the initial value (i.e., the so-called seed value) of the pseudo-random number generator 404.3, starting from the falling edge of the synchronization voltage signal 415, a pseudo-random number from the pseudo-random number generator 404.3 is assigned to each system clock cycle (double-emit ground). That is, the time position of the relevant system clock cycle after the falling edge of the synchronization voltage signal 415 can be inferred from the pseudo-random value.

[0170] For this purpose, a pseudo-random number generator 404.3 can be used. Its advantage is that even if an attacker successfully injects interference into the synchronized voltage signal 415, the randomness of the quantum random bits at the output 411 of the entropy extractor 404.4 will only be slightly affected, because the attacker must know the relevant feedback polynomial of the pseudo-random number generator 404.3. For example, the feedback polynomial can be randomly selected from a large number of possibilities. The same applies to the seed value of the pseudo-random number generator 404.3, which the attacker must also determine. Another advantage of using a pseudo-random number generator 404.3 instead of a simple digital counter is that the feedback logic using a simple primitive feedback polynomial requires less area compared to a binary counter. If the linear feedback shift register of the pseudo-random number generator is long enough, each clock cycle between two pulses of the voltage signal 405 generated by the entropy source 401 will typically be assigned a unique pseudo-random number.

[0171] Entropy extractor 404.4 can be used to determine errors (i.e., unwanted states) in the output signal 410 of pseudo-random number generator 404.3. For this purpose, entropy extractor 404.4 can have two linear feedback shift registers that can be compared with each other via comparators. A traditional binary counter can be omitted here. Depending on the register depth, feedback can also be achieved using a simple primitive polynomial as the generator or feedback polynomial. The length of the linear feedback shift register is freely adjustable. Longer shift registers typically exhibit good random statistical or random distribution characteristics. Shorter shift registers allow for higher data rates. The advantage of using shift registers here is that fewer logic gates are required, the circuit logic depth can be smaller, and thus the clock frequency can be higher. This reduces the probability of two identical numbers and increases the random bit rate.

[0172] A corresponding entropy extraction method can be proposed, which first determines two values ​​of the output signal 410 of the pseudo-random number generator 404.3 and stores these two values ​​in the shift register of the entropy extractor 404.4. If the shift register of the entropy extractor 404.4 stores two values, the entropy extractor 404.4 can compare these two values. Thus, the values ​​in the shift register of the entropy extractor 404.4 include the first value and the second value determined by the pseudo-random number generator 404.3. Subsequently, the entropy extractor 404.4 can evaluate these two values. If the first value is less than the second value and the difference between the first value and the second value is greater than a minimum difference ε, the entropy extractor 404.4 can set the value of its output 411 to a first logic value. If the first value is greater than the second value and the difference between the first value and the second value is greater than the minimum difference ε, the entropy extractor 404.4 can set its output 411 to a second logic value different from the first logic value. If the difference between the first and second values ​​is less than the minimum difference ε, the entropy extractor 404.4 can discard both values. In this case, the entropy extractor 404.4 can prompt the so-called watchdog 404.5 to increment its error counter by a first error counter step. The first error counter step can be negative. Conversely, if the difference between the first and second values ​​is greater than the minimum difference ε, the entropy extractor 404.4 can decrement the watchdog 404.5's error counter by a second error counter step. The second error counter step can be the same as the first error counter step. The corresponding logical value (e.g., 0 or 1) set by the entropy extractor 404.4 for its output 411 corresponds to a random number. The entropy extractor 404.4 continuously outputs random numbers through its output, thereby generating a random number stream ZBS. This random number stream ZBS can be used in the encryption engine 800, as detailed below.

[0173] The watchdog 404.5 can be connected to the internal data bus 419 (as a transmission mechanism for the random bit stream ZBS). The internal data bus 419 can be connected, for example, to the encryption engine 800 and / or one or more memories and / or one or more CPUs (see also reference). Figure 8 (Description of the above). The watchdog 404.5 can be connected to the voltage monitor 413 via one or more optional digital input / output signal lines 414. The watchdog 404.5 can monitor the voltage value determined by the voltage monitor 413. The voltage monitor 413 can be designed to determine and / or monitor one or more voltages in the quantum random number generator 400, and optionally also monitor one or more voltages within the corresponding application circuitry (e.g., encryption engine 800 and / or system 1000). The voltage monitor 413 can be, for example, an ADC.

[0174] The watchdog timer 404.5 is tasked with monitoring the entropy quality of the random numbers forming the random bit stream ZBS at the output 411 of the entropy extractor 404.4. The watchdog timer 404.5 can be designed to detect at least three defined error conditions. The watchdog timer 404.5 can forward the valid quantum random bits 411 via line 412 to a (backup) pseudo-random number generator (PRNG) 404.6, which may have an additional linear feedback shift register, by generating a seed value S. The watchdog timer 404.5 can prevent a finite state machine 404.8 from using valid quantum random bits. Here, the finite state machine is connected, for example, to an internal data bus 419. If an error occurs, the watchdog timer 404.5 can set specific error bits for further evaluation, which other bus participants (e.g., microcontrollers (MCUs)) can read and / or write via the external data bus DB, the data bus interface DBIF, and the internal data bus 419.

[0175] For example, if the watchdog timer 404.5 detects an error in the quantum random number generator 400, it can put the quantum random number generator 400 into an emergency operating state. To do this, the watchdog timer 404.5 can, for example, set the selection signal 416 of the downstream signal multiplexer 404.7 such that the signal multiplexer 404.7 applies the pseudo-random number PRN (in the form of a pseudo-random bit stream) of the optional PRNG 404.6 to the input of the finite state machine 404.8 via the pseudo-random signal line 417, instead of applying the potentially erroneous random number RN from the output 411 of the entropy extractor 404.4 to the input of the finite state machine.

[0176] An optional additional linear feedback shift register in PRNG 404.6 can be configured to generate pseudo-random numbers (PRNs). The seed value S can contain the last valid quantum random bits at the output 411 of the entropy extractor 404.4. The watchdog 404.5 can then apply or output these last valid quantum random bits 411 to the input of the optional PRNG 404.6. The seed value S can then be used as a random, secure starting value for the generator polynomial of the optional additional linear feedback shift register in PRNG 404.6, used to generate the pseudo-random numbers PRN and transmit them via pseudo-random signal line 417. The generator polynomial and its order are freely selectable. With the optional backup pseudo-random number generator 404.6, at least temporarily secure random numbers can be provided in case of error.

[0177] Finite state machine 404.8 can be designed to receive random numbers forming a random bit stream ZBS or optionally receive pseudo-random numbers PRN (optionally at the output of signal multiplexer 404.7) and generate at least one quantum random data word 418 based on it. The quantum random data word 418 can optionally be written from automaton 404.8 to memory 404.9 via pseudo-random signal line 417, optionally to volatile memory (RAM) or FIFO (First In - First Out) memory. It is conceivable that once the quantum random data word 418 is written to memory 404.9, automaton 404.8 sets a completion flag 404.10 via internal data bus 419. Thereafter, the processor (MCU) can, for example, access memory 404.9 and read the quantum random data word 418, and use it, for example, for encryption. That is, as an addition to or alternative to the random bit data stream ZBS, encryption engine 800 (see...) Figure 8 Encryption can also be performed using quantum random data words 418. Therefore, the following description of random bit data streams (ZBS) also applies to quantum random data words 418.

[0178] Figure 7 A schematic diagram of an exemplary layout of an integrated electronic circuit 500 is shown, which includes a quantum random number generator 400 having an entropy source 401 and is shown in a top view within a pad frame 503.

[0179] The integrated electronic circuit 500 (e.g., a microcontroller with a CPU) may have an internal region 505. Sub-circuits of the integrated electronic circuit 500 may be arranged in this internal region 505.

[0180] Internal area 505 may be surrounded by wiring area 504. Power supply lines, data bus lines and / or other lines may be laid or present in wiring area 504.

[0181] The wiring area 504 and internal area 505 of the integrated electronic circuit 500 may be surrounded by a pad frame 503 (also referred to as a pad edge). The pad frame 503 may include connection pads 502 (connection surfaces) (optionally for electrical bonding connections and / or other electrical connection connections).

[0182] The entropy source 401 and / or the quantum random number generator 400 may be wholly or at least primarily disposed within the pad frame 503, more specifically, between at least two connection pads 502. This is likely due to the fact that the gaps between the individual connection pads 502 may not be filled by electronic circuitry. However, these gaps still require processing during the fabrication of the integrated electronic circuitry 500, potentially incurring manufacturing costs. Therefore, placing the entropy source 401 and / or the quantum random number generator 400 wholly or at least primarily disposed within the pad frame 503 reduces the additional costs associated with supplying these devices.

[0183] At least the photon source 55 and / or photon detector 54 can be placed or arranged in the pad frame 503 (optionally between two connection pads 502). Furthermore, the ADC 403, the voltage converter 408 for powering the entropy source 403, the pulse broadening circuit 406, and / or other analog components of the quantum random number generator 400 can be placed in the pad frame 503 (optionally between two connection pads 502).

[0184] Figure 8 A schematic diagram of an encrypted communication system 1000 is shown, comprising a quantum random number generator (optionally the quantum random number generator 400 described above), an encryption engine 800, and a data interface 600.

[0185] System 1000 is connected to an external data processing device or an external computing system 700 (optionally a microprocessor or MCU) via data interface 600 and data bus 601.

[0186] The quantum random number generator 400 has at least the aforementioned entropy source 401. The quantum random number generator 400 can be the aforementioned quantum random number generator 400, that is, in addition to the entropy source 401, the quantum random number generator 400 may also include one or more of the above-mentioned references. Figure 5 The aforementioned unit. Therefore, the above description also applies to System 1000. See below for reference. Figure 8 The various units of the quantum random number generator 400 will be described again, and this description also applies to the quantum random number generator 400 described above.

[0187] The quantum random number generator 400 is designed to output the generated random bit data stream ZBS (as described above) to the encryption engine 800.

[0188] The encryption engine 800 can be designed to encrypt the first portion of the random bits in the random bit data stream ZBS into an encrypted random bit data stream VZS. For this, the encryption engine 800 can use a key that can be stored in the memory 801 of the encryption engine 800.

[0189] The MCU 700 can be designed to call encrypted random bits via the data bus 601 and the data interface 600 and use them as encrypted random numbers.

[0190] The encryption engine 800 can be designed to decrypt encrypted instructions sent from the external computing system 700 to the system 1000, which are output by the MCU 700 to the system 1000 via the data bus 601 and the interface 600.

[0191] The encryption engine 800 can be designed to output decryption commands to the system 1000, or the encryption engine 800 itself can use these decryption commands when it is the receiver of the decryption commands. In this way, the MCU 700 can reliably control the system 1000.

[0192] The watchdog 404.5 or similar device may be designed to monitor the entropy of the random bit stream ZBS, the operating voltage of the entropy source 401 and / or voltage converter 408 (which provides the power supply voltage VSUP to the entropy source 401), the externally applied power supply voltage and / or the power supply voltage device CLV (which provides the power supply voltage to the digital device section) to ensure that they are functioning correctly or at the correct values.

[0193] The additional monitoring loop 1001 can be designed to detect other anomalies.

[0194] The voltage pre-regulator 1002 can be designed to supply power to other voltage regulators and keep the current constant (to eliminate side channels generated by current consumption).

[0195] Test interface 1003 is capable of performing manufacturing tests.

[0196] that is, Figure 8 A schematic diagram of an encrypted communication system 1000 is shown, comprising a quantum random number generator (optionally the quantum random number generator 400 described above), an encryption engine 800, and a data interface 600. The system 100 is connected to an external data processing device (optionally a microprocessor or MCU 700) via the data interface 600 and a data bus 601. The quantum random number generator 400 has at least the entropy source 401 described above.

[0197] Specifically, the quantum random number generator 400 generates a random bit stream ZBS, in which random bits are used by the encryption engine 800 for key generation and / or other encryption operations. Here, the aforementioned entropy source 401 enables a high random bit rate in the random bit stream ZBS, which improves the security of the encryption operations of the encryption engine 800.

[0198] The Quantum Random Number Generator 400 can achieve a high random bit rate, which can form the basis for secure encryption operations. This high random bit rate can significantly improve security against quantum attacks. The high random bit rate lays the foundation for fast and secure key generation and encryption operations, thus achieving high security and high efficiency.

[0199] The encryption engine 800 may have an encryption unit 801, which is designed to generate at least one encryption key based on the first portion of random bits in the random bit stream ZBS. The encryption unit 801 may be designed to encrypt data sent by the encryption system 1000 to other bus participants via the data bus 600 in the form of an output data stream VZS, based on the generated key. Encryption in the encryption engine 800 can be performed using computer-implemented algorithms and / or machine-implemented algorithms.

[0200] The encryption engine 800 can be (optionally) fully implemented as a computer-based device.

[0201] The encryption engine 800 may have a memory 802. The computer-implemented encryption algorithm (more precisely, program code) may be stored, at least temporarily, in the memory 801.

[0202] The encryption engine 800 may include a CPU 803. When executing a computer-implemented algorithm, the CPU 803 can execute the algorithm program code stored in the memory 802. The technical advantage is that it can securely encrypt data sent from system 1000 to another bus participant (e.g., MCU 700) via data bus 601. Here, CPU 803 refers not only to components of the encryption engine 800 but can also be a component of system 1000 and / or the quantum random number generator 400.

[0203] The data sent or output by system 1000 may include the second set of random bits in the random bit stream ZBS. The intersection of the first set of random bits in the first part of the random bit stream ZBS and the second set of random bits in the second part of the random bit stream ZBS may be empty or zero, so that system 1000 will not send any random bits that system 1000 has used for data encryption to other bus participants (such as MCU 700) of data bus 601.

[0204] The quantum random number generator 400 may include an entropy module (also known as a watchdog 404.5) designed to monitor the entropy of random bits in the random bit stream ZBS generated by the quantum random number generator 400, or the entropy of random data derived from it. The entropy module 404.5 may be designed to determine and / or monitor predetermined parameter measurements of the entropy of the random bits in the random bit stream ZBS. Such measurements may include, for example, the average value, standard deviation, etc. The entropy module 404.5 may be designed to compare the measured values ​​with a permissible range and take predetermined countermeasures when the measured values ​​exceed the permissible range. In this way, the entropy module 404.5 ensures that the randomness is sufficient to ensure secure encryption operations using the random bits in the random bit stream ZBS. If necessary, from a security practice perspective, the entropy module 404.5 may also require a reasonable deviation from randomness. For example, when the quantum random number generator 400 generates a predetermined number of consecutive random bits in the random bit stream ZBS and these random bits have the same logical value, the entropy module may reverse the subsequent random bits in the random bit stream ZBS. Optionally, the activation and deactivation of this targeted deviation from the ideal random bit stream ZBS can be achieved by writing encryption instructions to registers or flags of the quantum random number generator 400 or its device portion via the system 1000's data interface 601. The entropy module 404.5 can perform this monitoring using a computer-implemented algorithm and / or a machine-implemented algorithm. The program code for the computer-implemented algorithm can be stored in the quantum random number generator 400's memory 404.9. This program code can be executed by the quantum random number generator 400 or the system 1000's CPU. The advantage of using the entropy module 404.5 is that it improves the security of the encryption process of the encryption engine 800 and enhances the availability of random bits in the random bit stream ZBS of the quantum random number generator 400.

[0205] The quantum random number generator 400 may include a filter module (also known as an entropy extractor 404.4). The filter module 404.4 of the quantum random number generator 400 may be designed to improve the statistical properties of random bits in the random bit stream ZBS by eliminating systematic patterns and / or ensuring a uniform distribution of random bits. Computer-implemented algorithms and / or machine-implemented algorithms may also be used (similarly applicable to the description of algorithms above). The filter module may also be part of the control logic. The advantage of the filter module 404.4 is that it enables the random bits in the random bit stream ZBS to be optimized for cryptographic applications. Optionally, the filter module 404.5 may include a digital high-pass filter, which limits the ideal white noise of the ideal random bit data stream to a low-frequency range, thus avoiding too many consecutive random bits with identical logical content in the random bit stream ZBS.

[0206] System 100 may include an interface unit (also known as data bus interface 600) designed to enable encrypted communication between system 1000 (more precisely, encryption engine 800) and external systems connected to the common data bus 601 as bus participants. Interface unit 600 may be designed to support at least one or more different communication protocols, thus enabling system 1000 to be used in different networks. Optionally, for the above purposes, interface unit 600 may be configured via voltage levels at external terminals set for this purpose and / or via dedicated encryption instructions. Interface unit 600 can ensure that encrypted data VZS can be securely transmitted through system 1000 and then through encryption engine 800. Communication protocol control may include computer-implemented algorithms and / or machine-implemented algorithms (similarly applicable to the description of algorithms above) and / or software programs (computer implementation also means machine implementation, unless otherwise expressly stated herein). This enables secure data transmission between quantum random number generator 400 and / or encryption engine 800 and / or other bus participants (e.g., MCU 700) of the common data bus 601. Here, system 1000 and / or encryption engine 800 (as part of system 1000) transmit data to other bus participants 700 on data bus 601, including the second random bit portion of the random bits in the random bit stream ZBS of the aforementioned quantum random number generator 400, and / or the status information of the quantum random number generator 400 and / or its device portion, and / or the status information of the encryption engine 800, and / or the status information of other device portions of system 1000. Data received by system 1000 and / or encryption engine 800 from other bus participants (e.g., MCU 700) via data bus 601 may also include the aforementioned control data used to configure the quantum random number generator 400 and / or encryption engine 800.

[0207] System 1000 and / or encryption engine 800 and / or quantum random number generator 400 may include one or more CPU cores and / or one or more memories, wherein at least temporarily stored are device part simulation program code for computer implementation and / or machine implementation of system 1000 and / or encryption engine 800 and / or quantum random number generator 400 and / or other device parts of system 1000.

[0208] During the operation of System 1000, the quantum random number generator 400 can continuously generate random bits in the random bit stream ZBS.

[0209] The generated random bits can be monitored by the entropy module 404.5 to ensure that these random bits do indeed have sufficient entropy.

[0210] The monitored random bits can be filtered by filter module 404.4 to optionally ensure that these random bits do not contain any systematic patterns, are uniformly distributed, and / or do not contain any random structures that may eventually lead to the random transmission of messages in plaintext over a period of time.

[0211] The first portion of the filtered random bits can be supplied to the encryption unit 801 of the encryption engine 800, which uses the random bits in the first portion of the filtered random bits to generate an encryption key and / or data for the encryption system 1000.

[0212] Interface unit 600 can ensure that encrypted data is securely transmitted to external systems or other bus participants (such as MCU 700) on external data bus 601.

[0213] These components work together to ensure a high level of security for System 1000 and Encryption Engine 800, because the generated random bits are highly random and the encryption operations are extremely difficult to crack.

[0214] The encryption engine 800 may have a key management unit 804. The key management unit 804 may be designed to manage the generated encryption keys, store the keys, and / or provide the keys to the necessary processes or units that require them. Its advantage is that it can securely manage the keys of the encryption engine 800.

[0215] System 1000 may include a line control unit, which may be designed to monitor signals on the communication lines between the various modules of system 1000 and / or encryption engine 800, thereby ensuring that data integrity is maintained.

[0216] The power control unit can act as part of the so-called "watchdog" of the system 1000, which monitors the proper functioning of the system 1000 (health check), detects attacks or measures the probability of an attack currently occurring when necessary, and determines the corresponding measurement value when necessary.

[0217] It is conceivable that the encryption engine 800 is implemented as a post-quantum encryption engine or includes a post-quantum encryption engine. In this way, the encryption engine 800 can resist attacks from quantum computers and, if necessary, resist attacks from modern artificial intelligence algorithms.

[0218] In this regard, the encryption engine 800 and / or system 1000 may include a post-quantum coprocessor 805. A post-quantum coprocessor (PQK) can be defined as a dedicated processor designed to execute computer-implemented and / or machine-implemented post-quantum cryptographic algorithms. Optionally, the post-quantum coprocessor 805 is a device portion of the encryption engine 800. The post-quantum coprocessor 805 may also be a device portion of the system 100 and work in conjunction with the encryption engine 800, thereby improving resistance to quantum attacks.

[0219] Encryption Engine 800 and / or System 1000 can use one or more of the following PQC encryption methods:

[0220] "BIKE1-L1-CPA", "BIKE1-L3-CPA", "BIKE1-L1-FO", "BIKE1-L3-FO", "Kyber512", "Kyber768", "Kyber1024", "Kyber512-90" s", "Kyber768-90s", "Kyber1024-90s", "LEDAcryptKEM-LT12", "LEDAcryptKEM-LT32", "LEDAcryptKEM-LT52", "NewHope-51 2-CCA", "NewHope-1024-CCA", "NTRU-HPS-2048-509", "NTRU-HPS-2048-677", "NTRU-HPS-4096-821", "NTRU-HRSS-701", "Li ghtSaber-KEM", "Saber-KEM", "FireSaber-KEM", "BabyBear", "BabyBearEphem", "MamaBear", "MamaBearEphem", "PapaBear ”, “PapaBearEphem”, “FrodoKEM-640-AES”, “FrodoKEM-640-SHAKE”, “FrodoKEM-976-AES”, “FrodoKEM-976-SHAKE”, “FrodoK EM-1344-AES", "FrodoKEM-1344-SHAKE", "SIDH-p434", "SIDH-p503", "SIDH-p610", "SIDH-p751", "SIDH-p434-compressed" , "SIDH-p503-compressed", "SIDH-p610-compressed", "SIDH-p751-compressed", "SIKE-p434", "SIKE-p503", "SIKE-p610" , "SIKE-p751", "SIKE-p434-compressed", "SIKE-p503-compressed", "SIKE-p610-compressed", "SIKE-p751-compressed".

[0221] Encryption Engine 800 and / or System 1000 can use one or more of the following PQC signature methods to sign data packets:

[0222] “DILITHIUM_2”、“DILITHIUM_3”、“DILITHIUM_4”、“MQDSS-31-48”、“MQDSS-31-64”、“SPHINCS+-Haraka-128f-robust”、“SPHINCS+-Haraka-128f-simple”、“SPHINCS+-Haraka-128s-robust”、“SPHINCS+-Haraka-128s-simple”、“SPHINCS+-Haraka-192f-robust”、“SPHINCS+-Haraka-192f-simple”、“SPHINCS+-Haraka-192s-robust”、“SPHINCS+-Haraka-192s-simple”、“SPHINCS+-Haraka-256f-robust”、“SPHINCS+-Haraka-256f-simple”、“SPHINCS+-Haraka-256s-robust”、“SPHINCS+-Haraka-256s-simple”、“SPHINCS+-SHA256-128f-robust”、“SPHINCS+-SHA256-128f-simple”、“SPHINCS+-SHA256-128s-robust”、“SPHINCS+-SHA256-128s-simple”、“SPHINCS+-SHA256-192f-robust”、“SPHINCS+-SHA256-192f-simple”、“SPHINCS+-SHA256-192s-robust”、“SPHINCS+-SHA256-192s-simple”、“SPHINCS+-SHA256-256f-robust”、“SPHINCS+-SHA256-256f-simple”、“SPHINCS+-SHA256-256s-robust”、“SPHINCS+-SHA256-256s-simple”、“SPHINCS+-SHAKE256-128f-robust”、“SPHINCS+-SHAKE256-128f-simple”、“SPHINCS+-SHAKE256-128s-robust”、“SPHINCS+-SHAKE256-128s-simple”、“SPHINCS+-SHAKE256-192f-robust”、“SPHINCS+-SHAKE256-192f-simple”、"SPHINCS+-SHAKE256-192s-robust", "SPHINCS+-SHAKE256-192s-simple", "SPHINCS+-SHAKE256-256f-r obust", "SPHINCS+-SHAKE256-256f-simple", "SPHINCS+-SHAKE256-256s-robust", "SPHINCS+-SHAKE256 -256s-simple", "picnic_L1_FS", "picnic_L1_UR", "picnic_L3_FS", "picnic_L3_UR", "picnic_L5_FS", "picnic_L5_UR", "picnic2_L1_FS", "picnic2_L3_FS", "picnic2_L5_FS", "qTesla-pI", "qTesla-p-III". ,

[0223] The second part of the random bits in the random bit stream ZBS can be used to generate the associated signature and key.

[0224] The encryption engine 800 and / or system 1000 may include a (quantum-resistant) key generator 806. This key generator 806 is an optional part of the encryption engine 800 and / or system 1000 and can be designed to generate keys (according to current technology) that are resistant to quantum attacks. The quantum-resistant key generator 806 achieves this by using random bits from the first portion of the random bits in the random bit stream ZBS to generate the key, thus creating a secure key resistant to quantum attacks.

[0225] A quantum random number generator can be designed such that the random bit rate of its provided random bit stream ZBS is sufficient to generate quantum-resistant keys.

[0226] These keys can be generated by the quantum-resistant key generator 806, and then the post-quantum coprocessor 805 uses these keys to encrypt data transmitted by the system 1000 and / or its encryption engine 800 and / or its device components.

[0227] The interface unit 600 can be designed to ensure quantum-resistant key secure transmission.

[0228] This ensures the security of data transmission to and from System 1000.

[0229] System 1000 can be envisioned for applications with high computing power requirements, such as high-frequency trading systems or other time-critical applications.

[0230] System 1000 and / or encryption engine 800 may include a parallel encryption processor 807. The parallel encryption processor 807 enables encryption engine 800 to execute multiple encryption operations simultaneously, thereby minimizing processing time. The system may include more than one CPU and / or more than one quantum random number generator 400 to run or execute encryption operations, optionally algorithmically implemented encryption operations. Its advantage lies in enabling system 1000 to accelerate data processing.

[0231] System 1000 may have a (high-speed) clock line 808 (or a clock line 808 operating at a higher frequency than other clock lines). Clock line 808 may be designed to synchronize the operation of parallel encryption processor 807 with other modules of encryption engine 800 and / or system 1000, thereby avoiding delays and achieving the desired synchronization effect.

[0232] The quantum random number generator 400 can provide the required random bits at a high random bit rate, which are directly forwarded to the parallel encryption processor 807. The parallel encryption processor 808 can be designed to use these random bits to perform parallel encryption operations. The clock line 808 can be designed to ensure the synchronous operation of the device portions of the system 1000. Performing parallel encryption through the parallel encryption processor 807 can bring the advantage of increased processing speed to the system 1000, providing powerful computing capabilities and enabling the simultaneous execution of multiple encryption operations, which may be advantageous in time-critical applications.

[0233] An energy-efficient encryption engine 800 can be provided, for example, for use in mobile devices (such as smartphones, tablets, etc.) and / or Internet of Things (IoT) systems.

[0234] The encryption engine 800 and / or system 1000 may have an energy-saving module 809. The energy-saving module 809 may be designed to monitor and / or regulate the energy consumption of the system 1000 and / or encryption engine 800. It is conceivable that the energy-saving module 809 is designed to disable unused modules in the system 1000 and / or encryption engine 800 and / or reduce the power of these modules, thereby achieving the desired energy-saving effect.

[0235] It is conceivable that system 1000 receives encryption instructions via data bus 601 requesting a limitation and / or cessation of random bit generation. For example, system 1000 could also have a power-down pin to reduce power consumption. The main advantage is that entropy source 401 might require a higher voltage, which in turn optimizes power consumption.

[0236] The encryption engine 800 and / or system 1000 may include a (low-power) clock line 810, which is a dedicated clock line that operates at a (lower) frequency (or a frequency lower or smaller than other frequencies used) to reduce power consumption.

[0237] Functionality and Synergy: The internal random number generator (ZZG) can operate in either an energy-saving mode or a normal operating mode. In energy-saving mode, power consumption is low and the random bit rate is typically low (it may even be zero). In normal operating mode, power consumption is higher and the random bit rate is also higher, with the energy-saving module ensuring that only necessary random bits are generated. A low-power clock line synchronizes the operation of the random number generator ZZG and the encryption engine KE with low power consumption. The technical advantage of this variant is that it significantly reduces power consumption while maintaining the security of encryption operations.

[0238] Technical advantages: This variant can minimize energy consumption, making it particularly suitable for battery-powered devices.

[0239] A technical drawback is that in applications requiring powerful computing capabilities, reducing power may not be sufficient to meet the demands.

[0240] An encryption engine 800 with a focus on security can be provided. This encryption engine 800 can meet the highest security requirements.

[0241] The encryption engine 800 and / or system 1000 may include a security monitor 811. The security monitor 811 may be designed to continuously monitor the status of the quantum random number generator 400, the encryption engine 800, and / or other device components of the system 1000. The security monitor 811 may be designed to shut down and / or reconfigure the quantum random number generator 400, the encryption engine 800, and / or other device components of the system 1000 and / or place them in a predetermined security mode and / or emergency operating state in the event of an (identified) attack and / or error. The security module 811 may be designed to signal such events to one or more bus participants (e.g., MCU 700) on the data bus 601 (e.g., via an interrupt line and / or via an interrupt line combination to set specific register flags and / or via an interrupt combination to set specific register values ​​in the registers of the system 1000 and / or via setting specific register values ​​in the registers of the system 1000), which improves and ensures the security of the entire encryption engine 800 and system 1000. Security monitor 811 may be part of the aforementioned watchdog 404.5, which performs a health check. Security monitor 811 may be implemented entirely or at least largely in hardware to reduce its tamperability.

[0242] The encryption engine 800 and / or system 1000 may include a (secure) communication unit 812, which may be designed to ensure encrypted communication and / or eavesdropping-proof communication via interface 600 (optionally all external interfaces of system 1000), thus enabling secure communication.

[0243] Encrypted communication, or eavesdropping-proof communication, refers to the techniques and methods used to ensure the confidentiality and integrity of information during transmission. Such communication technologies protect messages from unauthorized access, eavesdropping, and / or tampering by third parties.

[0244] Encryption can be understood as the process of converting a message (plaintext) into unreadable text (ciphertext) using an algorithm. Even if an unauthorized third party intercepts the message, they will not be able to read it without the matching decryption key. Examples of encryption methods can include symmetric encryption (such as AES) and / or asymmetric encryption (such as RSA).

[0245] The quantum random number generator 400 can continuously provide random bits, and the security monitor 811 can monitor the integrity of these random bits. The communication unit 812 can ensure that all external data transmissions via the data bus 601 are encrypted and / or protected against eavesdropping. High security of the encryption engine 800 and system 1000 can be achieved through the computer- and / or machine-implemented monitoring algorithms in the security monitor 811 and / or the encryption software in the communication unit 812.

[0246] Each module can be implemented in hardware and / or software. Control of one, more, or all modules described herein can be accomplished through one or more computer-implemented algorithms and / or machine-implemented algorithms. The CPU of the quantum random number generator 400, the CPU of the encryption engine 800, and / or the CPU of the system 1000 can be designed to execute the program code for each algorithm. One or more algorithms can be stored in the memory of the quantum random number generator 400, the memory of the encryption engine 800, and / or the CPU of the system 1000. "Control" is also understood as pure regulation, i.e., feedback control.

[0247] Figure 9 An exemplary method 30000 for fabricating a microelectronic integrated circuit 500 with a monolithically integrated entropy source 401 in a semiconductor substrate 110 is illustrated.

[0248] The method begins with a dataset 30020 providing a netlist for the microelectronic integrated circuit 2 (30010). This netlist is typically an output data file of a so-called EDA tool used for circuit development of the microelectronic circuit 2. Generally, the provided netlist contains sub-circuit blocks for entropy source 401 or sub-circuit blocks containing entropy source 401 within its data. At this point, the sub-circuit blocks themselves may still be unstructured and are essentially characterized by their interface and simulation behavior model. That is, the designer of the microelectronic integrated circuit 2 does not need to understand the internal structure of entropy source 401 or the sub-circuit blocks containing entropy source 401. The use of this entropy source 401 can be charged on a royalty basis, and the method does not need to disclose the specific technical design of the entropy source 401.

[0249] Preferably, the architect of the microelectronic integrated circuit 2 now generates a preliminary overall layout 30027 of the microelectronic integrated circuit 2 based on the provided netlist 30020 and the existing layout data of the known sub-block 30026, wherein the layout components of the entropy source 401 are still missing or only represented to a degree that is insufficient for manufacturing.

[0250] The next step is to provide layout data 30035 for entropy source 401 (30030). Providing layout data 30035 for entropy source 401 is preferably not done by the architect of microelectronic circuit 2, but by the company or individual manufacturing microelectronic integrated circuit 2. Then, based on dataset 30050 of the overall layout using microelectronic integrated circuit 2, the company or individual preferably performs the process of generating dataset 30050 of the overall layout 30055 (30040) on its server using a computer-implemented layout method. Here, the computer-implemented layout method combines the layout data 30035 of entropy source 401 with layout data 30027 of other device portions of microelectronic integrated circuit 2, as well as any other layout information and / or structural layout data (if necessary) that may be needed to manufacture microelectronic integrated circuit 2, merging them into the overall layout dataset 30050 by the computer-implemented synthesis method. Then, in CMOS semiconductor process, BiCOMS semiconductor process or bipolar semiconductor device semiconductor process, based on the overall layout dataset 30050, the 30060 microelectronic circuit is fabricated on the wafer.

[0251] Finally, microelectronic integrated circuit 2 (30070) is separated from the wafer complex, and the entropy source 401 of microelectronic integrated circuit 30080 is used as the random bit source of a sub-component of quantum random number generator QRNG 28.

[0252] The method is characterized in that: during the process of synthesizing the layout data 30050 of the overall layout 30040, the layout data 30035 of the entropy source 401 includes the layout data of the photon source 54 (especially the first SPAD diode or Zener diode or photon source 54); during the process of synthesizing the layout data 30050 of the overall layout 30040, the layout data of the entropy source 401 includes the layout data of the photon detector 55 (especially the second SPAD diode and / or single photon detector); in the overall layout 30050, the layouts of the photon source 54 and the photon detector 55 are stacked one on top of the other, such that after the microelectronic integrated circuit 2 30060 is fabricated in and / or on the semiconductor substrate 49, the photon source 54 and the photon detector 55 are fabricated by the fabrication 30060 of the microelectronic integrated circuit 2 in the semiconductor process as being formed by stacking one on top of the other in the semiconductor substrate 49, below the horizontal surface O of the semiconductor substrate 49, and substantially vertically.

[0253] The following examples illustrate the various possible uses of the aforementioned results or equipment.

[0254] It is conceivable that the aforementioned system 1000 and / or the aforementioned quantum random number generator 400 can be applied to devices in robotic or automatic control systems, for example, a driver assistance system for a motor vehicle. It is conceivable that the driver assistance system is designed to control the lateral and / or longitudinal guidance of the motor vehicle based on the random bit data stream ZBS generated by the quantum random number generator 400.

[0255] It is conceivable that the aforementioned System 1000 and / or the aforementioned quantum random number generator 400 can be applied to mobile devices (e.g., smartphones, tablets, etc.) and / or Internet of Things (IoT) systems. It is conceivable that System 1000 and / or the quantum random number generator 400 can be integrated into a security chip in a smartphone or other handheld device, mobile device, or data processing device (e.g., a laptop). This chip can generate encryption keys. Additionally or alternatively, the chip can also provide high tamper resistance. For example, keys can be generated on-site or on-demand using entropy source 401, so that even if the device is compromised, it will not store keys and / or have keys that can be stolen. It is conceivable that, additionally or alternatively, System 1000 and / or the quantum random number generator 400 can be integrated into various mobile applications to encrypt and protect data transactions. For this purpose, a software layer can be set up that interacts with System 1000 and / or the quantum random number generator 400 to obtain keys for encrypting and decrypting application data. This ensures end-to-end data security for various applications on mobile devices or IoT systems. A communication protocol can also be envisioned that uses keys generated as described above to establish and / or maintain secure communication links. In other words, System 1000 and / or the quantum random number generator 400 can be seamlessly integrated into (optionally existing) mobile communication protocols to create quantum-secure communication networks. A blockchain system utilizing the output data of System 1000 and / or the quantum random number generator 400 on a smartphone is also envisioned. This significantly improves the security of the blockchain and its resistance to attacks, further protecting transactions and data stored on the blockchain. The random numbers generated by the quantum random number generator can be used as encryption keys to protect the blockchain, making blockchain technology more suitable for applications such as cryptocurrencies and contract tracking on mobile devices.

[0256] It is conceivable that the above-described system 1000 and / or the above-described quantum random number generator 400 can be applied to plug-in connectors.

[0257] List of reference numerals

[0258] 10P doped substrate

[0259] 29N type region (HVNW / NEPI)

[0260] 22. First District (e.g., NBL)

[0261] 32 Second Zone (e.g., PBL)

[0262] 45N+ type region (N+)

[0263] 46P+ type area (PBODY)

[0264] 47 Absorption Region

[0265] 48 epitaxial layers

[0266] 49 carrier substrate

[0267] 51P+ type region (P+)

[0268] 50 First PN junction

[0269] 52 Second PN junction

[0270] 53 Metallization layer or metal layer

[0271] 54 photon detectors

[0272] 541 bottom

[0273] 542 top surface

[0274] 543 Side / Side Surface

[0275] 55 Photon Source

[0276] 551 bottom

[0277] 552 top surface

[0278] 553 Side / Side Surface

[0279] 554 Third PN Junction

[0280] 58 photons

[0281] 110 substrate

[0282] 122 Cathode Photon Source

[0283] 132 Cathode Photon Detector

[0284] 124, 134 anodes

[0285] 141 metallization layer

[0286] 142 metallization layer

[0287] 400 quantum random number generator

[0288] 401 Entropy Source

[0289] 403 Analog-to-Digital Converter

[0290] 404.3 Pseudo-random number generator

[0291] 404.4 Entropy Extractor or Filter Module

[0292] 404.6 (Backup) Pseudo-random number generator

[0293] 404.7 signal multiplexer

[0294] 404.8 Finite Automata

[0295] 404.9 memory

[0296] 404.10 Completion Mark

[0297] Output signal of 405 entropy source

[0298] 406 pulse broadening circuit

[0299] Output signal of 407 analog-to-digital converter

[0300] 408 voltage converter

[0301] Output signal of 410 pseudo-random number generator

[0302] 411 Output of the entropy extractor or filter module

[0303] 412 Watchdog to (backup) Pseudo-random number generator line

[0304] 413 Voltage Monitor

[0305] 414 Input / Output Signal Lines

[0306] 415 Synchronization Voltage Signal

[0307] 416 Selection Signal

[0308] 418 quantum random data words

[0309] 419 Internal Data Bus

[0310] 421 Voltage Converter Circuit

[0311] 500 Integrated Electronic Circuits

[0312] 501 frame / outer edge

[0313] 502 connection pads

[0314] 503 pad frame

[0315] 504 cabling area

[0316] 505 interior area

[0317] 600 data interface

[0318] 601 External Data Bus

[0319] 700 External Data Processing Device

[0320] 800 encryption engine

[0321] 801 Encryption Engine Memory

[0322] 802 memory

[0323] 803 CPU

[0324] 804 Key Management Unit

[0325] 805 post-quantum coprocessor

[0326] 806 (Quantum-resistant) Key Generator

[0327] 807 (parallel) encryption processor

[0328] 808 (High-Speed) Clock Circuit

[0329] 809 Energy Saving Module

[0330] 810 (Low Power) Clock Circuit

[0331] 811 Security Monitor

[0332] 812 (Security) Communication Unit

[0333] 1000 Encrypted Communication System

[0334] 1001 monitoring loop

[0335] 1002 Voltage Pre-Regulator

[0336] 1003 Test Interface

[0337] 30000 Methods for fabricating microelectronic integrated circuits

[0338] 30010 provides a dataset of netlists for microelectronic integrated circuits;

[0339] 30020 Netlist

[0340] 30025 generates an overall preliminary layout.

[0341] Layout data of other devices in 30026 microelectronic integrated circuits

[0342] Overall layout of 30027 microelectronic integrated circuits

[0343] 30026 is a known sub-block layout data in which the layout components of the entropy source are still missing or only represented to a degree insufficient for manufacturing.

[0344] 30030 provides the layout data of the entropy source;

[0345] 30040 uses a computer-implemented layout method to generate a dataset of overall layout data.

[0346] Dataset of the overall layout of 30050

[0347] 30060 Dataset based on overall layout for fabricating microelectronic circuits on wafers of wafer complexes

[0348] 30070 separates microelectronic integrated circuits from wafer complexes;

[0349] The 30080 uses the entropy source of microelectronic integrated circuits as a random bit source (especially in quantum random number generators).

[0350] VDD power supply line

[0351] V ENT Power supply voltage lines

[0352] V REF Reference voltage circuit

[0353] GND reference potential line

[0354] ZBS Random Bit (Data) Stream

[0355] VZS encrypted random bit data stream

[0356] Surface of O substrate

[0357] Surface of S-carrier substrate

Claims

1. A monolithically integrated entropy source (401), optionally used as an entropy source for a quantum random number generator (400), wherein, The entropy source (401) includes: - A photon source (55) designed to emit photons (58), wherein the photon source (55) comprises: - A first outer casing, wherein the first outer casing is formed by a first bottom surface (551), a first top surface (552), and at least one first side surface (553) connecting the first bottom surface (551) and the first top surface (552) to each other; and - A photon detector (54) designed to detect photons (58) emitted by the photon source (55). Its features are, The first bottom surface of the photon source (55) is arranged facing the photon detector (54).

2. The entropy source (401) according to claim 1, characterized in that, The photon detector (54) includes: - A second outer casing, wherein the second outer casing is formed by a second bottom surface (541), a second top surface (542), and at least one second side surface (543) connecting the second bottom surface (541) and the second top surface (542) to each other. - Wherein, the first bottom surface (541) of the photon source (55) is arranged facing the second bottom surface (541) of the photon detector (55).

3. A monolithically integrated entropy source (401), optionally used as an entropy source for a quantum random number generator (400), wherein, The entropy source (401) includes: - A photon source (55) designed to emit photons (58); and - A photon detector (54) designed to detect photons (58) emitted by the photon source (55), wherein the photon detector (54) comprises: - A second outer casing, wherein the second outer casing is formed by a second bottom surface (541), a second top surface (542), and at least one second side surface (543) connecting the second bottom surface (541) and the second top surface (542) to each other. Its features are, - The second bottom surface (541) of the photon detector (54) is arranged facing the photon source (55).

4. The entropy source (401) according to any one of the preceding claims, characterized in that, The photon source (55) is a silicon LED and / or a single photon source, optionally a SPAD or an avalanche Zener diode, wherein the avalanche Zener diode optionally has a breakdown voltage of less than 10V.

5. The entropy source (401) according to any one of the preceding claims, characterized in that, The photon source (55) includes: - A third PN junction (554) formed by a third P-type layer (46) and a third N-type layer (45). - The third P-type layer (46) and the third N-type layer (45) may optionally be in contact with each other.

6. The entropy source (401) according to any one of claims 1 to 5, characterized in that, The photon detector (54) includes a single-photon detector, which may be a single-photon avalanche diode or a SPAD.

7. The entropy source (401) according to any one of claims 1 to 6, characterized in that, The photon detector (55) includes: - A first PN junction (50) formed by a first P-type layer (32) and a first N-type layer (22). The first P-type layer (32) and the first N-type layer (22) may optionally be in contact with each other.

8. The entropy source (401) according to claim 7, characterized in that, The photon detector (55) includes: - An absorption region (47) is designed to absorb photons (58) emitted by the photon source (55), such that the absorption region (47) generates an electron-hole pair for each photon (58), optionally generating exactly one electron-hole pair. - Wherein, the absorption region (47) is in contact with the first PN junction (50), and the first PN junction (50) is designed to generate charge avalanche due to the generated electron-hole pairs, and - The photon detector (54) is designed to detect the corresponding photons (58) emitted by the photon source (55) based on the generated charge avalanche.

9. The entropy source (401) according to claim 8, characterized in that, The absorption region (47) has a P-type doped substrate (10) or is composed of a P-type doped substrate (10), which completely covers the surface of the first PN junction (50) facing the photon source (55).

10. The entropy source (401) according to claim 8, characterized in that, The absorption region (47) has a P-type doped substrate (10) that partially covers the surface of the first PN junction (50) facing the photon source (55) and forms a channel extending from the surface of the first PN junction (50) toward the photon source (55), the channel being laterally defined by an N-type doped substrate (29).

11. The entropy source (401) according to claim 8, characterized in that, The absorption region (47) has an N-type doped substrate (29) or is composed of an N-type doped substrate (29), which completely covers the surface of the first PN junction (50) facing the photon source (55).

12. The entropy source (401) according to any one of claims 8 to 11, characterized in that, The absorption region (47) is in contact with the photon source (55) and optionally with the p-type doped substrate (46) of the photon source (55).

13. The entropy source (401) according to any one of claims 1 to 12, characterized in that, The photon detector (55) includes: - A second PN junction (52) formed by a second P-type layer (32) and another N-type layer or the first N-type layer (22). - wherein the second P-type layer (32) and the other N-type layer or the first N-type layer (22) may optionally be in contact with each other.

14. The entropy source (401) according to any one of claims 1 to 13, characterized in that, The entropy source (401) has a metal layer (53), which is optionally disposed together with an internal silicide layer, the metal layer shielding the entropy source (401) from the outside.

15. The entropy source (401) according to claim 14, characterized in that, The entropy source (401) has at least two anodes (124, 134) for the photon source (55) and the photon detector (54), the at least two anodes being electrically connected to each other via the metal layer (53).

16. The entropy source (401) according to any one of the preceding claims, characterized in that, The photon source (55) and / or the photon detector (54), optionally the entropy source (401), are constructed in a rotationally symmetrical manner along an axis perpendicular to the first bottom surface (541) and / or the second bottom surface (551).

17. The entropy source (401) according to any one of the preceding claims, characterized in that, The entropy source (401) is made using BCD technology.

18. The entropy source (401) according to any one of claims 1 to 17, characterized in that, The entropy source (401) includes: - A substrate (110) having a carrier substrate (49) and an epitaxial layer (48). - Wherein, when dependent on any one of claims 7 to 13, the epitaxial layer (48) has the first PN junction (50); when dependent on claim 13, the carrier substrate (49) has the second PN junction (52).

19. The entropy source (401) according to any one of claims 1 to 18, characterized in that, The upper and / or lower sides of the entropy source (401) are mirrored and / or include a light-blocking layer at least within the regions of the photon source (55) and / or the photon detector (54).

20. A method for operating an entropy source (401) according to any one of claims 1 to 19, characterized in that, The method includes: - Photons (58) are emitted by the photon source (55), such that the photons (58) leave the photon source (55) via the first bottom surface (551) of the photon source toward the photon detector (54); and / or - The photons (58) emitted by the photon source (55) are received on the second bottom surface of the photon detector.

21. A quantum random number generator (400), characterized in that, The quantum random number generator (400) includes: - Entropy source (401) according to any one of the preceding claims; and - An electronic circuit designed to generate random bits (411) by relying on the output signal (405) of an entropy source (401), and optionally output the generated random bits (411). - Wherein, the characteristics of the output signal (405) of the entropy source (401) depend on the time frequency of the photons (58) detected by the photon detector (54).

22. The quantum random number generator (400) according to claim 21, characterized in that, The quantum random number generator (400) includes a pseudo-random number generator (404.3) designed to generate a digital output signal (410) based on the output signal (405) of the entropy source (401) and a generator polynomial that can be predetermined or adjustable.

23. The quantum random number generator (400) according to claim 22, characterized in that, The quantum random number generator (400) includes an entropy extractor (404.4) designed to generate the random bits (411) based on the digital output signal (410) of the pseudo-random number generator (404.3).

24. The quantum random number generator (400) according to claim 23, characterized in that, The entropy extractor (404.4) is designed to generate the random bits (411), wherein: - Determine the first and second values ​​of the digital output signal (410); - If the first value of the digital output signal (410) is less than the second value of the digital output signal (410), and the difference between the first value of the digital output signal (410) and the second value of the digital output signal (410) is greater than the minimum difference (ε), then the output value of the random bit generation unit (404.4) is set to the first logic value; If the first value of the digital output signal (410) is greater than the second value of the digital output signal (410), and the difference between the first value of the digital output signal (410) and the second value of the digital output signal (410) is greater than the minimum difference (ε), then the output value of the random bit generation unit (404.4) is set to the second logic value.

25. The quantum random number generator (400) according to claim 24, characterized in that, The random bit generation unit (404.4) is designed such that if the difference between the first value and the second value of the digital output signal (410) is less than a predetermined minimum difference (e), then the first value and the second value of the digital output signal (410) are discarded.

26. The quantum random number generator (400) according to claim 26, characterized in that, The quantum random number generator (400) includes a monitoring unit (404.5) designed to monitor the output of the random bit generation unit and optionally detect a fault in the quantum random number generator (400) if the number of values ​​discarded by the random bit generation unit (404.4) exceeds a predetermined limit.

27. An integrated electronic circuit (500), characterized in that, The circuit (500) includes a monolithically integrated entropy source (401) according to any one of claims 1 to 19 and / or a quantum random number generator (400) according to any one of claims 21 to 26, wherein the integrated circuit (500) may be a microelectronic integrated circuit.

28. A computer-readable medium, characterized in that, The computer-readable medium contains data that defines operating guidelines suitable for controlling a semiconductor manufacturing apparatus to manufacture, when the data is output to the semiconductor manufacturing apparatus, an entropy source (401) according to any one of claims 1 to 19, a quantum random number generator (400) according to any one of claims 21 to 16, and / or an integrated electronic circuit (500) according to claim 27.

29. The computer-readable medium according to claim 28, characterized in that, The data includes a digital representation of the entropy source (401), the quantum random number generator (400), and / or the integrated electronic circuit (500) to be used to manufacture the entropy source (401), the quantum random number generator (400), and / or the integrated electronic circuit (500) when the data is output to the semiconductor manufacturing equipment, by using the digital representation and the operating instructions.

30. The computer-readable medium according to claim 28 or 29, characterized in that, Manufacturing the entropy source (401), the quantum random number generator (400), and / or the integrated electronic circuit (500) using the semiconductor manufacturing equipment according to the operating instructions includes: - In semiconductor processes, optionally in CMOS semiconductor processes, BiCMOS semiconductor processes, or bipolar device semiconductor processes, bipolar CMOS technology may be used to fabricate (30060) the entropy source (401), the quantum random number generator (400), and / or the integrated electronic circuit (500) on a wafer.

31. A method for manufacturing a computer-readable medium according to any one of claims 29 to 31, the computer-readable medium comprising first data, the first data defining operating instructions suitable for controlling a semiconductor manufacturing apparatus to manufacture, by means of the semiconductor manufacturing apparatus, the integrated electronic circuit (500) according to claim 27 when the data is output to the semiconductor manufacturing apparatus, characterized in that, The method includes: - Provide (30030) second data, the second data defining an operating guide suitable for controlling the semiconductor manufacturing equipment to manufacture an entropy source (401) according to any one of claims 1 to 19 by means of the semiconductor manufacturing equipment when the second data is output to the semiconductor manufacturing equipment. - The first data (30040) is generated based on the following: - The second data provided, and - Third data, the third data defining an operational guideline applicable to controlling the semiconductor manufacturing equipment so that, when the third data is output to the semiconductor manufacturing equipment, the semiconductor manufacturing equipment is used to manufacture the remainder of the integrated electronic circuit (500) according to claim 27, excluding the entropy source (401).

32. The method according to claim 31, characterized in that: - The operating instructions for the first data contain the overall layout of the entire circuit (500). - The operation guidelines for the second data include a layout of the entropy source (401) or consist of a layout of the entropy source (401), and - The operation guidelines for the third data include or consist of an overall preliminary layout (500) of the entire circuit, wherein the overall preliminary layout does not include the layout of the entropy source (401).

33. The method according to claim 32, characterized in that, Generating (30040) the first data includes: - By means of a computer-implemented layout method, or optionally by means of a computer-implemented synthesis method, the layout data of the entropy source (401) is merged with the overall preliminary layout data, or optionally synthesized, in order to obtain the overall layout data.

34. The method according to claim 32 or 33, characterized in that, The method includes: - Provide a netlist for the (30010) circuit (500), wherein the netlist includes blocks of the entropy source (401); and - Based on the provided netlist (30020), generate (30025) the overall preliminary layout (30027) of the circuit (500).

35. A method for fabricating an entropy source (401) according to any one of claims 1 to 19, a quantum random number generator (400) according to any one of claims 21 to 26, and / or an integrated electronic circuit (500) according to claim 27, characterized in that, The method includes: - The entropy source (401), the quantum random number generator (400), and / or the integrated electronic circuit (500) may be made using a semiconductor manufacturing apparatus, optionally by using a computer-readable medium according to any one of claims 28 to 30.

36. A system (1000), characterized in that, The system (1000) includes: - The entropy source (401) according to any one of claims 1 to 19 may optionally be a quantum random number generator (400) according to any one of claims 21 to 26; and - An encryption engine (800) is designed to encrypt the data stream using the output signal (405) of the entropy source (401) and optionally using random bits generated by the quantum random number generator (400).

37. The system (1000) according to claim 36, characterized in that, - The quantum random number generator (400) is designed to output multiple random bits in the form of a random bit stream (ZBS), and - The encryption engine (800) is designed to use the first part of the random bit stream (ZBS) to generate the key.

38. The system (1000) according to claim 37, characterized in that, - The encryption engine (800) is designed to use the generated key to encrypt a second portion of the random bit stream (ZBS) in order to obtain an encrypted random bit data stream (VZB).

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