Analog front-end circuit and arc detection chip and equipment

Abstract

The invention discloses an analog front-end circuit and an arc detection chip and device. The analog front-end circuit comprises a first signal amplification circuit, a filter circuit, a second signal amplification circuit, a signal processing circuit, a temperature balance circuit and a third signal amplification circuit. The first signal amplification circuit, the filter circuit and the second signal amplification circuit can be used as main signal channels. The first signal amplification circuit, the filter circuit, the signal processing circuit, the temperature balance circuit and the third signal amplification circuit can be used as auxiliary feature extraction channels. Through a dual-channel collaborative architecture, the integrity of an original waveform is guaranteed, and adaptive optimization of feature extraction is realized; the temperature balance circuit and the data compression module form a closed-loop adjustment mechanism so as to improve the reliability and long-term stability of the analog front-end circuit in a wide temperature range environment.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to an analog front-end circuit and an arc detection chip and device. Background Technology

[0002] Electrical fires, as a major type of disaster threatening public safety, are primarily caused by fault arcing. This type of fault is usually triggered by physical defects such as deteriorated electrical circuit insulation and loose connections, accompanied by high-temperature discharge and posing a significant risk of ignition by flammable materials.

[0003] With the accelerated construction of new power systems and the widespread application of diversified electrical equipment, the current waveform of the power distribution network exhibits complex distortion characteristics. This makes it easy for the abnormal signals of fault arcs to be masked by the dynamic current fluctuations of normal loads, making accurate diagnostic technology a core bottleneck restricting the effectiveness of electrical fire prevention and control.

[0004] Analog front-end (AFE) circuits are used for preliminary processing of acquired signals. Understandably, the performance and parameters of the AFE circuit will affect the accuracy of the final detection. When arcing occurs in the circuit under test, the arc signal in the acquired signal exhibits microsecond-level abrupt changes and a wide dynamic range. Furthermore, when using an analog front-end circuit to sample and detect the current transmitted in the circuit under test, changes in the ambient temperature can cause parameter drift in some components of the analog front-end circuit. These temperature variations significantly affect sampling accuracy and signal fidelity. Summary of the Invention

[0005] The purpose of this application is to provide an analog front-end circuit and an arc detection chip and device, which aims to solve the problem of detection accuracy in traditional arc detection.

[0006] A first aspect of this application provides an analog front-end circuit, including: a first signal amplification circuit, a filter circuit, a second signal amplification circuit, a signal processing circuit, a temperature balancing circuit, and a third signal amplification circuit; the input terminal of the first signal amplification circuit is used to input a measured signal, the input terminal of the filter circuit is connected to the output terminal of the first signal amplification circuit, the input terminal of the second signal amplification circuit is connected to the output terminal of the filter circuit, the input terminal of the signal processing circuit is connected to the output terminal of the filter circuit, the input terminal of the third signal amplification circuit is connected to the output terminal of the signal processing circuit, the input terminal of the temperature balancing circuit is connected to the output terminal of the signal processing circuit, and the output terminal of the temperature balancing circuit is connected to the signal processing circuit; wherein, the signal processing circuit includes a data compression module, the temperature balancing circuit is used to generate and output a feedback signal based on the signal output by the signal processing circuit, and the feedback signal is used to configure the compression threshold of the data compression module.

[0007] In one embodiment, the signal processing circuit further includes a rectifier module, the input terminal of which is connected to the output terminal of the filter circuit, and the output terminal of which is connected to the input terminal of the data compression module.

[0008] In one embodiment, the data compression module includes a signal filtering unit and a signal dimensionality reduction unit; the input of the signal filtering unit is connected to the output of the rectifier module, and the input of the signal dimensionality reduction unit is connected to the output of the signal filtering unit; the signal filtering unit is used to extract and output signals higher than the compression threshold according to the compression threshold.

[0009] In one embodiment, the signal processing circuit further includes an integrator, the input of which is connected to the output of the data compression module, and the output of which is connected to the input of the third signal amplification circuit and the input of the temperature balancing circuit.

[0010] In one embodiment, the output of the temperature balancing circuit is also connected to the integrator, and the feedback signal is also used to configure the integration time of the integrator.

[0011] In one embodiment, the temperature balancing circuit includes an operational amplifier, a first transistor, a second transistor, a compensation capacitor, a first resistor, and a second resistor. The first terminal of the first resistor is connected to the output terminal of the signal processing circuit, the second terminal of the first resistor is connected to the collector of the first transistor, the emitter of the first transistor is connected to the emitter of the second transistor, the base of the first transistor is grounded, the collector of the second transistor is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the signal processing circuit, and the base of the second transistor is grounded. The non-inverting input terminal of the operational amplifier is connected to the first terminal of the second resistor, the inverting input terminal of the operational amplifier is grounded, the first terminal of the compensation capacitor is connected to the output terminal of the operational amplifier, and the second terminal of the compensation capacitor is connected to the non-inverting input terminal of the operational amplifier.

[0012] In one embodiment, the filtering circuit includes multiple filters cascaded in sequence.

[0013] In one embodiment, the third signal amplification circuit includes multiple amplifiers cascaded in sequence.

[0014] A second aspect of this application provides an arc detection chip, including a processor and an analog front-end circuit as described above, wherein the processor is connected to the analog front-end circuit.

[0015] A third aspect of this application provides an arc detection device, including a current transformer and an arc detection chip as described above, wherein the current transformer is connected to the arc detection chip.

[0016] The beneficial effects of this application embodiment compared with the prior art are as follows: the first signal amplification circuit, the filter circuit, and the second signal amplification circuit can serve as the main signal path, which is used to amplify, filter, and re-amplify the measured signal. The signal output by the second signal amplification circuit can be used to provide a basis for waveform feature analysis of the measured signal.

[0017] The first signal amplification circuit, filter circuit, signal processing circuit, temperature balancing circuit, and third signal amplification circuit can serve as auxiliary feature extraction pathways, providing high-precision feature output for the identification of fault arcs.

[0018] The analog front-end circuit with a dual-path collaborative architecture can achieve adaptive optimization of feature extraction while ensuring the integrity of the original waveform; the temperature balancing circuit and the data compression module form a closed-loop regulation mechanism to improve the reliability and long-term stability of the analog front-end circuit in a wide temperature range environment. Attached Figure Description

[0019] Figure 1A schematic diagram of an analog front-end circuit provided in an embodiment of this application;

[0020] Figure 2 This is another schematic diagram of an analog front-end circuit provided in an embodiment of this application; Figure 3 A detailed circuit diagram of a temperature balancing circuit provided in one embodiment of this application; Figure 4 This is a schematic diagram of an arc detection chip provided in an embodiment of this application; Figure 5 This is a schematic diagram of an arc detection device provided in an embodiment of this application.

[0021] Figure Descriptions: 10. Analog front-end circuit; 20. Arc detection chip; 30. Processor; 40. Arc detection device; 50. Current transformer; 100. First signal amplification circuit; 200. Filtering circuit; 210. First filter; 220. Second filter; 230. Third filter; 300. Second signal amplification circuit; 400. Signal processing circuit; 410. Data compression module; 420. Rectifier module; 430. Integrator; 500. Temperature balancing circuit; 600. Third signal amplification circuit; 610. First-stage amplifier; 620. Second-stage amplifier. Detailed Implementation

[0022] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0023] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0024] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0025] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] Figure 1 A schematic diagram of an analog front-end circuit according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and the details are as follows: An analog front-end circuit 10 includes: a first signal amplification circuit 100, a filter circuit 200, a second signal amplification circuit 300, a signal processing circuit 400, a temperature balancing circuit 500, and a third signal amplification circuit 600.

[0027] The input terminal of the first signal amplification circuit 100 is used to input the signal to be measured. The input terminal of the filter circuit 200 is connected to the output terminal of the first signal amplification circuit 100, and the input terminal of the second signal amplification circuit 300 is connected to the output terminal of the filter circuit 200.

[0028] The input terminal of the signal processing circuit 400 is connected to the output terminal of the filter circuit 200, the input terminal of the third signal amplification circuit 600 is connected to the output terminal of the signal processing circuit 400, the input terminal of the temperature balancing circuit 500 is connected to the output terminal of the signal processing circuit 400, and the output terminal of the temperature balancing circuit 500 is connected to the signal processing circuit 400.

[0029] Among them, such as Figure 2 As shown, the signal processing circuit 400 includes a data compression module 410 and a temperature balancing circuit 500 for generating and outputting a feedback signal based on the signal output by the signal processing circuit 400. The feedback signal is used to configure the compression threshold of the data compression module 410.

[0030] Understandably, the first signal amplification circuit 100 amplifies the weak measured signal, increasing the signal amplitude to meet the level range requirements of subsequent processing. The filter circuit 200 filters out noise and other clutter signals from the signal, retaining the arc characteristics in the measured signal, improving the signal-to-noise ratio, and laying the foundation for accurate identification of arc characteristics. The output of the second signal amplification circuit 300 can be used to connect to external circuits and equipment, and the second signal amplification circuit 300 can further adjust the signal gain to adapt to external circuits and equipment.

[0031] The data compression module 410 can be used to dynamically compress the filtered signal to retain the necessary key arc feature information while adapting to the input range of subsequent modules, thus avoiding information loss. The temperature balancing circuit 500 generates a real-time feedback signal based on the signal output of the signal processing circuit 400 to dynamically adjust the compression threshold of the data compression module 410, ensuring that the compression threshold can still accurately match the energy distribution of the arc feature when the ambient temperature changes, thereby maintaining a stable balance between detection sensitivity and anti-interference capability.

[0032] The first signal amplification circuit 100, the filter circuit 200, and the second signal amplification circuit 300 can serve as the main signal path, amplifying, filtering, and then re-amplifying the measured signal. The signal output from the second signal amplification circuit 300 can be used to provide a basis for waveform characteristic analysis of the measured signal.

[0033] The first signal amplification circuit 100, the filter circuit 200, the signal processing circuit 400, the temperature balancing circuit 500, and the third signal amplification circuit 600 can serve as auxiliary feature extraction pathways to provide high-precision feature output for the identification of fault arcs.

[0034] The analog front-end circuit 10 with a dual-path collaborative architecture can achieve adaptive optimization of feature extraction while ensuring the integrity of the original waveform; the temperature balance circuit 500 and the data compression module 410 form a closed-loop regulation mechanism to improve the reliability and long-term stability of the analog front-end circuit 10 in a wide temperature range environment.

[0035] The analog front-end circuit 10 in this embodiment can achieve high-precision, high-reliability, and low-cost arc detection, and is especially suitable for intelligent low-voltage electrical appliances, new energy systems, special vehicles, and electrical systems.

[0036] In one embodiment, the signal processing circuit 400 further includes a rectifier module 420, the input terminal of which is connected to the output terminal of the filter circuit 200, and the output terminal of the rectifier module 420 is connected to the input terminal of the data compression module 410.

[0037] The rectifier module 420 can convert AC signals into unipolar pulsating signals, which facilitates subsequent compression, feature extraction, and signal integration processing.

[0038] In one embodiment, the data compression module 410 includes a signal filtering unit and a signal dimensionality reduction unit.

[0039] The input of the signal filtering unit is connected to the output of the rectifier module 420, and the input of the signal reduction unit is connected to the output of the signal filtering unit.

[0040] The signal filtering unit is used to extract and output signals that are higher than the compression threshold based on the compression threshold.

[0041] Understandably, without an electric arc, the measured signal typically fluctuates within a certain amplitude range. However, once an electric arc is generated, the amplitude of the measured signal will change significantly. By filtering the signal according to a set compression threshold, only signal segments with amplitudes exceeding the compression threshold are retained, while stationary segments irrelevant to the electric arc characteristics are removed. This significantly reduces data redundancy and improves the timeliness and accuracy of subsequent analysis.

[0042] The signal dimensionality reduction unit compresses the input signal from multi-dimensional features into a low-dimensional feature vector, thereby preserving the key time-frequency features required for arc identification under limited bandwidth.

[0043] Specifically, the data compression module 410 can compress key features of the input signal, such as peak amplitude, pulse width, di / dt abrupt change, and main frequency component of high-frequency noise (100kHz~1MHz), compressing the data volume to 1 / 5 to 1 / 10 of the original data, while ensuring that the arc features are not distorted.

[0044] In one embodiment, the signal processing circuit 400 further includes an integrator 430, the input of which is connected to the output of the data compression module 410, and the output of which is connected to the input of the third signal amplification circuit 600 and the input of the temperature balancing circuit 500.

[0045] Integrator 430 can perform integration on the compressed signal. When an electric arc occurs, integrator 430 can extract the energy accumulation characteristics of the electric arc signal and output a DC component that is positively correlated with the duration and intensity of the electric arc, so that subsequent circuits can more accurately identify the electric arc.

[0046] In one embodiment, the output of the temperature balancing circuit 500 is also connected to the integrator 430, and the feedback signal is also used to configure the integration time of the integrator 430.

[0047] It is understandable that the temperature balance circuit 500 can form a feedback closed-loop regulation mechanism based on the signal output of the integrator 430, so that the time constant of the integrator 430 can be dynamically compensated as the temperature drifts, thereby improving the stability of the integrator 430 in a wide temperature range.

[0048] For example, when the temperature rises, the feedback signal can extend the integration time of integrator 430. When the temperature falls, the feedback signal can shorten the integration time of integrator 430, thereby achieving temperature drift compensation for integrator 430.

[0049] In one embodiment, such as Figure 3As shown, the temperature balancing circuit 500 includes an operational amplifier U1, a first transistor Q1, a second transistor Q2, a compensation capacitor C1, a first resistor R1, and a second resistor R2. The first end of the first resistor R1 is connected to the output terminal of the signal processing circuit 400, and the second end of the first resistor R1 is connected to the collector of the first transistor Q1. The emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2, and the base of the first transistor Q1 is grounded. The collector of the second transistor Q2 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the signal processing circuit 400. The base of the second transistor Q2 is grounded. Specifically, the second end of the second resistor R2 can be connected to the data compression module 410 and the integrator 430 respectively to provide feedback signals to the data compression module 410 and the integrator 430.

[0050] The non-inverting input terminal of operational amplifier U1 is connected to the first terminal of the second resistor R2, the inverting input terminal of operational amplifier U1 is grounded, the first terminal of compensation capacitor C1 is connected to the output terminal of operational amplifier U1, and the second terminal of compensation capacitor C1 is connected to the non-inverting input terminal of operational amplifier U1.

[0051] Specifically, both the first transistor Q1 and the second transistor Q2 are NPN transistors. It should be noted that the internal resistance of the transistors drifts with temperature changes. When the signal output from the signal processing circuit 400 is input through the first resistor R1, the first transistor Q1 and the second transistor Q2 can combine with the operational amplifier U1 and the compensation capacitor C1 to form a closed-loop feedback network. This allows the generation and output of a feedback signal based on the signal output from the signal processing circuit 400. The data compression module 410 can then adjust the compression threshold in real time according to this feedback signal.

[0052] Specifically, in some embodiments, the output of the signal processing circuit 400 can be calibrated within a wide temperature range of -55℃ to +120℃ through temperature compensation of the temperature balancing circuit 500, thereby offsetting the effects of temperature drift and ensuring that the output drift of the analog front-end circuit 10 is stable within 150ppm, thus improving the reliability and consistency of the analog front-end circuit 10 in complex electrical environments.

[0053] In one embodiment, the filter circuit 200 includes a plurality of filters arranged in cascade.

[0054] By cascading multiple filters in sequence, layered suppression of noise in different frequency bands can be achieved.

[0055] For example, such as Figure 2As shown, in one embodiment, the filtering circuit 200 includes a first filter 210, a second filter 220, and a third filter 230 cascaded in sequence. The input terminal of the first filter 210 is connected to the output terminal of the first signal amplification circuit 100, the input terminal of the second filter 220 is connected to the output terminal of the first filter 210, and the input terminal of the third filter 230 is connected to the output terminal of the second filter 220. The output terminal of the third filter 230 can be connected to the input terminals of the second signal amplification circuit 300 and the signal processing circuit 400, respectively. The first filter 210, the second filter 220, and the third filter 230 can filter signals of different frequency bands in the signal, for example, they can specifically filter out high-frequency interference, harmonic noise, and other clutter signals in the signal, thereby ensuring that the arc characteristics in the measured signal are purely preserved, providing a high signal-to-noise ratio basis for fault identification.

[0056] In one embodiment, the third signal amplification circuit 600 includes a plurality of amplifiers arranged in cascade.

[0057] By cascading multiple amplifiers, the weak DC component output by the integrator 430 can be amplified step by step to match the input impedance and dynamic range requirements of subsequent circuits, so as to facilitate the identification of the signal output by the third signal amplifier circuit 600.

[0058] For example, such as Figure 2 As shown, in one embodiment, the third signal amplification circuit 600 includes a first-stage amplifier 610 and a second-stage amplifier 620. The input terminal of the first-stage amplifier 610 is connected to the output terminal of the signal processing circuit 400, and the input terminal of the second-stage amplifier 620 is connected to the output terminal of the first-stage amplifier 610. The two amplifiers can be designed with low noise and high common-mode rejection ratio.

[0059] Figure 4 A schematic diagram of the structure of an arc detection chip according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: An arc detection chip 20 includes a processor 30 and an analog front-end circuit 10 as described in any of the above embodiments, wherein the processor 30 is connected to the analog front-end circuit 10.

[0060] Since the arc detection chip 20 has all the technical features of the analog front-end circuit 10, the arc detection chip 20 also has the beneficial effects of the analog front-end circuit 10, and will not be described again in this embodiment.

[0061] The processor 30 can perform real-time analysis based on the signal output by the analog front-end circuit 10 to determine whether there is an arc fault in the circuit under test.

[0062] Specifically, the processor 30 may be a microcontroller (MCU) with a built-in high-precision analog-to-digital converter (ADC) module.

[0063] In some embodiments, a system-in-package (SiP) process can be used to integrate the analog front-end circuit 10 and the processor 30 within the arc detection chip 20.

[0064] Figure 5 A schematic diagram of an arc detection device according to an embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: An arc detection device 40 includes a current transformer 50 and an arc detection chip 20 as described in any of the above embodiments, wherein the current transformer 50 is connected to the arc detection chip 20.

[0065] The current transformer 50 can perform non-contact sampling of the current of the line under test, and can generate and output the test signal corresponding to the current of the line under test.

[0066] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and circuits is merely an example. In practical applications, the above functions can be assigned to different functional units and circuits as needed, that is, the internal structure of the device can be divided into different functional units or circuits to complete all or part of the functions described above. The functional units and circuits in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and circuits are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and circuits in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0067] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0068] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An analog front-end circuit, characterized in that, include: The circuit comprises a first signal amplifier circuit, a filter circuit, a second signal amplifier circuit, a signal processing circuit, a temperature balancing circuit, and a third signal amplifier circuit. The input terminal of the first signal amplification circuit is used to input the signal to be measured, the input terminal of the filter circuit is connected to the output terminal of the first signal amplification circuit, and the input terminal of the second signal amplification circuit is connected to the output terminal of the filter circuit. The input terminal of the signal processing circuit is connected to the output terminal of the filter circuit, the input terminal of the third signal amplification circuit is connected to the output terminal of the signal processing circuit, the input terminal of the temperature balancing circuit is connected to the output terminal of the signal processing circuit, and the output terminal of the temperature balancing circuit is connected to the signal processing circuit. The signal processing circuit includes a data compression module, and the temperature balancing circuit is used to generate and output a feedback signal based on the signal output by the signal processing circuit. The feedback signal is used to configure the compression threshold of the data compression module.

2. The analog front-end circuit as described in claim 1, characterized in that, The signal processing circuit further includes a rectifier module, the input of which is connected to the output of the filter circuit, and the output of which is connected to the input of the data compression module.

3. The analog front-end circuit as described in claim 2, characterized in that, The data compression module includes a signal filtering unit and a signal dimensionality reduction unit; The input terminal of the signal filtering unit is connected to the output terminal of the rectifier module, and the input terminal of the signal reduction unit is connected to the output terminal of the signal filtering unit. The signal filtering unit is used to extract and output signals that are higher than the compression threshold based on the compression threshold.

4. The analog front-end circuit as described in claim 3, characterized in that, The signal processing circuit also includes an integrator, the input of which is connected to the output of the data compression module, and the output of which is connected to the input of the third signal amplification circuit and the input of the temperature balancing circuit.

5. The analog front-end circuit as described in claim 4, characterized in that, The output of the temperature balancing circuit is also connected to the integrator, and the feedback signal is also used to configure the integration time of the integrator.

6. The analog front-end circuit as described in claim 4, characterized in that, The temperature balancing circuit includes an operational amplifier, a first transistor, a second transistor, a compensation capacitor, a first resistor, and a second resistor. The first terminal of the first resistor is connected to the output terminal of the signal processing circuit, the second terminal of the first resistor is connected to the collector of the first transistor, the emitter of the first transistor is connected to the emitter of the second transistor, the base of the first transistor is grounded, the collector of the second transistor is connected to the first terminal of the second resistor, the second terminal of the second resistor is connected to the signal processing circuit, and the base of the second transistor is grounded. The non-inverting input terminal of the operational amplifier is connected to the first terminal of the second resistor, the inverting input terminal of the operational amplifier is grounded, the first terminal of the compensation capacitor is connected to the output terminal of the operational amplifier, and the second terminal of the compensation capacitor is connected to the non-inverting input terminal of the operational amplifier.

7. The analog front-end circuit as described in any one of claims 1 to 3, characterized in that, The filtering circuit includes multiple filters arranged in cascade.

8. The analog front-end circuit as described in any one of claims 1 to 3, characterized in that, The third signal amplification circuit includes multiple amplifiers cascaded in sequence.

9. An arc detection chip, characterized in that, It includes a processor and an analog front-end circuit as described in any one of claims 1 to 8, wherein the processor is connected to the analog front-end circuit.

10. An arc detection device, characterized in that, It includes a current transformer and an arc detection chip as described in claim 9, wherein the current transformer is connected to the arc detection chip.

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