Method and system for identifying influence of epitaxial wafer defects on performance of SiC device
By using NUV-PL scanning and 3D position modeling to identify defects in SiC epitaxial wafers, the problem of difficult defect location identification in SiC devices is solved, measurement efficiency and yield are improved, and intuitive defect location display is provided.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2024-10-18
- Publication Date
- 2026-04-21
AI Technical Summary
Existing technologies cannot accurately identify the location of epitaxial wafer defects in SiC devices and their impact on device performance, making it impossible to determine the extent to which SiC device performance is affected by epitaxial wafer defects.
Photoluminescence parameters of the epitaxial wafer of SiC device were obtained by NUV-PL scanning. The apex direction and step flow direction of the triangular epitaxial wafer defect were determined. The first and second orientations of the defect in SiC device were identified by combining the photoluminescence parameters. A three-dimensional position model of the defect was constructed, and the impact of the defect on the device performance was analyzed.
It improves the measurement efficiency and layout design accuracy of SiC devices, increases device yield, provides a more intuitive display of defect locations, and assists in device performance analysis.
Smart Images
Figure CN121899600A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically to a method and system for identifying the impact of epitaxial wafer defects on the performance of SiC devices. Background Technology
[0002] In recent years, increasing emphasis has been placed on energy conservation and emission reduction, which has placed higher demands on loss control and efficiency improvement of large power electronic equipment. As an important component of power electronic equipment, semiconductor power devices have received widespread attention from the industry. Silicon carbide (SiC), a third-generation semiconductor material, has great development prospects due to its excellent performance. SiC devices have a higher bandgap and, compared with silicon devices, higher breakdown field strength, operating frequency, and thermal conductivity. They have broad application prospects in high voltage, high frequency, and high power density fields.
[0003] For bulk power devices, breakdown voltage is a crucial indicator, representing the maximum voltage the device can withstand. Theoretically, SiC devices can withstand several times the breakdown voltage of silicon devices. However, due to immature growth techniques, SiC high-voltage epitaxy contains a high density of defects. These defects significantly impact the breakdown voltage performance of SiC devices. Furthermore, because SiC epitaxial wafers require a step-flow growth method, the impact of defects on device performance varies depending on their location within the device. Additionally, during SiC device manufacturing, it is difficult to accurately determine the degree of impact on device performance simply by observing the relative position of defects to the device. Summary of the Invention
[0004] This invention addresses the shortcomings of existing technologies by providing a method and system for identifying the impact of epitaxial wafer defects on the performance of SiC devices. It solves the problem that existing SiC devices cannot determine the degree of impact of epitaxial wafer defects on their performance because the location of these defects cannot be identified during the manufacturing process.
[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:
[0006] A method for identifying the impact of epitaxial wafer defects on the performance of SiC devices includes the following steps:
[0007] Photoluminescence parameters of the epitaxial wafer of the SiC device were obtained by NUV-PL scanning.
[0008] The direction of the sharp corner of the triangular epitaxial wafer defect is determined based on the scanning results of NUV-PL scanning, and the step flow direction of the SiC device is determined based on the direction of the sharp corner.
[0009] The first orientation of the triangular epitaxial wafer defect within the SiC device is determined based on the step flow direction, and the second orientation of the triangular epitaxial wafer defect within the SiC device is determined based on the photoluminescence parameters.
[0010] The defect location of the triangular epitaxial wafer defect is obtained based on the first and second orientations;
[0011] The impact on device performance is obtained based on the location of the defect.
[0012] Optionally, determining the first orientation of the triangular epitaxial wafer defect within the SiC device based on the step flow direction includes the following steps:
[0013] When the orientation of the triangular epitaxial wafer defect relative to the active region is opposite to the step flow direction, the first orientation of the triangular epitaxial wafer defect is the upstream orientation;
[0014] When the orientation of the triangular epitaxial wafer defect relative to the active region is the same as the step flow direction, the first orientation of the triangular epitaxial wafer defect is the downstream orientation.
[0015] Optionally, determining the second orientation of the triangular epitaxial wafer defect within the SiC device based on the photoluminescence parameters includes the following steps:
[0016] Based on the photoluminescence parameters, the positional relationship between the triangular epitaxial wafer defect and the space charge region, the terminal region, and the active region is obtained.
[0017] When the triangular epitaxial wafer defect is located outside the space charge region, the second orientation of the triangular epitaxial wafer defect is the external orientation;
[0018] When a portion of the triangular epitaxial wafer defect is located outside the terminal region and another portion of the triangular epitaxial wafer defect is located inside the terminal region, the second orientation of the triangular epitaxial wafer defect is the central orientation.
[0019] When all the defects in the triangular epitaxial wafer are located within the active region and the terminal region, the second orientation of the defects in the triangular epitaxial wafer is the internal orientation.
[0020] Optionally, obtaining the defect location of the triangular epitaxial wafer defect based on the first and second orientations includes the following steps:
[0021] The first and second orientations are combined to obtain the defect location, wherein the defect location includes the upstream exterior, upstream middle, interior, downstream middle, and downstream exterior.
[0022] Optionally, obtaining the device performance impact result based on the defect location includes the following steps:
[0023] A mapping relationship between defect types and their impact on device performance is established, and the defect type of the triangular epitaxial wafer is generated based on the defect location;
[0024] Based on the defect type, the impact on device performance is obtained.
[0025] Optionally, the direction of the sharp corner is opposite to the step flow direction of the SiC device.
[0026] Optionally, after obtaining the photoluminescence parameters of the epitaxial wafer of the SiC device by NUV-PL scanning, the following steps are also included:
[0027] Based on the photoluminescence parameters, a three-dimensional location model of the extended defects in the SiC device is constructed.
[0028] A system for identifying the impact of epitaxial wafer defects on the performance of SiC devices, the system comprising a parameter acquisition unit, a step flow direction determination unit, an orientation identification unit, a defect location unit, and a result output unit;
[0029] The parameter acquisition unit is used to acquire the photoluminescence parameters of the epitaxial wafer of the SiC device through NUV-PL scanning.
[0030] The step flow direction determination unit is used to determine the sharp corner direction of the triangular epitaxial wafer defect based on the scanning results of NUV-PL scanning, and to determine the step flow direction of the SiC device based on the sharp corner direction.
[0031] The orientation identification unit is used to determine the first orientation of the triangular epitaxial wafer defect within the SiC device based on the step flow direction, and to determine the second orientation of the triangular epitaxial wafer defect within the SiC device based on the photoluminescence parameters.
[0032] The defect location unit is used to obtain the defect location of the triangular epitaxial wafer defect based on the first orientation and the second orientation.
[0033] The result output unit is used to obtain the device performance impact result based on the defect location.
[0034] A testing apparatus that performs the method for identifying the impact of epitaxial wafer defects on the performance of SiC devices as described in any of the preceding claims.
[0035] A computer-readable storage medium storing at least one line of program code, which is loaded and executed by a processor to implement the method for identifying the impact of epitaxial wafer defects on the performance of SiC devices as described in any of the preceding claims.
[0036] Compared with the prior art, the technical solution provided by this invention has the following advantages:
[0037] NUV-PL scanning technology is used to identify defects on the epitaxial wafer, and the precise location of the defects is determined by the first and second orientations. This allows for analysis of the positional relationship between the defects and the active region of the device. Based on this relationship, the impact and degree of the defects on device performance can be determined, improving the efficiency of subsequent device measurements. It can also assist in layout design, increasing the device yield. Furthermore, a three-dimensional position model of the defects under the device is constructed to provide a more intuitive display of the defect location. Attached Figure Description
[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 This is a flowchart of a method for identifying the impact of epitaxial wafer defects on the performance of SiC devices, as proposed in Embodiment 1.
[0040] Figure 2 This is a schematic diagram of the three-dimensional location model of the extended defects under the SiC junction barrier Schottky (JBS) diode device proposed in this embodiment.
[0041] Figure 3 This is a schematic diagram of the upstream defect proposed in Embodiment 1;
[0042] Figure 4 This is a schematic diagram of the downstream defects proposed in Embodiment 1;
[0043] Figure 5 This is a schematic diagram of the external defect in the SiC JBS three-dimensional location model proposed in Embodiment 1;
[0044] Figure 6 This is a schematic diagram of the central defect in the SiC JBS three-dimensional location model proposed in Embodiment 1.
[0045] Figure 7 This is a schematic diagram of the internal defect proposed in Embodiment 1 in the three-dimensional location model of SiC JBS.
[0046] Reference numerals: 1. Active region; 2. Termination region; 3. External region of the device; 4. Top view; 5. Space charge region; 6. Epitaxial layer; 7. Substrate layer; 8. Three-dimensional position model; 9. Upstream external defect; 10. Upstream middle defect; 11. Internal defect; 12. Downstream middle defect; 13. Downstream external defect; 16. Upstream defect; 17. Downstream defect; 18. Structure of upstream external defect inside the device; 19. Structure of downstream external defect inside the device; 20. Structure of upstream middle defect inside the device; 21. Structure of downstream middle defect inside the device; 22. Structure of internal defect inside the device; 23. Neutral region. Detailed Implementation
[0047] The present invention will be further described in detail below with reference to the embodiments. The following embodiments are explanations of the present invention, but the present invention is not limited to the following embodiments.
[0048] like Figure 1 As shown, a method for identifying the impact of epitaxial wafer defects on the performance of SiC devices includes the following steps: obtaining the photoluminescence parameters of the epitaxial wafer of the SiC device by scanning with NUV-PL (near-ultraviolet photoluminescence technology).
[0049] Among them, NUV-PL scanning is a non-destructive method for characterizing defects in SiC device epitaxial wafers. The active region and the outer region of the active region of the SiC device produce different wavelengths of light under near-ultraviolet light irradiation, which are manifested as different colors in the acquired images. Therefore, the boundary between the active region and the non-active region of the SiC device can be clearly distinguished.
[0050] On the other hand, since the defects on the device surface are three-dimensional defects, they will form depressions on the device surface. After scanning with near-ultraviolet photoluminescence technology, the acquired image will show a different color from the surrounding area. Therefore, the defect and its position relative to the active area can be clearly observed on the image.
[0051] To facilitate understanding, this embodiment constructs a three-dimensional location model 8 of the extended defects in a SiC device based on photoluminescence parameters. This allows operators to more clearly observe the defect locations using the three-dimensional location model 8. Specifically, the photoluminescence parameters include the dominant wavelength of light emitted by the epitaxial wafer under ultraviolet light irradiation at multiple test locations. Then, based on these photoluminescence parameters, a model is constructed as follows: Figure 2 The three-dimensional position model shown is 8.
[0052] Specifically, the constructed three-dimensional position model 8 includes a top view 4, an epitaxial layer 6, and a substrate layer 7. The top view 4 includes an active region 1, an epitaxial layer 6, and a substrate layer 7. The top view 4 also includes an active region 1, a terminal region 2, and a device external region 3. The epitaxial layer 6 includes a space charge region 5 when the device is reverse biased. Using this space charge region 5 when the device is reverse biased, the defect types existing in the epitaxial layer 6 can be divided into five categories: upstream external defects 9, upstream middle defects 10, internal defects 11, downstream middle defects 12, and downstream external defects 13. The defect type of the triangular epitaxial wafer defect in this embodiment is specifically identified through the following process.
[0053] Furthermore, since the step flow method is required to stabilize the crystal form during silicon carbide epitaxial growth, the size of the defects also increases during the epitaxial growth process. This leads to a significant correlation between the blocking performance of the device and the relative orientation of the defects. Therefore, the direction of the sharp corner of the triangular epitaxial wafer defect is first determined based on the scanning results of NUV-PL scanning, and the step flow direction of the SiC device is determined based on the direction of the sharp corner. Specifically, the triangular defect, as a typical defect on the surface of the epitaxial wafer of the SiC device, appears as a triangle with a distinct sharp corner in the image of NUV-PL technology. Since SiC growth uses the step flow method, the direction of the step flow can be confirmed based on the direction of the sharp corner of the triangular defect in the image. That is, the operator can observe the direction of the sharp corner based on the scanning results. After knowing the direction of the sharp corner, since the direction of the sharp corner is opposite to the step flow direction of the SiC device, the step flow direction can be determined.
[0054] Then, the first orientation of the triangular epitaxial wafer defect within the SiC device is determined based on the step flow direction. Specifically, this includes the following steps: when the orientation of the triangular epitaxial wafer defect relative to the active region is opposite to the step flow direction, the first orientation of the triangular epitaxial wafer defect is the upstream orientation; when the orientation of the triangular epitaxial wafer defect relative to the active region is the same as the step flow direction, the first orientation of the triangular epitaxial wafer defect is the downstream orientation.
[0055] Defects in different orientations of the first orientation can cause the device to exhibit asymmetric breakdown characteristics. This orientation-related asymmetry is not just a superficial problem, but involves the three-dimensional defect morphology inside the epitaxial layer.
[0056] like Figure 3 As shown, the direction indicated by the arrow represents the step flow direction. The direction pointed to by the sharp corner of the triangular epitaxial wafer defect in the NUV-PL image is opposite to the step flow direction. When the orientation of the triangular epitaxial wafer defect relative to the active region is opposite to the step flow direction, the first orientation of the triangular epitaxial wafer defect is the upstream orientation, that is: the orientation of the upstream defect 16 of the device relative to the active region 1 of the device is opposite to the step flow direction.
[0057] like Figure 4 As shown, the direction indicated by the arrow represents the step flow direction. The direction pointed by the apex of the triangular defect in the NUV-PL image is opposite to the step flow direction. When the orientation of the triangular epitaxial wafer defect relative to the active region is the same as the step flow direction, the first orientation of the triangular epitaxial wafer defect is the downstream orientation, that is: the orientation of the downstream defect 17 of the device relative to the active region 1 of the device is the same as the step flow direction.
[0058] After identifying the first orientation of the triangular epitaxial wafer defect, it is necessary to identify the distance of the defect (second orientation). The three-dimensional position model of the extended defect under the device (model 8) shows the positional relationship of the defect within the device at various distances. The distance relationship between the defect and the active region of the device can be divided into external, central, and internal. The position of the external defect in the three-dimensional model is shown below. Figure 5 As shown, the location of the defect in the middle in the 3D model is as follows: Figure 6 As shown, the location of the internal defects in the 3D model is as follows: Figure 7 As shown.
[0059] Specifically, determining the second orientation of a triangular epitaxial wafer defect within a SiC device based on photoluminescence parameters includes the following steps: obtaining the positional relationship of the triangular epitaxial wafer defect relative to the space charge region, the termination region, and the active region based on the photoluminescence parameters; when the triangular epitaxial wafer defect is located outside the space charge region, the second orientation of the triangular epitaxial wafer defect is the external orientation; when a portion of the triangular epitaxial wafer defect is located outside the termination region and another portion is located inside the termination region, the second orientation of the triangular epitaxial wafer defect is the central orientation; when the entire triangular epitaxial wafer defect is located within the active region and the termination region, the second orientation of the triangular epitaxial wafer defect is the internal orientation.
[0060] Then, based on the first and second orientations, the defect location of the triangular epitaxial wafer is obtained, specifically including the following steps: combining the first and second orientations to obtain the defect location, wherein the defect location includes the upstream outer, upstream middle, inner, downstream middle, and downstream outer.
[0061] Next, the device performance impact results are obtained based on the defect location, specifically including the following steps: constructing a mapping relationship between defect type and device performance impact results, and generating the defect type of the triangular epitaxial wafer based on the defect location; based on the defect type, obtaining the device performance impact results, wherein the defect types include upstream external defect 9, upstream middle defect 10, internal defect 11, downstream middle defect 12, and downstream external defect 13.
[0062] The impact of upstream external defect 9 on device performance is relatively small; the impact of upstream mid-section defect 10 on device performance is significant degradation or even failure; the impact of internal defect 11 on device performance is severe degradation or even failure; the impact of downstream mid-section defect 12 on device performance is some degree of degradation; and the impact of downstream external defect 13 on device performance is relatively small.
[0063] More specifically, such as Figure 5 As shown, if a triangular epitaxial wafer defect is completely outside the space charge region 5 when the device is reverse biased, it is considered an external defect. Figure 5 The direction indicated by the middle arrow represents the direction of the step flow. External defects can be divided into upstream external defects (9) and downstream external defects (13). Figure 5 The diagram shows the structure 18 of upstream external defects inside the device and the structure 19 of downstream external defects inside the device. Since they are mainly located in the neutral region 23, and the voltage of the JBS device is mainly borne by the space charge region 5 when it is reverse biased, the performance change of the neutral region 23 will not affect the withstand voltage performance of the space charge region 5. Therefore, the external defects have little impact on the blocking performance of the device.
[0064] like Figure 6 As shown, if the defective portion of the triangular epitaxial wafer is outside device terminal 2, and the other portion is inside device terminal 2, it is considered a central defect. Figure 6 The direction indicated by the middle arrow represents the direction of the stepped flow. The middle defects can be divided into upstream middle defects 10 and downstream middle defects 12. Figure 6 The diagram shows the structure 20 of the upstream mid-section defect inside the device and the structure 21 of the downstream mid-section defect inside the device.
[0065] For upstream middle defect 10, since the expansion direction of upstream defect 16 is close to the positive relationship with the boundary of space charge region 5, and its tail is located in the high electric field region within space charge region 5, it has a higher average electric field amplitude. At the same time, since the defect is relatively closer to the interior of active region 1, the initial leakage current will enter the defect breakdown path earlier, resulting in a longer avalanche path length. Under the combined effect of these two factors, the avalanche multiplication factor of upstream defect 16 under reverse bias shows an exponential growth trend.
[0066] For the downstream middle defect 12, the downstream defect 17 mainly stays in the low electric field region outside the space charge region 5 because its expansion direction is almost parallel to the boundary of the space charge region 5. At the same time, since the defect is relatively far away from the active region 1, the initial leakage current mainly starts to accumulate in the middle of the defect path. Therefore, the effective avalanche path length is relatively shorter. However, since the angle between its expansion direction and the initial direction of the leakage current is closer to orthogonal, its upper end has a larger leakage current density. However, since the avalanche process is not sensitive to the initial value of the leakage current, the avalanche multiplication factor of the downstream defect 17 only shows an approximately linear growth, exhibiting asymmetric characteristics that are quite different from those of the upstream defect 16.
[0067] The avalanche multiplication factor increases with the increase of the electric field, and eventually avalanche breakdown occurs when it reaches infinity. Therefore, the faster the avalanche multiplication factor increases, the lower the electric field strength when the device undergoes avalanche breakdown, which means the lower the breakdown voltage of the device.
[0068] In summary, both upstream mid-section defect 10 and downstream mid-section defect 12 affect device performance, leading to degradation. However, because the avalanche multiplication factor of upstream mid-section defect 10 under reverse bias exhibits an exponential growth trend, the device will experience more severe degradation or even failure. The avalanche multiplication factor of downstream mid-section defect 12 only shows an approximately linear growth, so its impact on device performance is weaker than that of upstream mid-section defect 10, but it will still cause some degree of degradation. On the other hand, because the avalanche multiplication factor of upstream mid-section defect 10 grows faster than that of downstream mid-section defect 12, the upstream mid-section defect 10 has a greater impact on device performance.
[0069] like Figure 7 As shown, if the defect is entirely within the active region 1 and terminal 2 of the device, it is considered internal defect 11. Figure 7 The direction indicated by the middle arrow represents the direction of the step flow and shows the structure 22 of the internal defect inside the device. The internal defect 11 is located at the center of the device. Since it is almost completely exposed to the high electric field, it will generally cause severe degradation or even failure of the device.
[0070] Example 2
[0071] A system for identifying the impact of epitaxial wafer defects on the performance of SiC devices, the system includes a parameter acquisition unit, a step flow direction determination unit, an orientation identification unit, a defect location unit, and a result output unit.
[0072] The parameter acquisition unit is used to acquire the photoluminescence parameters of the epitaxial wafer of the SiC device through NUV-PL scanning.
[0073] The step flow direction determination unit is used to determine the sharp corner direction of the triangular epitaxial wafer defect based on the scanning results of NUV-PL scanning, and to determine the step flow direction of the SiC device based on the sharp corner direction.
[0074] The orientation recognition unit is used to determine the first orientation of the triangular epitaxial wafer defect within the SiC device based on the step flow direction, and to determine the second orientation of the triangular epitaxial wafer defect within the SiC device based on photoluminescence parameters.
[0075] The defect location unit is used to obtain the defect location of the triangular epitaxial wafer defect based on the first orientation and the second orientation.
[0076] The result output unit is used to obtain the impact of the defect location on device performance.
[0077] Since the system in this embodiment executes the method for identifying the impact of epitaxial wafer defects on SiC device performance as described in Embodiment 1, it will not be described in detail in this embodiment.
[0078] Example 3
[0079] A testing apparatus that performs the method for identifying the impact of epitaxial wafer defects on the performance of SiC devices as described in Example 1, for testing the performance impact of epitaxial wafer defects.
[0080] A computer-readable storage medium storing at least one line of program code, which is loaded and executed by a processor to implement the method for identifying the impact of epitaxial wafer defects on the performance of SiC devices as described in Embodiment 1.
[0081] More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wire segments, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0082] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless segments, wire segments, optical cables, RF, etc., or any suitable combination thereof.
[0083] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules, units, or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units, modules, or components may be combined or integrated into another device, or some features may be ignored or not executed.
[0084] The units may or may not be physically separate. The components shown as units can be one or more physical units, meaning they can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0085] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0086] In particular, according to embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication component, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), it performs the functions defined in the methods of this application. It should be noted that the computer-readable medium described above in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof.
[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.
[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A method for identifying the impact of epitaxial wafer defects on the performance of SiC devices, characterized in that, Includes the following steps: Photoluminescence parameters of the epitaxial wafer of the SiC device were obtained by NUV-PL scanning. The direction of the sharp corner of the triangular epitaxial wafer defect is determined based on the scanning results of NUV-PL scanning, and the step flow direction of the SiC device is determined based on the direction of the sharp corner. The first orientation of the triangular epitaxial wafer defect within the SiC device is determined based on the step flow direction, and the second orientation of the triangular epitaxial wafer defect within the SiC device is determined based on the photoluminescence parameters. The defect location of the triangular epitaxial wafer defect is obtained based on the first and second orientations; The impact on device performance is obtained based on the location of the defect.
2. The method for identifying the impact of epitaxial wafer defects on SiC device performance according to claim 1, characterized in that, Determining the first orientation of the triangular epitaxial wafer defect within the SiC device based on the step flow direction includes the following steps: When the orientation of the triangular epitaxial wafer defect relative to the active region is opposite to the step flow direction, the first orientation of the triangular epitaxial wafer defect is the upstream orientation; When the orientation of the triangular epitaxial wafer defect relative to the active region is the same as the step flow direction, the first orientation of the triangular epitaxial wafer defect is the downstream orientation.
3. The method for identifying the impact of epitaxial wafer defects on SiC device performance according to claim 1, characterized in that, Determining the second orientation of the triangular epitaxial wafer defect within the SiC device based on the photoluminescence parameters includes the following steps: Based on the photoluminescence parameters, the positional relationship between the triangular epitaxial wafer defect and the space charge region, the terminal region, and the active region is obtained. When the triangular epitaxial wafer defect is located outside the space charge region, the second orientation of the triangular epitaxial wafer defect is the external orientation; When a portion of the triangular epitaxial wafer defect is located outside the terminal region and another portion of the triangular epitaxial wafer defect is located inside the terminal region, the second orientation of the triangular epitaxial wafer defect is the central orientation. When all the defects in the triangular epitaxial wafer are located within the active region and the terminal region, the second orientation of the defects in the triangular epitaxial wafer is the internal orientation.
4. A method for identifying the impact of epitaxial wafer defects on SiC device performance according to any one of claims 1 to 3, characterized in that, The defect location of the triangular epitaxial wafer defect is obtained based on the first and second orientations, including the following steps: The first and second orientations are combined to obtain the defect location, wherein the defect location includes the upstream exterior, upstream middle, interior, downstream middle, and downstream exterior.
5. The method for identifying the impact of epitaxial wafer defects on SiC device performance according to claim 4, characterized in that, The results of the impact on device performance based on the location of the defect include the following steps: A mapping relationship between defect types and their impact on device performance is established, and the defect type of the triangular epitaxial wafer is generated based on the defect location; Based on the defect type, the impact on device performance is obtained.
6. The method for identifying the impact of epitaxial wafer defects on SiC device performance according to claim 1, characterized in that, The direction of the sharp corner is opposite to the step flow direction of the SiC device.
7. The method for identifying the impact of epitaxial wafer defects on SiC device performance according to claim 1, characterized in that, After obtaining the photoluminescence parameters of the epitaxial wafer of the SiC device by NUV-PL scanning, the following steps are also included: Based on the photoluminescence parameters, a three-dimensional location model of the extended defects in the SiC device is constructed.
8. A system for identifying the impact of epitaxial wafer defects on the performance of SiC devices, characterized in that, The system includes a parameter acquisition unit, a step flow direction determination unit, an orientation recognition unit, a defect location unit, and a result output unit; The parameter acquisition unit is used to acquire the photoluminescence parameters of the epitaxial wafer of the SiC device through NUV-PL scanning. The step flow direction determination unit is used to determine the sharp corner direction of the triangular epitaxial wafer defect based on the scanning results of NUV-PL scanning, and to determine the step flow direction of the SiC device based on the sharp corner direction. The orientation identification unit is used to determine the first orientation of the triangular epitaxial wafer defect within the SiC device based on the step flow direction, and to determine the second orientation of the triangular epitaxial wafer defect within the SiC device based on the photoluminescence parameters. The defect location unit is used to obtain the defect location of the triangular epitaxial wafer defect based on the first orientation and the second orientation. The result output unit is used to obtain the device performance impact result based on the defect location.
9. A testing device, characterized in that, The testing equipment performs the method described in any one of claims 1-7 for identifying the impact of epitaxial wafer defects on the performance of SiC devices.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one piece of program code, which is loaded and executed by a processor to implement the method for identifying the impact of epitaxial wafer defects on the performance of SiC devices as described in any one of claims 1-7.