Low-temperature transistor modeling gold sample screening method

Abstract

The invention discloses a low-temperature transistor modeling gold sample screening method. Firstly, a transistor test structure is designed; secondly, simulating the series of transistors with specific gate lengths and gate widths to obtain a simulation result of a business model under a type corner, and counting a median value used for determining a parameter of a gold sample; and testing the plurality of transistor test structures die at room temperature, comparing the simulation result of each parameter with the actual measurement result, and obtaining an alternative sample of the gold sample according to the standard that each parameter meets the screening criterion. The method is suitable for the gold sample selection process before the low-temperature integrated circuit establishes the intensive model, the gold sample screening efficiency can be greatly improved, and a large amount of manpower and material resources and time cost are saved.

Description

Technical Field

[0001] This invention relates to a method for selecting gold samples for low-temperature transistor modeling, belonging to the field of low-temperature integrated circuit technology. Background Technology

[0002] High-performance infrared detectors and front-end electronics are core components of the electronic systems of infrared space telescopes. High-performance infrared detectors typically operate within a temperature range of 7K-120K to achieve low dark current and low noise performance. Meanwhile, the accompanying front-end electronics, designed to reduce heat leakage from the infrared detector leads and shorten the transmission distance of noise-sensitive signals, often operate within a near-maximum temperature range of 30K-120K. Therefore, due to limitations imposed by operating temperature, size, weight, and power consumption, these electronic systems generally require the use of low-temperature integrated circuits (LTICs), typically including infrared detector readout circuits (ROICs) and analog front-end ASICs.

[0003] In the design and simulation of infrared detector readout circuits (ROICs) and analog front-end ASICs, obtaining accurate and reliable results requires a CMOS transistor compact model with high computational efficiency and accuracy. Commercial CMOS compact models provided by chip manufacturers typically operate within a temperature range of -40℃ to 125℃. However, the reliability of the simulation results drops sharply below -55℃ (218K). Therefore, researchers in low-temperature integrated circuits generally need to develop their own low-temperature CMOS transistor compact model.

[0004] Following the standard screening process at room temperature, establishing a low-temperature CMOS transistor ensemble model first requires DC testing of a large number of CMOS transistor samples. Based on test parameters related to the threshold voltage, a "golden die" sample is determined. Then, comprehensive testing is conducted on the golden die sample to extract all the parameters required for building the ensemble model. Following this, model fitting, validation, optimization, and release are performed.

[0005] Previous researchers have rarely mentioned how gold samples were selected when performing low-temperature modeling of standard CMOS process transistors. Only a few papers mention researchers using standard screening procedures to obtain so-called gold samples, where the number of transistors tested could reach several thousand, requiring a huge workload and a long cycle. If a standard room-temperature screening procedure is used for low-temperature screening, the testing efficiency is significantly reduced again. The main reasons are: 1. Testing requires a low-temperature probe station to provide a 7K-120K low-temperature environment, and each cooling and warming process takes several hours; 2. The sample stage area of ​​the low-temperature probe station is small, limiting the number of dies that can be placed; 3. The low-temperature probe station is used by manually moving multiple independent probe arms, which is inefficient and has a limited range of movement, further limiting the number of dies that can be tested.

[0006] According to statistical theory, when the population distribution is unknown, relying on the Central Limit Theorem, the sample mean of a large sample (n>30) approximately follows a normal distribution. In engineering applications, n>50 can be considered to satisfy the Central Limit Theorem requirement. Therefore, if a standard screening process is used to obtain a "golden sample" of a certain size and a certain parameter, at least 30 samples of that size need to be tested. If this design requires building 100 transistor models of different sizes, testing 5 parameters for each transistor, then 100×5×30=15000 tests are required. Therefore, relying on the statistical median data obtained from a large number of sample tests to determine which device or die is the so-called "golden sample" is inefficient due to the limitations of the low-temperature probe station, requiring a significant amount of time and manpower. Summary of the Invention

[0007] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose a low-temperature transistor modeling method for gold sample screening. This method uses room temperature instead of a low-temperature environment for gold sample screening, which greatly improves the efficiency of gold sample screening and saves a lot of manpower, material resources and time costs.

[0008] The technical solution of this invention is: A method for selecting gold samples for low-temperature transistor modeling is proposed. Based on the conditional independence assumption of temperature, the statistical distribution of transistor threshold voltage obtained by statistics is independent of temperature. Gold samples selected at room temperature still have the same statistical characteristics at low temperatures, that is, the same transistor threshold voltage distribution can be obtained, which can be used for intensive transistor modeling.

[0009] Furthermore, methods for screening gold samples at room temperature include: Based on the PDK provided by the chip manufacturer, extract one transistor of each different size to form a transistor test structure; Simulations were performed on each transistor in the transistor test structure to obtain the corresponding transistor IV curves, and the threshold voltage was statistically analyzed. , , and the drain current in the linear region and saturation region drain current ; I-V tests were performed sequentially on multiple transistor test structure dies at room temperature, and the threshold voltage was statistically determined based on the actual measurement results. , , and the drain current in the linear region and saturation region drain current The corresponding values ​​obtained from the simulation are used as standard values ​​for comparison. If the error of all five parameters is less than the set threshold, they are used as candidate samples for the gold sample until the cumulative number of candidate samples meets the requirements.

[0010] Furthermore, the threshold voltage obtained based on the simulation results , , and the drain current in the linear region and saturation region drain current , as the standard value.

[0011] Furthermore, the transistor test structure consists of transistors of various sizes with different gate lengths and gate widths, and one transistor test structure die contains one transistor device of each size.

[0012] Furthermore, simulations were performed on each transistor in the transistor test structure to obtain simulation results of the commercial model under the typical corner, and to obtain the IV curves of transistors of various sizes.

[0013] Furthermore, for the transistor test structure die, if one or more of the five parameter values ​​obtained from the actual measurement of a transistor device at room temperature have an error exceeding a set threshold compared to the standard value, then the transistor device is discarded.

[0014] Furthermore, the gold sample obtained at room temperature was subjected to low-temperature testing to extract all the parameters required to establish the transistor intensive model.

[0015] The advantages of this invention compared to the prior art are: (1) This invention proposes a method for selecting gold samples in low-temperature transistor modeling, which selects gold sample parameters based on the temperature condition independence assumption of threshold voltage, including threshold voltage. , , and linear region current and saturation region current With five parameters, this method is applicable to the selection process of gold samples before establishing an intensive model for low-temperature integrated circuits. It can greatly improve the efficiency of gold sample screening and save a lot of manpower, material resources and time costs.

[0016] (2) This invention can be applied to high-performance infrared readout circuits and front-end electronic components. It is a key basic technology in the field of high-sensitivity infrared detection, represented by infrared space telescopes. It can also be extended to the broader field of low-temperature electronics, serving the development of integrated circuits and components for extreme environments in the field of deep space exploration. Attached Figure Description

[0017] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a flowchart of the gold sample screening method for low-temperature transistor modeling according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the selection of the test sample size for the low-temperature transistor according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the transistor test structure die according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the simulation curve and the measured curve of the threshold voltage Vtsat in an embodiment of the present invention. Detailed Implementation

[0018] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0019] This invention proposes a method for selecting the best candidates for low-temperature transistor modeling, based on the assumption of conditional independence at temperature. The variance of a stochastic parameter P in the transistor model can be described by the following formula:

[0020] in, P is a constant proportional to the area, and W and L are the gate width and gate length of the transistor. It is the parameter P and its variation with the spacing. It is the distance between two transistors.

[0021] In the above formula, the random parameters depend only on the transistor size and location. The variance of the threshold voltage is almost independent of temperature, so variations of this magnitude do not substantially affect the statistical results of the threshold voltage. Considering that traditional screening processes rely on evaluating the threshold voltage (saturation threshold voltage)... linear region threshold voltage Transconductance peak method threshold voltage By selecting gold samples from transistors obtained from different operating regions or using different extraction methods (approximate values ​​of the same threshold voltage), it can be reasonably inferred that the conditional probability distribution of temperature is independent of other device parameters. That is, gold samples at room temperature retain the same statistical characteristics at low temperatures. Therefore, gold samples can be screened by comparing actual test results at room temperature with simulation results from commercial models at the typical corner.

[0022] This method is as follows Figure 1 As shown, the specific steps include the following: Step 1: Based on the PDK provided by the chip manufacturer, design the test structure according to the transistor dimensions required for establishing a compact transistor model, i.e., a series of transistors with corresponding gate lengths and widths. The selection of the low-temperature transistor test sample size is as follows: Figure 2 As shown.

[0023] Step 2: Simulate the transistors in the transistor size design test structure to obtain simulation results of the commercial model under the typical corner, obtain the IV curves of transistors of all sizes, and statistically analyze the threshold voltage. , , and linear region current and saturation region current Five parameters are used to determine the median value of the five parameters that a gold sample should have.

[0024] Step 3: Perform IV testing on the transistor test structure die at room temperature. The number of transistors in each die corresponds to the sample size (gate length and gate width) in Step 1. During testing, all transistor sizes are sequentially traversed according to a specific transistor size arrangement to avoid omissions. The transistor test structure die is shown below. Figure 3 As shown, each transistor in the transistor test structure has a sample of a corresponding size. The test structure composed of all transistors will be manufactured into a chip, forming a die.

[0025] Step 4: Calculate the threshold voltage from the test results in Step 3. , , and linear region drain current and saturation region current Five parameters were used, and the results were compared with those in step 2. The screening criteria were that the error of all five parameters was less than 5%, and the candidate samples for the gold sample were obtained.

[0026] The simulated and measured curves of the threshold voltage Vtsat are as follows: Figure 4 As shown in the figure, taking parameter Vtsat as an example, when the deviation of the measured Vtsat2 from the simulated Vtsat1 is less than 5%, this parameter can be considered as a candidate for the gold standard. Further evaluation of the other four parameters is needed. If all four meet the criteria, the transistor device can be listed as a candidate for the gold standard of this transistor size. If the deviation of any parameter exceeds 5%, the transistor device is rejected.

[0027] Step 5: Continue testing the next transistor test structure die. For any transistor size, multiple candidate samples can be selected until the cumulative number of candidate samples meets the requirements. At this point, gold samples for each transistor size have been obtained through room temperature testing. Subsequently, these gold samples are subjected to low-temperature testing to extract all the parameters required to build the intensive model.

[0028] This invention obtains the parameters of a typical corner transistor through simulation, and pre-determines whether a sample might be a gold sample before statistically analyzing all data. Based on the normal distribution characteristics of chip manufacturing processes, the probability of a typical corner (TT) on a wafer typically follows this statistical law: the distribution probability of a TT corner on a wafer is approximately 68.27% (within ±1σ), which is a theoretical calculation based on the normal distribution of process parameters. Therefore, from a probabilistic perspective, for every 3 samples tested, 2 of them are likely to be TT corners. Thus, if we assume that one gold sample can be found for every 3 samples tested, the number of tests would be 100 × 5 × 3 = 1500. Compared to the standard screening process, the number of tests using this invention is only 1 / 10 of the standard screening process. Considering the limitations of low-temperature screening, this invention greatly improves screening efficiency.

[0029] The embodiments described above are merely preferred embodiments of the present invention. Ordinary variations and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for screening gold samples using low-temperature transistor modeling, characterized in that, Based on the assumption of conditional independence of temperature, the statistical distribution of transistor threshold voltage is independent of temperature. The gold sample selected at room temperature still has the same statistical characteristics at low temperatures.

2. The method for screening gold samples using low-temperature transistor modeling according to claim 1, characterized in that, Methods for screening gold samples at room temperature include: Based on the PDK provided by the chip manufacturer, extract one transistor of each different size to form a transistor test structure; Simulations were performed on each transistor in the transistor test structure to obtain the corresponding transistor IV curves, and the threshold voltage was statistically analyzed. , , and linear region drain current and saturation region drain current ; I-V tests were performed sequentially on multiple transistor test structure dies at room temperature, and the threshold voltage was statistically determined based on the actual measurement results. , , and linear region drain current and saturation region drain current The corresponding values ​​obtained from the simulation are used as standard values ​​for comparison. If the error of all five parameters is less than the set threshold, they are used as candidate samples for the gold sample until the cumulative number of candidate samples meets the requirements.

3. The method for screening gold samples using low-temperature transistor modeling according to claim 2, characterized in that, Threshold voltage obtained based on simulation results , , and linear region drain current and saturation region drain current , as the standard value.

4. The method for screening gold samples using low-temperature transistor modeling according to claim 2, characterized in that, The transistor test structure consists of transistors of various sizes with different gate lengths and gate widths. One transistor test structure die contains one transistor device of each size.

5. The method for screening gold samples using low-temperature transistor modeling according to claim 2, characterized in that, Simulations were performed on each transistor in the transistor test structure to obtain simulation results of the commercial model under the typical corner, and the IV curves of transistors of various sizes were obtained.

6. The method for screening gold samples using low-temperature transistor modeling according to claim 2, characterized in that, For transistor test die, if one or more of the five parameter values ​​obtained from the actual measurement of a transistor device at room temperature have an error exceeding the set threshold compared to the standard value, then the transistor device is discarded.

7. A method for screening gold samples for low-temperature transistor modeling according to any one of claims 1 to 6, characterized in that, The gold sample obtained at room temperature was subjected to low-temperature testing to extract all the parameters required to establish a low-temperature intensive model of transistors.

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