Linear voltage stabilizing circuit and voltage stabilizing control method

Abstract

The invention discloses a linear voltage stabilizing circuit and a voltage stabilizing control method. The circuit comprises a voltage adjusting module, an error amplifying module and a voltage generating module. The voltage adjusting module is used for determining second reference voltage according to the set parameters and the first reference voltage; the error amplification module is used for outputting control voltage; the voltage generation module is used for generating output voltage according to the control voltage; the error amplification module is also used for generating a control voltage according to the second reference voltage and the output voltage; the voltage adjusting module is also used for determining a phase deviation state; adjusting a first delay parameter according to the phase deviation state; and the setting parameters are adjusted according to the phase deviation state. According to the linear voltage stabilizing circuit, the change of the output voltage is directly fed back to the error amplification module, the change of the output voltage is fed back to the error amplification module by adjusting the second reference voltage, the change of the output voltage is quickly responded by adopting a dual feedback path, and the performance of the linear voltage stabilizing circuit is remarkably optimized.

Description

Technical Field

[0001] This application relates to the field of voltage regulator circuit technology, and more specifically, to a linear voltage regulator circuit and a voltage regulation control method. Background Technology

[0002] Linear voltage regulators can provide stable and low-noise power supply voltages, playing an important role in applications requiring low noise and fast response.

[0003] With the rapid development of controller technology, high-performance controllers are becoming more and more precise and the signal speed is getting faster and faster, which puts forward higher requirements for the performance of linear voltage regulator circuits.

[0004] In related technologies, the output voltage is directly fed back to the error amplification module to adjust for changes in the output voltage. However, due to the physical characteristics of the devices, there is an upper limit to the optimization of their response speed and accuracy, making it difficult to further improve the performance of linear voltage regulator circuits. Summary of the Invention

[0005] In view of the above problems, the present invention proposes a linear voltage regulator circuit and a voltage regulation control method.

[0006] In a first aspect, embodiments of this application provide a linear voltage regulator circuit, comprising: a voltage adjustment module, an error amplification module, and a voltage generation module; wherein the voltage adjustment module is used to determine a second reference voltage based on set parameters and a received first reference voltage; wherein the initial value of the set parameters is determined by a preset reference value received by the voltage adjustment module; a first input terminal of the error amplification module is used to receive the second reference voltage; an output terminal of the error amplification module is used to output a control voltage; the voltage generation module is used to generate an output voltage based on the control voltage; wherein the second input terminal of the error amplification module is used to receive the output voltage; the error amplification module is also used to generate a control voltage based on the second reference voltage and the output voltage; the voltage adjustment module is also used to generate a first clock signal based on the output voltage, a received initial clock signal, and a first delay parameter; the voltage adjustment module is also used to generate a second clock signal based on the initial clock signal, the output voltage, and a second delay parameter; wherein the first delay parameter is greater than the second delay parameter; the voltage adjustment module is also used to determine the phase deviation state of the first clock signal and the second clock signal; The voltage adjustment module is also used to set the value of the setting parameter to the received preset reference value, and adjust the value of the first delay parameter according to the phase deviation state, until the phase deviation value between the first clock signal and the second clock signal is determined to be equal to the preset phase value according to the phase deviation state, and then lock the value of the first delay parameter to the target delay value; wherein, when the value of the setting parameter is the preset reference value and the phase deviation value is the preset phase value, the corresponding value of the first delay parameter is the target delay value; the voltage adjustment module is also used to adjust the size of the setting parameter according to the phase deviation state if the value of the first delay parameter is locked to the target delay value and the phase deviation value is determined to be not equal to the preset phase value according to the phase deviation state.

[0007] Secondly, embodiments of this application also provide a voltage regulation control method, the method comprising: determining a second reference voltage based on a received first reference voltage and a setting parameter; generating a control voltage based on the second reference voltage and an output voltage; generating an output voltage based on the control voltage; generating a first clock signal based on a received initial clock signal, an output voltage, and a first delay parameter; generating a second clock signal based on the initial clock signal, an output voltage, and a second delay parameter; wherein the first delay parameter is greater than the second delay parameter; determining a phase deviation state between the first clock signal and the second clock signal; adjusting the value of the first delay parameter according to the phase deviation state until, when the phase deviation value between the first clock signal and the second clock signal is determined to be equal to a preset phase value, the value of the first delay parameter is locked as a target delay value; wherein, when the value of the setting parameter is a preset reference value and the phase deviation value is a preset phase value, the corresponding value of the first delay parameter is the target delay value; if the value of the first delay parameter is locked as the target delay value, when the phase deviation value is determined to be not equal to the preset phase value according to the phase deviation state, the magnitude of the setting parameter is adjusted according to the phase deviation state.

[0008] The technical solution provided by this invention includes a linear voltage regulator circuit comprising: a voltage adjustment module, an error amplification module, and a voltage generation module; wherein, the voltage adjustment module is used to determine a second reference voltage based on set parameters and a received first reference voltage; wherein, the initial value of the set parameters is determined by a preset reference value received by the voltage adjustment module; the first input terminal of the error amplification module is used to receive the second reference voltage; the output terminal of the error amplification module is used to output a control voltage; the voltage generation module is used to generate an output voltage based on the control voltage; wherein, the second input terminal of the error amplification module is used to receive the output voltage; the error amplification module is also used to generate a control voltage based on the second reference voltage and the output voltage; the voltage adjustment module is also used to generate a first clock signal based on the output voltage, a received initial clock signal, and a first delay parameter; the voltage adjustment module is also used to generate a second reference voltage based on the initial clock signal, the output voltage, and the first reference voltage; A second clock signal is generated using two delay parameters; wherein the first delay parameter is greater than the second delay parameter; the voltage adjustment module is also used to determine the phase deviation state of the first clock signal and the second clock signal; the voltage adjustment module is also used to set the value of the setting parameter to the received preset reference value, and adjust the value of the first delay parameter according to the phase deviation state, until the phase deviation value between the first clock signal and the second clock signal is equal to the preset phase value, and then lock the value of the first delay parameter to the target delay value; wherein, when the value of the setting parameter is the preset reference value and the phase deviation value is the preset phase value, the corresponding value of the first delay parameter is the target delay value; the voltage adjustment module is also used to adjust the size of the setting parameter according to the phase deviation state if the value of the first delay parameter is locked to the target delay value, and the phase deviation value is not equal to the preset phase value. On the one hand, the change in output voltage is directly fed back to the second input terminal of the error amplification module; on the other hand, the change in output voltage is also fed back to the first input terminal of the error amplification module through the adjustment of the second reference voltage. By adopting a dual feedback path, the output voltage change can be responded to quickly, thereby significantly optimizing the performance of the linear voltage regulator circuit. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments and drawings obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0010] Figure 1 A schematic diagram of a linear voltage regulator circuit provided in the embodiments of this application is shown.

[0011] Figure 2 It shows Figure 1 A schematic diagram of the load regulation of a linear voltage regulator circuit.

[0012] Figure 3 It shows Figure 1 A schematic diagram of the linear regulation rate of a medium-linear voltage regulator circuit.

[0013] Figure 4 It shows Figure 1 A schematic diagram of the temperature regulation rate of a linear voltage regulator circuit.

[0014] Figure 5 A schematic diagram of a linear voltage regulator circuit provided in an embodiment of this application is shown.

[0015] Figure 6 A schematic diagram of the structure of a voltage adjustment module provided in an embodiment of this application is shown.

[0016] Figure 7 A schematic diagram of the structure of a clock generation unit provided in an embodiment of this application is shown.

[0017] Figure 8 A schematic diagram of the structure of a clock generation unit provided in an embodiment of this application is shown.

[0018] Figure 9 A schematic diagram of the structure of a voltage adjustment unit provided in an embodiment of this application is shown.

[0019] Figure 10 A flowchart illustrating the adjustment process of a logic subunit provided in an embodiment of this application is shown.

[0020] Figure 11 A flowchart illustrating the adjustment of another logic subunit provided in an embodiment of this application is shown.

[0021] Figure 12 A flowchart illustrating the adjustment process of another logic subunit provided in an embodiment of this application is shown.

[0022] Figure 13 A schematic diagram of a voltage generation module provided in an embodiment of this application is shown.

[0023] Figure 14 A schematic diagram of another voltage generation module provided in an embodiment of this application is shown.

[0024] Figure 15 A schematic flowchart of a voltage regulation control method provided in an embodiment of this application is shown.

[0025] Figure 16 A schematic flowchart of another voltage regulation control method provided in an embodiment of this application is shown. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0027] Terminology Explanation In the embodiments of this application, the low-dropout regulator (LDO), also known as a low-dropout linear regulator or low-voltage-drop regulator, is a type of linear DC regulator that can provide a stable DC voltage power supply.

[0028] In the embodiments of this application, the bandgap voltage reference circuit achieves a temperature-independent voltage reference by using the sum of a voltage with a positive temperature coefficient and a voltage with a negative temperature coefficient, whose temperature coefficients cancel each other out.

[0029] In the embodiments of this application, an error amplifier (EA) is an electronic device that can be used to amplify an "error" signal. The error amplifier detects the minute difference (i.e., error) between the input signal and the reference signal and amplifies it with high precision so that subsequent circuits can make accurate adjustments and corrections accordingly.

[0030] In the embodiments of this application, load regulation refers to the ability of a linear voltage regulator circuit to maintain a stable output voltage when the output current of the load changes. In the embodiments of this application, the linear regulation rate refers to the ability of a linear voltage regulator circuit to maintain a stable output voltage when the input voltage changes.

[0031] In the embodiments of this application, the temperature regulation rate refers to the ability of a linear voltage regulator circuit to maintain a stable output voltage when the ambient temperature changes.

[0032] In the embodiments of this application, a digital-to-analog converter (DAC) is a circuit that converts a numerical code value into an analog level of different voltages. The output analog voltage value is generally determined by a reference voltage and an n-bit input numerical code value (data), and the output voltage Vout = reference voltage × (data / 2). n ).

[0033] In this application, a delay chain (DLY) is a circuit module that precisely sets the signal delay time using digital or analog methods. A delay chain can output an input signal after a certain delay time. The total delay is determined by the delay time of a single delay step and the number of activated steps. The delay time is affected by process technology, voltage, and temperature.

[0034] In this application, VCDL (Voltage-Controlled Delay Line) is a circuit module that adjusts the signal delay time by voltage.

[0035] In this application, intrinsic delay refers to the propagation delay of a logic gate in a digital circuit or integrated circuit under no-load conditions, i.e., the inherent delay without considering the influence of external load capacitance. It also refers to the delay duration of a delay chain when the number of open steps is 0.

[0036] In this application, a D flip-flop is a digital circuit unit. The basic function of a D flip-flop is to update the state of the input port to the output port and latch it at the effective edge of the clock signal. Some flip-flops have a reset / set function, which can be achieved by adjusting the signal at the reset or set terminal.

[0037] In the embodiments of this application, a finite state machine (FSM) is a numerical logic circuit that can realize a mathematical model of the response to external events in different states.

[0038] In embodiments of this application, the R-2R DAC (R-2R Resistor Ladder Digital-to-Analog Converter) utilizes a precision resistor network (typically with only two resistance values: R and 2R) to convert digital signals into analog voltages or currents.

[0039] In the embodiments of this application, the resistor-string DAC (Resistor-String Digital-to-Analog Converter) is a voltage divider network consisting of a large number of resistors with the same resistance value connected in series. Through a multiplexer (such as an analog switch tree or decoder) controlled by digital input code, a corresponding voltage is selected from each node of the voltage divider as the analog output.

[0040] In the embodiments of this application, a current-steering digital-to-analog converter (DAC) is a circuit that achieves digital-to-analog conversion by controlling a constant current source array precisely controlled by digital code to direct current to different output paths.

[0041] In this application, a multi-bit adder / subtractor is a digital logic circuit capable of performing addition or subtraction operations on two multi-bit wide binary numbers, and the control signal can determine whether an addition or subtraction operation is currently being performed.

[0042] Linear voltage regulators can convert unstable input power sources (such as those from batteries, solar panels, energy harvesters, etc.) into stable output power. In addition, when there is noise in the input power supply, linear voltage regulators can also suppress the noise of the input power supply and produce a low-noise output power supply.

[0043] Because linear voltage regulators can provide stable and low-noise power supply voltages, they play an important role in applications requiring low noise and fast response.

[0044] With the rapid development of controller technology, high-performance controllers are becoming more and more precise and the signal speed is getting faster and faster, which puts forward higher requirements for the performance of linear voltage regulator circuits.

[0045] In related technologies, the output voltage is directly fed back to the error amplification module to adjust for changes in the output voltage.

[0046] Figure 1 A schematic diagram of a linear voltage regulator circuit in the related art is shown, such as... Figure 1 As shown, the linear voltage regulator circuit 100 includes a reference voltage generation module 110, an error amplification module 120, and a voltage generation module 130.

[0047] The reference voltage generation module 110 can be a bandgap reference circuit. The input voltage Vin provided by the input power supply Battery is input to the reference voltage generation module 110, and the reference voltage generation module 110 can generate a reference voltage Vref with extremely low process / voltage / temperature variation coefficient.

[0048] The error amplification module 120 may include an error amplifier, the negative input of which is used to receive a reference voltage Vref, and the output of which is connected to the voltage generation module 130.

[0049] The voltage generation module 130 can generate an output voltage Vout to provide a stable power supply for the load, and generate a load current ILoad when the load is working.

[0050] The voltage generation module 130 includes a PMOS (Positive channel Metal Oxide Semiconductor) power transistor, a load, and a capacitor.

[0051] The gate of the PMOS power transistor is connected to the output of the error amplifier module 120. The voltage generation module 130 feeds back the generated output voltage Vout to the positive input of the error amplifier, thereby stabilizing the value of the output voltage Vout to the reference voltage Vref through negative feedback.

[0052] With the development of controller technology and the increase in signal speed, the requirements for stable and low-noise power supplies are becoming increasingly stringent, placing higher performance demands on linear voltage regulator circuits.

[0053] Figure 2 It shows Figure 1 A schematic diagram of the load regulation rate of a linear voltage regulator circuit; Figure 3 It shows Figure 1 A schematic diagram of the linear regulation rate of a medium-linear voltage regulator circuit; Figure 4 It shows Figure 1 A schematic diagram of the temperature regulation rate of a linear voltage regulator circuit. Although... Figure 1 The linear voltage regulator circuit shown can achieve a stable output, but in actual use, such as... Figure 2-4 As shown, if the load current ILoad, input voltage Vin, or ambient temperature Temp changes (e.g., the load current I...), load Deviation from current reference value TYP I load When the input voltage Vin deviates from the voltage reference value TYP Vin and the ambient temperature Temp deviates from the temperature reference value TYPTemp, the output voltage Vout will fluctuate and deviate from the reference voltage Vref.

[0054] Due to the physical characteristics of the devices, such as the presence of fluctuations, the compensation capability of the error amplifier is limited. The size and characteristics of the error amplifier, as well as its gain and bandwidth, all affect the accuracy and speed of compensation, and these are all constrained by semiconductor technology and physical laws. Moreover, the compensation capability of the error amplifier decreases at higher signal frequencies. In addition, the relevant parameters of some components in the linear voltage regulator circuit will also change due to temperature variations.

[0055] In other words, there is an upper limit to the optimization of the response speed and accuracy of linear voltage regulator circuits in related technologies, making it difficult to further improve the performance of linear voltage regulator circuits.

[0056] To address the aforementioned problems, the inventors have proposed a linear voltage regulator circuit and a voltage regulation control method as provided in this application. The linear voltage regulator circuit includes: a voltage adjustment module, an error amplification module, and a voltage generation module. The voltage adjustment module determines a second reference voltage based on set parameters and a received first reference voltage. The initial value of the set parameters is determined by a preset reference value received by the voltage adjustment module. The first input terminal of the error amplification module receives the second reference voltage. The output terminal of the error amplification module outputs a control voltage. The voltage generation module generates an output voltage based on the control voltage. The second input terminal of the error amplification module receives the output voltage. The error amplification module also generates a control voltage based on the second reference voltage and the output voltage. The voltage adjustment module further generates a first clock signal based on the output voltage, a received initial clock signal, and a first delay parameter. The voltage adjustment module also generates a first clock signal based on the second reference voltage and the received initial clock signal and a first delay parameter. An initial clock signal, output voltage, and a second delay parameter generate a second clock signal; wherein, the first delay parameter is greater than the second delay parameter; the voltage adjustment module is also used to determine the phase deviation state of the first clock signal and the second clock signal; the voltage adjustment module is also used to set the value of the setting parameter to the received preset reference value, and adjust the value of the first delay parameter according to the phase deviation state, until the phase deviation value between the first clock signal and the second clock signal is equal to the preset phase value, and then lock the value of the first delay parameter to the target delay value; wherein, when the value of the setting parameter is the preset reference value and the phase deviation value is the preset phase value, the corresponding value of the first delay parameter is the target delay value; the voltage adjustment module is also used to adjust the magnitude of the setting parameter according to the phase deviation state if the value of the first delay parameter is locked to the target delay value, and the phase deviation value is not equal to the preset phase value. On the one hand, the change in output voltage is directly fed back to the second input terminal of the error amplification module; on the other hand, the change in output voltage is also fed back to the first input terminal of the error amplification module through the adjustment of the second reference voltage. By adopting a dual feedback path, the output voltage change can be responded to quickly, thereby significantly optimizing the performance of the linear voltage regulator circuit.

[0057] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0058] Please see Figure 5 , Figure 5 A schematic diagram of a linear voltage regulator circuit provided in an embodiment of this application is shown, as follows: Figure 5 As shown, the linear voltage regulator circuit 200 provided in this application embodiment includes: a voltage adjustment module 210, an error amplification module 220, and a voltage generation module 230.

[0059] In embodiments of this application, the voltage adjustment module 210 is used to receive a first reference voltage Vref1, and the voltage adjustment module 210 is used to determine a second reference voltage Vref2 based on the setting parameters and the received first reference voltage Vref1. The voltage adjustment module 210 is also used to receive a preset reference value and determine the initial value of the setting parameters based on the preset reference value.

[0060] The first input terminal of the error amplifier module 220 is used to receive the second reference voltage Vref2; the output terminal of the error amplifier module 220 is used to output the control voltage.

[0061] The voltage generation module 230 is used to receive the control voltage and generate the output voltage Vout based on the control voltage.

[0062] In the embodiments of this application, the control voltage output by the error amplification module 220 will affect the magnitude of the final generated output voltage Vout.

[0063] The first input terminal of the error amplifier module 220 is used to receive the second reference voltage Vref2, and the second input terminal of the error amplifier module 220 is used to receive the output voltage Vout. The error amplifier module 220 is used to generate a control voltage based on the second reference voltage Vref2 and the output voltage Vout. In other words, the control voltage is affected by both the second reference voltage Vref2 and the output voltage Vout.

[0064] In embodiments of this application, the voltage adjustment module 210 is further configured to receive the output voltage Vout, generate a first clock signal based on the output voltage Vout, the received initial clock signal Clock, and a first delay parameter; and generate a second clock signal based on the initial clock signal Clock, the output voltage Vout, and a second delay parameter.

[0065] The first delay parameter is greater than the second delay parameter; the voltage adjustment module 210 is also used to determine the phase deviation state of the first clock signal and the second clock signal.

[0066] The voltage adjustment module 210 is also used to adjust the magnitude of the first delay parameter according to the phase deviation state in the first stage; and to adjust the magnitude of the setting parameter according to the phase deviation state in the second stage.

[0067] In the embodiments of this application, the first clock signal is a clock signal obtained by generating a phase delay based on the output voltage Vout and the first delay parameter from the initial clock signal; the second clock signal is a clock signal obtained by generating a phase delay based on the output voltage Vout and the second delay parameter from the initial clock signal Clock.

[0068] The delay amplitude of the first clock signal is affected by both the output voltage Vout and the first delay parameter; the delay amplitude of the second clock signal is affected by both the output voltage Vout and the second delay parameter. Specifically, the larger the output voltage Vout, the smaller the resulting delay amplitude; the larger the delay parameter, the larger the resulting delay amplitude. With the same output voltage Vout, the delay amplitude of the first clock signal is greater than that of the second clock signal.

[0069] Due to the regulation of the error amplification module 220, the value of the output voltage Vout will eventually stabilize at the value of the reference voltage (i.e., the target control voltage) input to the first input terminal of the error amplification module 220. In other words, when the output voltage Vout is stable (i.e., the output voltage Vout = the target control voltage), the phase of the generated first clock signal and the phase of the second clock signal are also stable. At this time, the phase deviation value between the first clock signal and the second clock signal (i.e., the deviation value between the phase of the first clock signal and the phase of the second clock signal) is stable.

[0070] When the output voltage Vout changes, the delay amplitude of the first clock signal changes, and the delay amplitude of the second clock signal also changes. However, since the first delay parameter is greater than the second delay parameter, when the output voltage Vout changes, the change in the delay amplitude of the first clock signal (the amount of increase or decrease) will be greater than the change in the delay amplitude of the second clock signal.

[0071] As the output voltage Vout increases, the delay amplitude of the clock signal decreases. Since the first delay parameter is greater than the second delay parameter, the reduction in the delay amplitude of the first clock signal is greater than the reduction in the delay amplitude of the second clock signal.

[0072] When the output voltage Vout decreases, the delay amplitude of the clock signal increases. Since the first delay parameter is greater than the second delay parameter, the increase in the delay amplitude of the first clock signal will be greater than the increase in the delay amplitude of the second clock signal.

[0073] Assuming the output voltage Vout is stable, the phase of the first clock signal is the first phase 1, and the phase of the second clock signal is the second phase 1. At this time, the phase deviation between the first clock signal and the second clock signal is 1 = first phase 1 - second phase 1.

[0074] If the output voltage Vout increases, the delay amplitude of the clock signal will decrease. Assuming that the phase of the first clock signal is the first phase 2 and the phase of the second clock signal is the second phase 2, if the output voltage Vout increases, then the first phase 2 is less than the first phase 1, and the second phase 2 is less than the second phase 1. Since the first delay parameter is greater than the second delay parameter, the reduction in the delay amplitude of the first clock signal will be greater than the reduction in the delay amplitude of the second clock signal, that is, (first phase 1 - first phase 2) > (second phase 1 - second phase 2).

[0075] Then the phase deviation value 2 (first phase 2 - second phase 2) will be less than the phase deviation value 1 (first phase 1 - second phase 1). In other words, when the output voltage Vout increases, the phase deviation value between the first clock signal and the second clock signal will decrease.

[0076] If the output voltage Vout decreases, the delay amplitude of the clock signal will increase. Assuming the phase of the first clock signal is the first phase 3 and the phase of the second clock signal is the second phase 3, if the output voltage Vout increases, then the first phase 3 is greater than the first phase 1, and the second phase 3 is greater than the second phase 1. Since the first delay parameter is greater than the second delay parameter, the increase in the delay amplitude of the first clock signal will be greater than the increase in the delay amplitude of the second clock signal, that is, (first phase 3 - first phase 1) > (second phase 3 - second phase 1).

[0077] Then the phase deviation value 3 (first phase 3 - second phase 3) will be greater than the phase deviation value 1 (first phase 1 - second phase 1). In other words, as the output voltage Vout decreases, the phase deviation value between the first clock signal and the second clock signal will increase.

[0078] That is, if the output voltage Vout is equal to the target control voltage, then the phase deviation between the first clock signal and the second clock signal is equal to the phase deviation 1; if the output voltage Vout is greater than the target control voltage, then the phase deviation between the first clock signal and the second clock signal is less than the phase deviation 1; if the output voltage Vout is less than the target control voltage, then the phase deviation between the first clock signal and the second clock signal is greater than the phase deviation 1.

[0079] To facilitate testing, the linear voltage regulator circuit provided in this application adjusts the magnitude of the first delay parameter according to the phase deviation state in the first stage, so that when the output voltage Vout is stable, the phase deviation value between the first clock signal and the second clock signal is adjusted to a preset phase value.

[0080] For example, if the phase deviation between the first clock signal and the second clock signal is determined to be less than a preset phase value based on the phase deviation status, the first delay parameter will be increased; if the phase deviation between the first clock signal and the second clock signal is determined to be less than a preset phase value based on the phase deviation status, the first delay parameter will be decreased; if the phase deviation between the first clock signal and the second clock signal is determined to be equal to a preset phase value based on the phase deviation status, the first delay parameter at this time will be used as the target delay value for subsequent control.

[0081] The preset phase value can be set according to actual usage needs. It can be understood that the larger the preset phase value, the greater the change in the phase deviation between the first clock signal and the second clock signal when the output voltage Vout fluctuates, and the easier it is to detect.

[0082] The preset phase value can also be set according to the circuit devices used. For example, if a trigger is used to detect the phase deviation between the first clock signal and the second clock signal, setting the preset phase value to an integer multiple of 180 degrees can make the circuit design more convenient.

[0083] The linear voltage regulator circuit 200 provided in this application adjusts the magnitude of the first delay parameter to the target delay value mentioned above. At this time, if the output voltage is equal to the target control voltage, the phase deviation between the first clock signal and the second clock signal is equal to the preset deviation value.

[0084] Therefore, when the value of the first delay parameter is locked to the target delay value, the relationship between the output voltage Vout and the target control voltage can be determined by detecting the phase deviation state. There are three possible relationships between the output voltage Vout and the target control voltage: the first is that the output voltage Vout equals the target control voltage, in which case the phase deviation value equals the preset phase value; the second is that the output voltage Vout is greater than the target control voltage, in which case the phase deviation value is less than the preset phase value; and the third is that the output voltage Vout is less than the target control voltage, in which case the phase deviation value is less than the preset phase value.

[0085] If the output voltage Vout is determined to be equal to the target control voltage based on the phase deviation status, the setting parameters are not adjusted, meaning the value of the second reference voltage Vref2 remains unchanged. If the output voltage Vout is determined to be greater than the target control voltage based on the phase deviation status, the value of the second reference voltage Vref2 is reduced by adjusting the setting parameters, and the value of the generated control voltage is then adjusted to reduce the magnitude of the output voltage Vout. If the output voltage Vout is determined to be less than the target control voltage based on the phase deviation status, the value of the second reference voltage Vref2 is reduced by adjusting the setting parameters, and the value of the generated control voltage is then adjusted to reduce the magnitude of the output voltage Vout.

[0086] In the embodiments of this application, on the one hand, the output voltage Vout is directly input to the second input terminal of the error amplification module 120 to form negative feedback. When the output voltage Vout changes, the control voltage is adjusted through negative feedback. On the other hand, the setting parameters are adjusted according to the change of the output voltage Vout to adjust the magnitude of the second reference voltage Vref2, thereby adjusting the control voltage. Thus, through the dual feedback path, the output voltage Vout can be responded to quickly when it changes.

[0087] In the embodiments of this application, the voltage adjustment module 210 can be implemented in various ways, such as by analog circuits, digital circuits, controllers, etc., or by one or more combinations of analog circuits, digital circuits, and controllers. The specific implementation can be set according to the needs of the application scenario. This application does not limit this, and will explain it in detail below.

[0088] Please see Figure 6 , Figure 6 This paper shows a schematic diagram of the structure of a voltage adjustment module provided in an embodiment of this application, as shown below. Figure 6 As shown, the voltage adjustment module 210 includes: a clock generation unit 211, a deviation confirmation unit 212, and a voltage adjustment unit 213.

[0089] In the embodiments of this application, the clock generation unit 211 is used to generate a first clock signal Clock1 based on the received initial clock signal Clock and output voltage Vout, and to generate a second clock signal Clock2 based on the output voltage Vout, the initial clock signal Clock and a first delay parameter.

[0090] The first delay parameter is greater than the second delay parameter, so that when the output voltage Vout increases, the reduction in the delay amplitude of the first clock signal Clock1 is greater than the reduction in the delay amplitude of the second clock signal Clock2.

[0091] In some implementations, the clock generation unit 211 can be implemented using an adjustable delay chain, which can delay the input signal for a certain period of time before outputting it. The delay time is adjusted by an external control voltage. The adjustable delay chain can be implemented using analog circuits (e.g., VCDL), digital circuits, or a combination thereof, such as multiple inverter chains, multi-stage differential buffers / amplifiers, or combinations with different loads. The specific implementation can be set according to the needs of the application scenario, and this application does not limit it.

[0092] Please see Figure 7 , Figure 7 This paper illustrates a schematic diagram of the structure of a clock generation unit provided in an embodiment of this application, as shown below. Figure 7 As shown, the clock generation unit includes: a first delay subunit 2111 and a second delay subunit 2112.

[0093] The first delay subunit 2111 is used to delay the initial clock signal Clock according to the first delay parameter to obtain the first clock signal Clock1.

[0094] The second delay subunit 2112 is used to delay the initial clock signal Clock according to the second delay parameter to obtain the second clock signal Clock2.

[0095] In embodiments of this application, the second delay subunit 2112 can be set as the intrinsic delay of the first delay subunit 2111, that is, the value of the second delay parameter is 0. The change in intrinsic delay of the second delay subunit 2112 due to voltage changes is much lower than the change in the first delay subunit 2111.

[0096] Therefore, it can be considered that when the first delay parameter remains unchanged, the change in the delay amplitude of the signal through the first delay subunit 2111 is much greater than the change in the delay amplitude through the second delay subunit 2112 when the output voltage Vout changes.

[0097] In some implementations, the deviation confirmation unit 212 is used to determine a detection value based on a first clock signal and a second clock signal, and the detection value is used to determine the phase deviation state.

[0098] The phase deviation state includes three states: the first state, the second state, and the third state. In the first state, the phase difference between the first clock signal and the second clock signal is less than the preset phase value, and the output voltage Vout is greater than the target control voltage. In the second state, the phase difference between the first clock signal and the second clock signal is equal to the preset phase value, and the output voltage Vout is equal to the target control voltage. In the third state, the phase difference between the first clock signal and the second clock signal is greater than the preset phase value, and the output voltage Vout is less than the target control voltage.

[0099] In some implementations, the deviation detection unit 212 may include a comparator and a counter to determine the phase deviation value between the first clock signal and the second clock signal by confirming the time difference between the first clock signal and the second clock signal passing through the zero point.

[0100] In other embodiments, the deviation detection unit 212 may also use a dedicated controller to determine the phase deviation between the first clock signal and the second clock signal.

[0101] In some other implementations, the deviation detection unit 212 may be implemented using a D flip-flop. Figure 8This paper shows a schematic diagram of the structure of a deviation confirmation unit 212 provided in an embodiment of this application, as shown below. Figure 8 As shown, the deviation confirmation unit 212 includes: a first D flip-flop DFF0 and a second D flip-flop DFF1.

[0102] Wherein, the data input terminal D0 of the first D flip-flop DFF0 is used to receive the second clock signal Clock2; the clock port CK0 of the first D flip-flop DFF0 is used to receive the first clock signal Clock1; the first D flip-flop is used to determine the first detection value according to the first clock signal Clock1 and the second clock signal Clock2, and is used to output the first detection value PD0 through the data output port Q0 of the first D flip-flop.

[0103] Specifically, the data input terminal D1 of the second D flip-flop DFF1 is used to receive the first clock signal Clock1; the clock port CK1 of the second D flip-flop DFF1 is used to receive the second clock signal Clock2; the second D flip-flop DFF0 is used to determine the second detection value PD1 based on the first clock signal Clock1 and the second clock signal Clock2, and is used to output the second detection value PD1 through the data output port Q1 of the second D flip-flop DFF1.

[0104] In some implementations, the set port SET0 of the first D flip-flop DFF0 is used to receive a reset signal, and the reset port of the first D flip-flop DFF0 is used to connect to a low level.

[0105] In some implementations, the reset port RST1 of the second D flip-flop DFF1 is used to receive the reset signal RST; the set port of the second D flip-flop DFF1 is used to connect to a low level.

[0106] In the embodiments of this application, the reset signal RST is valid when it is at the first level, and the reset port and set port of the D flip-flop are both valid when they are at the first level.

[0107] For example, if the first level is high, then when the system is reset, the reset signal is high, and the data port D0 of the first D flip-flop DFF0 outputs the first detection value PD0=1, and the second D flip-flop DFF1 outputs the second detection value PD1=0.

[0108] In the embodiments of this application, the preset phase value is 180°. It is understood that in other embodiments, the preset phase value can also be set to other values, such as 360°.

[0109] When the phase deviation between the first clock signal Clock1 and the second clock signal Clock2 is less than 180°, the data port D0 of the first D flip-flop DFF0 outputs the first detection value PD0=1, and the second D flip-flop DFF1 outputs the second detection value PD1=0. Then the phase deviation state is the first state.

[0110] When the phase deviation between the first clock signal Clock1 and the second clock signal Clock2 is 180°, the data port D0 of the first D flip-flop DFF0 outputs the first detection value PD0=0, and the second D flip-flop DFF1 outputs the second detection value PD1=0. Then the phase deviation state is the second state.

[0111] When the phase deviation between the first clock signal clock1 and the second clock signal clock2 is greater than 180°, the data port D0 of the first D flip-flop DFF0 outputs the first detection value PD0=0, and the second D flip-flop DFF1 outputs the second detection value PD1=1. Then the phase deviation state is the third state.

[0112] In the embodiments of this application, the voltage adjustment unit 213 is used to receive a first reference voltage Vref1 and a preset reference value. The preset reference value serves as the initial value for the setting parameters.

[0113] In the embodiments of this application, the voltage adjustment unit 213 can determine the second reference voltage Vref2 according to the setting parameters and the received first reference voltage Vref1. When the value of the setting parameters is a preset reference value, the value of the determined second reference voltage Vref2 is equal to the target control voltage. That is, the control target of the linear voltage regulator circuit 200 is to control the output voltage Vout at the target control voltage.

[0114] Users can determine the value of the preset reference value according to the actual needs of the scenario and the magnitude of the target control voltage, and input it into the linear voltage regulator circuit 200 for regulation.

[0115] In some implementations, the voltage adjustment unit 213 may include a digital-to-analog converter (DAC) to which setting parameters and a first reference voltage Vref1 are input to obtain a second reference voltage Vref2.

[0116] In other embodiments, the voltage adjustment unit 213 may include a controller and a voltage generation unit (such as a digital-to-analog converter or a resistor ladder network). The setting parameters and the first reference voltage Vref1 are input into the controller, which determines the digital signal of the specific second reference voltage Vref2 and transmits the digital signal of the second reference voltage Vref2 to the voltage generation unit to obtain the second reference voltage Vref2.

[0117] In the embodiments of this application, the voltage adjustment unit 213 is used to adjust the magnitude of the first delay parameter according to the phase deviation state in the first stage so that when the output voltage Vout is stable (the value of the parameter is set to a preset reference value, and the output voltage Vout = target control voltage), the phase deviation value between the first clock signal Clock1 and the second clock signal Clock2 is adjusted to a preset phase value, and the magnitude of the first delay parameter is the target delay value.

[0118] Specifically, based on the phase deviation state, it can be determined whether the phase deviation value between the first clock signal and the second clock signal is equal to, greater than, or less than the preset phase value.

[0119] In the embodiments of this application, the voltage adjustment module 210 can, in the second stage, set the first delay parameter to the target delay value and adjust the setting parameter according to the phase deviation state so that when the output voltage Vout fluctuates, the relationship between the output voltage Vout and the target control voltage can be determined by the phase deviation state.

[0120] Please see Figure 9 , Figure 9 A schematic diagram of the structure of a voltage adjustment unit provided in an embodiment of this application is shown, as follows: Figure 9 As shown, the voltage adjustment unit 213 includes a logic subunit LOGIC and a digital-to-analog converter DAC.

[0121] The logic subunit LOGIC is used to determine the phase deviation state based on the second detection value PD1 and the first detection value PD0.

[0122] The logic subunit LOGIC is also used to adjust the value of the first delay parameter DLY_CODE according to the phase deviation state; the first output of the logic subunit LOGIC is used to output the adjusted first delay parameter DLY_CODE.

[0123] In some implementations, the first delay subunit 2111 is connected to the first output terminal of the logic subunit LOGIC, so that the first clock subunit 2111 delays the initial clock signal Clock according to the first delay parameter DLY_CODE to obtain the first clock signal Clock1.

[0124] It is understandable that when the phase deviation state is determined to be the second state, the phase difference between the first clock signal Clock1 and the second clock signal Clock2 is equal to the preset phase value. At this time, the value of the first delay parameter DLY_CODE is equal to the target delay value and participates in the control of subsequent stages.

[0125] The logic subunit LOGIC is also used in the second stage to adjust the value of the setting parameter CODE_ADJ according to the phase deviation state; the second output terminal of the logic subunit LOGIC is used to output the adjusted setting parameter CODE_ADJ. The initial value of the setting parameter CODE_ADJ is determined by the preset reference value CODE received by the logic subunit LOGIC; that is, the initial value of the setting parameter CODE_ADJ = the preset reference value CODE.

[0126] The first input terminal v1 of the digital-to-analog converter (DAC) is used to receive the first reference voltage Vref1. The second input terminal data of the DAC is connected to the second output terminal of the logic subunit LOGIC. The DAC is used to determine the second reference voltage Vref2 based on the first reference voltage Vref1 and the setting parameter CODE_ADJ. The output terminal v3 of the DAC is used to output the second reference voltage Vref2.

[0127] In the embodiments of this application, when the linear voltage regulator circuit 200 is powered normally, the initial value of the setting parameter CODE_ADJ is equal to the preset reference value, and the value of the output voltage Vout is equal to the target control voltage.

[0128] The output voltage Vout powers the first delay subunit 2111 and the second delay subunit 2112. The initial clock signal Clock is input to the first delay subunit 2111 and the second delay subunit 2112.

[0129] During initialization, the phases of the first clock signal Clock1 and the second clock signal Clock2 need to be offset by a preset phase value (e.g., 180°).

[0130] Please refer to Figure 10 , Figure 10 This application provides an embodiment of a flowchart illustrating the adjustment process of a logic subunit, as shown below. Figure 10 As shown, when the reset signal RST is high (i.e., RST=1), the first detection value PD0 is set to high (i.e., PD0=1), the second detection value PD1 is reset to low (i.e., PD1=0), and the initial value of the first delay parameter DLY_CODE is 1 (it can also be other values, which are not restricted here).

[0131] When the reset signal RST changes from high to low, the first stage begins.

[0132] In the first stage, the logic subunit LOGIC detects PD0=1 and PD1=0, and determines the phase deviation state as the first state, that is, the phase deviation value of the first clock signal Clock1 and the second clock signal Clock2 is less than 180°. Then, the value of the first delay parameter DLY_CODE is adjusted, that is, the first delay parameter DLY_CODE of the current detection cycle = the first delay parameter DLY_CODE of the previous detection cycle + 1.

[0133] The phase deviation state is checked repeatedly until the first detection value PD0=0 and the second detection value PD1=0. That is, the logic sub-unit LOGIC determines that the phase deviation state is the second state, that is, the phase deviation value of the first clock signal Clock1 and the second clock signal Clock2 is equal to 180°. At this time, the lock is successful. The current value of the first delay parameter DLY_CODE is used as the target delay value lock_code. The first stage is completed, and the output voltage of the linear regulator circuit 200 can normally turn on the relevant load.

[0134] Please refer to Figure 11 , Figure 11 This application provides an embodiment of an adjustment flowchart for another logic subunit, as shown below. Figure 11 As shown, upon transitioning from the first stage to the second stage, the linear regulator circuit 200 operates normally. The output voltage Vout is obtained based on the first reference voltage Vref1 and the setting parameter CODE_ADJ. At this time, the initial value of the setting parameter CODE_ADJ is the preset reference value CODE, and the output voltage Vout = the target control voltage. The phase deviation state is the second state, that is, the phase deviation between the first delay signal Clock1 and the second delay signal Clock is 180 degrees. At this time, the first detection value PD0 = the second detection value PD1 = 0.

[0135] If the output voltage Vout decreases due to changes in load current, input voltage, or temperature at the location of the linear regulator circuit 200 (i.e., characteristic changes), then the phase deviation between the first delay signal Clock1 and the second delay signal Clock will be greater than 180 degrees. In this case, the second detection value PD1 = 1. The logic subunit LOGIC makes the first adjustment to the setting parameters, that is, the setting parameter CODE_ADJ of the current detection cycle is equal to the setting parameter (i.e., CODE) of the previous detection cycle + 1. As a result, the second reference voltage Vref2 increases and the output voltage Vout increases.

[0136] After the first adjustment, if the phase deviation between the first delay signal Clock1 and the second delay signal Clock is still greater than 180 degrees, i.e., the second detection value PD1=1, the logic subunit LOGIC will adjust the setting parameters for the second time. That is, the setting parameter CODE_ADJ of the current detection cycle is equal to the setting parameter of the previous detection cycle (i.e., CODE+1)+1. As a result, the second reference voltage Vref2 increases, and the output voltage Vout increases.

[0137] After the second adjustment, the phase deviation between the first delayed signal Clock1 and the second delayed signal Clock is detected to be 180 degrees, that is, the second detection value PD1 = the first detection value PD0 = 0. The linear regulator circuit 200 continues to work stably and continues to determine whether the output voltage Vout deviates from the target control voltage by monitoring the phase deviation status.

[0138] Please refer to Figure 12 , Figure 12 This application provides an embodiment of a flowchart illustrating the adjustment process of another logic subunit, such as... Figure 12 As shown, upon transitioning from the first stage to the second stage, the linear regulator circuit 200 operates normally. The output voltage Vout is obtained based on the first reference voltage Vref1 and the setting parameter CODE_ADJ. At this time, the initial value of the setting parameter CODE_ADJ is the preset reference value CODE, and the output voltage Vout = the target control voltage. The phase deviation state is the second state, that is, the phase deviation between the first delay signal Clock1 and the second delay signal Clock is 180 degrees. At this time, the first detection value PD0 = the second detection value PD1 = 0.

[0139] If the output voltage Vout rises due to changes in load current, input voltage, or temperature at the location of the linear regulator circuit 200 (i.e., characteristic changes), then the phase deviation between the first delay signal Clock1 and the second delay signal Clock will be less than 180 degrees. In this case, the second detection value PD1 = 0. The logic subunit LOGIC makes the first adjustment to the setting parameters, that is, the setting parameter CODE_ADJ of the current detection cycle is equal to the setting parameter (i.e., CODE) of the previous detection cycle - 1. As a result, the second reference voltage Vref2 decreases and the output voltage Vout decreases.

[0140] After the first adjustment, the phase deviation between the first delayed signal Clock1 and the second delayed signal Clock is detected to be 180 degrees, that is, the second detection value PD1 = the first detection value PD0 = 0. The linear regulator circuit 200 continues to work stably and continues to determine whether the output voltage Vout deviates from the target control voltage by monitoring the phase deviation status.

[0141] In some implementations, the logic subunit LOGIC can be a code-value logic state machine, a finite state machine, a controller, a multi-bit adder / subtractor, etc., and this application does not impose any restrictions on it.

[0142] The first input terminal v1 of the digital-to-analog converter (DAC) is used to receive the first reference voltage Vref1, and the second input terminal data of the DAC is used to receive the updated setting parameter CODE_ADJ. The DAC is used to determine the second reference voltage Vref2 based on the first reference voltage Vref1 and the updated setting parameter CODE_ADJ, and the output terminal v2 of the DAC is used to output the second reference voltage Vref2.

[0143] In the embodiments of this application, the digital-to-analog converter (DAC) can be an R-2R DAC, a resistor string DAC, a current-driven DAC, etc., and there are no limitations herein.

[0144] Please see Figure 13 , Figure 13 This paper illustrates a structural schematic diagram of a voltage generation module provided in an embodiment of this application, as shown below. Figure 13 As shown, the voltage generation module 230 includes a switching unit 231 and a load unit 232.

[0145] The control terminal of the switching unit 231 is used to receive the control voltage, the first terminal of the switching unit 231 is used to receive the input voltage Vin, and the second terminal of the switching unit 231 is connected to the connection terminal of the load unit 232; the connection terminal of the load unit 232 is used to connect to the voltage adjustment module 210.

[0146] The switching unit 231 may include a power transistor, which may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), JFET (Junction Field-Effect Transistor), BJT (Bipolar Junction Transistor), PMOS (Positive channel Metal Oxide Semiconductor), or other similar devices.

[0147] The load unit 232 may include resistors, capacitors and other devices to perform voltage division and signal filtering, thereby generating a low-noise output voltage Vout, thus providing a stable power supply for the load module.

[0148] Please see Figure 14 , Figure 14This paper illustrates a schematic diagram of another voltage generation module provided in an embodiment of this application, as shown below. Figure 14 As shown, the switching unit 231 of the voltage generation module 230 includes a PMOS transistor PG. The gate of the PMOS transistor PG is used to receive the control voltage VPG, and the source of the PMOS transistor PG is used to receive the input voltage Vin.

[0149] Load unit 232 includes resistor Rload, resistor R load One end generates the output voltage Vout, and the resistor R load One end of the resistor is connected to the drain of the PMOS transistor PG and to the voltage adjustment module 210, feeding back the output voltage Vout to the voltage adjustment module 210; resistor R load One end is also used to connect to the load module Iload, for use in supplying power to the load module I. load A stable output voltage Vout is output. Resistor R load The other end is used for grounding.

[0150] Please see Figure 15 , Figure 15 A schematic flowchart of a voltage regulation control method provided in an embodiment of this application is shown. Figure 15 As shown, the voltage regulation control method provided in this application embodiment can be applied to the above-mentioned linear voltage regulation control circuit 200. Specifically, the voltage regulation control method includes steps S310 to S370.

[0151] Step S310: Determine the second reference voltage based on the received first reference voltage and the setting parameters; wherein, the initial value of the setting parameters is determined by the received preset reference value.

[0152] Step S320: Generate a control voltage based on the second reference voltage and the output voltage.

[0153] Step S330: Generate the output voltage based on the control voltage.

[0154] Step S340: Generate a first clock signal based on the received initial clock signal, output voltage, and first delay parameter.

[0155] Step S350: Generate a second clock signal based on the initial clock signal, the output voltage, and the second delay parameter; wherein the first delay parameter is greater than the second delay parameter.

[0156] Step S360: Determine the phase deviation state of the first clock signal and the second clock signal.

[0157] Step S370: Adjust the value of the first delay parameter according to the phase deviation state until the phase deviation value between the first clock signal and the second clock signal is equal to the preset phase value, and then lock the value of the first delay parameter to the target delay value.

[0158] Specifically, when the value of the set parameter is a preset reference value and the value of the phase deviation is a preset phase value, the value of the corresponding first delay parameter is the target delay value.

[0159] In the first stage, before powering the load, the magnitude of the first delay parameter is adjusted to the target delay parameter by using the phase deviation state. That is, the magnitude of the first delay parameter corresponding to the second phase deviation state is determined as the target delay parameter.

[0160] In some implementations, the step of adjusting the value of the first delay parameter according to the phase deviation state includes the following steps.

[0161] (1) If the phase deviation state is the first state, the magnitude of the first delay parameter is increased by the first preset unit.

[0162] Understandably, the size of the first preset unit can be set according to the accuracy requirements and hardware conditions; the smaller the value of the first preset unit, the higher the accuracy.

[0163] (2) If the phase deviation state is the second state, then the value of the first delay parameter is locked as the target delay value.

[0164] (3) If the phase deviation state is the third state, the magnitude of the first delay parameter is reduced by the first preset unit; in the third state, the phase difference between the first clock signal and the second clock signal is greater than the preset phase value.

[0165] Step S380: If the value of the first delay parameter is locked to the target delay value, then when it is determined from the phase deviation state that the phase deviation value is not equal to the preset phase value, the size of the setting parameter is adjusted according to the phase deviation state.

[0166] In the second stage, the magnitude of the first delay parameter is locked to the target delay parameter. At this time, the load can be powered normally, and the output voltage can be adjusted during the operation of the load.

[0167] In some implementations, step S380, if the value of the first delay parameter is locked to the target delay value, then when it is determined from the phase deviation state that the phase deviation value is not equal to the preset phase value, the size of the setting parameter is adjusted according to the phase deviation state, including the following steps.

[0168] (1) If the phase deviation state is the first state, the size of the setting parameter is reduced by a second preset unit; in the first state, the phase difference between the first clock signal and the second clock signal is less than the preset phase value.

[0169] (2) If the phase deviation state is the third state, the size of the setting parameter is increased by the second preset unit; in the third state, the phase difference between the first clock signal and the second clock signal is greater than the preset phase value.

[0170] In some embodiments, the voltage regulation control method provided in this application further includes the steps of: if the value of the received reset signal is a first level, then setting the initial value of the first delay parameter to a preset delay value; and setting the initial value of the setting parameter to a preset reference value.

[0171] Specifically, when the reset signal value is at the first level, the phase deviation state is reset to the first state; in the first state, the phase difference between the first clock signal and the second clock signal is less than a preset phase value.

[0172] In some embodiments, the voltage regulation control method provided in this application further includes the step of: if the value of the reset signal changes from a first level to a second level, then the step of adjusting the value of the first delay parameter according to the phase deviation state is performed until the phase deviation value between the first clock signal and the second clock signal is determined to be equal to a preset phase value according to the phase deviation state. The first level is opposite to the second level.

[0173] Optionally, if the first level is high, then the second level is low.

[0174] Optionally, if the first level is low, then the second level is high.

[0175] In the embodiments of this application, the control voltage is affected by two factors: a second reference voltage and the output voltage. On the one hand, the generation of the control voltage is directly adjusted by the output voltage; on the other hand, the magnitude of the second reference voltage is adjusted according to the change in the output voltage, thereby adjusting the control voltage. Thus, through a dual feedback path, a rapid response can be made when the output voltage changes.

[0176] Please see Figure 16 , Figure 16 A schematic flowchart of another voltage regulation control method provided in an embodiment of this application is shown, as follows: Figure 16 As shown, the voltage regulation control method provided in this application embodiment includes steps S401 to S412.

[0177] Step S401: When the reset signal RST is high, set the value of the first delay parameter DLY_CODE to the initial delay value, set the value of the setting parameter to the preset reference value, set the value of the first detection value PD0 to 1, and reset the value of the second detection value PD1 to 0.

[0178] Understandably, the initial delay value can be set as needed, for example, it can be set to 1.

[0179] Step S402: Determine whether the reset signal RST is low.

[0180] If the reset signal RST is high, then return to step S401. If the reset signal RST changes from high level to low level, the first stage is entered, and step S403 is executed.

[0181] Step S403: Determine whether the first detection value PD0 is 0.

[0182] If the first detection value PD0≠0, it indicates that the phase deviation state is the first state, that is, the phase deviation value is greater than 180°, which means that the output voltage Vout is smaller, and then step S404 is executed.

[0183] If the first detection value PD0 = 0, then the phase deviation state is further determined by combining the second detection value PD1, and step S405 is executed.

[0184] Step S404: Increase the value of the first delay parameter DLY_CODE by a first preset unit, and return to step S403 to monitor the phase deviation status of the next detection cycle.

[0185] The value of the first preset unit can be set to 1, or it can be set according to actual needs; there are no restrictions here.

[0186] Step S405: Determine whether the second detection value PD1 is 0.

[0187] If the second detection value PD1≠0, it indicates that the phase deviation state is the third state, that is, the phase deviation value is less than 180°, which indicates that the output voltage Vout has increased, and then step S406 is executed.

[0188] If the second detection value PD1 = 0, it indicates that the phase deviation state is the second state, that is, the phase deviation value is equal to 180°, then step S407 is executed.

[0189] Step S406: Reduce the value of the first delay parameter DLY_CODE by a first preset unit, and return to step S403 to monitor the phase deviation status of the next detection cycle.

[0190] Step S407: Lock the value of the first delay parameter DLY_CODE to the target delay value lock_code, and proceed to the second stage. Here, the current value of the first delay parameter DLY_CODE is the target delay value lock_code.

[0191] Step S408: Determine whether the reset signal RST is high.

[0192] If the reset signal RST is high, then return to step S401. If the reset signal RST is still low, then proceed to step S409.

[0193] Step S409: Determine whether the second detection value PD1 is 1.

[0194] If the second detection value PD1 = 1, it indicates that the phase deviation state is the first state, that is, the phase deviation value is greater than 180°, which means that the output voltage Vout is smaller, and then step S410 is executed.

[0195] If the second detection value PD1≠1, then the phase deviation state is further determined by combining it with the first detection value PD0, and step S411 is executed.

[0196] Step S410: Increase the value of the setting parameter CODE_ADJ by a second preset unit, and return to step S409 to monitor the phase deviation status of the next detection cycle.

[0197] The value of the second preset unit can be set to 1, or it can be set according to actual needs; there are no restrictions here.

[0198] Step S411: Determine whether the first detection value PD0 is 1.

[0199] If the first detection value PD0 = 1, it indicates that the phase deviation state is the second state, that is, the phase deviation value is equal to 180°. Then, return to step S408 to continue monitoring the phase deviation state in the next detection cycle.

[0200] If the first detection value PD0≠1, it indicates that the phase deviation state is the third state, that is, the phase deviation value is less than 180°, which indicates that the output voltage Vout has increased, and then step S412 is executed.

[0201] Step S412: Decrease the value of the setting parameter CODE_ADJ by a second preset unit, and return to step S409 to monitor the phase deviation status of the next detection cycle.

[0202] In summary, the embodiments of this application provide a linear voltage regulator circuit and a voltage regulation control method. The linear voltage regulator circuit includes: a voltage adjustment module, an error amplification module, and a voltage generation module. The voltage adjustment module determines a second reference voltage based on set parameters and a received first reference voltage. The initial value of the set parameters is determined by a preset reference value received by the voltage adjustment module. The first input terminal of the error amplification module receives the second reference voltage. The output terminal of the error amplification module outputs a control voltage. The voltage generation module generates an output voltage based on the control voltage. The second input terminal of the error amplification module receives the output voltage. The error amplification module also generates a control voltage based on the second reference voltage and the output voltage. The voltage adjustment module also generates a first clock signal based on the output voltage, a received initial clock signal, and a first delay parameter. The voltage adjustment module also generates a first clock signal based on the initial clock signal and a received initial clock signal. A second clock signal is generated from a clock signal, an output voltage, and a second delay parameter; wherein, the first delay parameter is greater than the second delay parameter; the voltage adjustment module is also used to determine the phase deviation state of the first clock signal and the second clock signal; the voltage adjustment module is also used to set the value of the setting parameter to a received preset reference value, and adjust the value of the first delay parameter according to the phase deviation state, until the phase deviation value between the first clock signal and the second clock signal is equal to a preset phase value, at which point the value of the first delay parameter is locked to a target delay value; wherein, when the value of the setting parameter is a preset reference value and the phase deviation value is a preset phase value, the corresponding value of the first delay parameter is the target delay value; the voltage adjustment module is also used to adjust the magnitude of the setting parameter according to the phase deviation state if the value of the first delay parameter is locked to the target delay value, and the phase deviation value is not equal to the preset phase value. On one hand, the change in output voltage is directly fed back to the second input terminal of the error amplification module; on the other hand, the change in output voltage is also fed back to the first input terminal of the error amplification module through the adjustment of the second reference voltage. By adopting a dual feedback path, the output voltage change can be responded to quickly, thereby significantly optimizing the performance of the linear voltage regulator circuit.

[0203] In this embodiment, the modules / units included in the various devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0204] For example, for various devices or products applied to or integrated into a controller, each module / unit can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the controller, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices or products applied to or integrated into a controller module, each module / unit can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., controller, circuit module, etc.) or different components of the controller module, or at least some modules / units can be implemented using hardware methods such as circuits. The unit can be implemented using software programs that run on the processor integrated within the controller module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, all of their modules / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., controller, circuit module, etc.) or different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0205] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0206] In the several embodiments provided in this application, the coupling between modules can be electrical, mechanical, or other forms of coupling.

[0207] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0208] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A linear voltage regulator circuit, characterized in that, The circuit includes: a voltage adjustment module, an error amplification module, and a voltage generation module; The voltage adjustment module is used to determine the second reference voltage based on the set parameters and the received first reference voltage; The first input terminal of the error amplification module is used to receive the second reference voltage; the output terminal of the error amplification module is used to output the control voltage. The voltage generation module is used to generate the output voltage according to the control voltage; The second input terminal of the error amplification module is used to receive the output voltage; the error amplification module is also used to generate the control voltage based on the second reference voltage and the output voltage. The voltage adjustment module is further configured to generate a first clock signal based on the output voltage, the received initial clock signal, and a first delay parameter; the voltage adjustment module is further configured to generate a second clock signal based on the initial clock signal, the output voltage, and a second delay parameter; wherein the first delay parameter is greater than the second delay parameter; the voltage adjustment module is further configured to determine the phase deviation state between the first clock signal and the second clock signal; The voltage adjustment module is further configured to set the value of the setting parameter to a received preset reference value, and adjust the value of the first delay parameter according to the phase deviation state, until the phase deviation value between the first clock signal and the second clock signal is determined to be equal to a preset phase value according to the phase deviation state, and then lock the value of the first delay parameter to the target delay value; wherein, when the value of the setting parameter is the preset reference value and the value of the phase deviation is the preset phase value, the corresponding value of the first delay parameter is the target delay value; The voltage adjustment module is further configured to, if the value of the first delay parameter is locked to the target delay value, adjust the magnitude of the setting parameter according to the phase deviation state when it is determined that the phase deviation value is not equal to the preset phase value.

2. The linear voltage regulator circuit according to claim 1, characterized in that, The voltage adjustment module includes: A clock generation unit is configured to generate a first clock signal based on the received initial clock signal, the output voltage, and the first delay parameter; and to generate a second clock signal based on the initial clock signal, the output voltage, and the second delay parameter. A deviation confirmation unit is used to determine the detection value based on the first clock signal and the second clock signal; A voltage adjustment unit is configured to set the value of the setting parameter to a received preset reference value, and determine the phase deviation state based on the detected value; and adjust the value of the first delay parameter based on the phase deviation state until the phase deviation value between the first clock signal and the second clock signal is determined to be equal to a preset phase value based on the phase deviation state; wherein, when the value of the setting parameter is the preset reference value and the value of the phase deviation is the preset phase value, the corresponding value of the first delay parameter is the target delay value; The voltage adjustment unit is further configured to lock the value of the first delay parameter to the target delay value, and when it is determined from the phase deviation state that the phase deviation value is not equal to the preset phase value, adjust the size of the setting parameter according to the phase deviation value; The voltage adjustment unit is also used to determine a second reference voltage based on the first reference voltage and the setting parameters.

3. The linear voltage regulator circuit according to claim 2, characterized in that, The clock generation unit includes: a first delay subunit and a second delay subunit; The first delay subunit is used to delay the initial clock signal according to the first delay parameter to obtain the first clock signal; The second delay subunit is used to delay the initial clock signal according to the second delay parameter to obtain the second clock signal.

4. The linear voltage regulator circuit according to claim 3, characterized in that, The detection value includes a first detection value and a second detection value, and the deviation confirmation unit includes: a first D trigger and a second D trigger; The data input terminal of the first D flip-flop is used to receive the second clock signal; the clock port of the first D flip-flop is used to receive the first clock signal; the first D flip-flop is used to determine the first detection value based on the first clock signal and the second clock signal, and is used to output the first detection value through the data output port of the first D flip-flop. The data input terminal of the second D flip-flop is used to receive the first clock signal; the clock port of the second D flip-flop is used to receive the second clock signal; the second D flip-flop is used to determine the second detection value based on the first clock signal and the second clock signal, and is used to output the second detection value through the data output port of the second D flip-flop.

5. The linear voltage regulator circuit according to claim 4, characterized in that, The voltage adjustment unit includes: a logic subunit and a digital-to-analog converter; The logic subunit is used to determine the phase deviation state based on the first detection value and the second detection value; The logic subunit is further configured to set the value of the setting parameter to a preset reference value for reception, and adjust the value of the first delay parameter according to the phase deviation state until the phase deviation value between the first clock signal and the second clock signal is determined to be equal to the preset phase value according to the phase deviation state; the first output terminal of the logic subunit is configured to output the adjusted first delay parameter; The logic subunit is further configured to lock the value of the first delay parameter to the target delay value, and when it is determined from the phase deviation state that the phase deviation value is not equal to the preset phase value, adjust the size of the setting parameter according to the phase deviation state; the second output terminal of the logic subunit is configured to output the adjusted setting parameter. The first input terminal of the digital-to-analog converter is used to receive a first reference voltage, the second input terminal of the digital-to-analog converter is connected to the second output terminal of the logic subunit, the digital-to-analog converter is used to determine the second reference voltage according to the first reference voltage and the setting parameters, and the output terminal of the digital-to-analog converter is used to output the second reference voltage.

6. The linear voltage regulator circuit according to claim 5, characterized in that, The first delay subunit is connected to the first output terminal of the logic subunit; the first clock subunit is used to delay the initial clock signal according to the first delay parameter to obtain a first clock signal.

7. The linear voltage regulator circuit according to any one of claims 1 to 6, characterized in that, The voltage generation module includes: a switching unit and a load unit; The control terminal of the switching unit is used to receive the control voltage, the first terminal of the switching unit is used to receive the input voltage, and the second terminal of the switching unit is connected to the connection terminal of the load unit; the connection terminal of the load unit is used to connect to the voltage adjustment module.

8. A voltage regulation control method, characterized in that, The method, applied to the linear voltage regulator circuit of claim 1, comprises: The second reference voltage is determined based on the received first reference voltage and the set parameters; A control voltage is generated based on the second reference voltage and the output voltage; The output voltage is generated based on the control voltage; A first clock signal is generated based on the received initial clock signal, the output voltage, and the first delay parameter; A second clock signal is generated based on the initial clock signal, the output voltage, and the second delay parameter; wherein the first delay parameter is greater than the second delay parameter; Determine the phase deviation state between the first clock signal and the second clock signal; The value of the first delay parameter is adjusted according to the phase deviation state until the phase deviation value between the first clock signal and the second clock signal is equal to a preset phase value, at which point the value of the first delay parameter is locked to the target delay value; wherein, when the value of the set parameter is the preset reference value and the phase deviation value is the preset phase value, the corresponding value of the first delay parameter is the target delay value. If the value of the first delay parameter is locked to the target delay value, then when it is determined from the phase deviation state that the phase deviation value is not equal to the preset phase value, the size of the setting parameter is adjusted according to the phase deviation state.

9. The voltage stabilization control method according to claim 8, characterized in that, The method further includes: If the received reset signal is at the first level, then the initial value of the first delay parameter is set to the preset delay value, and the initial value of the setting parameter is set to the preset reference value; wherein, when the value of the reset signal is at the first level, the phase deviation state is reset to the first state; in the first state, the phase difference between the first clock signal and the second clock signal is less than the preset phase value; The method further includes: If the value of the reset signal changes from the first level to the second level, then the step of adjusting the value of the first delay parameter according to the phase deviation state is executed until the phase deviation value between the first clock signal and the second clock signal is determined to be equal to a preset phase value according to the phase deviation state; wherein, the first level and the second level are opposite.

10. The voltage regulation control method according to claim 8, characterized in that, The step of adjusting the magnitude of the first delay parameter according to the phase deviation state includes: If the phase deviation state is the first state, then the magnitude of the first delay parameter is increased by a first preset unit; If the phase deviation state is the second state, then the value of the first delay parameter is locked as the target delay value; If the phase deviation state is the third state, the magnitude of the first delay parameter is reduced by the first preset unit; in the third state, the phase difference between the first clock signal and the second clock signal is greater than a preset phase value.

11. The voltage regulation control method according to claim 8, characterized in that, Adjusting the setting parameter based on the phase deviation state includes: If the phase deviation state is the first state, then the magnitude of the setting parameter is reduced by a second preset unit; in the first state, the phase difference between the first clock signal and the second clock signal is less than a preset phase value; If the phase deviation state is the third state, the value of the setting parameter is increased by the second preset unit; in the third state, the phase difference between the first clock signal and the second clock signal is greater than the preset phase value.

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