Memory device, flash memory controller and control method thereof

Abstract

The invention discloses a memory device, a flash memory controller and a control method thereof, the flash memory controller is coupled to a main device and a flash memory module, and the flash memory controller is used for receiving a command from the main device to access the flash memory module; the control method comprises the following steps of: setting a first bandwidth for communicating with the main device; determining a reference data rate according to configuration information of the flash memory module; judging whether the first bandwidth far exceeds a required bandwidth according to the reference data rate; and setting a second bandwidth lower than the first bandwidth for communicating with the main device if it is determined that the first bandwidth is far beyond the required bandwidth.

Description

Technical Field

[0001] This invention relates to a flash memory controller. Background Technology

[0002] PCIe (Peripheral Component Interconnect) is a high-speed interface standard used to connect various components in computers and servers, such as graphics cards, storage devices, and network cards. Each version of PCIe introduces improvements in bandwidth and performance. For example, PCIe 3.0 has a bandwidth of 8 GT / s (billions of transfers per second) per lane, PCIe 4.0 has a bandwidth of 16 GT / s per lane, and PCIe 5.0 has a bandwidth of 32 GT / s per lane.

[0003] A solid-state drive (SSD) is a storage device that uses NAND flash memory to store data. Compared to traditional hard disk drives (HDDs), it offers faster access speeds, greater durability, and lower power consumption. The PCIe interface plays a crucial role in connecting the SSD to the host device (e.g., the motherboard), enabling high-speed data transfer and improving overall system performance.

[0004] In traditional PCIe-enabled solid-state drives (SSDs), when the SSD is connected to a host device, both are configured with the maximum permissible bandwidth. For example, assuming the SSD supports PCIe 5.0, the SSD and host device would be configured with a bandwidth of 32GT / s per lane. This configuration remains constant throughout all data transfers and receptions. However, due to the varying ways users interact with electronic devices—for example, a user might only watch online videos or type on a computer—data transfer between the host device and the SSD might be very limited. In these cases, maintaining a high bandwidth configuration consumes more power, resulting in unnecessary power consumption. Summary of the Invention

[0005] Therefore, one object of the present invention is to provide a flash memory controller that can adjust the maximum bandwidth based on the configuration information of the flash memory module and the current data throughput between the flash memory controller and the host device, so as to solve the problems described in the prior art.

[0006] In one embodiment of the present invention, a control method for a flash memory controller is disclosed, wherein the flash memory controller is coupled to a host device and a flash memory module, and the flash memory controller receives a command from the host device to access the flash memory module; and the control method includes: setting a first bandwidth for communicating with the host device; determining a reference data rate based on configuration information of the flash memory module; determining whether the first bandwidth significantly exceeds a required bandwidth based on the reference data rate; and if it is determined that the first bandwidth significantly exceeds the required bandwidth, setting a second bandwidth lower than the first bandwidth for communicating with the host device.

[0007] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller receives a command from a host device to access a flash memory module, and the flash memory controller includes: a read memory, a microprocessor, and a flow monitor. The flow monitor is configured to perform the following operations: setting a first bandwidth for communication with the host device; determining a reference data rate based on configuration information of the flash memory module; determining, based on the reference data rate, whether the first bandwidth significantly exceeds a required bandwidth; and if it is determined that the first bandwidth significantly exceeds the required bandwidth, setting a second bandwidth lower than the first bandwidth for communication with the host device.

[0008] In one embodiment of the present invention, a memory device is disclosed, comprising a flash memory module and a flash memory controller, wherein the flash memory controller is configured to receive a command from a host device to access the flash memory module. The flash memory controller performs the following operations: setting a first bandwidth for communication with the host device; determining a reference data rate based on configuration information of the flash memory module; determining, based on the reference data rate, whether the first bandwidth significantly exceeds a desired bandwidth; and if it is determined that the first bandwidth significantly exceeds the desired bandwidth, setting a second bandwidth lower than the first bandwidth for communication with the host device. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a memory device according to an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

[0011] Figure 3 This is a diagram illustrating the superblock configuration in a flash memory module.

[0012] Figure 4 This is a schematic diagram of a flow monitor according to an embodiment of the present invention.

[0013] Figure 5 This is a flowchart of a control method for a flash memory controller according to an embodiment of the present invention.

[0014] [Symbol Explanation]

[0015] 100: Memory device

[0016] 110: Flash memory controller

[0017] 112: Microprocessor

[0018] 112M: Read-Only Memory

[0019] 112C: Program Code

[0020] 114: Control Logic

[0021] 116: Buffer memory

[0022] 118: Interface Logic

[0023] 119: Traffic Monitor

[0024] 120: Flash memory module

[0025] 130: Main unit

[0026] 132: Encoder

[0027] 134: Decoder

[0028] 136: Randomizer

[0029] 138: Derandomizer

[0030] 140: DRAM

[0031] 200: Block

[0032] 202: Floating gate transistor

[0033] 310, 320, 330, 340: Chips; 312, 314, 322, 324, 332, 334, 342, 344: Planes; 361, 362: Superblocks

[0034] 410: Temporary Register

[0035] 420: Flow counter

[0036] 430: Timer

[0037] 440: Calculation Circuit

[0038] 450: Speed ​​control circuit

[0039] 500-510: Steps

[0040] B0~BN: Blocks

[0041] BL1, BL2, BL3: Bit lines

[0042] WL0~WL2, WL4~WL6: Character lines Detailed Implementation

[0043] Figure 1 This is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, control logic 114, a buffer memory 116, interface logic 118, and a traffic monitor. The read-only memory 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a de-randomizer 138. The encoder 132 is used to encode the data written to the flash memory module 120 to generate a corresponding check code (or error correction code, ECC). The decoder 134 is used to decode the data read from the flash memory module 120. The randomizer 136 is used to randomize the data written to the flash memory module 120, and the de-randomizer 138 is used to de-randomize the data read from the flash memory module 120.

[0044] In a typical configuration, flash memory module 120 comprises multiple flash memory chips, and each flash memory chip contains a plurality of blocks. The flash memory controller 110 performs data copying, erasing, and merging operations on flash memory module 120 in units of blocks. Furthermore, a block can record a specific number of data pages, and the flash memory controller 110 writes data to flash memory module 120 in units of data pages. In other words, a block is the smallest unit of erasure in flash memory module 120, and a data page is the smallest unit of writing in flash memory module 120.

[0045] In practice, the flash memory controller 110, which executes program code 112C through microprocessor 112, can perform various control operations using its internal components. For example, it can use control logic 114 to control the access operations of flash memory module 120 (especially the access operations of at least one block or at least one data page), use buffer memory 116 and / or a dynamic random access memory (DRAM) 140 to perform the necessary buffering operations, and use interface logic 118 to communicate with a host device 130.

[0046] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the main device 130 may be an electronic device that can be connected to the memory device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the memory device 100 may be a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and may be disposed in an electronic device, such as a mobile phone, watch, portable medical monitoring device (e.g., medical bracelet), laptop, or desktop computer, and in this case, the main device 130 may be a processor of the electronic device.

[0047] In this embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of multiple word lines, multiple bit lines, and multiple memory cells. Since the architecture of 3D NAND-type flash memory is well known to those skilled in the art, it will not be described in detail in this specification.

[0048] Figure 2 This is a schematic diagram of a block 200 in a flash memory module 120 according to an embodiment of the present invention, wherein the flash memory module 120 is a stereo NAND flash memory. Figure 2 As shown, block 200 contains multiple memory cells (such as the floating gate transistor 202 shown in the figure or other charge trap elements), which form a three-dimensional NAND flash memory architecture through multiple bit lines (only BL1 to BL3 are shown in the figure) and multiple word lines (such as WL0 to WL2, WL4 to WL6 shown in the figure). Figure 2 In the example of the topmost plane, all the floating gate transistors on word line WL0 constitute at least one data page, all the floating gate transistors on word line WL1 constitute at least another data page, and all the floating gate transistors on word line WL2 constitute at least another data page... and so on. Furthermore, the definition between word line WL0 and data pages (logical data pages) varies depending on the flash memory writing method. Specifically, when writing using Single-Level Cell (SLC), all floating-gate transistors on word line WL0 correspond to a single logical data page; when writing using Multi-Level Cell (MLC), all floating-gate transistors on word line WL0 correspond to two logical data pages; when writing using Triple-Level Cell (TLC), all floating-gate transistors on word line WL0 correspond to three logical data pages; and when writing using Quad-Level Cell (QLC), all floating-gate transistors on word line WL0 correspond to four logical data pages. Since those skilled in the art should be familiar with the structure of 3D NAND flash memory and the relationship between word lines and data pages, the relevant details will not be elaborated upon here.

[0049] Different types of blocks have different access times, and the access time will be longer if the memory cells in the block need to store more bits. Specifically, QLC blocks have the longest access time, while SLC blocks have the fastest access speed. From another perspective, the data throughput of the flash memory controller 110 is lowest when accessing QLC blocks, and highest when accessing SLC blocks.

[0050] In practice, the flash memory controller 110 configures blocks belonging to different planes within the flash memory module 120 as superblocks to facilitate data access management. Specifically, see... Figure 3The flash memory module contains two channels, channel 1 and channel 2, which are connected to multiple flash memory chips 310, 320, 330, and 340, respectively. Flash memory chip 310 contains two planes 312 and 314; flash memory chip 320 contains two planes 322 and 324; flash memory chip 330 contains two planes 332 and 334; and flash memory chip 340 contains two planes 342 and 344. Each plane contains multiple blocks B0-BN. During the configuration or initialization of flash memory module 120, flash memory controller 110 configures the first block B0 of all planes as super block 361, the second block B1 of all planes as super block 362, and so on. Figure 3 As shown, superblock 361 contains eight physical blocks, and flash memory controller 110 treats it as a regular block when accessing superblock 361. For example, superblock 361 itself is an erasure unit, meaning that although the eight blocks B0 in superblock 361 can be erased individually, flash memory controller 110 must erase all eight blocks B0 together. Furthermore, data writing to superblock 361 can be performed sequentially, for example, writing the first data page of plane 312, the first data page of plane 314, the first data page of plane 322, and the first data page of plane 324 first. After the first data page of plane 344 is written, subsequent data will be written sequentially to the second data page of plane 312, the second data page of plane 314, and so on. In other words, flash memory controller 110 will not begin writing the second data page of each block B0 before completing the writing of the first data page of each block B0 in superblock 361. A superblock is a logical set of blocks, rather than a physical set of blocks, set up by the flash memory controller 110 for easier management of the flash memory module 120. Furthermore, the flash memory controller 110 can also perform calculations on a superblock basis when performing garbage collection, calculating the number of valid data pages in a block, and calculating block write times.

[0051] Since blocks within a superblock can be accessed in parallel, the number of channels, the number of dies, and / or the number of planes corresponding to the superblock can reflect the bandwidth / speed between the flash memory controller 110 and the flash memory module 120. For example, with other configurations being equal, a superblock with more channels, more dies, and / or more planes will have higher bandwidth / speed, thereby improving the data transfer speed between the flash memory controller 110 and the flash memory module 120.

[0052] In this embodiment, since the maximum bandwidth required between the host device 130 and the memory device 100 is limited by the type of the accessed block and the configuration information of the flash memory module 120, the present invention provides a traffic monitor 119 for controlling the maximum bandwidth between the host device 130 and the memory device 100 according to the type of the accessed block and / or the configuration information of the flash memory module 120, so as to avoid using high bandwidth and high power consumption when transmitting low data volume, thereby avoiding unnecessary power consumption.

[0053] Figure 4 This is a schematic diagram of a flow monitor 119 according to an embodiment of the present invention, wherein the flow monitor 119 is implemented in hardware, that is, the flow monitor 119 is composed of multiple circuit elements. Figure 4 As shown, the flow monitor 119 includes a register 410, a flow counter 420, a timer 430, a calculation circuit 440, and a speed control circuit 450. The register 410 is configured to store flash patterns written by the microprocessor 112. For example, the register 410 stores SLC bandwidth, MLC bandwidth, TLC bandwidth, QLC bandwidth, and configuration information, such as the number of channels, number of dies, and / or number of planes corresponding to a superblock. In this embodiment, SLC bandwidth refers to the maximum data transfer rate between flash memory controller 110 and flash memory module 120 when flash memory controller 110 accesses SLC blocks; MLC bandwidth refers to the maximum data transfer rate between flash memory controller 110 and flash memory module 120 when flash memory controller 110 accesses MLC blocks; TLC bandwidth refers to the maximum data transfer rate between flash memory controller 110 and flash memory module 120 when flash memory controller 110 accesses TLC blocks; and QLC bandwidth refers to the maximum data transfer rate between flash memory controller 110 and flash memory module 120 when flash memory controller 110 accesses QLC blocks. In this embodiment, SLC bandwidth is greater than MLC bandwidth, MLC bandwidth is greater than TLC bandwidth, and TLC bandwidth is greater than QLC bandwidth.

[0054] Furthermore, the configuration information recorded in the register 410 may include the type of block currently being read / written. For example, when the flash memory controller 110 is accessing an SLC block in the flash memory module 120, the microprocessor 112 updates the configuration information to record that the currently accessed block is an SLC block; if the flash memory controller 110 is accessing a TLC block in the flash memory module 120, the microprocessor 112 updates the configuration information to record that the currently accessed block is a TLC block.

[0055] The flow counter 420 is used to calculate the amount of data transferred between the host device 130 and the flash memory controller 110. The timer 430 is used to provide the duration of time from when the flow counter 420 started calculating the data size to the present time. The calculation circuit 440 is used to calculate the data throughput between the host device 130 and the flash memory controller 110 based on the data size provided by the flow counter 420 and the time provided by the timer 430.

[0056] Speed ​​control circuit 450 is used to determine the appropriate bandwidth between host device 130 and memory device 100 based on information provided by register 410 and throughput calculated by calculation circuit 440. Specifically, the information in register 410 can serve as a reference data rate, which speed control circuit 450 can refer to along with the throughput between host device 130 and memory device 100 to dynamically adjust the bandwidth. The reference data rate may be the maximum possible data rate between flash memory controller 110 and flash memory module 120. In one embodiment, flash memory controller 110 may have multiple predetermined bandwidths corresponding to multiple PCIe specification versions. For example, these predetermined bandwidths may correspond to 64GT / s, 32GT / s, 16GT / s, 8GT / s, and 5GT / s per lane for PCIe 6.0, PCIe 5.0, PCIe 4.0, PCIe 3.0, and PCIe 2.0, respectively.

[0057] It should be noted that the reference data rate determined based on the information provided by the register 410 may vary. Specifically, if the flash memory controller 110 is accessing an SLC block in the flash memory module 120, the speed control circuit 450 will determine a higher reference data rate because SLC has the fastest access speed; if the flash memory controller 110 is accessing a QLC block in the flash memory module 120, the speed control circuit 450 will determine a lower reference data rate because SLC has a longer access time.

[0058] In one embodiment, if the flash memory controller 110 and the host device 130 initially negotiate an agreement with a first bandwidth (e.g., 32 GT / s per channel), and the speed control circuit 450 of the flow monitor 119 refers to information in the register 410 and the currently accessed block type, and determines that the reference data rate is lower than a threshold determined based on a second bandwidth, the speed control circuit 450 can determine that the current bandwidth is much higher than the required bandwidth, resulting in unnecessary power consumption. The second bandwidth is the next lower bandwidth, for example, 16 GT / s per channel, and the threshold can be set to 80% of the second bandwidth. In this case, the speed control circuit 450 sends a request and a target speed (target bandwidth) to the PCIe Media Access Control (MAC) layer in the interface logic 118, where the target speed may be the second bandwidth, for example, 16 GT / s per channel. Then, after the interface logic 118 and the host device 130 complete the bandwidth adjustment negotiation, the PCIe media access control layer will send an acknowledgment (ACK) message to the speed control circuit 450 to complete the bandwidth adjustment.

[0059] In one embodiment, if the flash memory controller 110 and the host device 130 negotiate a third bandwidth (e.g., 8 GT / s per channel), and the speed control circuit 450 of the flow monitor 119 determines that the throughput provided by the calculation circuit 440 is greater than a threshold determined based on the third bandwidth (e.g., the threshold is equal to 80% of the third bandwidth), the speed control circuit 450 can determine that the current bandwidth is too close to the required bandwidth, which may affect the performance of the flash memory controller 110 in subsequent operations. In this case, the speed control circuit 450 sends a request and a target speed (target bandwidth) to the PCIe media access control layer in the interface logic 118, where the target speed may be the next higher bandwidth, such as 16 GT / s per channel. Afterwards, after the interface logic 118 and the host device 130 complete the bandwidth adjustment negotiation, the PCIe media access control layer sends an acknowledgment message to the speed control circuit 450 to complete the bandwidth adjustment.

[0060] In one embodiment, if the flash memory controller 110 negotiates a fourth bandwidth (e.g., 16 GT / s per channel) with the host device 130, and the speed control circuit 450 of the flow monitor 119 determines that the throughput provided by the computing circuit 440 is lower than a threshold determined based on a fifth bandwidth, the speed control circuit 450 can determine that the current bandwidth is much higher than the required bandwidth, resulting in unnecessary power consumption. The fifth bandwidth is the next lower bandwidth, for example, 8 GT / s per channel, and the threshold can be set to 80% of the fifth bandwidth. In this case, the speed control circuit 450 sends a request and a target speed (target bandwidth) to the PCIe media access control layer in the interface logic 118, where the target speed may be the fifth bandwidth, for example, 8 GT / s per channel. After the interface logic 118 and the host device 130 complete the bandwidth adjustment negotiation, the PCIe media access control layer sends an acknowledgment message to the speed control circuit 450 to complete the bandwidth adjustment.

[0061] Figure 5 A flowchart of a control method for a flash memory controller 110 according to an embodiment of the present invention is shown. In step 500, the process begins, and the memory device 100 is powered on and connected to the host device 130. In step 502, the flash memory controller 110 performs an initialization process with the host device 130 and sets a preset bandwidth for communication with the host device 130. In this embodiment, the preset bandwidth is the maximum bandwidth supported by the flash memory controller 110. For example, if the PCIe interface of the flash memory controller 110 supports up to PCIe 5.0, the preset bandwidth is 32GT / s per channel; if the PCIe interface of the flash memory controller 110 supports up to PCIe 6.0, the preset bandwidth is 64GT / s per channel. In addition, the microprocessor 112 writes the flash mode into the register 410 of the traffic monitor 119, wherein the flash mode includes SLC bandwidth, MLC bandwidth, TLC bandwidth, QLC bandwidth and configuration information of the corresponding superblock such as the number of channels, the number of dies and / or the number of planes.

[0062] In step 504, the speed control circuit 450 determines the reference data rate based on the information recorded in the register 410 and the currently accessed block type. Then, the speed control circuit 450 further determines whether the reference data rate is lower than the next lower bandwidth of the currently set bandwidth (for example, if the current bandwidth is 64GT / s per channel for PCIe 6.0, then the next lower bandwidth is 32GT / s per channel for PCIe 5.0). If yes, the process proceeds to step 506; if no, the process proceeds to step 508.

[0063] In one embodiment, the speed control circuit 450 can determine a higher reference data rate when a superblock corresponds to a greater number of channels, a greater number of dies, and / or more planes. In another embodiment, the speed control circuit 450 can determine a higher reference data rate when the currently read / written block is an SLC or MLC block, and a lower reference data rate when the currently read / written block is a TLC or QLC block. In one embodiment, the speed control circuit 450 can use a lookup table to determine the reference data rate, which records combinations of different configuration information and block types and their corresponding reference data rates.

[0064] In step 506, the speed control circuit 450 determines that the current bandwidth far exceeds the required bandwidth. Therefore, the speed control circuit 450 sends a request and target bandwidth to the PCIe media access control layer within the interface logic 118 to reduce the bandwidth between the flash memory controller 110 and the host device 130. In this embodiment, the target bandwidth is the next lower bandwidth after the current bandwidth.

[0065] In step 508, the speed control circuit 450 obtains the current throughput between the host device 130 and the flash memory controller 110 from the calculation circuit 440. The speed control circuit 450 further determines whether the throughput is greater than a first threshold value determined based on the current bandwidth between the host device 130 and the flash memory controller 110, and whether the throughput is less than a second threshold value determined based on the next lower bandwidth of the current bandwidth. In this embodiment, the first threshold value can be 80% of the current bandwidth, and the second threshold value can be 80% of the next lower bandwidth of the current bandwidth. If the throughput meets any of the above conditions, the process proceeds to step 510; if the throughput does not meet any of the above conditions, the process returns to step 504.

[0066] In step 510, the speed control circuit 450 determines that the current bandwidth is inappropriate. Therefore, the speed control circuit 450 sends a request and target bandwidth to the PCIe Media Access Control layer within the interface logic 118 to increase or decrease the bandwidth between the flash memory controller 110 and the host device 130. Specifically, if the throughput is determined to be greater than a first threshold, such as 80% of the current bandwidth, the speed control circuit 450 determines that the current bandwidth is too close to the required bandwidth. Therefore, the speed control circuit 450 sends a request to the PCIe Media Access Control layer within the interface logic 118 to increase the bandwidth between the flash memory controller 110 and the host device 130. Furthermore, if the throughput is determined to be lower than a second threshold, such as 80% of the next lower bandwidth of the current bandwidth, the speed control circuit 450 determines that the current bandwidth far exceeds the required bandwidth. Therefore, the speed control circuit 450 sends a request to the PCIe Media Access Control layer within the interface logic 118 to decrease the bandwidth between the flash memory controller 110 and the host device 130.

[0067] In summary, the flash memory controller and its control method of the present invention adjust the bandwidth according to the configuration information of the flash memory module and / or the current throughput between the flash memory controller and the host device. This allows for setting the most suitable bandwidth to avoid consuming too much energy by using high bandwidth when transmitting low data amounts, thereby avoiding unnecessary power consumption.

[0068] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A control method for a flash memory controller, wherein the flash memory controller is coupled to a host device and a flash memory module, and the flash memory controller receives a command from the host device to access the flash memory module; and the control method comprises: A first bandwidth is set for communication with the master device; A reference data rate is determined based on configuration information of the flash memory module; Based on the reference data rate, determine whether the first bandwidth significantly exceeds a required bandwidth; and If it is determined that the first bandwidth far exceeds the required bandwidth, a second bandwidth lower than the first bandwidth is set for communication with the main device.

2. The control method as described in claim 1, characterized in that, The configuration information includes the number of channels, the number of dies, and / or the number of planes corresponding to a superblock in the flash memory module.

3. The control method as described in claim 2, characterized in that, The step of determining the reference data rate based on the configuration information of the flash memory module includes: A higher reference data rate is determined when the superblock corresponds to a greater number of channels, a greater number of grains, and / or a greater number of planes.

4. The control method as described in claim 1, characterized in that, The configuration information includes a block type of a block being read / written in the flash memory module, wherein the block type indicates whether the block is a single-level cell (SLC) block, a multi-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block.

5. The control method as described in claim 4, characterized in that, The step of determining the reference data rate based on the configuration information of the flash memory module includes: The higher reference data rate is determined when the block being read / written in the flash memory module is a single-level storage block or a dual-level storage block; When the block being read / written in the flash memory module is a three-level storage block or a four-level storage block, a lower reference data rate is determined.

6. The control method as described in claim 1, characterized in that, The flash memory controller records a plurality of predetermined bandwidths, wherein the first bandwidth and the second bandwidth are two of the plurality of predetermined bandwidths, and the second bandwidth is the next lower bandwidth of the first bandwidth; and the step of determining whether the first bandwidth far exceeds the required bandwidth based on the reference data rate includes: Determine whether the reference data rate is lower than a threshold value determined based on the second bandwidth; as well as If the reference data rate is determined to be lower than the threshold, then the first bandwidth is determined to be far greater than the required bandwidth.

7. The control method as described in claim 1, characterized in that, The flash memory controller records a plurality of predetermined bandwidths, the first bandwidth being one of the plurality of predetermined bandwidths; and the control method further includes: If it is determined that the first bandwidth does not far exceed the required bandwidth, it is determined whether the throughput between the flash memory controller and the host device is higher than a threshold value determined based on the first bandwidth; as well as If it is determined that the throughput between the flash memory controller and the host device is higher than the threshold, a third bandwidth higher than the first bandwidth is set for communication with the host device.

8. The control method as described in claim 1, characterized in that, The flash memory controller records a plurality of predetermined bandwidths, wherein the first bandwidth and the second bandwidth are two of the plurality of predetermined bandwidths, and the second bandwidth is the next lower bandwidth of the first bandwidth; and the step of determining whether the first bandwidth far exceeds the required bandwidth based on the reference data rate includes: If it is determined that the first bandwidth does not far exceed the required bandwidth, it is determined whether the throughput between the flash memory controller and the host device is lower than a threshold value determined based on the second bandwidth; as well as If it is determined that the throughput between the flash memory controller and the host device is lower than the threshold, the second bandwidth is set for communication with the host device.

9. A flash memory controller for receiving a command from a host device to access a flash memory module, the flash memory controller comprising: A read-only memory is used to store a program code; A microprocessor is used to execute the program code to control access to the flash memory module; as well as A traffic monitor; The traffic monitor is used to perform the following operations: A first bandwidth is set for communication with the master device; A reference data rate is determined based on configuration information of the flash memory module; Based on the reference data rate, determine whether the first bandwidth far exceeds a required bandwidth; as well as If it is determined that the first bandwidth far exceeds the required bandwidth, a second bandwidth lower than the first bandwidth is set for communication with the main device.

10. The flash memory controller as described in claim 9, characterized in that, The configuration information includes the number of channels, the number of dies, and / or the number of planes corresponding to a superblock in the flash memory module.

11. The flash memory controller as claimed in claim 10, characterized in that, The step of determining the reference data rate based on the configuration information of the flash memory module includes: A higher reference data rate is determined when the superblock corresponds to a greater number of channels, a greater number of grains, and / or a greater number of planes.

12. The flash memory controller as described in claim 9, characterized in that, The configuration information includes a block type of a block being read / written in the flash memory module, wherein the block type indicates whether the block is a single-level cell (SLC) block, a multi-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block.

13. The flash memory controller as described in claim 12, characterized in that, The step of determining the reference data rate based on the configuration information of the flash memory module includes: The higher reference data rate is determined when the block being read / written in the flash memory module is a single-level storage block or a dual-level storage block; When the block being read / written in the flash memory module is a three-level storage block or a four-level storage block, a lower reference data rate is determined.

14. The R flash memory controller as described in claim 9, characterized in that, The flash memory controller records a plurality of predetermined bandwidths, wherein the first bandwidth and the second bandwidth are two of the plurality of predetermined bandwidths, and the second bandwidth is the next lower bandwidth of the first bandwidth; and the step of determining whether the first bandwidth far exceeds the required bandwidth based on the reference data rate includes: Determine whether the reference data rate is lower than a threshold value determined based on the second bandwidth; as well as If the reference data rate is determined to be lower than the threshold, then the first bandwidth is determined to be far greater than the required bandwidth.

15. The control method as described in claim 9, characterized in that, The flash memory controller records a plurality of predetermined bandwidths, the first bandwidth being one of the plurality of predetermined bandwidths; and the control method further includes: If it is determined that the first bandwidth does not far exceed the required bandwidth, it is determined whether the throughput between the flash memory controller and the host device is higher than a threshold value determined based on the first bandwidth; as well as If it is determined that the throughput between the flash memory controller and the host device is higher than the threshold, a third bandwidth higher than the first bandwidth is set for communication with the host device.

16. The control method as described in claim 9, characterized in that, The flash memory controller records a plurality of predetermined bandwidths, wherein the first bandwidth and the second bandwidth are two of the plurality of predetermined bandwidths, and the second bandwidth is the next lower bandwidth of the first bandwidth; and the step of determining whether the first bandwidth far exceeds the required bandwidth based on the reference data rate includes: If it is determined that the first bandwidth does not far exceed the required bandwidth, it is determined whether the throughput between the flash memory controller and the host device is lower than a threshold value determined based on the second bandwidth; as well as If it is determined that the throughput between the flash memory controller and the host device is lower than the threshold, the second bandwidth is set for communication with the host device.

17. A memory device comprising: A flash memory module; and A flash memory controller for receiving a command from the host device to access the flash memory module; The flash memory controller performs the following operations: A first bandwidth is set for communication with the master device; A reference data rate is determined based on configuration information of the flash memory module; Based on the reference data rate, determine whether the first bandwidth far exceeds a required bandwidth; as well as If it is determined that the first bandwidth far exceeds the required bandwidth, a second bandwidth lower than the first bandwidth is set for communication with the main device.

18. The memory device as claimed in claim 17, characterized in that, The configuration information includes the number of channels, the number of dies, and / or the number of planes corresponding to a superblock in the flash memory module.

19. The memory device as claimed in claim 17, characterized in that, The configuration information includes a block type of a block being read / written in the flash memory module, wherein the block type indicates whether the block is a single-level cell (SLC) block, a multi-level cell (MLC) block, a triple-level cell (TLC) block, or a quad-level cell (QLC) block.

20. The memory device as claimed in claim 17, characterized in that, The flash memory controller records a plurality of predetermined bandwidths, wherein the first bandwidth and the second bandwidth are two of the plurality of predetermined bandwidths, and the second bandwidth is the next lower bandwidth of the first bandwidth; and the step of determining whether the first bandwidth far exceeds the required bandwidth based on the reference data rate includes: Determine whether the reference data rate is lower than a threshold value determined based on the second bandwidth; as well as If the reference data rate is determined to be lower than the threshold, then the first bandwidth is determined to be far greater than the required bandwidth.

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