Cross-architecture parallel scheduling method and system for heterogeneous computing power resources
By establishing a resource database and optimizing algorithms, combined with MPI interfaces and main process coordination, the problem of cross-architecture parallel scheduling of heterogeneous computing nodes was solved, achieving seamless integration and efficient parallel computing of heterogeneous computing resources, and avoiding resource waste and performance imbalance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 江西省科技基础条件平台中心(江西省计算中心)
- Filing Date
- 2026-01-20
- Publication Date
- 2026-04-21
Smart Images
Figure CN121900913A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of resource scheduling technology, and in particular to a cross-architecture parallel scheduling method and system for heterogeneous computing resources. Background Technology
[0002] With the diversification of computing technologies, a single computing center often contains computing nodes with multiple architectures (such as x86, ARM, and the domestic C86). Due to differences in their underlying technology stacks (compilers, mathematical libraries, communication libraries), these nodes form "technology silos," meaning that traditional parallel job schedulers (such as Slurm and PBS) can typically only schedule jobs to queues of homogeneous nodes. However, many computing centers adopt a "tiered expansion" model, resulting in a limited homogeneous resource pool for a single architecture, which cannot meet the core requirements of large-scale parallel computing jobs. Forcing heterogeneous nodes into the same queue will create a "weakest link" effect due to uneven node performance, severely slowing down the overall execution efficiency of the job.
[0003] Currently, while some research uses virtualization technology to shield the underlying heterogeneity, the virtualization layer introduces additional performance overhead. Other solutions focus on resource scheduling within cloud environments or container platforms, failing to address the fundamental problem of cross-architecture collaborative parallel computing at the physical machine level: how to enable multiple processes of an MPI parallel job to run directly on physical nodes of different architectures and efficiently and correctly synchronize data. Summary of the Invention
[0004] The purpose of this invention is to provide a cross-architecture parallel scheduling method and system for heterogeneous computing resources, aiming to solve at least one of the problems in the background art.
[0005] In a first aspect, the present invention provides a cross-architecture parallel scheduling method for heterogeneous computing resources, the method comprising: The computing nodes are classified and registered according to their CPU instruction set architecture, and their dynamic load status is continuously collected to establish and maintain a resource database that includes node architecture type, single-core computing efficiency and currently available resources. Receive parallel computing jobs, analyze their total computational workload and user-defined job completion time constraints, run an optimization algorithm based on the resource database, output the minimum set of cores required to meet the time constraints, and determine the corresponding candidate node groups; On each computing node in the candidate node group, the parallel process of the job is started, and the management process on one of the nodes is designated as the master process to coordinate the overall execution of the job. During job execution, parallel processes running on each node exchange and synchronize data across nodes through collective communication operations via message passing interfaces, with the main process responsible for synchronization control.
[0006] In some embodiments, the step of running an optimization algorithm to output the minimum set of cores required to satisfy the time constraint and determining the corresponding candidate node group includes: Sort all available CPU cores in the resource database in descending order of their single-core computing efficiency; The computation cores are accumulated in descending order, and in each iteration, the computational efficiency of the lowest-efficient core in the currently accumulated core set is used as the basis for the estimated completion time of the computation job. When the iteration reaches a certain number of cores, if the estimated completion time is less than or equal to the job completion time limit constraint for the first time, the iteration stops, and the currently accumulated cores and their respective nodes are determined as the minimum core set and candidate node group.
[0007] In some embodiments, the method further includes: Based on the architecture type of each node in the candidate node group, load or call the application executable file pre-generated using the corresponding architecture compiler for each architecture.
[0008] In some embodiments, the steps of the collective communication operation include: Each node's parallel process sends its local computation results to the node where the main process resides for specified aggregation computation via the MPI_Reduce call.
[0009] In some embodiments, the step of continuously collecting its dynamic load status includes: Client processes deployed on each computing node collect CPU utilization, memory usage, and queue information of their respective nodes at fixed intervals and report them to the central management node to update the resource database.
[0010] In some embodiments, if the optimization algorithm fails to meet the job completion time constraint after traversing all available cores, it outputs the shortest achievable estimated completion time and its corresponding core configuration scheme.
[0011] In some embodiments, the step of designating the management process on one of the nodes as the master process includes: The candidate nodes are either explicitly specified by the user when submitting the job, or automatically elected by the scheduling system based on the network topology, latency, or node load status of the candidate node group.
[0012] Secondly, the present invention provides a cross-architecture parallel scheduling system for heterogeneous computing resources, the system comprising: The resource management module is used to classify and register computing nodes according to their CPU instruction set architecture, continuously collect their dynamic load status, and establish and maintain a resource database containing node architecture type, single-core computing efficiency, and currently available resources. The scheduling optimization module is used to receive parallel computing jobs, parse their total computing workload and user-defined job completion time constraints, run an optimization algorithm based on the resource database, output the minimum set of cores required to meet the time constraints, and determine the corresponding candidate node group. The job execution module is used to start the parallel process of the job on each computing node in the candidate node group, and designate the management process on one of the nodes as the master process to coordinate the overall execution of the job. The control module is used to enable parallel processes running on each node to exchange and synchronize data across nodes through collective communication operations via message passing interfaces during job execution, with the main process responsible for synchronization control.
[0013] Thirdly, the present invention provides a storage medium that stores one or more programs, which, when executed by a processor, implement the above-described method for cross-architecture parallel scheduling of heterogeneous computing resources.
[0014] Fourthly, the present invention provides an electronic device, the electronic device comprising a memory and a processor, wherein: The memory is used to store computer programs; When the processor executes the computer program stored in the memory, it implements the above-described method for cross-architecture parallel scheduling of heterogeneous computing resources.
[0015] Compared with the prior art, the present invention has the following advantages: This invention achieves efficient aggregation and utilization of heterogeneous computing resources at the physical machine level by constructing a complete cross-architecture parallel scheduling mechanism. Specifically, by establishing a resource database containing architecture type and single-core efficiency, the problem of quantifying and uniformly managing the capabilities of heterogeneous nodes is solved. Furthermore, an optimization algorithm based on efficiency descending iteration is adopted to accurately calculate the minimum set of cores required while meeting job time limits, fundamentally avoiding resource waste and the "weakest link" effect. On this basis, by pre-compiling executable files for different architectures and using MPI standard interfaces (such as MPI_Reduce) for cross-node data synchronization, combined with a main process coordination mechanism, it is ensured that a single parallel job can run collaboratively on physical nodes with different architectures such as x86 and ARM. Ultimately, seamless integration and efficient parallel computing of heterogeneous computing resources are achieved without the need for a virtualization layer. Attached Figure Description
[0016] Figure 1This is a flowchart of a cross-architecture parallel scheduling method for heterogeneous computing resources proposed in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a cross-architecture parallel scheduling system for heterogeneous computing resources proposed in an embodiment of the present invention.
[0017] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.
[0019] like Figure 1 As shown, an embodiment of the present invention proposes a cross-architecture parallel scheduling method for heterogeneous computing resources. The method includes steps S101 to S104, wherein: Step S101: Register the computing nodes according to their CPU instruction set architecture, continuously collect their dynamic load status, and establish and maintain a resource database containing node architecture type, single-core computing efficiency and currently available resources. In heterogeneous computing environments, computing nodes with different instruction set architectures (such as x86, ARM, and C86) exhibit differentiated hardware performance and operational characteristics, which traditional scheduling systems cannot directly identify and quantify. This step constructs a resource database that accurately reflects the heterogeneous state and real-time capabilities of the cluster by classifying and registering nodes according to their architecture and continuously collecting their dynamic load and single-core efficiency. This provides a unified and quantified resource view foundation for subsequent precise cross-architecture scheduling.
[0020] Furthermore, to monitor the dynamic load status of each computing node in real time and enable reasonable adjustment and optimization of resource allocation, the cross-architecture parallel scheduling method for heterogeneous computing resources continuously collects the dynamic load status of nodes. Client processes are also deployed on each computing node. These client processes collect key data such as CPU utilization, memory usage, and queue information at fixed intervals. After collection, the client processes report this data to the central management node. The central management node updates the resource database based on the reported data, ensuring that the information in the resource database remains consistent with the actual load status of each computing node, providing accurate data support for subsequent resource scheduling.
[0021] Step S102: Receive parallel computing jobs, parse their total computing workload and user-defined job completion time constraints, run an optimization algorithm based on the resource database, output the minimum set of cores required to meet the time constraints, and determine the corresponding candidate node group; With a heterogeneous resource view, relying on traditional experience or simple rules for resource allocation can easily lead to the "weakest link" effect due to uneven node performance, resulting in resource waste or failure to meet job deadlines. By analyzing job workload and time constraints and running an optimization algorithm based on efficiency-descending iteration, the minimum core set required to meet job time requirements is accurately calculated from global resources. This achieves a leap from having available resources to meeting requirements with optimal resources.
[0022] Furthermore, in some embodiments, all available CPU cores in the resource database are first sorted in descending order of their single-core computing efficiency; then, the computing cores are accumulated in descending order iteratively, and in each iteration, the estimated completion time of the job is calculated based on the computing efficiency of the lowest-efficient core in the currently accumulated core set; when the iteration reaches a certain number of cores, if the estimated completion time is less than or equal to the job completion time constraint for the first time, the iteration stops, and the currently accumulated cores and their respective nodes are determined as the minimum core set and candidate node group.
[0023] First, all available CPU cores in the resource database are sorted in descending order of single-core computing efficiency. Then, the number of computing cores is added iteratively in descending order. In each iteration, the estimated completion time of the job is calculated based on the lowest efficiency core in the currently added core set. When the iteration reaches a certain number of cores, if the calculated estimated completion time is less than or equal to the job's specified completion time constraint for the first time, the iteration stops, and the currently added cores and their corresponding nodes are determined as the minimum set of cores that meet the conditions, along with the corresponding candidate node group.
[0024] Furthermore, if the optimization algorithm fails to meet the job completion time constraint after traversing all available cores, it outputs the shortest achievable estimated completion time and its corresponding core configuration scheme.
[0025] Step S103: On each computing node in the candidate node group, start the parallel process of the job, and designate the management process on one of the nodes as the master process to coordinate the overall execution of the job. Even after determining the resource combination, the job still cannot be executed if the job processes cannot be correctly started and a coordination mechanism cannot be established on each heterogeneous node. This step establishes a unified execution control plane for cross-architecture parallel computing by starting parallel processes on candidate nodes and designating a master process for global coordination. This solves the problem of coordinating multi-process startup, status monitoring, and overall control in heterogeneous environments.
[0026] It should be noted that in the above cross-architecture parallel scheduling method, after determining the candidate node group, considering that different nodes have different architecture types, and different architectures have different execution methods and requirements for applications, it is also necessary to load or call the application executable file pre-generated using the corresponding architecture compiler for each architecture of each node in the candidate node group. This ensures that the application can run correctly and efficiently on nodes with different architectures, avoiding runtime errors or performance degradation caused by architecture incompatibility, and guaranteeing the smooth progress of the entire parallel scheduling process.
[0027] In addition, in some embodiments, there are two ways to designate the master process. One is that the user explicitly designates it when submitting the job. The user can choose the node that they think is most suitable as the master process based on their understanding of the system architecture, node performance and job characteristics. This method gives the user a certain degree of autonomy. The other is that the scheduling system automatically elects the master process based on the network topology latency or node load status of the candidate node group. The scheduling system selects the node with low network latency and light load as the master process by analyzing the network connectivity and current load of the nodes. This ensures that the master process can communicate and coordinate with other nodes efficiently, thereby improving the performance and stability of the entire parallel scheduling system.
[0028] Step S104: During job execution, parallel processes running on each node exchange and synchronize data across nodes through collective communication operations via message passing interfaces, with the main process responsible for synchronization control.
[0029] When the same job is executed in parallel across different architecture nodes, data exchange and computation synchronization between processes are necessary; otherwise, the computation results will be inconsistent or meaningless. By calling standard message passing interfaces (such as MPI) for collective communication operations and utilizing the main process for synchronization control, reliable data consistency across heterogeneous hardware platforms is achieved.
[0030] Specifically, in the cross-architecture parallel scheduling of heterogeneous computing resources, collective communication is a crucial step in integrating the computation results of each node. Parallel processes on each node send their locally computed results to the node hosting the main process via MPI_Reduce calls. Upon receiving this data from different nodes, the main process node performs aggregation calculations on this data according to a pre-defined method, such as summation or averaging. This collective communication method efficiently integrates the computation results from each node, thereby yielding the final result of the entire parallel computing task.
[0031] In summary, based on the aforementioned method for cross-architecture parallel scheduling of heterogeneous computing resources, a complete cross-architecture parallel scheduling mechanism is constructed to achieve efficient aggregation and utilization of heterogeneous computing resources at the physical machine level. Specifically, by establishing a resource database containing architecture type and single-core efficiency, the problem of quantifying and uniformly managing the capabilities of heterogeneous nodes is solved. Furthermore, an optimization algorithm based on efficiency descending iteration is adopted to accurately calculate the minimum set of cores required while meeting job time limits, fundamentally avoiding resource waste and the "weakest link" effect. On this basis, by pre-compiling executable files for different architectures and using MPI standard interfaces (such as MPI_Reduce) for cross-node data synchronization, combined with the main process coordination mechanism, it is ensured that a single parallel job can run collaboratively on physical nodes with different architectures such as X86 and ARM. Ultimately, seamless integration and efficient parallel computing of heterogeneous computing resources are achieved without the need for a virtualization layer.
[0032] like Figure 2 As shown, one embodiment of the present invention proposes a cross-architecture parallel scheduling system for heterogeneous computing resources, the system comprising: The resource management module 10 is used to classify and register computing nodes according to their CPU instruction set architecture, continuously collect their dynamic load status, and establish and maintain a resource database containing node architecture type, single-core computing efficiency and currently available resources. The scheduling optimization module 20 is used to receive parallel computing jobs, parse their total computing workload and user-defined job completion time constraints, run an optimization algorithm based on the resource database, output the minimum set of cores required to meet the time constraints, and determine the corresponding candidate node group. The job execution module 30 is used to start the parallel process of the job on each computing node in the candidate node group, and designate the management process on one of the nodes as the main process to coordinate the overall execution of the job. The control module 40 is used to enable parallel processes running on each node to perform cross-node data exchange and synchronization through collective communication operations via message passing interfaces during job execution, with the main process responsible for synchronization control.
[0033] In another aspect, the present invention also proposes a storage medium on which one or more programs are stored, which, when executed by a processor, implement the above-described method for cross-architecture parallel scheduling of heterogeneous computing resources.
[0034] In another aspect, the present invention also proposes an electronic device, including a memory and a processor, wherein the memory is used to store computer programs and the processor is used to execute the computer programs stored in the memory, so as to realize the above-mentioned method for cross-architecture parallel scheduling of heterogeneous computing resources.
[0035] Those skilled in the art will understand that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain stored, communicated, propagated, or transmitted programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.
[0036] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.
[0037] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.
[0038] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A cross-architecture parallel scheduling method for heterogeneous computing resources, characterized in that, The method includes: The computing nodes are classified and registered according to their CPU instruction set architecture, and their dynamic load status is continuously collected to establish and maintain a resource database containing node architecture type, single-core computing efficiency and currently available resources. Receive parallel computing jobs, analyze their total computational workload and user-defined job completion time constraints, run an optimization algorithm based on the resource database, output the minimum set of cores required to meet the time constraints, and determine the corresponding candidate node groups; On each computing node in the candidate node group, the parallel process of the job is started, and the management process on one of the nodes is designated as the master process to coordinate the overall execution of the job. During job execution, parallel processes running on each node exchange and synchronize data across nodes through collective communication operations via message passing interfaces, with the main process responsible for synchronization control.
2. The cross-architecture parallel scheduling method for heterogeneous computing resources according to claim 1, characterized in that, The steps of running an optimization algorithm to output the minimum set of cores required to satisfy the time constraint and to determine the corresponding candidate node group include: Sort all available CPU cores in the resource database in descending order of their single-core computing efficiency; The computation cores are accumulated in descending order, and in each iteration, the computational efficiency of the lowest-efficient core in the currently accumulated core set is used as the basis for the estimated completion time of the computation job. When the iteration reaches a certain number of cores, if the estimated completion time is less than or equal to the job completion time limit constraint for the first time, the iteration stops, and the currently accumulated cores and their respective nodes are determined as the minimum core set and candidate node group.
3. The cross-architecture parallel scheduling method for heterogeneous computing resources according to claim 2, characterized in that, The method further includes: Based on the architecture type of each node in the candidate node group, load or call the application executable file pre-generated using the corresponding architecture compiler for each architecture.
4. The cross-architecture parallel scheduling method for heterogeneous computing resources according to claim 3, characterized in that, The steps of the collective communication operation include: Each node's parallel process sends its local computation results to the node where the main process resides for specified aggregation computation via the MPI_Reduce call.
5. A cross-architecture parallel scheduling method for heterogeneous computing resources according to claim 4, characterized in that, The step of continuously collecting its dynamic load status includes: Client processes deployed on each computing node collect CPU utilization, memory usage, and queue information of their respective nodes at fixed intervals and report them to the central management node to update the resource database.
6. The cross-architecture parallel scheduling method for heterogeneous computing resources according to claim 1, characterized in that, If the optimization algorithm fails to meet the job completion time constraint after traversing all available cores, it outputs the shortest achievable estimated completion time and its corresponding core configuration scheme.
7. A cross-architecture parallel scheduling method for heterogeneous computing resources according to claim 6, characterized in that, The step of designating the management process on one of the nodes as the master process includes: The candidate nodes are either explicitly specified by the user when submitting the job, or automatically elected by the scheduling system based on the network topology, latency, or node load status of the candidate node group.
8. A cross-architecture parallel scheduling system for heterogeneous computing resources, characterized in that, The system includes: The resource management module is used to classify and register computing nodes according to their CPU instruction set architecture, continuously collect their dynamic load status, and establish and maintain a resource database containing node architecture type, single-core computing efficiency, and currently available resources. The scheduling optimization module is used to receive parallel computing jobs, analyze their total computing workload and user-defined job completion time constraints, run an optimization algorithm based on the resource database, output the minimum set of cores required to meet the time constraints, and determine the corresponding candidate node group. The job execution module is used to start the parallel process of the job on each computing node in the candidate node group, and designate the management process on one of the nodes as the master process to coordinate the overall execution of the job. The control module is used to enable parallel processes running on each node to exchange and synchronize data across nodes through collective communication operations via message passing interfaces during job execution, with the main process responsible for synchronization control.
9. A storage medium, characterized in that, The storage medium stores one or more programs, which, when executed by a processor, implement a cross-architecture parallel scheduling method for heterogeneous computing resources as described in any one of claims 1-7.
10. An electronic device comprising a memory and a processor, wherein: The memory is used to store computer programs; When the processor executes a computer program stored in the memory, it implements a cross-architecture parallel scheduling method for heterogeneous computing resources as described in any one of claims 1-7.