Self-adaptive optimization method and device for preprocessing conjugate gradient solver

Abstract

The invention provides a self-adaptive optimization method for a preprocessing conjugate gradient solver, which comprises the following steps: generating a microkernel adaptive to a target heterogeneous processor according to a hardware feature library, and constructing a communication optimization template; adjusting the size of a line block and a dyeing strategy according to an input matrix feature and a hardware operation state, adapting to access optimization, calculating a color dependency relationship in real time through a color dependency model, and rearranging a calculation sequence to reduce convergence steps; matrix boundary features are identified, alignment column index vectors of a virtual boundary layer are inserted, and a data prefetching strategy is adjusted according to the shared memory utilization rate; a pipeline scheduling strategy is constructed according to hardware asynchronous flow characteristics, and a communication strategy is adaptively adjusted; and generating an execution strategy of the PCG solver. The invention further provides an adaptive optimization device of the preprocessing conjugate gradient solver, a storage medium and electronic equipment. Therefore, automatic adaptation and high-performance operation of the PCG solver in a heterogeneous platform and a dynamic scene are realized.

Description

Technical Field

[0001] This invention relates to the field of high-performance computing optimization technology, and in particular to an adaptive optimization method, apparatus, storage medium, and electronic device for a preprocessing conjugate gradient solver. Background Technology

[0002] The preconditioned conjugate gradient (PCG) algorithm is a core technology for solving large-scale symmetric positive definite sparse linear equation systems, and is widely used in major scientific and engineering fields such as climate simulation, fluid mechanics, aerospace simulation, and molecular dynamics. With the development of heterogeneous computing technology, dedicated acceleration units, represented by GPUs (Graphics Processing Units) and DCUs (Deep Computing Units), have become the core computing power support for supercomputing systems, aiming to improve the computational performance and resource utilization of PCG solvers.

[0003] Traditional conjugate gradient solver optimization methods often employ static optimization strategies, performing parameter tuning and code solidification during the compilation phase for specific hardware architectures (such as specific GPU models) and fixed problem sizes. These methods typically rely on static presuppositions of hardware characteristics and problem scenarios, lacking adaptability to dynamic computing environments. However, in practical applications, the sparsity pattern of sparse matrices, grid size, and hardware resource load often exhibit dynamic characteristics, making it difficult for traditional static optimization methods to match the optimal computational strategy in real time, resulting in the performance potential not being fully realized.

[0004] Existing conjugate gradient solver optimization techniques are mainly designed for regular mesh structures and single hardware platforms. However, complex scenarios in real-world scientific computing (such as unstructured mesh fluid simulation and multi-scale coupled simulation) often involve irregular sparse matrices and heterogeneous hybrid architectures. Furthermore, acceleration units from different vendors (such as NVIDIA GPUs, AMD DCUs, and domestically developed DCUs) exhibit significant differences in core layout, memory access architecture, and instruction set characteristics. Existing optimization solutions are mostly hardware-specific designs, lacking cross-platform adaptability, leading to severe performance degradation of conjugate gradient solvers when migrating between different heterogeneous platforms.

[0005] With the advent of the exascale supercomputing era, the scale and complexity of computing tasks are growing exponentially. How to achieve dynamic adaptive optimization of conjugate gradient solvers on heterogeneous computing platforms, while balancing performance, versatility, and portability, has become a key technical challenge that urgently needs to be addressed in the field of high-performance computing.

[0006] Currently, most optimization methods for conjugate gradient solvers employ traditional static optimization techniques, which lack adaptability to dynamic computation scenarios and heterogeneous hardware environments. This is particularly true when dealing with large-scale sparse matrices and cross-platform migration, where significant limitations exist. The main problems and drawbacks are as follows:

[0007] (1) Insufficient adaptability of static optimization strategies: Traditional conjugate gradient solvers often determine fixed parallel strategies, block sizes, and memory access patterns during the compilation phase, relying on preset matrix characteristics and hardware parameters. When the sparsity pattern or grid size of the actual input matrix changes, or when hardware load fluctuates, static optimization parameters cannot be adjusted in real time, leading to decreased parallel efficiency, increased memory access conflicts, and performance bottlenecks. For example, a fixed block size will cause resource waste when dealing with small-scale matrices, and may lead to frequent data exchanges when processing large-scale matrices.

[0008] (2) Poor compatibility with heterogeneous hardware platforms: There are significant differences in the number of computing cores, shared memory architecture, memory bandwidth, and instruction set characteristics of different heterogeneous processors (such as the Tensor Core of NVIDIA GPUs and the computing cluster architecture of domestic DCUs). Existing optimization solutions are mostly customized for specific hardware and have not formed a unified adaptive adaptation mechanism. This results in the need for a lot of manual tuning when the PCG solver is migrated across platforms, and it is difficult to fully utilize the performance potential of the target hardware. For example, shared memory access strategies optimized for GPUs may cause serious bank conflicts on DCU platforms.

[0009] (3) Imbalance between parallelism and convergence: One of the core bottlenecks of conjugate gradient solvers is the efficient execution of preprocessing operators. This invention focuses on the commonly used SYMGS (Symmetric Gauss-Seidel Iteration). Unlike Jacobi preprocessing, which has a natural advantage in parallelism, SYMGS has strong data dependencies. Traditional parallel optimization methods (such as red-black coloring) improve parallelism by sacrificing some data dependencies, but this often leads to an increase in the number of convergence steps, offsetting the benefits of parallelization. Existing technologies lack a mechanism for dynamically balancing parallelism and convergence, and cannot adjust optimization strategies according to real-time computation status. Performance degradation is particularly significant in large-scale parallel scenarios.

[0010] (4) Insufficient synergistic optimization of communication and computation: In large-scale parallel conjugate gradient solvers, communication operations such as inter-process boundary data exchange (Exchange Halo) and global reduction (AllReduce) have significant overhead. Existing technologies mostly adopt fixed communication strategies and do not make full use of the asynchronous execution characteristics of hardware to achieve deep overlap between computation and communication, resulting in communication latency that cannot be effectively masked and parallel efficiency decreasing sharply with the growth of node size.

[0011] In conclusion, the existing technology obviously has inconveniences and defects in practical use, so it is necessary to improve it. Summary of the Invention

[0012] To address the aforementioned shortcomings, the present invention aims to provide an adaptive optimization method, apparatus, storage medium, and electronic device for preprocessing conjugate gradient solvers, which enables automatic adaptation and high-performance operation of PCG solvers on heterogeneous platforms and in dynamic scenarios.

[0013] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0014] In a first aspect, embodiments of the present invention provide an adaptive optimization method for preprocessing a conjugate gradient solver, comprising:

[0015] The static pre-optimization step generates a microkernel adapted to the target heterogeneous processor based on a preset hardware feature library, and constructs a communication optimization template based on hardware interconnect characteristics.

[0016] The line block coloring and convergence control steps dynamically adjust the line block size and coloring strategy based on the real-time input matrix characteristics and hardware operating status, and dynamically adapt to memory access optimization. By constructing a color dependency model, the color dependency relationship is calculated in real time, and the calculation order is dynamically rearranged to reduce the number of convergence steps.

[0017] The memory access optimization steps include identifying matrix boundary features, dynamically inserting aligned column index vectors of the virtual boundary layer, and adjusting the data prefetching strategy based on the feedback of shared memory utilization to achieve shared memory reuse.

[0018] The communication-computing collaborative scheduling steps involve constructing a dynamic pipeline scheduling strategy based on the asynchronous flow characteristics of hardware, and adaptively adjusting the communication packet size and data exchange timing according to communication latency and computing load.

[0019] The execution strategy deployment steps generate an execution strategy for the preprocessed conjugate gradient solver based on the microkernel, the communication optimization template, the line block size and coloring strategy, the color dependency model, and the pipeline scheduling strategy.

[0020] According to the adaptive optimization method for preprocessing conjugate gradient solvers of the present invention, the static pre-optimization step further includes:

[0021] The hardware feature library construction sub-step involves performing feature analysis on the target heterogeneous processor, collecting predetermined hardware parameters, and constructing a standardized hardware feature library.

[0022] The pre-generation microkernel sub-step automatically generates the microkernel adapted to the target heterogeneous processor based on the hardware feature library and a predetermined microkernel generation framework.

[0023] The pre-set communication optimization template sub-step involves pre-setting multiple communication optimization templates based on the hardware interconnection characteristics of different hardware.

[0024] According to the adaptive optimization method for the preprocessed conjugate gradient solver of the present invention, the line block coloring and convergence control steps further include:

[0025] The features of the input matrix are extracted in real time, while the hardware operating status is monitored.

[0026] Based on the real-time characteristics of the input matrix and the hardware operating status, a matching line block size is selected from the pre-generated template, and a parallel execution strategy is generated through a hash coloring algorithm to balance data locality and parallelism.

[0027] By constructing a color dependency model, the color dependency relationship between different colors is calculated, and a predetermined correlation ranking algorithm is used to adjust the calculation order to reduce the number of convergence steps.

[0028] Real-time monitoring of iterative convergence speed, adaptive adjustment of coloring granularity, and balance between parallelism and convergence.

[0029] According to the adaptive optimization method for the preprocessed conjugate gradient solver of the present invention, the memory access optimization step further includes:

[0030] Automatically identify the matrix boundary features and dynamically insert the alignment column index vector of the virtual boundary layer;

[0031] Based on the feedback on shared memory utilization, the data prefetching strategy is dynamically adjusted to achieve multi-level reuse of solution vectors;

[0032] The thread access mode is dynamically adjusted based on real-time memory access monitoring data.

[0033] According to the adaptive optimization method for the preprocessed conjugate gradient solver of the present invention, the communication-computation cooperative scheduling step further includes:

[0034] Based on local computing and boundary communication tasks, the pipeline scheduling strategy is constructed according to the asynchronous flow characteristics of hardware.

[0035] Based on communication latency and computational load, the size of the communication packet and the timing of data exchange are adaptively adjusted, and a redundant communication pruning mechanism is automatically triggered to prune redundant communication.

[0036] According to the adaptive optimization method for preprocessing conjugate gradient solvers of the present invention, after the execution strategy deployment step, the method further includes:

[0037] The performance monitoring and feedback process involves analyzing key performance indicators collected in real time using a predetermined performance evaluation model to obtain performance evaluation information.

[0038] The adaptive iterative optimization step dynamically adjusts performance optimization parameters and forms a historical optimization knowledge base based on the performance evaluation information, providing an initial strategy for subsequent similar tasks.

[0039] According to the adaptive optimization method of the preprocessing conjugate gradient solver of the present invention, the core optimization of the microkernel includes: optimizing instruction scheduling by integrating hardware instruction set characteristics, avoiding shared memory storage conflicts by adopting thread reordering and address mapping strategies, and / or introducing a multi-stage pipeline mechanism to achieve parallel computation and memory access, thereby masking memory access latency;

[0040] The communication optimization templates include: a remote direct memory access direct data transmission template, an asynchronous stream communication scheduling template, and / or redundant communication pruning rules;

[0041] The input matrix features include: matrix dimension, sparsity mode, and / or computational precision;

[0042] The hardware operating status includes: computing core load, shared memory utilization, video memory bandwidth usage, and / or network communication latency.

[0043] The execution strategy of the PCG solver includes: microkernel selection, parallel thread partitioning, memory access optimization configuration and / or communication scheduling;

[0044] The key performance indicators include: single-card performance, floating-point efficiency, memory access bandwidth utilization, communication latency and / or convergence steps;

[0045] The performance optimization parameters include: block size, coloring strategy, and / or communication scheduling timing.

[0046] In a second aspect, embodiments of the present invention provide an adaptive optimization apparatus for a preprocessed conjugate gradient solver constructed based on any one of the methods described above, the apparatus comprising:

[0047] The static pre-optimization module is used to generate a microkernel adapted to the target heterogeneous processor based on a preset hardware feature library, and to build a communication optimization template based on hardware interconnect characteristics.

[0048] The line block coloring and convergence control module is used to dynamically adjust the line block size and coloring strategy based on the real-time input matrix features and hardware operating status, and dynamically adapt to memory access optimization. It calculates color dependency relationships in real time by constructing a color dependency model and dynamically rearranges the calculation order to reduce the number of convergence steps.

[0049] The memory access optimization module is used to identify matrix boundary features, dynamically insert the alignment column index vector of the virtual boundary layer, and adjust the data prefetching strategy based on the feedback of shared memory utilization to achieve shared memory reuse.

[0050] The communication-computing collaborative scheduling module is used to construct dynamic pipeline scheduling strategies based on the asynchronous flow characteristics of hardware, and adaptively adjust the communication packet size and data exchange timing according to communication latency and computing load.

[0051] The execution strategy deployment module is used to generate an execution strategy for the preprocessed conjugate gradient solver based on the microkernel, the communication optimization template, the line block size and coloring strategy, the color dependency model, and the pipeline scheduling strategy.

[0052] Thirdly, embodiments of the present invention provide a storage medium for storing a computer program for performing any of the methods described herein.

[0053] Fourthly, embodiments of the present invention provide an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement any of the methods described above.

[0054] This invention provides an adaptive optimization technique for a preprocessed conjugate gradient solver, comprising:

[0055] (1) Multi-dimensional static pre-optimization framework. In the static optimization stage, a conjugate gradient solver pre-optimization system for heterogeneous processors is constructed, which includes three core aspects: First, based on the hardware feature library, a high-performance microkernel adapted to the target heterogeneous processor (GPU / DCU) is automatically generated, and instruction scheduling is optimized by integrating hardware instruction set characteristics; second, parallel strategy templates are pre-generated through line block partitioning and hash coloring algorithms to balance data locality and parallelism; third, a communication optimization template library is constructed based on hardware interconnection characteristics, and asynchronous communication and computation overlap schemes are preset for the hardware interconnection characteristics of different hardware to provide a foundation for dynamic optimization. Thus, hardware adaptation and basic optimization are completed in advance, avoiding redundant computation overhead at runtime and improving optimization efficiency.

[0056] (2) Dynamic line block coloring and convergence control mechanism. As the core of dynamic optimization, the line block size and coloring strategy are dynamically adjusted based on the real-time characteristics of the input matrix (sparse mode, grid size) and the hardware operating status. It also dynamically adapts to memory access optimization by constructing a color dependency model to calculate color dependencies in real time and dynamically rearranging the calculation order to reduce the number of convergence steps. Simultaneously, it adjusts the parallel granularity based on hardware load feedback to avoid resource waste or load imbalance. Thus, a dynamic balance between parallelism and convergence is achieved, maximizing parallel efficiency while ensuring solution accuracy.

[0057] (3) Virtual boundary memory access optimization and shared memory reuse technology. This key technology is applicable to structured grid problems. It can dynamically identify matrix boundary features, dynamically insert alignment column index vectors of the virtual boundary layer, and adjust the data prefetching strategy based on the feedback of shared memory utilization to achieve shared memory reuse. Combined with the multi-level reuse strategy of shared memory to optimize the memory access mode, the data prefetching strategy and cache allocation scheme are adjusted based on real-time memory access monitoring data to avoid conflicts in shared memory banks. As a result, better alignment vector memory access is achieved, while making full use of shared memory and significantly improving memory access efficiency.

[0058] (4) Asynchronous communication-computation collaborative scheduling mechanism. Local computation and boundary communication tasks are dynamically divided, and a dynamic pipeline scheduling strategy is constructed based on the asynchronous flow characteristics of hardware; communication latency and computation load are monitored in real time, and the communication packet size and data exchange timing are adaptively adjusted to achieve deep overlap between computation and communication; at the same time, redundant communication such as zero vectors is automatically pruned to reduce communication overhead. As a result, communication latency is better masked and the efficiency of large-scale parallelism is improved.

[0059] (5) Execution strategy deployment mechanism. Based on the above static pre-optimization template and dynamic adjustment strategy, the execution strategy of the final preprocessed conjugate gradient solver is generated.

[0060] This invention addresses the problems of poor adaptability of traditional conjugate gradient solvers on heterogeneous processors, unstable performance in dynamic scenarios, and severe efficiency degradation in large-scale parallelism. It proposes a two-stage optimization method integrating static pre-optimization and dynamic adaptive adjustment, achieving automatic adaptation and high-performance operation of the PCG solver on heterogeneous platforms and in dynamic scenarios. This invention utilizes a multi-dimensional static pre-optimization framework to pre-compile hardware characteristic adaptation and generate basic optimization templates, reducing runtime optimization overhead. Dynamic line block coloring and convergence control mechanisms resolve the imbalance between parallelism and convergence, ensuring a balance between accuracy and efficiency. Virtual boundary memory access optimization technology improves memory access efficiency, significantly enhancing resource utilization. An asynchronous communication-computation collaborative scheduling mechanism effectively masks communication latency, ensuring scalability in large-scale parallel scenarios. This invention significantly improves the automation and versatility of conjugate gradient solver optimization, reduces the migration cost to heterogeneous platforms, and provides an efficient solution for solving large-scale sparse linear equation systems in scientific computing, engineering simulation, and other fields, demonstrating significant practical value in promoting the development of high-performance computing applications. Attached Figure Description

[0061] Figure 1 This is a flowchart illustrating the adaptive optimization method for the preprocessing conjugate gradient solver provided in Embodiment 1 of the present invention;

[0062] Figure 2 This is a flowchart illustrating the adaptive optimization method for the preprocessing conjugate gradient solver provided in Embodiment 2 of the present invention;

[0063] Figure 3 This is a schematic diagram of the adaptive optimization device for the preprocessing conjugate gradient solver provided in Embodiment 3 of the present invention;

[0064] Figure 4 This is a schematic diagram of the adaptive optimization device for the preprocessing conjugate gradient solver provided in Embodiment 4 of the present invention;

[0065] Figure 5 This is a schematic diagram of the structure of the electronic device provided in Embodiment 5 of the present invention. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0067] It should be noted that references to "an embodiment," "embodiment," "example embodiment," etc., in this specification refer to the described embodiment including specific features, structures, or characteristics, but not every embodiment must include these specific features, structures, or characteristics. Furthermore, such expressions do not refer to the same embodiment. Moreover, when describing specific features, structures, or characteristics in conjunction with embodiments, whether or not explicitly described, it is indicated that incorporating such features, structures, or characteristics into other embodiments is within the knowledge of those skilled in the art.

[0068] Furthermore, certain terms are used in the specification and subsequent claims to refer to specific components or parts. Those skilled in the art will understand that manufacturers may use different names or terms to refer to the same component or part. This specification and subsequent claims do not distinguish components or parts by differences in name, but rather by differences in function. The terms "comprising" and "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "including but not limited to." Additionally, the term "connection" here includes any direct and indirect electrical connection means. Indirect electrical connection means include connections made through other means.

[0069] This invention provides a dynamic adaptive optimization method for conjugate gradient solvers for heterogeneous processors, aiming to solve problems such as poor static adaptability, difficulty in cross-platform migration, imbalance between parallelism and convergence, and inability to effectively mask communication overhead in traditional conjugate gradient solver optimization, and to achieve automatic adaptation and performance tuning of conjugate gradient solvers under heterogeneous computing platforms.

[0070] The adaptive optimization method for the preprocessing conjugate gradient solver provided in this invention will be described in detail below with reference to the accompanying drawings and through specific embodiments and application scenarios.

[0071] In the optimization practice of conjugate gradient solvers on existing supercomputing platforms, it has been found that traditional static optimization methods are difficult to adapt to the hardware characteristics of heterogeneous processors and dynamically changing computing scenarios, especially when dealing with large-scale sparse matrices. The contradiction between parallel efficiency and convergence performance, as well as the imbalance between communication and computation, are prominent issues. Specific technical challenges are: first, how to dynamically explore the parallel potential of SYMGS iterations while ensuring convergence accuracy, and balance parallelism and convergence; second, how to build a cross-platform adaptive mechanism to automatically match the hardware characteristics of different heterogeneous processors and avoid manual tuning; and third, how to achieve dynamic coordination between computation and communication to effectively mask communication latency in large-scale parallel scenarios.

[0072] To address the aforementioned issues, this invention proposes a two-stage conjugate gradient solver optimization framework that integrates static pre-optimization and dynamic adaptive adjustment. Through core technologies such as line block coloring dynamic parallelism, virtual boundary memory access optimization, and asynchronous communication scheduling, it achieves high performance and high portability of the conjugate gradient solver on heterogeneous platforms.

[0073] Figure 1 This is a flowchart illustrating the adaptive optimization method for a preprocessed conjugate gradient solver provided in Embodiment 1 of the present invention. The method includes:

[0074] Step S101, static pre-optimization step, generates a microkernel adapted to the target heterogeneous processor based on the preset hardware feature library, and constructs a communication optimization template based on the hardware interconnection characteristics.

[0075] Preferably, the core optimizations of the microkernel include: optimizing instruction scheduling by integrating hardware instruction set features, avoiding shared memory conflicts by adopting thread reordering and address mapping strategies, and / or introducing a multi-level pipeline mechanism to achieve parallel computation and memory access, masking memory access latency, etc.

[0076] Preferably, the communication optimization template includes: a remote direct memory access direct data transmission template, an asynchronous stream communication scheduling template, and / or redundant communication pruning rules, etc.

[0077] Preferably, the static pre-optimization step further includes:

[0078] The hardware feature library construction sub-step involves performing feature analysis on the target heterogeneous processor, collecting predetermined hardware parameters, and constructing a standardized hardware feature library.

[0079] The pre-generated microkernel sub-step automatically generates a microkernel adapted to the target heterogeneous processor based on a hardware feature library and a predetermined microkernel generation framework.

[0080] The pre-set communication optimization template sub-step involves pre-setting multiple communication optimization templates based on the hardware interconnection characteristics of different hardware.

[0081] Step S102, line block coloring and convergence control step, dynamically adjusts the line block size and coloring strategy based on the real-time input matrix characteristics and hardware operating status, and dynamically adapts to memory access optimization. It calculates the color dependency relationship in real time by constructing a color dependency model and dynamically rearranges the calculation order to reduce the number of convergence steps.

[0082] Preferably, the input matrix features include: matrix dimension, sparse pattern, and / or computational precision, etc.

[0083] Preferably, the hardware operating status includes: computing core load, shared memory utilization, video memory bandwidth usage, and / or network communication latency, etc.

[0084] Preferably, the line block staining and convergence regulation steps further include:

[0085] (21) Extract the input matrix features of the input matrix in real time and monitor the hardware operation status at the same time.

[0086] (22) Based on the real-time input matrix characteristics and hardware operating status, select the matching line block size from the pre-generated template, and generate a parallel execution strategy through the hash coloring algorithm to balance data locality and parallelism.

[0087] (23) By constructing a color dependency model, the color dependency relationship between different colors is calculated, and a predetermined correlation ranking algorithm is used to adjust the calculation order to reduce the number of convergence steps.

[0088] (24) Monitor the iteration convergence speed in real time, adaptively adjust the coloring granularity, and balance parallelism and convergence.

[0089] Step S103, memory access optimization step, identifies matrix boundary features, dynamically inserts the alignment column index vector of the virtual boundary layer, and adjusts the data prefetching strategy based on the feedback of shared memory utilization to achieve shared memory reuse.

[0090] Preferably, the memory access optimization step further includes:

[0091] (31) Automatically identify matrix boundary features and dynamically insert the alignment column index vector of the virtual boundary layer.

[0092] (32) Based on the feedback of shared memory utilization, the data prefetching strategy is dynamically adjusted to realize multi-level reuse of solution vectors.

[0093] (33) Adjust the thread access mode dynamically based on real-time memory access monitoring data.

[0094] Step S104, the communication-computing collaborative scheduling step, constructs a dynamic pipeline scheduling strategy based on the asynchronous flow characteristics of hardware, and adaptively adjusts the communication packet size and data exchange timing based on communication latency and computing load.

[0095] Preferably, the communication-computing collaborative scheduling step further includes:

[0096] (41) Based on the local computing and boundary communication tasks, construct a pipeline scheduling strategy according to the asynchronous flow characteristics of hardware.

[0097] (42) Based on communication delay and computing load, adaptively adjust the size of communication packets and the timing of data exchange, and automatically trigger the redundant communication pruning mechanism to prune redundant communication.

[0098] Step S105: Execute the strategy deployment step, and generate the execution strategy for the preprocessed conjugate gradient solver based on the microkernel, communication optimization template, line block size and coloring strategy, color dependency model, and pipeline scheduling strategy.

[0099] Preferably, the execution strategy of the PCG solver includes: microkernel selection, parallel thread partitioning, memory access optimization configuration and / or communication scheduling, etc.

[0100] The key technical points of this invention include:

[0101] Key Point 1: Multi-dimensional static pre-optimization framework.

[0102] (1) Technology: In the static optimization stage, a pre-optimization system for conjugate gradient solvers for heterogeneous processors is constructed. The core includes three aspects: First, a high-performance microkernel adapted to the target acceleration unit (GPU / DCU) is automatically generated based on the hardware feature library, and instruction scheduling is optimized by integrating hardware instruction set characteristics; Second, parallel strategy templates are pre-generated through line block partitioning and hash coloring algorithms to balance data locality and parallelism; Third, a communication optimization template library is constructed, and asynchronous communication and computation overlap schemes are preset for the hardware interconnection characteristics of different hardware to provide a basis for dynamic optimization.

[0103] (2) Effect: Hardware adaptation and basic optimization are completed in advance, avoiding repeated calculation overhead during runtime and improving optimization efficiency.

[0104] Key Point 2: Dynamic line block coloring and convergence regulation mechanism.

[0105] (1) Technology: As the core of dynamic optimization, the line block size and coloring strategy are dynamically adjusted based on the real-time input matrix characteristics (sparse mode, grid size) and hardware operating status. The color dependency relationship is calculated in real time by constructing a dependency model, and the calculation order is dynamically rearranged to reduce the number of convergence steps; at the same time, the parallel granularity is adjusted based on hardware load feedback to avoid resource waste or load imbalance.

[0106] (2) Effect: Achieve dynamic balance between parallelism and convergence, and maximize parallel efficiency while ensuring solution accuracy.

[0107] Key Point 3: Virtual Boundary Memory Access Optimization and Shared Memory Reuse Technology.

[0108] (1) Technology: This key technology is applicable to structured grid problems. It can dynamically identify matrix boundary features, automatically insert virtual boundary layers to align column index vectors, and optimize memory access mode by combining shared memory multi-level reuse strategy. Based on real-time memory access monitoring data, it adjusts data prefetching strategy and cache allocation scheme to avoid shared memory bank conflicts.

[0109] (2) Effect: Better alignment of vector memory access, while making full use of shared memory, significantly improving memory access efficiency.

[0110] Key Point 4: Asynchronous Communication-Computation Co-scheduling Mechanism.

[0111] (1) Technology: Dynamically divide local computing and boundary communication tasks, and construct a dynamic pipeline scheduling strategy based on the asynchronous flow characteristics of hardware; monitor communication latency and computing load in real time, and adaptively adjust the size of communication packets and the timing of data exchange to achieve deep overlap between computing and communication; at the same time, automatically prune redundant communication such as zero vectors to reduce communication overhead.

[0112] (2) Effect: Better masking of communication delays and improving the efficiency of large-scale parallel processing.

[0113] This invention addresses the problems of poor adaptability of traditional conjugate gradient solvers on heterogeneous processors, unstable performance in dynamic scenarios, and severe efficiency degradation in large-scale parallelism. It proposes a two-stage optimization method that integrates static pre-optimization and dynamic adaptive adjustment, thereby achieving automatic adaptation and high-performance operation of the conjugate gradient solver on heterogeneous platforms and in dynamic scenarios.

[0114] Through a multi-dimensional static pre-optimization framework, hardware feature adaptation and basic optimization template generation are completed in advance, reducing runtime optimization overhead; dynamic line block coloring and convergence control mechanisms solve the imbalance between parallelism and convergence, ensuring a balance between accuracy and efficiency; virtual boundary memory access optimization technology optimizes memory access efficiency and significantly improves resource utilization; asynchronous communication-computation collaborative scheduling mechanism effectively masks communication latency and ensures scalability in large-scale parallel scenarios.

[0115] This invention has been verified on heterogeneous processors such as NVIDIA V100 GPU, Hygon Z100 / BW DCU and supercomputing platforms such as Dawning 7000. Experimental results show that it can be adapted to different hardware platforms without manual parameter adjustment and has good cross-platform portability and dynamic adaptability.

[0116] This invention significantly improves the automation and versatility of conjugate gradient solver optimization, reduces the migration cost of heterogeneous platforms, and provides an efficient solution for solving large-scale sparse linear equation systems in fields such as scientific computing and engineering simulation. It has great practical value for promoting the development of high-performance computing applications.

[0117] Figure 2 This is a flowchart illustrating the adaptive optimization method for the preprocessed conjugate gradient solver provided in Embodiment 2 of the present invention. The present invention, considering the hardware characteristics of heterogeneous processors and the dynamic computational requirements of the conjugate gradient solver, proposes an input-adaptive conjugate gradient solver optimization method, including:

[0118] Step S201, static pre-optimization step, generates a microkernel adapted to the target heterogeneous processor based on the preset hardware feature library, and constructs a communication optimization template based on the hardware interconnection characteristics.

[0119] Preferably, the static pre-optimization step further includes:

[0120] The hardware feature extraction step extracts key hardware features from the input matrix in real time during runtime.

[0121] Preferably, the key hardware features include matrix dimensions (m, n, k), sparse mode, and computational precision (FP32 / FP64); at the same time, the hardware operating status is monitored, including the computational core load, shared memory utilization, video memory bandwidth usage, and network communication latency.

[0122] Preferably, the static pre-optimization step further includes:

[0123] (11) The hardware feature library construction sub-step firstly involves a comprehensive feature analysis of the target heterogeneous processor (such as GPU, DCU) and the collection of predetermined hardware parameters, including: number of computing cores, size of shared memory and bank partitioning, video memory bandwidth, asynchronous stream feature support, instruction set support (such as matrix multiplication instructions, vector operation instructions), network interconnection features (bandwidth, latency), etc., to construct a standardized hardware feature library and provide data support for subsequent optimization.

[0124] (12) The pre-generation microkernel sub-step automatically generates a microkernel adapted to the target heterogeneous processor based on a hardware feature library and a predetermined microkernel generation framework. This includes core operator templates (such as SPMV, SYMGS, DDOT, WAXPBY, etc.). Core optimizations include: optimizing instruction scheduling by integrating hardware instruction set features; avoiding shared memory bank conflicts by using thread reordering and address mapping strategies; and introducing a multi-level pipeline mechanism to achieve parallel computation and memory access, masking memory access latency. Corresponding parallel coloring templates are pre-generated for different possible block sizes (such as 16, 32, 64) to form a microkernel template library.

[0125] (13) Pre-set communication optimization template sub-step: Based on the hardware interconnection characteristics of different hardware, pre-set a variety of communication optimization templates, including RDMA (Remote Direct Memory Access) direct data transmission template, asynchronous stream communication scheduling template, redundant communication pruning rules (such as zero vector communication pruning conditions), etc., to provide a basis for dynamic communication scheduling.

[0126] Step S202, line block coloring and convergence control step, dynamically adjusts the line block size and coloring strategy according to the real-time input matrix characteristics and hardware operating status, and dynamically adapts to memory access optimization. Color dependency relationship is calculated in real time by constructing a color dependency model, and the calculation order is dynamically rearranged to reduce the number of convergence steps.

[0127] Preferably, the input matrix features include: matrix dimension, sparse pattern, and / or computational precision, etc.

[0128] Preferably, the hardware operating status includes: computing core load, shared memory utilization, video memory bandwidth usage, and / or network communication latency, etc.

[0129] Preferably, the line block staining and convergence regulation steps further include:

[0130] (21) Extract the input matrix features of the input matrix in real time and monitor the hardware operation status at the same time.

[0131] (22) Based on the real-time input matrix characteristics and hardware operating status, select the matching line block size from the pre-generated template, and generate a parallel execution strategy through the hash coloring algorithm to balance data locality and parallelism.

[0132] (23) By constructing a color dependency model, the color dependency relationship between different colors is calculated, and a predetermined correlation ranking algorithm is used to adjust the calculation order to reduce the number of convergence steps.

[0133] (24) Monitor the iteration convergence speed in real time, adaptively adjust the coloring granularity, and balance parallelism and convergence.

[0134] Step S203, memory access optimization step, identifies matrix boundary features, dynamically inserts the alignment column index vector of the virtual boundary layer, and adjusts the data prefetching strategy based on the feedback of shared memory utilization to achieve shared memory reuse.

[0135] Preferably, the memory access optimization step further includes:

[0136] (31) Automatically identify matrix boundary features and dynamically insert the alignment column index vector of the virtual boundary layer to optimize data access continuity.

[0137] (32) Based on the feedback of shared memory utilization, the data prefetching strategy is dynamically adjusted to realize multi-level reuse of solution vectors.

[0138] (33) Based on real-time memory access monitoring data, dynamically adjust the thread access mode to avoid memory bank conflicts.

[0139] Step S204, the communication-computing collaborative scheduling step, constructs a dynamic pipeline scheduling strategy based on the asynchronous flow characteristics of hardware, and adaptively adjusts the communication packet size and data exchange timing based on communication latency and computing load.

[0140] Preferably, the communication-computing collaborative scheduling step further includes:

[0141] (41) Based on local computing (internal point computing) and boundary communication tasks (e.g., ExchangeHalo, AllReduce), construct a dynamic pipeline scheduling strategy according to the asynchronous flow characteristics of hardware.

[0142] (42) Based on communication delay and computational load, the communication packet size and data exchange timing are adaptively adjusted to achieve deep overlap between computation and communication; the redundant communication pruning mechanism is automatically triggered to prune redundant communication, such as removing invalid communication operations such as zero vectors.

[0143] Step S205: Execute the strategy deployment step. Based on the static pre-optimization template and dynamic adjustment strategy, and according to the microkernel, communication optimization template, line block size and coloring strategy, color dependency model, and pipeline scheduling strategy, generate the final execution strategy of the preprocessed conjugate gradient solver.

[0144] Preferably, the execution strategy of the PCG solver includes: microkernel selection, parallel thread partitioning, memory access optimization configuration and / or communication scheduling scheme, etc., and the deployment and execution are completed through the execution engine.

[0145] Step S206, the performance monitoring and feedback step, involves collecting key performance indicators in real time using a hardware performance counter, and analyzing these indicators using a predetermined performance evaluation model to derive performance evaluation information. Preferably, the difference between actual performance and expected targets is compared using the performance evaluation model and the key performance indicators.

[0146] Preferably, the key performance indicators include: single-card performance, floating-point efficiency, memory access bandwidth utilization, communication latency and / or convergence steps, etc.

[0147] Step S207 is the adaptive iterative optimization step, which dynamically adjusts the performance optimization parameters based on the performance evaluation information and forms a historical optimization knowledge base to provide initial strategies for subsequent similar tasks.

[0148] Preferably, based on performance feedback data, optimization parameters are dynamically adjusted, including line block size, coloring strategy, and communication scheduling timing; the optimization results are associated with input features and hardware status and stored to form a historical optimization knowledge base, providing better initial strategies for subsequent similar tasks and continuously improving the optimization effect.

[0149] Preferably, the performance optimization parameters include: block size, coloring strategy, and / or communication scheduling timing, etc.

[0150] It should be noted that the adaptive optimization method for the preprocessed conjugate gradient solver provided in this embodiment of the invention can be executed by an electronic device, a apparatus, or a control module within that apparatus for executing the method. This embodiment of the invention uses an apparatus executing the method as an example to illustrate the adaptive optimization apparatus for the preprocessed conjugate gradient solver provided in this embodiment of the invention.

[0151] Figure 3 This is a schematic diagram of the adaptive optimization device for the preprocessing conjugate gradient solver provided in Embodiment 3 of the present invention. The device 100 includes a static pre-optimization module 10, a line block coloring and convergence control module 20, a memory access optimization module 30, a communication-computation cooperative scheduling module 40, and an execution strategy deployment module 50, wherein:

[0152] The static pre-optimization module 10 is used to generate a microkernel adapted to the target heterogeneous processor based on a preset hardware feature library, and to construct a communication optimization template based on hardware interconnection characteristics.

[0153] Preferably, the core optimizations of the microkernel include: optimizing instruction scheduling by integrating hardware instruction set features, avoiding shared memory conflicts by adopting thread reordering and address mapping strategies, and / or introducing a multi-level pipeline mechanism to achieve parallel computation and memory access, masking memory access latency, etc.

[0154] Preferably, the communication optimization template includes: a remote direct memory access direct data transmission template, an asynchronous stream communication scheduling template, and / or redundant communication pruning rules, etc.

[0155] Preferably, the static pre-optimization module 10 further performs the following:

[0156] (11) Perform characteristic analysis on the target heterogeneous processor, collect the predetermined hardware parameters, and construct a standardized hardware feature library.

[0157] (12) Based on the hardware feature library, automatically generate a microkernel adapted to the target heterogeneous processor through a predetermined microkernel generation framework.

[0158] (13) Based on the hardware interconnection characteristics of different hardware, a variety of communication optimization templates are preset.

[0159] The line block coloring and convergence control module 20 is used to dynamically adjust the line block size and coloring strategy according to the real-time input matrix characteristics and hardware operating status, and dynamically adapt to memory access optimization. It calculates the color dependency relationship in real time by constructing a color dependency model and dynamically rearranges the calculation order to reduce the number of convergence steps.

[0160] Preferably, the input matrix features include: matrix dimension, sparse pattern, and / or computational precision, etc.

[0161] Preferably, the hardware operating status includes: computing core load, shared memory utilization, video memory bandwidth usage, and / or network communication latency, etc.

[0162] Preferably, the line block coloring and convergence control module 20 further performs the following:

[0163] (21) Extract the input matrix features of the input matrix in real time and monitor the hardware operation status at the same time.

[0164] (22) Based on the real-time input matrix characteristics and hardware operating status, select the matching line block size from the pre-generated template, and generate a parallel execution strategy through the hash coloring algorithm to balance data locality and parallelism.

[0165] (23) By constructing a color dependency model, the color dependency relationship between different colors is calculated, and a predetermined correlation ranking algorithm is used to adjust the calculation order to reduce the number of convergence steps.

[0166] (24) Monitor the iteration convergence speed in real time, adaptively adjust the coloring granularity, and balance parallelism and convergence.

[0167] The memory access optimization module 30 is used to identify matrix boundary features, dynamically insert the alignment column index vector of the virtual boundary layer, and adjust the data prefetching strategy according to the feedback of shared memory utilization to realize shared memory reuse.

[0168] Preferably, the memory access optimization module 30 further performs the following:

[0169] (31) Automatically identify matrix boundary features and dynamically insert the alignment column index vector of the virtual boundary layer.

[0170] (32) Based on the feedback of shared memory utilization, the data prefetching strategy is dynamically adjusted to realize multi-level reuse of solution vectors.

[0171] (33) Adjust the thread access mode dynamically based on real-time memory access monitoring data.

[0172] The communication-computing collaborative scheduling module 40 is used to construct a dynamic pipeline scheduling strategy based on the asynchronous flow characteristics of the hardware, and to adaptively adjust the communication packet size and data exchange timing according to the communication latency and computing load.

[0173] Preferably, the communication-computing collaborative scheduling module 40 further performs:

[0174] (41) Based on the local computing and boundary communication tasks, construct a pipeline scheduling strategy according to the asynchronous flow characteristics of hardware.

[0175] (42) Based on communication delay and computing load, adaptively adjust the size of communication packets and the timing of data exchange, and automatically trigger the redundant communication pruning mechanism to prune redundant communication.

[0176] The execution strategy deployment module 50 is used to generate an execution strategy for the preprocessed conjugate gradient solver based on the microkernel, communication optimization template, block size and coloring strategy, color dependency model, and pipeline scheduling strategy.

[0177] Preferably, the execution strategy of the PCG solver includes: microkernel selection, parallel thread partitioning, memory access optimization configuration and / or communication scheduling, etc.

[0178] Figure 4 This is a schematic diagram of the adaptive optimization device for the preprocessing conjugate gradient solver provided in Embodiment 4 of the present invention. The device 100 includes a static pre-optimization module 10, a line block coloring and convergence control module 20, a memory access optimization module 30, a communication-computation cooperative scheduling module 40, an execution strategy deployment module 50, a performance monitoring and feedback module 60, and an adaptive iterative optimization module 70, wherein:

[0179] The static pre-optimization module 10 is used to generate a microkernel adapted to the target heterogeneous processor based on a preset hardware feature library, and to construct a communication optimization template based on hardware interconnection characteristics.

[0180] Preferably, the core optimizations of the microkernel include: optimizing instruction scheduling by integrating hardware instruction set features, avoiding shared memory conflicts by adopting thread reordering and address mapping strategies, and / or introducing a multi-level pipeline mechanism to achieve parallel computation and memory access, masking memory access latency, etc.

[0181] Preferably, the communication optimization template includes: a remote direct memory access direct data transmission template, an asynchronous stream communication scheduling template, and / or redundant communication pruning rules, etc.

[0182] Preferably, the static pre-optimization module 10 further performs the following:

[0183] (11) Perform characteristic analysis on the target heterogeneous processor, collect the predetermined hardware parameters, and construct a standardized hardware feature library.

[0184] (12) Based on the hardware feature library, automatically generate a microkernel adapted to the target heterogeneous processor through a predetermined microkernel generation framework.

[0185] (13) Based on the hardware interconnection characteristics of different hardware, a variety of communication optimization templates are preset.

[0186] The line block coloring and convergence control module 20 is used to dynamically adjust the line block size and coloring strategy according to the real-time input matrix characteristics and hardware operating status, and dynamically adapt to memory access optimization. It calculates the color dependency relationship in real time by constructing a color dependency model and dynamically rearranges the calculation order to reduce the number of convergence steps.

[0187] Preferably, the input matrix features include: matrix dimension, sparse pattern, and / or computational precision, etc.

[0188] Preferably, the hardware operating status includes: computing core load, shared memory utilization, video memory bandwidth usage, and / or network communication latency, etc.

[0189] Preferably, the line block coloring and convergence control module 20 further performs the following:

[0190] (21) Extract the input matrix features of the input matrix in real time and monitor the hardware operation status at the same time.

[0191] (22) Based on the real-time input matrix characteristics and hardware operating status, select the matching line block size from the pre-generated template, and generate a parallel execution strategy through the hash coloring algorithm to balance data locality and parallelism.

[0192] (23) By constructing a color dependency model, the color dependency relationship between different colors is calculated, and a predetermined correlation ranking algorithm is used to adjust the calculation order to reduce the number of convergence steps.

[0193] (24) Monitor the iteration convergence speed in real time, adaptively adjust the coloring granularity, and balance parallelism and convergence.

[0194] The memory access optimization module 30 is used to identify matrix boundary features, dynamically insert the alignment column index vector of the virtual boundary layer, and adjust the data prefetching strategy according to the feedback of shared memory utilization to realize shared memory reuse.

[0195] Preferably, the memory access optimization module 30 further performs the following:

[0196] (31) Automatically identify matrix boundary features and dynamically insert the alignment column index vector of the virtual boundary layer.

[0197] (32) Based on the feedback of shared memory utilization, the data prefetching strategy is dynamically adjusted to realize multi-level reuse of solution vectors.

[0198] (33) Adjust the thread access mode dynamically based on real-time memory access monitoring data.

[0199] The communication-computing collaborative scheduling module 40 is used to construct a dynamic pipeline scheduling strategy based on the asynchronous flow characteristics of the hardware, and to adaptively adjust the communication packet size and data exchange timing according to the communication latency and computing load.

[0200] Preferably, the communication-computing collaborative scheduling module 40 further performs:

[0201] (41) Based on the local computing and boundary communication tasks, construct a pipeline scheduling strategy according to the asynchronous flow characteristics of hardware.

[0202] (42) Based on communication delay and computing load, adaptively adjust the size of communication packets and the timing of data exchange, and automatically trigger the redundant communication pruning mechanism to prune redundant communication.

[0203] The execution strategy deployment module 50 is used to generate an execution strategy for the preprocessed conjugate gradient solver based on the microkernel, communication optimization template, block size and coloring strategy, color dependency model, and pipeline scheduling strategy.

[0204] Preferably, the execution strategy of the PCG solver includes: microkernel selection, parallel thread partitioning, memory access optimization configuration and / or communication scheduling, etc.

[0205] The performance monitoring and feedback module 60 analyzes the key performance indicators collected in real time through a predetermined performance evaluation model to obtain performance evaluation information.

[0206] Preferably, the difference between actual performance and expected target is compared through performance evaluation models and key performance indicators.

[0207] Preferably, the key performance indicators include: single-card performance, floating-point efficiency, memory access bandwidth utilization, communication latency and / or convergence steps, etc.

[0208] The adaptive iterative optimization module 70 dynamically adjusts performance optimization parameters and forms a historical optimization knowledge base based on performance evaluation information, providing initial strategies for subsequent similar tasks.

[0209] Preferably, the performance optimization parameters include: block size, coloring strategy, and / or communication scheduling timing, etc.

[0210] The adaptive optimization device for the preprocessing conjugate gradient solver provided in this embodiment of the invention can achieve... Figures 1-2 The various processes implemented in the example of the adaptive optimization method for the preprocessing conjugate gradient solver shown will not be repeated here to avoid repetition.

[0211] The adaptive optimization device for preprocessing conjugate gradient solvers provided in this invention employs a multi-dimensional static pre-optimization framework to pre-compile hardware characteristic adaptation and generate basic optimization templates, reducing runtime optimization overhead. Dynamic line block coloring and convergence control mechanisms address the imbalance between parallelism and convergence, ensuring a balance between accuracy and efficiency. Virtual boundary memory access optimization technology improves memory access efficiency, significantly enhancing resource utilization. An asynchronous communication-computation collaborative scheduling mechanism effectively masks communication latency, ensuring scalability in large-scale parallel scenarios. This invention significantly improves the automation and versatility of conjugate gradient solver optimization, reduces migration costs to heterogeneous platforms, and provides an efficient solution for solving large-scale sparse linear equation systems in scientific computing, engineering simulation, and other fields, demonstrating significant practical value in promoting the development of high-performance computing applications.

[0212] The present invention also provides a storage medium for storing, for example, Figures 1-2 A computer program for any of the adaptive optimization methods of the preprocessing conjugate gradient solver. For example, computer program instructions, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the present invention through the operation of the computer, achieving the same technical effect; to avoid repetition, these will not be elaborated here. The program instructions for invoking the methods of the present invention may be stored in a fixed or removable storage medium, and / or transmitted via data streams in broadcast or other signal carrying media, and / or stored in the storage medium of a computer device operating according to the program instructions.

[0213] According to one embodiment of the present invention, the present invention also provides such a Figure 5 The illustrated electronic device 400 may optionally include a storage medium 200 for storing a computer program and a processor 300 for executing the computer program. When the computer program is executed by the processor 300, it implements any of the aforementioned adaptive optimization methods for preprocessing conjugate gradient solvers, triggering the electronic device 400 to execute methods and / or technical solutions based on the foregoing embodiments, achieving the same technical effect. To avoid repetition, these methods will not be elaborated further here. It should be noted that the electronic devices in this embodiment include mobile electronic devices and non-mobile electronic devices. For example, mobile electronic devices may be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, super mobile personal computers, netbooks, or personal digital assistants, etc., while non-mobile electronic devices may be servers, network-attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This embodiment does not specifically limit the scope of the invention.

[0214] It should be noted that the present invention can be implemented in software and / or a combination of software and hardware, for example, using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In one embodiment, the software program of the present invention can be executed by a processor to implement the steps or functions described above. Similarly, the software program of the present invention (including associated data structures) can be stored in a computer-readable recording medium, such as RAM memory, a magnetic or optical drive, a floppy disk, or similar devices. Furthermore, some steps or functions of the present invention can be implemented in hardware, for example, as circuitry that works with a processor to perform the various steps or functions.

[0215] This invention can be implemented on a computer as a computer-based method, or in dedicated hardware, or a combination of both. Executable code or portions thereof for the method according to the invention can be stored on a computer program product. Examples of computer program products include memory devices, optical storage devices, integrated circuits, servers, online software, etc. Optionally, the computer program product includes non-transitory program code components stored on a computer-readable medium so as to execute the method according to the invention when the program product is executed on a computer.

[0216] In an optional embodiment, the computer program includes computer program code components adapted to perform all the steps of the method according to the invention when the computer program is run on a computer. Optionally, the computer program is embodied on a computer-readable medium.

[0217] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of the present invention is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0218] Of course, the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. An adaptive optimization method for preprocessing conjugate gradient solvers, characterized in that, include: The static pre-optimization step generates a microkernel adapted to the target heterogeneous processor based on a preset hardware feature library, and constructs a communication optimization template based on hardware interconnect characteristics. The line block coloring and convergence control steps dynamically adjust the line block size and coloring strategy based on the real-time input matrix characteristics and hardware operating status, and dynamically adapt to memory access optimization. By constructing a color dependency model, the color dependency relationship is calculated in real time, and the calculation order is dynamically rearranged to reduce the number of convergence steps. The memory access optimization steps include identifying matrix boundary features, dynamically inserting aligned column index vectors of the virtual boundary layer, and adjusting the data prefetching strategy based on the feedback of shared memory utilization to achieve shared memory reuse. The communication-computing collaborative scheduling steps involve constructing a dynamic pipeline scheduling strategy based on the asynchronous flow characteristics of hardware, and adaptively adjusting the communication packet size and data exchange timing according to communication latency and computing load. The execution strategy deployment steps generate an execution strategy for the preprocessed conjugate gradient solver based on the microkernel, the communication optimization template, the line block size and coloring strategy, the color dependency model, and the pipeline scheduling strategy.

2. The adaptive optimization method for the preprocessed conjugate gradient solver according to claim 1, characterized in that, The static pre-optimization step further includes: The hardware feature library construction sub-step involves performing feature analysis on the target heterogeneous processor, collecting predetermined hardware parameters, and constructing a standardized hardware feature library. The pre-generation microkernel sub-step automatically generates the microkernel adapted to the target heterogeneous processor based on the hardware feature library and a predetermined microkernel generation framework. The pre-set communication optimization template sub-step involves pre-setting multiple communication optimization templates based on the hardware interconnection characteristics of different hardware.

3. The adaptive optimization method for the preprocessed conjugate gradient solver according to claim 1, characterized in that, The line block coloring and convergence regulation steps further include: The features of the input matrix are extracted in real time, while the hardware operating status is monitored. Based on the real-time characteristics of the input matrix and the hardware operating status, a matching line block size is selected from the pre-generated template, and a parallel execution strategy is generated through a hash coloring algorithm to balance data locality and parallelism. By constructing a color dependency model, the color dependency relationship between different colors is calculated, and a predetermined correlation ranking algorithm is used to adjust the calculation order to reduce the number of convergence steps. Real-time monitoring of iterative convergence speed, adaptive adjustment of coloring granularity, and balance between parallelism and convergence.

4. The adaptive optimization method for the preprocessed conjugate gradient solver according to claim 2, characterized in that, The memory access optimization steps further include: Automatically identify the matrix boundary features and dynamically insert the alignment column index vector of the virtual boundary layer; Based on the feedback on shared memory utilization, the data prefetching strategy is dynamically adjusted to achieve multi-level reuse of solution vectors; The thread access mode is dynamically adjusted based on real-time memory access monitoring data.

5. The adaptive optimization method for the preprocessed conjugate gradient solver according to claim 2, characterized in that, The communication-computing collaborative scheduling step further includes: Based on local computing and boundary communication tasks, the pipeline scheduling strategy is constructed according to the asynchronous flow characteristics of hardware. Based on communication latency and computational load, the size of the communication packet and the timing of data exchange are adaptively adjusted, and a redundant communication pruning mechanism is automatically triggered to prune redundant communication.

6. The adaptive optimization method for the preprocessed conjugate gradient solver according to claim 2, characterized in that, Following the execution strategy deployment step, the following also includes: The performance monitoring and feedback process involves analyzing key performance indicators collected in real time using a predetermined performance evaluation model to obtain performance evaluation information. The adaptive iterative optimization step dynamically adjusts performance optimization parameters and forms a historical optimization knowledge base based on the performance evaluation information, providing an initial strategy for subsequent similar tasks.

7. The adaptive optimization method for the preprocessed conjugate gradient solver according to claim 2, characterized in that, The core optimizations of the microkernel include: optimizing instruction scheduling by integrating hardware instruction set features, avoiding shared memory storage conflicts by adopting thread reordering and address mapping strategies, and / or introducing a multi-level pipeline mechanism to achieve parallel computation and memory access, masking memory access latency; The communication optimization templates include: a remote direct memory access direct data transmission template, an asynchronous stream communication scheduling template, and / or redundant communication pruning rules; The input matrix features include: matrix dimension, sparsity mode, and / or computational precision; The hardware operating status includes: computing core load, shared memory utilization, video memory bandwidth usage, and / or network communication latency. The execution strategy of the PCG solver includes: microkernel selection, parallel thread partitioning, memory access optimization configuration and / or communication scheduling; The key performance indicators include: single-card performance, floating-point efficiency, memory access bandwidth utilization, communication latency and / or convergence steps; The performance optimization parameters include: block size, coloring strategy, and / or communication scheduling timing.

8. An adaptive optimization device for a preprocessed conjugate gradient solver constructed based on the method described in any one of claims 1 to 7, characterized in that, The device includes: The static pre-optimization module is used to generate a microkernel adapted to the target heterogeneous processor based on a preset hardware feature library, and to build a communication optimization template based on hardware interconnect characteristics. The line block coloring and convergence control module is used to dynamically adjust the line block size and coloring strategy based on the real-time input matrix features and hardware operating status, and dynamically adapt to memory access optimization. It calculates color dependency relationships in real time by constructing a color dependency model and dynamically rearranges the calculation order to reduce the number of convergence steps. The memory access optimization module is used to identify matrix boundary features, dynamically insert the alignment column index vector of the virtual boundary layer, and adjust the data prefetching strategy based on the feedback of shared memory utilization to achieve shared memory reuse. The communication-computing collaborative scheduling module is used to construct dynamic pipeline scheduling strategies based on the asynchronous flow characteristics of hardware, and adaptively adjust the communication packet size and data exchange timing according to communication latency and computing load. The execution strategy deployment module is used to generate an execution strategy for the preprocessed conjugate gradient solver based on the microkernel, the communication optimization template, the line block size and coloring strategy, the color dependency model, and the pipeline scheduling strategy.

9. A storage medium, characterized in that, Used to store a computer program for performing the method according to any one of claims 1 to 7.

10. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 7.

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