NPU fault-tolerant calculation method and system based on repeated execution of calculation core

Abstract

The invention relates to the technical field of chip fault tolerance, and discloses an NPU fault tolerance calculation method and system based on repeated execution of a calculation core. The method comprises the steps of receiving a to-be-executed program segment and input data corresponding to the to-be-executed program segment through a computing core; generating an initial execution state of the program segment; executing program segment calculation of the controlled path and generating a signature; executing a local fault-tolerant judgment task; re-executing the program segment based on a state rollback and signature comparison mechanism; and executing buffer release and task switching preparation operation. Compared with the prior art, the technical problems that in the prior art, an effective coping means for soft errors of a calculation path is lacked, and particularly under the condition that a register and an on-chip memory are shared in a multi-core NPU structure, and errors are possibly propagated in a cascading mode, efficient fault tolerance of specific program segment granularity cannot be achieved are solved. Due to the fact that the redundancy execution control mechanism and the signature comparison verification mechanism are introduced, the efficiency and stability of fault-tolerant calculation are improved.

Description

Technical Field

[0001] This invention relates to the field of chip fault tolerance technology, and in particular to an NPU fault-tolerant computing method and system based on repeated execution of the computing core. Background Technology

[0002] Currently, with the rapid evolution of AI chip architecture, dedicated Neural Processing Units (NPUs) have been widely deployed in applications such as smartphones, autonomous driving, edge computing, and high-performance servers. NPUs possess characteristics such as high parallelism, high throughput, and low power consumption, making them particularly suitable for the inference stage of deep learning models such as convolutional neural networks and Transformers. However, as process technology advances to 5nm and below, NPU chips, operating under conditions of high integration, high clock frequency, and high power density, become significantly more sensitive to soft errors or transient faults. Soft errors mainly originate from environmental radiation, metastable state transitions, electromagnetic interference, or transient power supply fluctuations. They typically do not cause permanent device damage, but can lead to unpredictable sudden changes in registers, ALU outputs, or intermediate memory data within the computation path. Because NPUs have a large number of shared register files, local SRAM caches, and on-chip network interconnects, a small error can rapidly propagate or even cascade amplify across multiple computing cores, causing sudden changes or irrecoverable errors in the neural network inference results.

[0003] Mainstream fault-tolerance methods include: using ECC (Error Correction Code) memory to repair single-bit or double-bit errors in storage units; and system-level redundancy structures, such as triple modular redundancy (TMR), dual-core execution comparison, or master-slave core mutual verification mechanisms. However, these solutions have significant shortcomings. For example, ECC solutions primarily protect memory and have no protection capability for logical units in the execution path; while system-level redundancy offers high reliability, it typically leads to a doubling of area resources or a sharp drop in performance-to-power ratio; furthermore, many operations in NPU inference tasks are fixed-point multiplication and addition or matrix operations, and in many cases, some output errors cannot be automatically tolerated or offset by subsequent layers. Especially in scenarios such as target detection, critical control path identification, industrial inspection, and medical inference, even the propagation of a single erroneous result can have serious consequences.

[0004] Therefore, there is an urgent need for an NPU fault-tolerant computing method based on repeated execution of the computing core, which can meet the requirements of local perception, autonomous verification and dynamic recalculation control of soft errors in the NPU execution path under the premise of controllable program segment granularity and acceptable redundancy overhead. Summary of the Invention

[0005] To address the aforementioned technical shortcomings, the purpose of this invention is to propose an NPU fault-tolerant computing method based on repeated execution of the computing core. This method aims to solve the problem of the lack of effective means to deal with soft errors in the computing path itself in the existing technology, especially the technical problem of not being able to achieve efficient fault tolerance at the granularity of specific program segments under the conditions of shared registers and on-chip memory in multi-core NPU architectures and the possibility of cascading error propagation.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention provides an NPU fault-tolerant computing method based on repeated execution of the computing core.

[0007] The NPU fault-tolerant computing method based on repeated execution of the computing core includes:

[0008] Step S10: Receive the i-th program segment to be executed via the NPU computing core. Corresponding program input data Based on the program segment to be executed Corresponding program input data A joint mechanism based on instruction dependency graph construction and data path activity identification is used to dynamically generate program segments to be executed. Initial execution state ;

[0009] Step S20: Based on the initial execution state A constraint mechanism based on register and memory differential tracing is used to define the program segment to be executed. The task is to execute the program segment and output the result of its first execution. Signature corresponding to the program segment ;

[0010] Step S30: Based on the first execution result of the program segment Signature corresponding to the program segment A fault-tolerant judgment task is performed using a local recalculation judgment mechanism based on a multi-condition triggering strategy, and a redundant calculation trigger flag is output. ;

[0011] Step S40: Calculate the trigger flag based on redundancy A combined mechanism based on state rollback and signature comparison is used to perform redundant recalculation and verification tasks, and outputs valid execution results that pass the verification.

[0012] Step S50: Based on the verified valid execution result, perform buffer release and task switching preparation operations using a context-aware data submission and control reclamation mechanism, and output the final updated status.

[0013] Preferably, in step S10, the initial execution state Including the current program counter value Current register set contents Local Memory area and program input data Associated memory fragment data Current task identifier and execution context .

[0014] Preferably, in step S20, based on the initial execution state A constraint mechanism based on register and memory differential tracing is used to define the program segment to be executed. The task is to execute the program segment and output the result of its first execution. Signature corresponding to the program segment The steps specifically include:

[0015] Step S201: Constructing the Register-Memory Differential Tracking Mapping Table: Initial Execution State The contents of the currently used register group in With Local Memory area and program input data Associated memory fragment data Establish an initial state snapshot, and based on the initial state snapshot, perform read / write access behavior collection tasks using a hardware-level or microarchitecture-level differential tagging mechanism, and output a read / write operation trace table. ;

[0016] Step S202: Limiting the path and buffering write operations: based on the read / write operation tracking table The path variables recorded in the code use a limited state variable access mechanism to execute the controllable path replay task, and output the program segment to control the path. Based on program segment control path Perform write-ahead buffered execution and output the first execution result of the program segment. ;

[0017] Step S203: Generating the signature corresponding to the program segment: based on the result of the first execution of the program segment A multi-factor signature mechanism based on execution path hashing and output fusion is used for signature calculation, and the signature corresponds to the output program segment. .

[0018] Preferably, in step S20, the program segment corresponds to a signature. The formula is expressed as:

[0019]

[0020] in, It is a collision-resistant hash function, SHA-256. Indicates the control path of the program segment; Input data into the program; This is the result of the first execution of the program segment.

[0021] Preferably, in step S30, the result of the first execution of the program segment is used as a basis. Signature corresponding to the program segment A fault-tolerant judgment task is performed using a local recalculation judgment mechanism based on a multi-condition triggering strategy, and a redundant calculation trigger flag is output. The steps specifically include:

[0022] Step S301: Status Trigger Signal Acquisition Stage: Acquire trigger-related status information, including the status of the current write buffer write volume. Does the program segment contain the status of the off-chip write operation flag? The status of the context switch signal for the current task And whether it is in a core synchronization blocking state Based on the trigger-related state information, a hybrid modeling approach using Boolean encoding based on term-by-term normalization is adopted to construct the trigger state vector. , ;

[0023] Step S302: Multi-factor weighted fusion stage: Introducing a weighted coefficient vector , ,in, To write pressure-sensitive factors; Protection priority factor for writing to external storage; This is a context switching priority factor; Multi-core synchronization consistency weighting factor; based on weighted coefficient vector and trigger state vector A fuzzy membership-driven weighted nonlinear combination method is used for fusion calculation, and the fusion activation trigger score is output. ;

[0024] Step S303: Trigger Flag Judgment Phase: Calculate the fusion activation trigger score. Compared with the preset trigger score threshold In comparison, if Then set the redundant calculation trigger flag. Otherwise, if Then set the redundant calculation trigger flag. .

[0025] Preferably, in step S30, the fusion activation trigger score is determined. The formula is expressed as:

[0026]

[0027] in, The weighted coefficient vector The j-th factor; For triggering state vector The j-th state vector; For dynamic fuzzy membership functions, including trapezoidal membership functions, Gaussian membership functions, and sigmoid membership functions, different flexible response models are constructed for different types of the j-th state vector.

[0028] Preferably, in step S40, the trigger flag is calculated based on redundancy. The steps for performing a redundant recalculation verification task using a joint mechanism based on state rollback and signature comparison, and outputting a valid execution result that has passed verification, specifically include:

[0029] Step S401: State rollback and reconstruction phase: If redundancy calculation triggers flag Then the redundant controller RCU is activated, and the redundant controller RCU retrieves the initial execution state. The contents of the register group Local Memory area and program input data Associated memory fragment data and the contents of the register group With memory fragment data Restore to the preset backup state and output the initial rollback state. ;

[0030] Step S402: Redundancy Recalculation and Signature Generation Stage: Based on the Initial Rollback State Re-execute step S20 and output the program segment rollback signature. ;

[0031] Step S403: Signature Comparison and Redundancy Control Judgment Stage: Rollback Signature Based on Program Segment Signature corresponding to the program segment The hash consistency check method is used to perform round-by-round comparison and judgment, and the result of the current round of verification is output. ;

[0032] If satisfied If the redundancy check passes, proceed to step S401 to perform a repeated rollback task until the redundancy check is satisfied. Or the preset maximum number of retries has been reached. Only then will the process terminate; finally, the output will show a valid execution result that has passed verification.

[0033] This invention also provides an NPU fault-tolerant computing system based on repeated execution of the computing core, comprising:

[0034] The task parsing and initial state generation module is used to receive the i-th program segment to be executed through the NPU computing core. Corresponding program input data Based on the program segment to be executed Corresponding program input data A joint mechanism based on instruction dependency graph construction and data path activity identification is used to dynamically generate program segments to be executed. Initial execution state ;

[0035] The execution and initial signature generation module is used to define the execution state based on the initial execution state. A constraint mechanism based on register and memory differential tracing is used to define the program segment to be executed. The task is to execute the program segment and output the result of its first execution. Signature corresponding to the program segment ;

[0036] The redundancy trigger judgment module is used to determine the result of the first execution of the program segment. Signature corresponding to the program segment A fault-tolerant judgment task is performed using a local recalculation judgment mechanism based on a multi-condition triggering strategy, and a redundant calculation trigger flag is output. ;

[0037] The redundant execution and signature comparison module is used to calculate the trigger flag based on redundancy. A combined mechanism based on state rollback and signature comparison is used to perform redundant recalculation and verification tasks, and outputs valid execution results that pass the verification.

[0038] The result submission and status reclamation module is used to perform buffer release and task switching preparation operations based on the verified valid execution results using a context-aware data submission and control reclamation mechanism, and output the final updated status.

[0039] The present invention also provides an NPU fault-tolerant computing device based on repeated execution of computing cores, comprising: a memory, a processor, and an NPU fault-tolerant computing program based on repeated execution of computing cores stored in the memory and executable on the processor. When the NPU fault-tolerant computing program based on repeated execution of computing cores is executed by the processor, it implements an NPU fault-tolerant computing method based on repeated execution of computing cores.

[0040] The present invention also provides a computer program product, including an NPU fault-tolerant computing program that is repeatedly executed based on a computing core. When the NPU fault-tolerant computing program that is repeatedly executed based on a computing core is executed by a processor, it implements the NPU fault-tolerant computing method that is repeatedly executed based on a computing core.

[0041] The beneficial effects of this invention are as follows: By introducing an initial state generation mechanism based on instruction dependency graph construction and data path activity identification, and combining it with a register and memory differential tracing execution path limitation mechanism, this invention achieves precise location of the potential soft error impact range at the program segment granularity without relying on external redundant hardware, effectively improving the accuracy of the fault tolerance mechanism and the efficiency of resource utilization.

[0042] This invention constructs a signature comparison-driven redundant recalculation verification mechanism, and combines it with a context-aware data submission and control recycling strategy to achieve dynamic autonomous fault-tolerant control of soft errors in critical paths. This avoids performance degradation and power consumption waste caused by global recalculation, and significantly improves the stability and response efficiency of the NPU in high reliability scenarios. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a flowchart illustrating the first embodiment of an NPU fault-tolerant computing method based on repeated execution of the computing core according to the present invention.

[0045] Figure 2 This is a schematic diagram of the NPU computing unit structure supporting fault-tolerant computing, representing a first embodiment of an NPU fault-tolerant computing method based on repeated execution of the computing core according to the present invention.

[0046] Figure 3 This is a schematic diagram of a device for an NPU fault-tolerant computing method based on repeated execution of the computing core according to the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Example 1: As Figure 1 The diagram shown is a flowchart of the first embodiment of the NPU fault-tolerant computing method based on repeated execution of the computing core according to the present invention. The first embodiment of the NPU fault-tolerant computing method based on repeated execution of the computing core according to the present invention is presented.

[0049] In the first embodiment, the NPU fault-tolerant computing method based on repeated execution of the computing core includes:

[0050] Step S10: Receive the i-th program segment to be executed via the NPU computing core. Corresponding program input data Based on the program segment to be executed Corresponding program input data A joint mechanism based on instruction dependency graph construction and data path activity identification is used to dynamically generate program segments to be executed. Initial execution state ;

[0051] It should be noted that the "joint mechanism based on instruction dependency graph construction and data path activity identification" refers to parsing the instruction sequence of the program segment to be executed into a control flow graph (CFG) and a data dependency graph (DDG) to identify the minimum computational path actually activated by the program segment under the current input data. This mechanism not only constructs a dynamic dependency chain from input variables to output results, but also combines active variable marking technology to annotate register accesses, memory block mappings, and input buffers.

[0052] Understandably, the technical effect of this step lies in replacing the traditional "full register / full memory" backup method based on fixed context snapshots with a "tailored state saving" method centered on the execution path. This mechanism significantly reduces the burden of state backup and recovery, and is particularly suitable for high-frequency asynchronous execution architectures in NPUs that use short program segments as scheduling units. Since the state may be quickly overwritten after each program segment is executed, recording only the key states in the active path helps with rapid subsequent location and rollback, and provides accurate initial conditions for redundant computations.

[0053] It should be understood that, compared to the unified context saving methods commonly used in existing technologies (such as full register file backup in thread-level context switches), the present invention constructs a minimal state set based on data activity and dependent path selectivity, significantly improving the real-time performance and resource efficiency of the soft error tolerance mechanism. With hardware support, hardware tracking of active path variables can be further implemented (e.g., using memory access tracking instructions, hardware active bit flags), thereby automating and reducing the latency of the state capture process, greatly reducing the recovery overhead before redundant computation is triggered.

[0054] For example, in a typical NPU inference task, a convolution weighted summation program segment uses only two registers and a local input buffer buf[0:7]. In traditional fault-tolerance mechanisms, the entire register file (e.g., 128 general-purpose registers) and the entire Local Memory image (e.g., 64KB) need to be saved, which incurs a backup burden of tens of KB. However, with the mechanism of this invention, the instruction dependency graph can identify that only the above two registers and the 64B input window need to be saved. In experiments, the state saving time was reduced by more than 82%, and the recovery latency was reduced by more than 75%, allowing the fault-tolerance process to complete state restoration and start redundant re-execution within one cycle, significantly improving the response efficiency under soft errors.

[0055] Step S20: Based on the initial execution state A constraint mechanism based on register and memory differential tracing is used to define the program segment to be executed. The task is to execute the program segment and output the result of its first execution. Signature corresponding to the program segment ;

[0056] It should be noted that the "register and memory differential tracing-based constraint mechanism" refers to setting the contents of the register set and local memory region to a protected state when using the initial state generated in step S10 as the starting point for program segment execution. By setting a read-only flag or hardware tracing flag, all read and write access behaviors are monitored. The differential tracing mechanism not only records the set of variables actually accessed in the program segment but also directs all write operations to the write buffer instead of directly writing to the original memory, thus effectively isolating potential erroneous write paths during the calculation process. After execution, the final output result, along with the input state data and control path recorded on the differential path, are used as input to calculate a unique signature for subsequent redundancy verification.

[0057] Understandably, by employing restricted execution and differential write isolation mechanisms, it is ensured that the output generated during the initial execution is significantly related to the path and has a clear dependency on the active input state. This structural constraint ensures the comparability and verifiability of subsequent signature-based result consistency judgments, preventing false errors caused by non-critical path variables. Especially in NPU execution environments with parallel scheduling of multiple program segments and rapid state switching, this mechanism provides a lightweight, context-aware method for defining result credibility.

[0058] For example, in a simulation experiment of executing a program segment for a standard CNN convolutional kernel, the method of this invention was compared with the traditional execution method. In the traditional method, when a multiply-accumulate instruction in the program segment causes a one-bit shift in the output result due to occasional voltage fluctuations, this minute deviation is not detected, and the erroneous result is directly written to on-chip shared memory, affecting subsequent inference paths for multiple channels. However, with the limited execution mechanism of this invention, this write does not enter actual memory but is only cached in the write buffer, and the generated signature is inconsistent with the normal path, triggering redundant recalculation and successfully detecting the error.

[0059] Step S30: Based on the first execution result of the program segment Signature corresponding to the program segment A fault-tolerant judgment task is performed using a local recalculation judgment mechanism based on a multi-condition triggering strategy, and a redundant calculation trigger flag is output. ;

[0060] It should be noted that the "local recalculation judgment mechanism based on multi-condition triggering strategy" means that after the program segment is executed for the first time, the result is not immediately assumed to be reliable. Instead, the result is comprehensively evaluated based on multiple judgment conditions dynamically driven by the current running state to determine whether there is a risk of soft error, thereby deciding whether to perform redundant calculation.

[0061] Understandably, by establishing a triggering model through a multi-condition weighted fusion mechanism, it is possible to perceive the stability of the program's execution context, resource consumption, and synchronization progress, thereby accurately triggering redundant computations while minimizing impact on the mainline performance. This mechanism is particularly suitable for NPU architectures with intensive asynchronous execution and frequent task context switching, significantly improving the sensitivity of soft error identification and the real-time performance of response.

[0062] It should be understood that, compared with traditional technologies that use fixed rules or single variables as the basis for error detection triggering, this invention introduces a fuzzy triggering strategy that integrates multiple dynamic operating indicators, giving the judgment logic stronger adaptability and expressive power. Specifically, this invention achieves dynamic adjustment of trigger sensitivity by constructing a multi-condition state vector and adjustable weight factors, which can avoid false triggering caused by oversensitivity and also avoid the problem of false omissions caused by rigid thresholds.

[0063] Step S40: Calculate the trigger flag based on redundancy A combined mechanism based on state rollback and signature comparison is used to perform redundant recalculation and verification tasks, and outputs valid execution results that pass the verification.

[0064] It should be noted that the "joint mechanism based on state rollback and signature comparison" in this step refers to the following: When it is determined in step S30 that the current program segment has a soft error risk, the initial execution state saved in step S10 is used as input, and the program segment execution environment is rolled back through register reconstruction and memory snapshot restoration. Subsequently, the same program segment is re-executed in a fully controlled state to obtain redundant calculation results, and a new set of signature results is generated based on the same input data and path structure as the first execution. The new signature is compared with the original signature for consistency. If they match, the execution result is considered reliable, and this result is used as the final valid output; if they do not match, the rollback-execution-comparison process is re-entered until the maximum number of retries is reached.

[0065] Understandably, this mechanism constructs a computational redundancy verification process centered on "state reconstruction" and "path verification," ensuring that program segment computation results achieve local autonomous fault tolerance without relying on multi-core voting or result arbitration. This mechanism not only functionally verifies computation output but also structurally constrains execution paths and data flows through the signature construction process. It effectively identifies non-persistent errors caused by transient interference, such as instruction disturbances, register flips, and memory pollution, and performs local repair and recomputation, preventing erroneous results from entering shared paths.

[0066] It should be understood that traditional NPU execution architectures lack a segment-level result traceability mechanism. In the event of a soft error, the only recourse is often task restart or rescheduling, which increases energy consumption and latency while failing to ensure result integrity. This invention, however, constructs a path consistency verification system based on hash signatures, externalizing previously difficult-to-observe perturbation behaviors into measurable signature differences. This significantly improves error identification and response efficiency in low-redundancy, low-resource modes. Unlike methods based on direct output value comparison, signature comparison is not only sensitive to changes in result values ​​but also effectively captures potential deviations caused by different execution paths.

[0067] For example, such as Figure 2As shown, the redundancy recalculation verification mechanism proposed in this invention has been integrated into the task execution path of the NPU Core. Taking the NPU Cluster shown in the figure as an example, each NPU Core includes an independent redundant computing control unit, Local Memory and write buffer, register group, and memory access unit. When a program segment is executed for the first time, the control unit automatically caches key input data and execution context state (including register snapshots and key memory page images) in Local Memory and generates a signature as a representation of the program segment's behavior. When step S30 triggers the redundant computing request, the control module quickly restores the original execution state, reloads the saved register and Local Memory contents through the state rollback module, and re-calls the computing unit to execute the original program segment. During the new execution process, the redundant computing control unit generates another set of signature information and compares it item by item with the signature obtained during the first execution. Once the signatures match, the current execution result is considered valid and output to the bus for subsequent modules to use; if the comparison fails, the state recovery process is called again. The maximum number of retries can be set during the NPU hardware configuration stage to ensure adjustable control granularity. In edge AI devices with limited hardware resources, this mechanism avoids the high energy consumption and scheduling complexity introduced by multi-core result arbitration by reusing existing resources within a single core, achieving efficient and low-power program segment-level fault tolerance and verification. This technology is particularly significant in processing high computational density tasks such as image recognition and edge detection, ensuring the reliability of results while effectively suppressing unpredictable disturbances to model inference results caused by soft errors.

[0068] Step S50: Based on the verified valid execution result, perform buffer release and task switching preparation operations using a context-aware data submission and control reclamation mechanism, and output the final updated status.

[0069] It should be noted that the "context-aware data submission and control reclamation mechanism" in this step refers to the following: after confirming that the current program segment has passed the redundancy recalculation check in step S40, the context-aware engine is activated to analyze the execution state, input-output dependencies, and subsequent scheduling chains of the current task. This mechanism determines whether the data submission conditions are met based on the context execution graph of the program segment (including control path nodes and data dependency edges). If they are met, the following two types of operations are performed: Data submission: The valid execution result is written from the computing unit to the corresponding Local Memory buffer, further pushed to the memory access unit, and finally submitted to the shared external storage or enters the cross-core communication path; Control reclamation: The local control resources bound to the execution of this segment (such as internal register groups, task controller suspend queues, instruction prefetch caches, etc.) are released, and the current computing thread is marked as "switchable" through the task controller feedback mechanism, entering the task switching scheduling preparation process.

[0070] Understandably, this mechanism establishes a task switching and resource release strategy based on "computation context," significantly reducing the data consistency risks caused by blind commits and early switching. By explicitly marking data as committable and controlling resource reclaimability, it can improve buffer resource reuse and enhance the scheduling efficiency of multi-task switching while maintaining execution correctness.

[0071] It should be understood that, compared to the traditional NPU architecture where tasks are submitted immediately upon completion, this mechanism introduces a "context consistency judgment" step before submission, which can effectively avoid erroneous data writing problems caused by factors such as out-of-order execution and unmet dependencies. It is particularly suitable for boundary consistency maintenance and delay scheduling optimization in large-scale parallel task execution scenarios.

[0072] For example, such as Figure 2 As shown, in the control and scheduling chain within the NPU Core, after a program segment completes execution and passes signature verification, it first checks whether there are any incomplete write records in its corresponding Local Memory write buffer, and then checks whether subsequent tasks depend on the current result. If both conditions are met, the result is immediately submitted to the memory access unit through the write buffer, and the currently bound computing resources and local register groups within the core are released, reserving space for the scheduling of the next task to be executed. This process ensures that NPU computing tasks maintain high throughput while possessing the ability to control execution and guarantee data consistency under abnormal paths.

[0073] Example 2: Furthermore, the present invention provides an NPU fault-tolerant computing system based on repeated execution of computing cores, employing an NPU fault-tolerant computing method based on repeated execution of computing cores as described in the above embodiments, which can solve the technical problem of NPU fault-tolerant computing based on repeated execution of computing cores. Compared with the prior art, the beneficial effects of the NPU fault-tolerant computing system based on repeated execution of computing cores provided by the present invention are the same as the beneficial effects of the NPU fault-tolerant computing method based on repeated execution of computing cores provided in the above embodiments, and other technical features of the NPU fault-tolerant computing system based on repeated execution of computing cores are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0074] Example 3: This invention provides an NPU fault-tolerant computing device based on repeated execution of the computing core. Please refer to... Figure 3A fault-tolerant computing device based on repetitive execution of a computing core using an NPU includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to execute the fault-tolerant computing method based on repetitive execution of a computing core as described in Embodiment 1 above. The fault-tolerant computing device based on repetitive execution of a computing core in this embodiment of the invention may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. This fault-tolerant computing device based on repetitive execution of a computing core is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the invention. A fault-tolerant computing device based on a computing core that repeatedly executes its execution may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory 1002 or a program loaded from a storage device 1003 into a random access memory 1004. The random access memory 1004 also stores various programs and data required for the operation of the fault-tolerant computing device based on the computing core that repeatedly executes its execution. The processing unit 1001, the read-only memory 1002, and the random access memory 1004 are interconnected via a bus 1005. An I / O interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. The communication device 1009 allows a fault-tolerant computing device based on repetitive execution of a computing core (NPU) to communicate wirelessly or wiredly with other devices to exchange data. While the figure illustrates a fault-tolerant computing device based on repetitive execution of a computing core with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0075] Example 4: This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described NPU fault-tolerant computing method based on repeated execution of computing cores. The computer program product provided by this invention can solve the technical problem of NPU fault-tolerant computing based on repeated execution of computing cores. Compared with the prior art, the beneficial effects of the computer program product provided by this invention are the same as those of the NPU fault-tolerant computing method based on repeated execution of computing cores provided in the above embodiments, and will not be repeated here.

[0076] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from read-only memory 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this invention.

[0077] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0078] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A fault-tolerant computing method for an NPU based on repeated execution of the computing core, characterized in that, The methods include: Step S10: Receive the i-th program segment to be executed via the NPU computing core. Corresponding program input data Based on the program segment to be executed Corresponding program input data A joint mechanism based on instruction dependency graph construction and data path activity identification is used to dynamically generate program segments to be executed. Initial execution state ; Step S20: Based on the initial execution state A constraint mechanism based on register and memory differential tracing is used to define the program segment to be executed. The task is to execute the program segment and output the result of its first execution. Signature corresponding to the program segment ; Step S30: Based on the first execution result of the program segment Signature corresponding to the program segment A fault-tolerant judgment task is performed using a local recalculation judgment mechanism based on a multi-condition triggering strategy, and a redundant calculation trigger flag is output. ; Step S40: Calculate the trigger flag based on redundancy A combined mechanism based on state rollback and signature comparison is used to perform redundant recalculation and verification tasks, and outputs valid execution results that pass the verification. Step S50: Based on the verified valid execution result, perform buffer release and task switching preparation operations using a context-aware data submission and control reclamation mechanism, and output the final updated status.

2. The NPU fault-tolerant computing method based on repeated execution of the computing core as described in claim 1, characterized in that, In step S10, the initial execution state Including the current program counter value Current register set contents LocalMemory area and program input data Associated memory fragment data Current task identifier and execution context .

3. The NPU fault-tolerant computing method based on repeated execution of the computing core as described in claim 2, characterized in that, In step S20, based on the initial execution state A constraint mechanism based on register and memory differential tracing is used to define the program segment to be executed. The task is to execute the program segment and output the result of its first execution. Signature corresponding to the program segment The steps specifically include: Step S201: Constructing the Register-Memory Differential Tracking Mapping Table: Initial Execution State The contents of the currently used register group in With Local Memory area and program input data Associated memory fragment data Establish an initial state snapshot, and based on the initial state snapshot, perform read / write access behavior collection tasks using a hardware-level or microarchitecture-level differential tagging mechanism, and output a read / write operation trace table. ; Step S202: Limiting the path and buffering write operations: based on the read / write operation tracking table The path variables recorded in the code use a limited state variable access mechanism to execute the controllable path replay task, and output the program segment to control the path. Based on program segment control path Perform write-ahead buffered execution and output the first execution result of the program segment. ; Step S203: Generating the signature corresponding to the program segment: based on the result of the first execution of the program segment A multi-factor signature mechanism based on execution path hashing and output fusion is used for signature calculation, and the signature corresponds to the output program segment. .

4. The NPU fault-tolerant computing method based on repeated execution of the computing core as described in claim 3, characterized in that, In step S20, the program segment corresponds to the signature. The formula is expressed as:

5. Among them, It is a collision-resistant hash function, SHA-256. Indicates the control path of the program segment; Input data into the program; This is the result of the first execution of the program segment.

6. The NPU fault-tolerant computing method based on repeated execution of the computing core as described in claim 1, characterized in that, In step S30, based on the result of the first execution of the program segment... Signature corresponding to the program segment A fault-tolerant judgment task is performed using a local recalculation judgment mechanism based on a multi-condition triggering strategy, and a redundant calculation trigger flag is output. The steps specifically include: Step S301: Status Trigger Signal Acquisition Stage: Acquire trigger-related status information, including the status of the current write buffer write volume. Does the program segment contain the status of the off-chip write operation flag? The status of the context switch signal for the current task And whether it is in a core synchronization blocking state Based on the trigger-related state information, a hybrid modeling approach using Boolean encoding based on term-by-term normalization is adopted to construct the trigger state vector. , ; Step S302: Multi-factor weighted fusion stage: Introducing a weighted coefficient vector , ,in, To write pressure-sensitive factors; Protection priority factor for writing to external storage; This is a context switching priority factor; Multi-core synchronization consistency weighting factor; based on weighted coefficient vector and trigger state vector A fuzzy membership-driven weighted nonlinear combination method is used for fusion calculation, and the fusion activation trigger score is output. ; Step S303: Trigger Flag Judgment Phase: Calculate the fusion activation trigger score. Compared with the preset trigger score threshold In comparison, if Then set the redundant calculation trigger flag. Otherwise, if Then set the redundant calculation trigger flag. .

7. The NPU fault-tolerant computing method based on repeated execution of the computing core as described in claim 5, characterized in that, In step S30, the fusion activation trigger score is calculated. The formula is expressed as:

8. Among them, The weighted coefficient vector The j-th factor; For triggering state vector The j-th state vector in the middle; For dynamic fuzzy membership functions, including trapezoidal membership functions, Gaussian membership functions, and sigmoid membership functions, different flexible response models are constructed for different types of the j-th state vector.

9. The NPU fault-tolerant computing method based on repeated execution of the computing core as described in claim 1, characterized in that, In step S40, the trigger flag is calculated based on redundancy. The steps for performing a redundant recalculation verification task using a joint mechanism based on state rollback and signature comparison, and outputting a valid execution result that has passed verification, specifically include: Step S401: State rollback and reconstruction phase: If redundancy calculation triggers flag Then the redundant controller RCU is activated, and the redundant controller RCU retrieves the initial execution state. The contents of the register group Local Memory area and program input data Associated memory fragment data and the contents of the register group With memory fragment data Restore to the preset backup state and output the initial rollback state. ; Step S402: Redundancy Recalculation and Signature Generation Stage: Based on the Initial Rollback State Re-execute step S20 and output the program segment rollback signature. ; Step S403: Signature Comparison and Redundancy Control Judgment Stage: Rollback Signature Based on Program Segment Signature corresponding to the program segment The hash consistency check method is used to perform round-by-round comparison and judgment, and the result of the current round of verification is output. ; If satisfied If the redundancy check passes, proceed to step S401 to perform a repeated rollback task until the redundancy check is satisfied. Or the preset maximum number of retries has been reached. Only then will the process terminate; finally, the valid execution result that has passed verification will be output.

10. A fault-tolerant computing system based on repeated execution of computing cores using an NPU, applied to the fault-tolerant computing method based on repeated execution of computing cores as described in any one of claims 1 to 7, characterized in that, The NPU fault-tolerant computing system based on repeated execution of the computing core includes: The task parsing and initial state generation module is used to receive the i-th program segment to be executed through the NPU computing core. Corresponding program input data Based on the program segment to be executed Corresponding program input data A joint mechanism based on instruction dependency graph construction and data path activity identification is used to dynamically generate program segments to be executed. Initial execution state ; The execution and initial signature generation module is used to define the execution state based on the initial execution state. A constraint mechanism based on register and memory differential tracing is used to define the program segment to be executed. The task is to execute the program segment and output the result of its first execution. Signature corresponding to the program segment ; The redundancy trigger judgment module is used to determine the result of the first execution of the program segment. Signature corresponding to the program segment A fault-tolerant judgment task is performed using a local recalculation judgment mechanism based on a multi-condition triggering strategy, and a redundant calculation trigger flag is output. ; The redundant execution and signature comparison module is used to calculate the trigger flag based on redundancy. A combined mechanism based on state rollback and signature comparison is used to perform redundant recalculation and verification tasks, and outputs valid execution results that pass the verification. The result submission and status reclamation module is used to perform buffer release and task switching preparation operations based on the verified valid execution results using a context-aware data submission and control reclamation mechanism, and output the final updated status.

11. A fault-tolerant computing device based on a computing core that repeatedly executes, characterized in that, The NPU fault-tolerant computing device based on repeated execution of computing cores includes: a memory, a processor, and an NPU fault-tolerant computing program based on repeated execution of computing cores stored in the memory and executable on the processor. When the NPU fault-tolerant computing program based on repeated execution of computing cores is executed by the processor, it implements the NPU fault-tolerant computing method based on repeated execution of computing cores according to any one of claims 1 to 7.

12. A computer program product, characterized in that, The computer program product includes an NPU fault-tolerant computing program that is repeatedly executed based on a computing core. When the NPU fault-tolerant computing program that is repeatedly executed based on a computing core is executed by a processor, it implements an NPU fault-tolerant computing method that is repeatedly executed based on a computing core, as described in any one of claims 1 to 7.

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