Electronic device

Abstract

The electronic device includes: a base layer; a pixel on the base layer in the first region; a plurality of scan lines including first scan lines electrically connected to the pixels; emission control lines electrically connected to the pixels; a scan driving circuit electrically connected to the plurality of scan lines; an emission driving circuit electrically connected to the emission control line; a plurality of driving voltage lines electrically connected to the pixels; and a plurality of signal lines including a first signal line electrically connected to the scan driving circuit and a second signal line electrically connected to the emission driving circuit, in which a load of a first circuit including the first scan line and the first signal line is greater than a load of a second circuit including the emission control line and the second signal line.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2024-0143347, filed on October 18, 2024, the entire contents of which are hereby incorporated by reference. Background Technology

[0002] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation system units, game consoles, and / or smartwatches include display panels and / or driving circuitry for displaying images. The driving circuitry includes scan driving circuitry configured to provide scan signals to multiple scan lines, data driving circuitry configured to provide data voltages to data lines, and / or transmit driving circuitry configured to provide transmit signals to transmit control lines. Summary of the Invention

[0003] Example embodiments of the inventive concept provide electronic devices with reduced power consumption.

[0004] Some exemplary embodiments of the present invention provide an electronic device comprising: a substrate layer including a first region and a second region adjacent to the first region; a pixel in the first region; a plurality of scan lines in the first region, including a first scan line electrically connected to the pixel; an emission control line in the first region and electrically connected to the pixel; a scan drive circuit in the second region and electrically connected to the plurality of scan lines; an emission drive circuit in the second region and electrically connected to the emission control line; a plurality of drive voltage lines in the second region and electrically connected to the pixel; and a plurality of signal lines in the second region, the plurality of signal lines including a first signal line electrically connected to the scan drive circuit and a second signal line electrically connected to the emission drive circuit, wherein the load of the first circuit including the first scan line and the first signal line is greater than the load of the second circuit including the emission control line and the second signal line.

[0005] In some example embodiments, the multiple scan lines may further include a second scan line, a third scan line, and a fourth scan line, and the multiple signal lines may further include a third signal line, a fourth signal line, and a fifth signal line electrically connected to the scan drive circuit.

[0006] In some example embodiments, the scan driving circuit can be configured to output a first scan signal to a first scan line, and the transmit driving circuit can be configured to output a transmit signal to a transmit control line. During a time period, the scan driving circuit can be configured to maintain the level of the first scan signal, and the transmit driving circuit can be configured to change the level of the transmit signal.

[0007] In some example embodiments, the scan driving circuit can be configured to output a second scan signal to a second scan line, a third scan signal to a third scan line, and a fourth scan signal to a fourth scan line, wherein, during a time period, the scan driving circuit can be configured to maintain the levels of the second scan signal and the third scan signal, and change the level of the fourth scan signal.

[0008] In some example embodiments, the load of the second circuit may be less than the load of each of the third circuit, which includes the second scan line and the third signal line, and the load of the fourth circuit, which includes the third scan line and the fourth signal line.

[0009] In some example embodiments, the load of the fifth circuit, which includes the fourth scan line and the fifth signal line, may be less than the load of each of the first circuit, the third circuit, and the fourth circuit.

[0010] In some example embodiments, the first width of the first scan line may be greater than the second width of the transmit control line.

[0011] In some example embodiments, the first distance between the first scan line and a plurality of other scan lines adjacent to the first scan line may be less than the second distance between the transmit control line and a plurality of other scan lines adjacent to the transmit control line.

[0012] In some example embodiments, the capacitive load of the first scan line may be greater than the capacitive load of the transmit control line.

[0013] In some example embodiments, the multiple scan lines may further include a second scan line, a third scan line, and a fourth scan line, and the capacitive load of the transmit control line may be less than the capacitive load of the second scan line and the capacitive load of the third scan line.

[0014] In some example embodiments, the capacitive load of the fourth scan line may be less than each of the capacitive loads of the first scan line, the second scan line, and the third scan line.

[0015] In some example embodiments, the multiple drive voltage lines may include a first drive voltage line provided with a first drive voltage and a second drive voltage line provided with a second drive voltage, wherein the first drive voltage line may include a first overlapping portion that overlaps with the multiple signal lines on a plane, and the second drive voltage line may include a second overlapping portion that overlaps with the multiple signal lines on a plane.

[0016] In some example embodiments, the first overlapping portion may include a first opening.

[0017] In some example embodiments, the first opening may be provided as multiple.

[0018] In some example embodiments, the first overlapping portion may include a first opening, and the second overlapping portion may include a second opening.

[0019] In some example embodiments, the first opening may be provided in multiple ways, and the second opening may be provided in multiple ways.

[0020] In some exemplary embodiments of the present invention, the electronic device includes: a display panel including a display area and a non-display area adjacent to the display area, wherein the display panel includes: pixels in the display area and including pixel circuits and emitting elements; a first scan line electrically connected to the pixel circuits; and an emitting control line electrically connected to the pixel circuits, wherein the capacitive load of the first scan line is greater than the capacitive load of the emitting control line.

[0021] In some example embodiments, the electronic device may further include: processing circuitry configured to: operate pixel circuitry based on a data write period and a self-period; during the data write period, change the level of a first scan signal provided to a first scan line; during the self-period, maintain the level of the first scan signal; and during both the data write period and the self-period, change the level of a transmit signal provided to a transmit control line.

[0022] In some example embodiments, the display panel may further include a second scan line, a third scan line, and a fourth scan line, wherein the capacitive load of the transmit control line may be less than the capacitive load of the second scan line and the capacitive load of the third scan line, the capacitive load of the fourth scan line may be less than the capacitive load of the first scan line, the capacitive load of the second scan line, and the capacitive load of the third scan line, and wherein the processing circuit may be configured to maintain the level of the signal provided to the second scan line and the signal provided to the third scan line during a self-period, and to change the level of the signal provided to the fourth scan line during a self-period.

[0023] In some example embodiments, the display panel may further include: a plurality of signal lines in a non-display area; and driving voltage lines in the non-display area, the driving voltage lines being configured to transmit driving voltages to pixels, and the driving voltage lines may include at least one opening in a plane overlapping the plurality of signal lines. Attached Figure Description

[0024] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate some exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0025] Figure 1AThese are perspective views of electronic devices based on some exemplary embodiments of the present invention;

[0026] Figure 1B This is a rear surface perspective view of an electronic device according to some exemplary embodiments of the present invention;

[0027] Figure 2A These are perspective views of electronic devices based on some exemplary embodiments of the present invention;

[0028] Figure 2B These are plan views of electronic devices based on some exemplary embodiments of the present invention;

[0029] Figure 3 These are block diagrams of electronic devices based on some exemplary embodiments of the present invention;

[0030] Figure 4A These are circuit diagrams of pixels according to some exemplary embodiments of the present invention;

[0031] Figure 4B These are circuit diagrams of pixels according to some exemplary embodiments of the present invention;

[0032] Figure 5 This is a cross-sectional view of a display panel according to some exemplary embodiments of the present invention;

[0033] Figure 6 These are schematic block diagrams of display panels according to some exemplary embodiments of the present invention;

[0034] Figure 7 These are timing diagrams illustrating signals according to some exemplary embodiments of the concept according to the present invention;

[0035] Figure 8 This is a plan view of a portion of a display panel according to some exemplary embodiments of the present invention;

[0036] Figure 9A These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0037] Figure 9B These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0038] Figure 10A These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0039] Figure 10B These are some example embodiments of the concept of the present invention. Figure 8Enlarged plan view of area AA';

[0040] Figure 10C These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0041] Figure 10D These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0042] Figure 10E These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0043] Figure 10F These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0044] Figure 10G These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA';

[0045] Figure 11 This is a table showing the power consumption of display panels according to some example embodiments of the present invention;

[0046] Figure 12A This is the layout of multiple scan lines and emission control lines according to some exemplary embodiments of the present invention;

[0047] Figure 12B This is the layout of multiple scan lines and emission control lines according to some exemplary embodiments of the present invention;

[0048] Figure 13 This is a table showing the values ​​of the capacitive loads of multiple scan lines and emitter control lines according to some exemplary embodiments of the present invention; and

[0049] Figure 14 This is a table showing the power consumption of display panels according to some example embodiments of the present invention.

[0050] [Explanation of reference numerals or symbols in the attached drawings]

[0051] ED: Electronic device; DP: Display panel

[0052] DA: Zone 1 NDA: Zone 2

[0053] GWL: First scan line; EML: Emit control line

[0054] CL1: First signal line; CL2: Second signal line

[0055] CC1: First circuit CC2: Second circuit

[0056] GW-ST1: Level 1; EM-ST: Level 2 Detailed Implementation

[0057] In this specification, it will be understood that when an element (or area, layer or portion, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, it may be directly disposed on, directly connected to or directly coupled to the other element, or other elements may be disposed therebetween.

[0058] The same reference numerals or symbols refer to the same elements throughout. In the drawings, the thickness, proportions, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0059] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, the elements should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, and / or portion from another element, component, region, layer, and / or portion. For example, a first element may be referred to as a second element without departing from the scope of the inventive concept. Similarly, a second element may be referred to as a first element. In this specification, unless the context clearly indicates otherwise, singular expressions are intended to include plural forms as well.

[0060] Additionally, terms such as "below," "under," "on the lower side," "above," "on top," or "on the upper side" can be used to describe the relationships between the elements illustrated in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0061] It will be further understood that, when used in this specification, the terms “comprising,” “including,” and / or “having” indicate the presence of the stated features, figures, steps, operations, elements, components, or combinations thereof, but do not preclude the presence and / or addition of one or more other features, figures, steps, operations, elements, components, and / or combinations thereof.

[0062] The terms "part" and / or "unit" refer to software and / or hardware components that perform a specific function. Hardware components may include, for example, field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). Software components may refer to executable code in addressable storage media and / or data used by the executable code. Thus, software components may be, for example, object-oriented software components, class components, and / or working components, and / or may include processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrangements, and / or variables.

[0063] When a component is described as being "connected to" or "electrically connected to" another component, the component may be directly connected to that other component, or one or more other intermediary components may be present. For example, a component described as being "connected to" another component may be "electrically connected to" that other component. Conversely, when a component is described as being "directly connected to" another component, no intermediary component is present.

[0064] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms (e.g., those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0065] In the following description, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0066] Figure 1A This is a perspective view of an electronic device ED according to some exemplary embodiments of the present invention. Figure 1B This is a rear surface perspective view of an electronic device ED according to some exemplary embodiments of the present invention.

[0067] refer to Figure 1A and Figure 1B An electronic device (ED) can be a device activated by an electrical signal. For example, an electronic device ED can display an image and can sense input applied from outside the electronic device ED. External input can be user input. User input can include various forms of external input such as a part of the user's body, a pen, light, heat, and / or pressure.

[0068] The electronic device ED may include a first display panel DP1 and / or a second display panel DP2. The first display panel DP1 and the second display panel DP2 may be separate panels. The first display panel DP1 may be referred to as the main display panel, and the second display panel DP2 may be referred to as an auxiliary display panel or an external display panel. The first display panel DP1 and the second display panel DP2 may be referred to as display panel DP (see [link to relevant documentation]). Figure 3 ).

[0069] The first display panel DP1 may include a first display area DA1, and the second display panel DP2 may include a second display area DA2. The area of ​​the second display panel DP2 may be smaller than the area of ​​the first display panel DP1. Corresponding to the dimensions of the first display panel DP1 and the second display panel DP2, the area of ​​the first display area DA1 may be larger than the area of ​​the second display area DA2.

[0070] The first display panel DP1 and the second display panel DP2 may each include a non-display area NDA (see...). Figure 3 The first display area DA1 and the second display area DA2 can be referred to as display area DA (see...). Figure 3 ).

[0071] When the electronic device ED is in the deployed state, the first display area DA1 may have a plane substantially parallel to the first direction DR1 and the second direction DR2. The thickness direction of the electronic device ED may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, the front (or upper) and rear (or lower) surfaces of the components constituting the electronic device ED may be defined based on the third direction DR3.

[0072] The first display panel DP1 and / or the first display area DA1 may include a folded area FA that can be folded or unfolded, and a plurality of non-folded areas NFA1 and NFA2 spaced apart from each other and with the folded area FA between them. The second display panel DP2 may overlap with any one of the plurality of non-folded areas NFA1 to NFA2. For example, the second display panel DP2 may overlap with the first non-folded area NFA1.

[0073] The display orientation of the first image IM1 displayed in a portion of the first display panel DP1 (e.g., the second non-folding area NFA2) and the display orientation of the second image IM2 displayed in the second display panel DP2 can be opposite. For example, the first image IM1 can be displayed on a third direction DR3, and the second image IM2 can be displayed on a fourth direction DR4, which is opposite to the third direction DR3.

[0074] In some exemplary embodiments of the present invention, the folding region FA can be bent about a folding axis extending in a direction parallel to the long side of the electronic device ED (e.g., parallel to the first direction DR1). When the electronic device ED is in a folded state, the folding region FA has a predetermined or alternately given curvature and a predetermined or alternately given radius of curvature. The first non-folding region NFA1 and the second non-folding region NFA2 can face each other, and the electronic device ED can be folded inward so that the first display area DA1 is not exposed to the outside.

[0075] In some exemplary embodiments of the present invention, the electronic device ED can be folded outwards, exposing the first display area DA1 to the outside. In some exemplary embodiments of the present invention, when in the unfolded state, the electronic device ED can be folded inwards or outwards, but these exemplary embodiments are not limited to this example.

[0076] although Figure 1A The illustration shows an example in which a folding region FA is defined (provided or included) in an electronic device ED, but some exemplary embodiments of the inventive concept are not limited to this example. For example, in an electronic device ED, multiple folding axes and corresponding multiple folding regions may be defined, and when in an unfolded state in each of the multiple folding regions, the electronic device ED may be folded inward and / or outward.

[0077] In some exemplary embodiments of the present invention, at least one of the first display panel DP1 and the second display panel DP2 can sense input via the pen PN, even without a digital converter. Therefore, since the digital converter for sensing the pen PN is omitted, the addition of a digital converter does not result in an increase in the thickness, weight, and / or reduced flexibility of the electronic device ED. Thus, not only the first display panel DP1, but also the second display panel DP2 can be designed to sense the pen PN.

[0078] Figure 2A This is a perspective view of an electronic device EDa according to some exemplary embodiments of the present invention. Figure 2B This is a plan view of an electronic device EDa, based on some exemplary embodiments of the present invention.

[0079] refer to Figure 2A and Figure 2B The electronic device EDa may include a display panel DP, a housing HS in which the display panel DP is embedded, and / or a band STR connected to the housing HS.

[0080] According to some exemplary embodiments of the present invention, a user can use the electronic device EDA while wearing it on their wrist WST. The user can arrange the strap STR, connected to the housing HS in which the display panel DP is embedded, to surround the user's wrist WST. In this case, the user can arrange the display surface of the display panel DP to face the user.

[0081] although Figure 2A The illustration shows an example of an electronic device EDA comprising a housing HS and a smartwatch with STR, but some exemplary embodiments of the inventive concept are not limited to this example. For example, the electronic device EDA can be used in televisions, monitors, external billboards, car navigation units, personal computers (e.g., tablets or laptops), personal digital terminals, game consoles, smartphones, cameras, and / or wearable devices. Wearable devices can include virtual reality devices, augmented reality devices, and / or smartwatches, etc. Virtual reality devices and / or augmented reality devices can be devices in the form of glasses that a user can wear. These devices are presented as examples only, and the electronic device EDA can be used in other devices without departing from the inventive concept.

[0082] The Display Panel (DP) can display image information (IM). The Display Panel (DP) can provide users with various image information. Image information can display time and various applications. For example, the Display Panel (DP) can display and provide the hour and minute hands to show the time. Additionally, the Display Panel (DP) can display and provide various applications to the user.

[0083] The electronic device EDA can be a touch-sensitive device. For example, when a user touches an application displayed on the display panel DP, the touched application can be executed. For instance, when a user touches a weather application displayed on the display panel DP, weather information can be provided to the user.

[0084] The upper surface of the display panel DP can be defined as a display surface and can have a plane defined by a first direction DR1 and a second direction DR2. The first direction DR1 and the second direction DR2 can be defined as directions that intersect each other perpendicularly. Through the display surface, an image IM generated in the electronic device EDA can be provided to the user.

[0085] The display surface may include a display area DA and / or a non-display area NDA surrounding the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display an image IM. The non-display area NDA may surround the display area DA.

[0086] When viewed on a flat surface, the electronic device EDa may have a circular shape, but the example embodiment is not limited to this example, and the electronic device ED may have various shapes such as polygonal shapes (e.g., rectangular shapes) or elliptical shapes.

[0087] Figure 3 This is a block diagram of an electronic device ED according to some exemplary embodiments of the present invention.

[0088] refer to Figure 3 The electronic device ED may include a display panel DP, a drive controller TC, a data drive circuit DDC, a first scan drive circuit SDC1, a second scan drive circuit SDC2, a transmit drive circuit EDC, and / or a voltage generator VG.

[0089] The drive controller TC can receive input signals including an input image signal RGB and / or a control signal CTRL. The drive controller TC can generate an output image signal DS by converting the data format of the input image signal RGB to meet the interface specifications with the data drive circuit DDC. The drive controller TC can output a first scan control signal SCS1, a second scan control signal SCS2, a transmit control signal ECS, and / or a data control signal DCS to control the image to be displayed on the display panel DP.

[0090] The data drive circuit DDC can receive the data control signal DCS and / or output the image signal DS from the drive controller TC. The data drive circuit DDC can convert the output image signal DS into a data signal and output the data signal to multiple data lines DL1 to DLm, which will be described later. The data signal can be an analog voltage corresponding to the grayscale value of the output image signal DS.

[0091] The display panel DP may include a display area DA and / or a non-display area NDA adjacent to the display area DA. The display area DA and the non-display area NDA may be referred to as the first area DA and the second area NDA, respectively.

[0092] The display panel DP may include a first scan driving circuit SDC1, a second scan driving circuit SDC2, and / or an emission driving circuit EDC. The first scan driving circuit SDC1, the second scan driving circuit SDC2, and / or the emission driving circuit EDC may be arranged in the non-display area NDA (e.g., the substrate layer BL (see...)). Figure 5 In the second zone of NDA).

[0093] In some example embodiments, the first scan driving circuit SDC1 and / or the transmit driving circuit EDC can be arranged on the first side of the display panel DP, and the second scan driving circuit SDC2 can be arranged on the second side of the display panel DP.

[0094] The display panel DP may include multiple data lines DL1 to DLm, multiple scan lines GWL1 to GWLn, GIL1 to GILn, GCL1 to GCLn and / or GBL1 to GBLn, multiple emission control lines EML1 to EMLn, and / or multiple pixels PX. The data lines DL1 to DLm, scan lines GWL1 to GWLn, GIL1 to GILn, GCL1 to GCLn and / or GBL1 to GBLn, emission control lines EML1 to EMLn, and / or pixels PX may be arranged in the display area DA. For example, the data lines DL1 to DLm, scan lines GWL1 to GWLn, GIL1 to GILn, GCL1 to GCLn and GBL1 to GBLn, emission control lines EML1 to EMLn, and pixels PX may be arranged on the substrate layer BL (see...). Figure 5 In the first zone DA of )

[0095] Data lines DL1 to DLm can extend from the data drive circuit DDC in the first direction DR1 and can be arranged in the second direction DR2 while being spaced apart from each other.

[0096] Scan lines GWL1 to GWLn, GIL1 to GILn, GCL1 to GCLn, and / or GBL1 to GBLn may include first scan lines GWL1 to GWLn, second scan lines GIL1 to GILn, third scan lines GCL1 to GCLn, and / or fourth scan lines GBL1 to GBLn. The first scan lines GWL1 to GWLn, second scan lines GIL1 to GILn, third scan lines GCL1 to GCLn, and fourth scan lines GBL1 to GBLn may be referred to as write scan lines GWL1 to GWLn, initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, and black scan lines GBL1 to GBLn, respectively.

[0097] The first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, and / or the third scan lines GCL1 to GCLn can be electrically connected to the first scan drive circuit SDC1. The transmit control lines EML1 to EMLn can be electrically connected to the transmit drive circuit EDC. The first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, the third scan lines GCL1 to GCLn, and / or the fourth scan lines GBL1 to GBLn can be electrically connected to the second scan drive circuit SDC2. Therefore, the first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, and / or the third scan lines GCL1 to GCLn can be electrically connected to the first scan drive circuit SDC1 and / or the second scan drive circuit SDC2.

[0098] The first scan drive circuit SDC1 can receive a first scan control signal SCS1 from the drive controller TC. In response to the first scan control signal SCS1, the first scan drive circuit SDC1 can output a first scan signal to the first scan lines GWL1 to GWLn, output a second scan signal to the second scan lines GIL1 to GILn, and / or output a third scan signal to the third scan lines GCL1 to GCLn.

[0099] The second scan drive circuit SDC2 can receive the second scan control signal SCS2 from the drive controller TC. In response to the second scan control signal SCS2, the second scan drive circuit SDC2 can output the first scan signal to the first scan lines GWL1 to GWLn, the second scan signal to the second scan lines GIL1 to GILn, the third scan signal to the third scan lines GCL1 to GCLn, and / or the fourth scan signal to the fourth scan lines GBL1 to GBLn.

[0100] The first scan drive circuit SDC1 and the second scan drive circuit SDC2 can be referred to as scan drive circuits.

[0101] The transmit driver circuit EDC can receive the transmit control signal ECS from the drive controller TC. In response to the transmit control signal ECS, the transmit driver circuit EDC can output the transmit signal to the transmit control lines EML1 to EMLn.

[0102] exist Figure 3 In the example illustrated, the first scan driving circuit SDC1 and the second scan driving circuit SDC2 are arranged facing the non-display area NDA, with the display area DA located between them. However, some exemplary embodiments of the present invention are not limited to this example. In some exemplary embodiments, at least a portion of the first scan driving circuit SDC1 and / or the second scan driving circuit SDC2 may be arranged in the display area DA, and the display panel DP may include only one of the first scan driving circuit SDC1 and the second scan driving circuit SDC2.

[0103] Each or more pixels PX can be electrically connected to the first scan lines GWL1 to GWLn, the second scan lines GIL1 to GILn, the third scan lines GCL1 to GCLn, the fourth scan lines GBL1 to GBLn, the emission control lines EML1 to EMLn, and / or the data lines DL1 to DLm. Each or more pixels PX can be electrically connected to four scan lines and / or one emission control line. For example, as... Figure 3As shown, the pixel PX in the first row can be electrically connected to the first scan lines GIL1, GCL1, GWL1, and GBL1, as well as the first emission control line EML1. Additionally, the pixel PX in the j-th row can be electrically connected to the j-th scan lines GILj, GCLj, GWLj, and GBLj, as well as the j-th emission control line EMLj.

[0104] Each or one of the pixels PX may include an emission element EE (see Figure 4A ) and / or the pixel circuit PXC that controls the emission of the emitting element EE (see Figure 4A The pixel circuit PXC may include one or more transistors and / or one or more capacitors. The first scan drive circuit SDC1, the second scan drive circuit SDC2, and / or the emitter drive circuit EDC may include transistors formed using the same process as the pixel circuit PXC.

[0105] The voltage generator VG can generate the voltage required for the operation of the display panel DP, or a sufficient voltage for the operation of the display panel DP. The voltage generator VG can generate a second drive voltage ELVDD, a first drive voltage ELVSS, a first initialization voltage VINT1, and / or a second initialization voltage VINT2.

[0106] Each or one of the pixels PX can receive a first driving voltage ELVSS, a second driving voltage ELVDD, a first initialization voltage VINT1, and / or a second initialization voltage VINT2 from the voltage generator VG.

[0107] Figure 4A This is a circuit diagram of a pixel PXji according to some exemplary embodiments of the present invention.

[0108] Figure 4A The diagram shows Figure 3 An example of the equivalent circuit diagram of pixel PXji, which is electrically connected to the i-th data line DLi, the j-th first scan line GWLj, the j-th second scan line GILj, the j-th third scan line GCLj, the j-th fourth scan line GBLj, and the j-th emission control line EMLj.

[0109] Figure 3 Each or one or more of the multiple pixels PX in the diagram can have the same characteristics as... Figure 4A The equivalent circuit diagram of pixel PXji shown in the figure has the same circuit construction. In some example embodiments, the pixel circuit PXC of pixel PXji may include first transistors to seventh transistors T1, T2, T3, T4, T5, T6 and T7, capacitor Cst and / or at least one emitting element EE. In some example embodiments, the emitting element EE may be a light-emitting diode.

[0110] Among the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, the third transistor T3 and / or the fourth transistor T4 may be N-type transistors comprising oxide semiconductor as the semiconductor layer, and each or one or more of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors comprising low-temperature polycrystalline silicon (LTPS) as the semiconductor layer. However, some exemplary embodiments of the inventive concept are not limited to this example, and all or one or more of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type transistors or N-type transistors. In some exemplary embodiments, at least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be an N-type transistor, and the other transistors may be P-type transistors.

[0111] The first scan line GWLj can transmit the first scan signal GWj, the second scan line GILj can transmit the second scan signal GIj, the third scan line GCLj can transmit the third scan signal GCj, and / or the fourth scan line GBLj can transmit the fourth scan signal GBj. The transmit control line EMLj can transmit the transmit signal EMj.

[0112] The data line DL can transmit the data signal Di. The data signal Di can have the same characteristics as the input to the electronic device ED (see...). Figure 3 The input image signal RGB (see) Figure 3 The corresponding voltage level.

[0113] The first driving voltage line to the fifth driving voltage lines VL1, VL2, VL3, VL4 and VL5 (see...) Figure 4B Each or one of the following can be electrically connected to pixel PXji. Each or one of the first to fifth drive voltage lines VL1, VL2, VL3, VL4, and VL5 can transmit the first drive voltage ELVSS, the second drive voltage ELVDD, the first initialization voltage VINT1, and / or the second initialization voltage VINT2. The first to fifth drive voltage lines VL1, VL2, VL3, VL4, and VL5 can each be referred to as a drive voltage line.

[0114] The first transistor T1 may include a first electrode electrically connected to the second drive voltage line VL2 via a fifth transistor T5, a second electrode electrically connected to the anode of the emitter element EE via a sixth transistor T6, and a gate electrode electrically connected to one end of the capacitor Cst. The first transistor T1 may receive the data signal Di transmitted by the data line DLi in accordance with the switching operation of the second transistor T2, and supply the drive current Id to the emitter element EE.

[0115] The second transistor T2 may include a first electrode electrically connected to the data line DLi, a second electrode electrically connected to the first electrode of the first transistor T1, and a gate electrode electrically connected to the first scan line GWLj. The second transistor T2 may be turned on in response to a first scan signal GWj received through the first scan line GWLj, and transmit the data signal Di transmitted from the data line DLi to the first electrode of the first transistor T1.

[0116] The third transistor T3 may include a first electrode electrically connected to the gate electrode of the first transistor T1, a second electrode electrically connected to the second electrode of the first transistor T1, and a gate electrode electrically connected to the third scan line GCLj. The third transistor T3 may be turned on in response to a third scan signal GCj received through the third scan line GCLj, and connect the gate electrode and the second electrode of the first transistor T1 to diode-connect the first transistor T1.

[0117] The fourth transistor T4 may include a first electrode electrically connected to the gate electrode of the first transistor T1, a second electrode electrically connected to the third drive voltage line VL3 to which the first initialization voltage VINT1 is transmitted, and a gate electrode electrically connected to the second scan line GILj. The fourth transistor T4 may be turned on in response to a second scan signal GIj received through the second scan line GILj, and transmit the first initialization voltage VINT1 to the gate electrode of the first transistor T1 to perform an initialization operation to initialize the voltage of the gate electrode of the first transistor T1.

[0118] The fifth transistor T5 may include a first electrode electrically connected to the second drive voltage line VL2, a second electrode electrically connected to the first electrode of the first transistor T1, and a gate electrode electrically connected to the emitter control line EMLj.

[0119] The sixth transistor T6 may include a first electrode electrically connected to the second electrode of the first transistor T1, a second electrode electrically connected to the anode of the emitter element EE, and a gate electrode electrically connected to the emitter control line EMLj.

[0120] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously in response to the transmit signal EMj received through the transmit control line EMLj, thereby allowing the drive current Id to be transmitted to the transmitting element EE.

[0121] The seventh transistor T7 may include a first electrode electrically connected to the anode of the emitter element EE, a second electrode electrically connected to the fourth drive voltage line VL4, and a gate electrode electrically connected to the fourth scan line GBLj. The seventh transistor T7 may be turned on in response to the fourth scan signal GBj received through the fourth scan line GBLj, and bypass the current of the anode of the emitter element EE to the fourth drive voltage line VL4.

[0122] One end of capacitor Cst can be electrically connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst can be electrically connected to the second drive voltage line VL2.

[0123] The anode of the emitting element EE can be electrically connected to the second electrode of the sixth transistor T6, and the cathode of the emitting element EE can be electrically connected to the first driving voltage line VL1 that transmits the first driving voltage ELVSS.

[0124] The circuit structure of pixel PXji is not limited to Figure 4A Furthermore, the number of transistors, the number of capacitors, and / or the connections between them in the pixel circuit PXC included inside the pixel PXji can be changed. Figure 4B This is a circuit diagram of a pixel PXjia according to some exemplary embodiments of the present invention.

[0125] exist Figure 4B In, with Figure 4A The same parts shown in the figure are indicated by the same reference numerals, and their descriptions will be omitted.

[0126] refer to Figure 4B Pixel PXjia may include pixel circuit PXCa and emitting element EE.

[0127] In some exemplary embodiments of the present invention, the pixel circuit PXCa may further include an eighth transistor T8. The eighth transistor T8 may include a first electrode electrically connected to a bias voltage line (or a fifth drive voltage line) VL5, a second electrode electrically connected to the first electrode of the first transistor T1, and a gate electrode electrically connected to the fourth scan line GBLj. The eighth transistor T8 may be turned on in response to a fourth scan signal GBj received via the fourth scan line GBLj.

[0128] The circuit structure of the pixel PXjia is not limited to Figure 4B Furthermore, the number of transistors, the number of capacitors, and / or the connections between them in the pixel circuit PXCa, which is located inside pixel PXjia, can be changed.

[0129] Figure 5 This is a cross-sectional view of a display panel DP according to some exemplary embodiments of the present invention.

[0130] refer to Figure 5 The display panel DP may include a display layer 100, a sensor layer 200 and / or an anti-reflective layer 300.

[0131] Display layer 100 may include a base layer BL, a circuit layer DP_CL disposed on the base layer BL, a component layer DP_ED and / or a package layer TFE.

[0132] On the basal layer BL, the first region DA can be defined (see Figure 3 ) and / or with the first zone DA (see Figure 3 The adjacent second zone NDA (see) Figure 3 ).

[0133] At least one inorganic layer may be formed on the upper surface of the substrate layer BL. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed from multiple layers. Multiple inorganic layers may constitute the barrier layers BR1 and / or BR2 and / or the buffer layer BFL, which will be described later. The barrier layers BR1 and / or BR2 and / or the buffer layer BFL may be selectively arranged.

[0134] Barrier layers BR1 and / or BR2 can reduce or prevent the introduction of foreign matter from the outside. Barrier layers BR1 and / or BR2 may include silicon oxide layers and / or silicon nitride layers. Each of these layers may be provided in multiples, and silicon oxide layers and silicon nitride layers may be stacked alternately.

[0135] Barrier layers BR1 and / or BR2 may include a first barrier layer BR1 and / or a second barrier layer BR2. A first rear surface metal layer BMC1 may be disposed between the first barrier layer BR1 and the second barrier layer BR2. In some exemplary embodiments of the present invention, the first rear surface metal layer BMC1 may be omitted.

[0136] A buffer layer BFL can be disposed on barrier layers BR1 to BR2. The buffer layer BFL can improve the adhesion between the substrate layer BL and the semiconductor pattern and / or conductive pattern. The buffer layer BFL may include at least one silicon oxide layer and / or at least one silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately.

[0137] The first semiconductor patterns S1, A1, and / or D1 may be disposed on the buffer layer BFL. The first semiconductor patterns S1, A1, and / or D1 may include silicon semiconductors. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon, etc. For example, the first semiconductor patterns S1, A1, and / or D1 may include low-temperature polycrystalline silicon.

[0138] Figure 5The illustration shows a portion of a first semiconductor pattern S1, A1, and / or D1 arranged on a buffer layer BFL, and other portions of the first semiconductor pattern S1, A1, and / or D1 may be further arranged in other regions. The first semiconductor pattern S1, A1, and / or D1 may be distributed across multiple pixels according to specific rules. Depending on whether it is doped, the first semiconductor pattern S1, A1, and / or D1 may have different electrical characteristics. The first semiconductor pattern S1, A1, and / or D1 may include a first portion region S1 and D1 with high conductivity and / or a second portion region A1 with low conductivity. The first portion region S1 and / or D1 may be doped with N-type dopant or P-type dopant. A P-type transistor may include a doped region doped with P-type dopant, and an N-type transistor may include a doped region doped with N-type dopant. The second portion region A1 may be an undoped region, or it may be doped to a concentration lower than that of the first portion regions S1 and / or D1.

[0139] The conductivity of the first region S1 and / or D1 can be greater than that of the second region A1, and the first region S1 and / or D1 can essentially function as electrodes and / or signal lines. The second region A1 can essentially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be the active region of a transistor, another portion of the semiconductor pattern can be the source or drain of a transistor, and / or other portions of the semiconductor pattern can be connecting electrodes or connecting signal lines.

[0140] The first electrode S1, the active region A1, and / or the second electrode D1 of the first transistor T1 are formed by a first semiconductor pattern S1, A1, and / or D1. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the active region A1 in opposite directions to each other.

[0141] Figure 5 The diagram illustrates a portion of the connection signal line CSL formed by the first semiconductor patterns S1, A1, and / or D1. Although not shown separately, the connection signal line CSL can be electrically connected on the plane to the seventh transistor T7 (see Figure 1). Figure 4A and Figure 4B The second electrode and the sixth transistor T6 (see) Figure 4A and Figure 4B The second electrode.

[0142] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 overlaps with a plurality of pixels in a common ground and may cover the first semiconductor pattern S1, A1 and / or D1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and hafnium oxide. In some example embodiments, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10 but also the insulating layer of the circuit layer DP_CL, which will be described later, may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above materials, but the example embodiments are not limited to this example.

[0143] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be part of a metal pattern. The third electrode G1 of the first transistor T1 overlaps with the active region A1 of the first transistor T1. In the process of doping the first semiconductor patterns S1, A1 and / or D1, the third electrode G1 of the first transistor T1 may act as a mask. The third electrode G1 may include titanium (Ti), silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, or aluminum nitride (Al). x N y ), tungsten (W), tungsten nitride (W) x N y Examples of indium oxides include copper (Cu), indium tin oxide (ITO), or indium zinc oxide (IZO), but the example embodiments are not limited to this example.

[0144] The second insulating layer 20 is disposed on the first insulating layer 10 and may cover the third electrode G1 of the first transistor T1. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. The second insulating layer 20 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In some example embodiments, the second insulating layer 20 may have a multi-layer structure including a silicon oxide layer and / or a silicon nitride layer.

[0145] The upper electrode UE and / or the second rear surface metal layer BMC2 may be disposed on the second insulating layer 20. The upper electrode UE may overlap with the third electrode G1. The upper electrode UE may be part of a metal pattern. A portion of the third electrode G1 and the upper electrode UE overlapping that portion of the third electrode G1 may define a capacitor Cst (see...). Figure 4A and Figure 4B In some exemplary embodiments of the present invention, the second insulating layer 20 may be replaced by an insulating pattern. In this case, the upper electrode UE may be disposed on the insulating pattern, and the upper electrode UE may act as a mask for the insulating pattern formed by the second insulating layer 20.

[0146] The second rear surface metal layer BMC2 can be arranged to correspond to the lower portion of the oxide thin-film transistor (e.g., the third transistor T3). The second rear surface metal layer BMC2 can be applied with a constant voltage or signal.

[0147] The third insulating layer 30 is disposed on the second insulating layer 20 and may cover the upper electrode UE and / or the second rear surface metal layer BMC2. The third insulating layer 30 may have a single-layer or multi-layer structure. For example, the third insulating layer 30 may have a multi-layer structure including a silicon oxide layer and / or a silicon nitride layer.

[0148] The second semiconductor patterns S3, A3, and / or D3 may be disposed on the third insulating layer 30. The second semiconductor patterns S3, A3, and / or D3 may comprise an oxide semiconductor. The oxide semiconductor may comprise multiple regions distinguished by whether or not a metal oxide has been reduced. Regions where the metal oxide has been reduced (hereinafter referred to as reduced regions) have higher conductivity than regions where the metal oxide has not been reduced (hereinafter referred to as non-reduced regions). Reduced regions S3 and / or D3 essentially function as the source / drain or signal line of a transistor. Non-reduced region A3 may substantially correspond to the active region (or semiconductor region or channel) of a transistor. In other words, a portion of the second semiconductor patterns S3, A3, and / or D3 may be the active region of a transistor, another portion of the second semiconductor patterns S3, A3, and / or D3 may be the source / drain region of a transistor, and / or other portions of the second semiconductor patterns S3, A3, and / or D3 may be signal transmission regions.

[0149] The first electrode S3, the active region A3, and / or the second electrode D3 of the third transistor T3 are formed by a second semiconductor pattern S3, A3, and / or D3. The first electrode S3 and / or the second electrode D3 comprise metal reduced from a metal-oxide-semiconductor. In cross-section, the first electrode S3 and the second electrode D3 may extend from the active region A3 in opposite directions to each other.

[0150] A fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 overlaps with a plurality of pixels in a common ground and may cover the second semiconductor pattern S3, A3 and / or D3. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide and hafnium oxide.

[0151] The third electrode G3 of the third transistor T3 is disposed on the fourth insulating layer 40. The third electrode G3 may be part of a metal pattern. The third electrode G3 of the third transistor T3 overlaps with the active region A3 of the third transistor T3. In the process of restoring the second semiconductor pattern S3, A3 and / or D3, the third electrode G3 may act as a mask. In some exemplary embodiments of the present invention, the fourth insulating layer 40 may be replaced by an insulating pattern.

[0152] The fifth insulating layer 50 is disposed on the fourth insulating layer 40 and may cover the third electrode G3. The fifth insulating layer 50 may be an inorganic layer.

[0153] The first connection electrode CNE10 can be disposed on the fifth insulating layer 50. The first connection electrode CNE10 can be connected to the connection signal line CSL through the first contact hole CH1 that penetrates the first insulating layer to the fifth insulating layers 10, 20, 30, 40 and 50.

[0154] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer. The organic layer may include general polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof, but the exemplary embodiments are not limited to this example.

[0155] The second connecting electrode CNE20 can be disposed on the sixth insulating layer 60. The second connecting electrode CNE20 can be connected to the first connecting electrode CNE10 through the second contact hole CH2 penetrating the sixth insulating layer 60. A seventh insulating layer 70 is disposed on the sixth insulating layer 60 and can cover the second connecting electrode CNE20. The seventh insulating layer 70 can be an organic layer.

[0156] The component layer DP_ED can be placed on the circuit layer DP_CL. The component layer DP_ED can include multiple emitter elements EE. Figure 5 The diagram in the image represents a transmitting element EE.

[0157] This can correspond to the emission element EE defining the emission region PXA. The emission region PXA can be defined by the pixel definition layer PDL, which will be described later.

[0158] The emitting element EE may include a first electrode AE, a first functional layer HFL, an emitting layer EL, a second functional layer EFL, and a second electrode CE. The first functional layer HFL, the second functional layer EFL, and / or the second electrode CE may be commonly provided to the pixel PX (see [link to relevant documentation]). Figure 3).

[0159] refer to Figure 5 The first electrode AE ​​of the emitting element EE can be disposed on the seventh insulating layer 70. The first electrode AE ​​of the emitting element EE can be connected to the second connecting electrode CNE20 through the third contact hole CH3 penetrating the seventh insulating layer 70.

[0160] The transmitting element EE may further include an auxiliary layer SLA. The auxiliary layer SLA may be disposed within the transmitting region PXA. The auxiliary layer SLA may be disposed between the first functional layer HFL and the transmitting layer EL. In some exemplary embodiments of the present invention, the auxiliary layer SLA may be omitted.

[0161] A pixel-defining layer (PDL) is disposed on a seventh insulating layer 70 and may cover a portion of the first electrode AE. Multiple emission openings (PDLop1) are provided in the pixel-defining layer (PDL). Multiple emission regions (PXA) may be defined by the emission openings (PDLop1).

[0162] The emission opening PDLop1 can expose at least a portion of the first electrode AE ​​of the emission element EE.

[0163] In some exemplary embodiments of the present invention, the pixel-defining layer (PDL) may include a black material. The PDL may include carbon black, and / or a black organic dye / pigment such as aniline black. The PDL may be formed by mixing a blue organic material and a black organic material. The PDL may further include a liquid-repellent organic material.

[0164] The emitting layer EL of the emitting element EE can be arranged in a region corresponding to the emitting opening PDLop1. The emitting layer EL can produce colored light of a predetermined or alternately given color. Although a patterned emitting layer EL has been described as an example, in some example embodiments, an emitting layer can be arranged in multiple emitting regions. For example, the emitting layer can produce white light or blue light. For example, the emitting layer can have a multilayer structure referred to as cascaded.

[0165] The emitter layer (EL) may include low molecular weight organic materials and / or polymeric organic materials as the emitter material. Alternatively, the emitter layer (EL) may include quantum dot materials as the emitter material. The core of the quantum dots may be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and / or combinations thereof.

[0166] The element layer DP_ED may further include a capping layer (not shown) disposed on the second electrode CE. The capping layer can be used to improve emission efficiency through the principle of constructive interference. The capping layer may include, for example, a material having a refractive index of 1.6 or greater relative to light with a wavelength of 589 nm. The capping layer may be an organic capping layer comprising organic materials, an inorganic capping layer comprising inorganic materials, and / or a composite capping layer comprising organic and inorganic materials. For example, the capping layer may include carbocyclic compounds, heterocyclic compounds, compounds containing amino groups, porphyrin derivatives, phthalocyanine derivatives, naphthalene phthalocyanine derivatives, alkali metal complexes, alkaline earth metal complexes, and / or any combination thereof. Carbocyclic compounds, heterocyclic compounds, and / or compounds containing amino groups may optionally be substituted with substituents including O, N, S, Se, Si, F, Cl, Br, I, and / or any combination thereof.

[0167] The encapsulation layer TFE is disposed on the component layer DP_ED. The encapsulation layer TFE comprises at least an inorganic layer or an organic layer. In some exemplary embodiments of the present invention, the encapsulation layer TFE may comprise two inorganic layers and an organic layer disposed between the two inorganic layers. In some exemplary embodiments of the present invention, the encapsulation layer TFE may comprise a plurality of alternately stacked inorganic layers and a plurality of organic layers.

[0168] The inorganic encapsulation layer protects the emitting element EE from moisture / oxygen, while the organic encapsulation layer protects the emitting element EE from foreign matter such as dust particles. The inorganic encapsulation layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer, etc., but the example embodiments are not limited to this example. The organic encapsulation layer may include an acrylic organic layer, but the example embodiments are not limited to this example.

[0169] The display panel DP may further include a sensor layer 200 and / or an anti-reflective layer 300.

[0170] Sensor layer 200 may be disposed on display layer 100. Sensor layer 200 can sense external input applied from the outside. External input may be user input. User input may include various forms of external input such as a part of the user's body, light, heat, pen, and / or pressure. Sensor layer 200 may be referred to as a sensor, input sensing layer, or input sensing panel. Sensor layer 200 may include sensor substrate layer 201, first sensor conductive layer 202, interlayer insulating layer 203, second sensor conductive layer 204, and / or cover layer 205.

[0171] The sensor substrate layer 201 can be directly disposed on the display layer 100. The sensor substrate layer 201 can be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Alternatively, the sensor substrate layer 201 can be an organic layer including epoxy resin, acrylic resin, or imide resin. The sensor substrate layer 201 can have a monolayer structure and / or a multilayer structure in which multiple layers are stacked along the third direction DR3.

[0172] The first sensor conductive layer 202 and / or the second sensor conductive layer 204 may each have a single-layer structure or a multi-layer structure in which multiple layers are stacked along the third direction DR3.

[0173] The single-layer conductive layer may include a metal layer and / or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and / or alloys thereof. The transparent conductive layer may include transparent conductive oxides such as indium tin oxide, indium zinc oxide, zinc oxide, and / or indium tin zinc oxide. For example, the transparent conductive layer may include conductive polymers such as PEDOT, metal nanowires, and / or graphene.

[0174] The conductive layer in a multilayer structure may include a metal layer. The metal layer may have a three-layer structure, such as titanium / aluminum / titanium. The conductive layer in a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0175] An interlayer insulating layer 203 may be disposed between the first sensor conductive layer 202 and the second sensor conductive layer 204. The interlayer insulating layer 203 may include an inorganic layer. The inorganic layer may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0176] In some example embodiments, the interlayer insulation layer 203 may include an organic layer. The organic layer may include at least one selected from acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0177] A capping layer 205 is disposed on the interlayer insulating layer 203 and may cover the second sensor conductive layer 204. The second sensor conductive layer 204 may include a conductive pattern. The capping layer 205 covers the conductive pattern and may reduce or eliminate the possibility of damage to the conductive pattern in subsequent processes. The capping layer 205 may include an inorganic material. For example, the capping layer 205 may include silicon nitride, but the example embodiment is not limited to this example. In some example embodiments of the inventive concept, the capping layer 205 may be omitted.

[0178] The anti-reflective layer 300 can be disposed on the sensor layer 200. The anti-reflective layer 300 may include a separating layer 310, multiple color filters 320 and / or a planarization layer 330.

[0179] The separator layer 310 can be arranged to overlap with the conductive pattern of the second sensor conductive layer 204. A cover layer 205 can be disposed between the separator layer 310 and the second sensor conductive layer 204. The separator layer 310 can reduce or prevent the reflection of external light by the second sensor conductive layer 204. The material constituting the separator layer 310 is not particularly limited, as long as the material constituting the separator layer 310 is a light-absorbing material. The separator layer 310 is a black layer, and in some example embodiments, the separator layer 310 may include a black colorant. The black colorant may include black dyes and / or black pigments. The black colorant may include carbon black, metals such as chromium, or oxides thereof.

[0180] Multiple partition openings can be defined in the partition layer 310. Each of the multiple partition openings can overlap with the emitting layer EL and / or the photoelectric conversion layer. A color filter 320 can be arranged corresponding to the multiple partition openings. The color filter 320 can transmit light provided from the emitting layer EL that overlaps with the color filter 320.

[0181] Planarization layer 330 may cover separator layer 310 and color filter 320. Planarization layer 330 may include organic material and may provide a flat surface on its upper surface. In some example embodiments, planarization layer 330 may be omitted.

[0182] In some exemplary embodiments of the present invention, the antireflective layer 300 may include a reflection adjustment layer 321 instead of a color filter 320. The reflection adjustment layer 321 may selectively absorb a portion of the bandwidth of light reflected from the interior of the display panel DP and / or the electronic device ED, and / or the light incident from the exterior of the display panel DP and / or the electronic device ED.

[0183] According to some example embodiments, the reflection adjustment layer 321 can absorb light in a first wavelength region of approximately 490 nm to approximately 505 nm and / or light in a second wavelength region of approximately 585 nm to 600 nm, and therefore can be provided to have a transmittance of approximately 40% or less in the first and / or second wavelength regions. The reflection adjustment layer 321 can absorb light emitted from the emitting layer EL at wavelengths outside the wavelength range of red, green, and / or blue light. As described above, since the reflection adjustment layer 321 absorbs light at wavelengths not belonging to the wavelength range of red, green, and / or blue light emitted from the emitting layer EL, the reduction in brightness of the display panel DP and / or electronic device ED can be reduced, prevented, or minimized. Additionally, the reduction in luminous efficiency of the display panel DP and / or electronic device ED can be reduced, prevented, or minimized, and visibility can be improved.

[0184] The reflection adjustment layer 321 may be provided as an organic layer comprising dyes, pigments, and / or combinations thereof. The reflection adjustment layer 321 may include tetrazaporphyrin (TAP) compounds, porphyrin compounds, metalloporphyrin compounds, oxazine compounds, squaric acid cyanide compounds, triarylmethane compounds, polymethystyl compounds, anthraquinone compounds, phthalocyanine compounds, azo compounds, perylene compounds, xanthannae compounds, diammonium dimethyl dipyrrole compounds, anthocyanin compounds, and / or combinations thereof.

[0185] In some example embodiments, the reflectivity adjustment layer 321 may have a transmittance of approximately 64% to approximately 72%. The transmittance of the reflectivity adjustment layer 321 may be adjusted according to the amount of pigment and / or dye included in the reflectivity adjustment layer 321.

[0186] Figure 6 This is a schematic block diagram of a display panel DP according to some exemplary embodiments of the present invention.

[0187] refer to Figure 3 and Figure 6 The display panel DP may include multiple levels and / or multiple signal lines SL (see...). Figure 9B ).exist Figure 6 As an example, the diagram illustrates multiple stages electrically connected to a pixel PX and multiple signal lines SL electrically connected to said multiple stages (see [link to diagram]). Figure 9B ).

[0188] Multiple levels may include Level 1-1 GW-ST1, Level 1-2 GW-ST2, Level 2 EM-ST, Level 3-1 GIGC-ST1, Level 3-2 GIGC-ST2 and / or Level 4 GB-ST.

[0189] In some exemplary embodiments of the present invention, the first-stage GW-ST1 and / or the third-stage GIGC-ST1 may be included in the first scan drive circuit SDC1, and the first-stage GW-ST2, the third-stage GIGC-ST2, and / or the fourth-stage GB-ST may be included in the second scan drive circuit SDC2. The second-stage EM-ST may be included in the transmit drive circuit EDC.

[0190] Multiple signal lines SL (see) Figure 9B The signal line may include a first signal line CL1, a second signal line CL2, a third signal line CL3, a fourth signal line CL4, and / or a fifth signal line CL5. In some exemplary embodiments of the present invention, the third signal line CL3 and the fourth signal line CL4 may be the same line. Therefore, a signal line may be referred to as the third signal line CL3 or the fourth signal line CL4.

[0191] Each or one of the signal lines CL1, CL2, CL3, CL4, and CL5 can be electrically connected to multiple pads PD1, PD2, PD3, and / or PD4. Each or one of the multiple pads PD1, PD2, PD3, and PD4 can output multiple signals, including a clock signal, to the signal lines CL1, CL2, CL3, CL4, and / or CL5.

[0192] The first-stage GW-ST1 can be electrically connected to the first signal line CL1 and / or the first scan line GWL. The first-stage GW-ST1, the first signal line CL1, and / or the first scan line GWL can be referred to as a single circuit, namely the first circuit CC1. Therefore, the first circuit CC1 can include the first-stage GW-ST1, the first signal line CL1, and / or the first scan line GWL. In some example embodiments, the first-stage GW-ST2 can have the same construction as the first-stage GW-ST1. The first-stage GW-ST1 and / or the first-stage GW-ST2 can be referred to as the first stage.

[0193] The second-stage EM-ST can be electrically connected to the second signal line CL2 and / or the transmit control line EML. The second-stage EM-ST, the second signal line CL2, and / or the transmit control line EML can be referred to as a circuit, namely the second circuit CC2. Therefore, the second circuit CC2 may include the second-stage EM-ST, the second signal line CL2, and / or the transmit control line EML.

[0194] In some exemplary embodiments of the present invention, the 3-1st stage GIGC-ST1 may be electrically connected to the third signal line CL3 and / or the fourth signal line CL4, and the 3-1st stage GIGC-ST1 may be electrically connected to the second scan line GIL and / or the third scan line GCL.

[0195] although Figure 6 The illustration shows an example where the second scan line GIL and the third scan line GCL are electrically connected to one level (e.g., level 3-1 GIGC-ST1), but some exemplary embodiments of the inventive concept are not limited to this example, and the second scan line GIL and / or the third scan line GCL can be electrically connected to different levels respectively. Therefore, although Figure 6 The illustration shows an example where one of the signal lines is referred to as the third signal line CL3 or the fourth signal line CL4. However, if the second scan line GIL and the third scan line GCL are electrically connected to different stages, the third signal line CL3 and the fourth signal line CL4 can be different lines from each other.

[0196] The 3-1 stage GIGC-ST1, the third signal line CL3, and / or the second scan line GIL can be referred to as a single circuit, namely the third circuit CC3. Therefore, the third circuit CC3 can include the 3-1 stage GIGC-ST1, the third signal line CL3, and / or the second scan line GIL. The 3-1 stage GIGC-ST1, the fourth signal line CL4, and / or the third scan line GCL can be referred to as a single circuit, namely the fourth circuit CC4. Therefore, the fourth circuit CC4 can include the 3-1 stage GIGC-ST1, the fourth signal line CL4, and / or the third scan line GCL. In some example embodiments, the 3-2 stage GIGC-ST2 can have the same construction as the 3-1 stage GIGC-ST1. The 3-1 stage GIGC-ST1 and / or the 3-2 stage GIGC-ST2 can be referred to as the third stage.

[0197] The fourth level GB-ST can be electrically connected to the fifth signal line CL5 and / or the fourth scan line GBL. The fourth level GB-ST, the fifth signal line CL5, and / or the fourth scan line GBL can be referred to as a circuit, namely the fifth circuit CC5. Therefore, the fifth circuit CC5 can include the fourth level GB-ST, the fifth signal line CL5, and / or the fourth scan line GBL.

[0198] Figure 7 This is a timing diagram illustrating signals according to some example embodiments of the concept according to the present invention.

[0199] Figure 7 The diagram illustrates the waveforms of each of the following signals corresponding to each time period: the transmitted signal EM, the first scan signal GW, the second scan signal GI, the third scan signal GC, and the fourth scan signal GB.

[0200] refer to Figure 4A , Figure 4B , Figure 6 and Figure 7The display panel (DP) can be driven at various driving frequencies. For example, the display panel (DP) can operate at predetermined or alternately given driving frequencies, such as 60Hz, 120Hz, or 240Hz. Additionally, the display panel (DP) can operate in a low scan rate mode, where it is driven at frequencies of tens of Hz or lower. For example, in Always-On Display (AOD) mode, the display panel (DP) can operate in a low scan rate mode. In some example embodiments, the display panel (DP) can be driven at a variable driving frequency. For example, the variable driving frequency can be varied within the range of 1Hz to 240Hz, but the range of driving frequencies is not particularly limited to the examples described above.

[0201] A frame of the display panel DP may include multiple time periods MD1 and / or MD2. Time periods MD1 and / or MD2 may include a data write time period MD1 and / or a self time period MD2. The data write time period MD1 may be referred to as an addressing time period, an addressing cycle, or a data write cycle, and the self time period MD2 may be referred to as a hold time period, a hold cycle, or a self cycle.

[0202] If the display panel DP is driven at 120Hz, a frame may include one data write period MD1 and / or one self-period period MD2. If the display panel DP is driven at 48Hz, a frame may include one data write period MD1 and / or four self-period periods MD2. However, this is merely an example to illustrate that the number of self-period periods MD2 included in a frame increases as the driving frequency of the display panel DP decreases, and some exemplary embodiments of the inventive concept are not limited to this example.

[0203] Pixel circuit PXC (see Figure 4A The pixel circuit (PXC) can be configured to operate in response to data write periods MD1 and / or from period MD2. The operation of the PXC during data write periods MD1 and from period MD2 will be described below.

[0204] During the data writing period MD1, the level of one or more of the transmit signal EM, the first scan signal GW, the second scan signal GI, the third scan signal GC, and the fourth scan signal GB can be changed.

[0205] During the logic high-level period of the third scan signal GC, the third transistor T3 can be turned on. The first transistor T1 can be connected to the diode of the turned-on third transistor T3. The logic high-level period of the third scan signal GC can be a compensation period used to compensate for the threshold voltage of the first transistor T1.

[0206] During the logic high-level period of the second scan signal GI, the fourth transistor T4 can be turned on. The first initialization voltage VINT1 can be transmitted to the gate electrode of the first transistor T1 through the fourth transistor T4, and the first transistor T1 can be initialized. The logic high-level period of the second scan signal GI can be an initialization period used to initialize the voltage level of the gate electrode of the first transistor T1.

[0207] During the logic low-level period of the first scan signal GW, the second transistor T2 is turned on, and the data signal Di can be transmitted to the first electrode of the first transistor T1 through the second transistor T2.

[0208] During the logic low level period of the fourth scan signal GB, the seventh transistor T7 is turned on, and the second initialization voltage VINT2 can be transmitted to the anode of the emitter element EE through the seventh transistor T7. Although Figure 7 The illustration shows an example in which the fourth scan signal GB is activated to a logic low level twice, but the example embodiment is not limited to this example and the fourth scan signal GB may be activated once, twice or more.

[0209] Subsequently, during the logic low-level period of the transmit signal EM, the fifth transistor T5 and the sixth transistor T6 can be turned on. A current path can be formed between the second drive voltage line VL2 and the emitter element EE through the fifth transistor T5, the first transistor T1, and the sixth transistor T6. Then, a drive current Id is generated based on the difference between the voltage at the gate electrode of the first transistor T1 and the voltage of the second drive voltage ELVDD, and the drive current Id is supplied to the emitter element EE, enabling the emitter element EE to emit light.

[0210] In this case, the logic high-level period of the transmitted signal EM can overlap with the logic high-level periods of each or one of the first scan signal GW, the second scan signal GI, the third scan signal GC, and the fourth scan signal GB.

[0211] During time period MD2, the levels of one or more of the transmit signal EM and the fourth scan signal GB can be changed, while the levels of one or more of the first scan signal GW, the second scan signal GI, and the third scan signal GC can be maintained. For example, the first scan signal GW can be maintained at a logic high level, and the second scan signal GI and / or the third scan signal GC can be maintained at a logic low level. Therefore, during time period MD2, the second transistor T2, the third transistor T3, and / or the fourth transistor T4 can remain in the off state.

[0212] During time period MD2, the anode of the emitting element EE can be initialized during the logic low-level period of the fourth scan signal GB, and the fifth transistor T5 and / or the sixth transistor T6 can be turned on during the logic low-level period of the emitting signal EM. A current path can be formed between the second drive voltage line VL2 and the emitting element EE through the fifth transistor T5, the first transistor T1, and the sixth transistor T6. Then, a drive current Id is generated based on the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second drive voltage ELVDD, and the drive current Id is supplied to the emitting element EE, enabling the emitting element EE to emit light.

[0213] Unlike the first scan signal GW, the second scan signal GI, and / or the third scan signal GC, the levels of the transmit signal EM and / or the fourth scan signal GB can be changed during time period MD2 and data write time period MD1. The load of the second circuit CC2 that generates and transmits the transmit signal EM and / or the load of the fifth circuit CC5 that generates and transmits the fourth scan signal GB can be designed to be smaller than each or one or more of the loads of the first circuit CC1 that generates and transmits the first scan signal GW, the third circuit CC3 that generates and transmits the second scan signal GI, and the fourth circuit CC4 that generates and transmits the third scan signal GC. The load of each or one circuit can include various loads such as resistive loads and capacitive loads. For example, because the loads of the second circuit CC2 and the fifth circuit CC5 are designed to be relatively small even when the levels of the transmit signal EM and the fourth scan signal GB are changed more frequently in low scan rate mode, the power consumption of the capacitive load during charging and discharging can be reduced, and as a result, the power consumption of the electronic device ED (see...) can be reduced. Figure 1A and Figure 1B The power consumption of ).

[0214] Figure 8 This is a plan view of a portion of a display panel DP according to some exemplary embodiments of the present invention. Figure 9A These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'. Figure 9B These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0215] refer to Figure 6 , Figure 8 , Figure 9A and Figure 9B The display panel DP may include a pad area PDA, a first line area SPA1 and / or a second line area SPA2.

[0216] Figure 9A and Figure 9B The area AA' shown in the diagram is a region that includes a portion of each or one or more of the first scan drive circuit SDC1 and the transmit drive circuit EDC and / or a portion of the second line area SPA2. In some example embodiments, the first line area SPA1 may be referred to as the first star area SPA1, and the second line area SPA2 may be referred to as the second star area SPA2.

[0217] The pad area of ​​the PDA can be an area that outputs multiple signals and / or multiple voltages corresponding to multiple signal lines SL and / or multiple drive voltage lines VL1 and / or VL2, respectively. The signal lines SL may include a first signal line CL1, a second signal line CL2, a third signal line CL3, and / or a fourth signal line CL4.

[0218] In some exemplary embodiments of the present invention, the first signal line CL1 may include four clock lines CLK1, CLK2, CLK3 and / or CLK4 corresponding to the first-stage GW-ST1, and / or the start signal line FLM. The second signal line CL2 may include two clock lines EM_CLK1 and / or EM_CLK2 corresponding to the second-stage EM-ST, and / or the start signal line ACL_FLM. The third signal line CL3 may include two clock lines NCLK1 and / or NCLK2 corresponding to the third-stage GIGC-ST1, and / or the start signal line NFLM.

[0219] In some exemplary embodiments of the present invention, the fourth signal line CL4 may be the same as the third signal line CL3. Additionally, although not illustrated, the fifth signal line CL5 may also include a clock line and / or a start signal line corresponding to the fourth level GB-ST.

[0220] The signals output from the PDA in the pad area can be transmitted to the first scan drive circuit SDC1 and the second scan drive circuit SDC2 via the corresponding signal lines SL, through the first line area SPA1 and / or the second line area SPA2 (see...). Figure 3 ), transmit drive circuit EDC and / or display area DA.

[0221] In some exemplary embodiments of the present invention, the second line region SPA2 may be a region in which the signal line SL and the drive voltage lines VL1 and / or VL2 overlap on a plane. The first drive voltage line VL1 may include a first overlapping portion CA1 that overlaps with the signal line SL on a plane, and the second drive voltage line VL2 may include a second overlapping portion CA2 that overlaps with the signal line SL on a plane.

[0222] Figure 9A The first driving voltage line VL1 and / or the second driving voltage line VL2 shown in the figure can be connected to... Figure 5The first connection electrode CNE10 shown in the figure is disposed on the same layer. Although not shown, in some example embodiments, the first drive voltage line VL1 may include multiple layers. For example, the first drive voltage line VL1 may include a first layer drive voltage line disposed on the same layer as the third electrode G1 of the first transistor T1 and / or a second layer drive voltage line disposed on the same layer as the first connection electrode CNE10. The first layer drive voltage line and the second layer drive voltage line may be electrically connected to each other.

[0223] Figure 9B The signal line SL shown in the diagram can be connected to... Figure 5 The third electrode G1 of the first transistor T1 shown in the diagram is arranged on the same first layer, on the same second layer as the upper electrode UE, and / or on the same third layer as the third electrode G3 of the third transistor T3. Some signal lines in the signal lines SL may include multiple layers, and the multiple layers may be at least two of the first to third layers.

[0224] As mentioned above, Figure 9A The first driving voltage line VL1 and / or the second driving voltage line VL2 shown in the figure are as follows: Figure 9B The signal line SL shown in the diagram can overlap with multiple layers on a plane. Therefore, parasitic capacitance may be generated due to the overlap between the signal line SL and the drive voltage lines VL1 and VL2 in the second line region SPA2.

[0225] Figure 10A These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0226] refer to Figure 10A A first opening OP1a may be defined in the first overlapping portion CA1a of the first driving voltage line VL1a. A second opening OP2a may be defined in the second overlapping portion CA2a of the second driving voltage line VL2a. The first opening OP1a and / or the second opening OP2a may each be referred to as an opening.

[0227] In some exemplary embodiments of the present invention, a plurality of first openings OP1a and / or second openings OP2a may be provided. The plurality of first openings OP1a and / or the plurality of second openings OP2a may have a quadrilateral shape. When viewed in a plane, the first opening OP1a may be defined in a portion adjacent to the center of the first driving voltage line VL1a. For example, the four sides of each or one of the first openings OP1a may be surrounded by the first driving voltage line VL1a. When viewed in a plane, the second opening OP2a may be defined in a portion adjacent to the center of the second driving voltage line VL2a. For example, the four sides of each or one of the second openings OP2a may be surrounded by the second driving voltage line VL2a.

[0228] Figure 10B These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0229] refer to Figure 10B A first opening OP1b can be defined in the first overlapping portion CA1b of the first driving voltage line VL1b. A second opening OP2b can be defined in the second overlapping portion CA2b of the second driving voltage line VL2b.

[0230] In some exemplary embodiments of the present invention, a plurality of first openings OP1b and / or second openings OP2b may be provided. The plurality of first openings OP1b and the plurality of second openings OP2b may have a rhomboid shape. When viewed in a plane, the first opening OP1b may be defined in a portion adjacent to the center of the first driving voltage line VL1b. For example, the four sides of each or one of the first openings OP1b may be surrounded by the first driving voltage line VL1b. When viewed in a plane, the second opening OP2b may be defined in a portion adjacent to the center of the second driving voltage line VL2b. For example, the four sides of each or one of the second openings OP2b may be surrounded by the second driving voltage line VL2b.

[0231] Figure 10C These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0232] refer to Figure 10C A first opening OP1c can be defined in the first overlapping portion CA1c of the first driving voltage line VL1c. A second opening OP2c can be defined in the second overlapping portion CA2c of the second driving voltage line VL2c.

[0233] In some exemplary embodiments of the present invention, a plurality of first openings OP1c and / or second openings OP2c may be provided. The plurality of first openings OP1c and / or the plurality of second openings OP2c may have a quadrilateral shape. Furthermore, when viewed in a plane, the first opening OP1c may be defined at the upper end of the first driving voltage line VL1c. For example, the first opening OP1c may contact one side of the first driving voltage line VL1c. Therefore, the side defining the first opening OP1c may be included in the outermost line of the first driving voltage line VL1c. That is, each or one or more of the first openings OP1c may be an open opening in which a portion is not closed.

[0234] When viewed in a plane, the second opening OP2c can be defined at the upper end of the second driving voltage line VL2c. For example, the second opening OP2c can contact one side of the second driving voltage line VL2c. Therefore, the side defining the second opening OP2c can be included in the outermost line of the second driving voltage line VL2c. That is, each or one or more of the second openings OP2c can be an open opening in which a portion is not closed.

[0235] Figure 10D These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0236] refer to Figure 10D A first opening OP1d can be defined in the first overlapping portion CA1d of the first driving voltage line VL1d. A second opening OP2d can be defined in the second overlapping portion CA2d of the second driving voltage line VL2d.

[0237] In some exemplary embodiments of the present invention, a plurality of first openings OP1d and / or second openings OP2d may be provided. The plurality of first openings OP1d and / or the plurality of second openings OP2d may have a triangular shape. Furthermore, when viewed in a plane, the first opening OP1d may be defined at the upper end of the first driving voltage line VL1d. For example, the first opening OP1d may contact one side of the first driving voltage line VL1d. Therefore, the side defining the first opening OP1d may be included in the outermost line of the first driving voltage line VL1d. That is, each or one or more of the first openings OP1d may be an open opening in which a portion is not closed.

[0238] When viewed in a plane, the second opening OP2d can be defined at the upper end of the second driving voltage line VL2d. For example, the second opening OP2d can contact one side of the second driving voltage line VL2d. Therefore, the side defining the second opening OP2d can be included in the outermost line of the second driving voltage line VL2d. That is, each or one or more of the second openings OP2d can be an open opening in which a portion is not closed.

[0239] Figure 10E These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0240] refer to Figure 10E A first opening OP1e can be defined in the first overlapping portion CA1e of the first driving voltage line VL1e. A second opening OP2e can be defined in the second overlapping portion CA2e of the second driving voltage line VL2e.

[0241] In some exemplary embodiments of the present invention, the first opening OP1e and / or the second opening OP2e may have an elongated quadrilateral shape. Figures 10A to 10D Unlike in China, in Figure 10E In this context, the first opening OP1e and the second opening OP2e can each be defined as one. Figure 10E The size of each or more of the first opening OP1e and the second opening OP2e can be greater than Figures 10A to 10D The dimensions of each or one or more openings in the structure.

[0242] When viewed in a plane, the first opening OP1e can be defined by removing a portion of the upper part of the first driving voltage line VL1e. Therefore, the width of the first driving voltage line VL1e can be reduced due to the first opening OP1e. For example, the first opening OP1e can contact one side of the first driving voltage line VL1e. Therefore, the side defining the first opening OP1e can be included in the outermost line of the first driving voltage line VL1e. That is, the first opening OP1e can be an open opening in which a portion is not closed.

[0243] When viewed in a plane, the second opening OP2e can be defined by removing a portion of the upper part of the second driving voltage line VL2e. Therefore, the width of the second driving voltage line VL2e can be reduced due to the second opening OP2e. For example, the second opening OP2e can contact one side of the second driving voltage line VL2e. Therefore, the side defining the second opening OP2e can be included in the outermost line of the second driving voltage line VL2e. That is, the second opening OP2e can be an open opening in which a portion is not closed.

[0244] Figure 10F These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0245] refer to Figure 10F A first opening OP1f can be defined in the first overlapping portion CA1f of the first driving voltage line VL1f. A second opening OP2f can be defined in the second overlapping portion CA2f of the second driving voltage line VL2f.

[0246] In some exemplary embodiments of the present invention, the first opening OP1f and / or the second opening OP2f may have an elongated quadrilateral shape. For example, in Figure 10E In Figure 10F In this context, the first opening OP1f and / or the second opening OP2f can each be defined as one.

[0247] As in Figure 10E In Figure 10F In the diagram, when viewed in a plane, the first opening OP1f can be defined by removing a portion of the lower part of the first driving voltage line VL1f. Therefore, the width of the first driving voltage line VL1f can be reduced due to the first opening OP1f. Similarly, when viewed in a plane, the second opening OP2f can be defined by removing a portion of the lower part of the second driving voltage line VL2f. Therefore, the width of the second driving voltage line VL2f can be reduced due to the second opening OP2f.

[0248] Figure 10G These are some example embodiments of the concept of the present invention. Figure 8 Enlarged plan view of area AA'.

[0249] refer to Figure 10G The first opening OP1g can be defined in the first overlapping portion CA1g of the first driving voltage line VL1g.

[0250] In some exemplary embodiments of the present invention, multiple first openings OP1g can be provided. The multiple first openings OP1g can have a quadrilateral shape. Figures 10A to 10F Unlike in China, in Figure 10G In this case, the first opening OP1g may be formed only in the first driving voltage line VL1g, and may not be defined in the second driving voltage line VL2g.

[0251] When viewed in a plane, the first opening OP1g can be defined at the lower end of the first driving voltage line VL1g. For example, the first opening OP1g can contact one side of the first driving voltage line VL1g. Therefore, the side defining the first opening OP1g can be included in the outermost line of the first driving voltage line VL1g. For example, each of the first openings OP1g can be an open opening in which a portion is not closed.

[0252] exist Figures 10A to 10G The illustrations show some example embodiments, but some example embodiments of the inventive concept are not limited thereto, and the shape and position of each or more of the first opening and the second opening can be applied in various ways, and the size of each or more of the first opening and the second opening can also be applied in various ways.

[0253] Figure 11 This illustrates some example embodiments of a display panel DP based on the concept of the present invention (see...). Figure 3 A table showing the power consumption of ( ).

[0254] exist Figure 11 In the middle, the display panel DP (see Figure 3 The power consumption for each frequency is shown in the table. Figure 11 The comparative example described in the text is Figure 9A An example of the power consumption of the display panel in the image, and Figure 11 The example described in is Figure 10A The display panel DP in the middle (see Figure 3 Example of power consumption.

[0255] refer to Figure 3 , Figure 8 , Figure 9A , Figure 10A and Figure 11 As shown in the reference above Figure 9A The above, Figure 9B The first driving voltage line VL1 and / or the second driving voltage line VL2 and the signal line SL shown in the figure can be arranged overlapping multiple layers on a plane. Therefore, parasitic capacitance may be generated in the second line region SPA2, especially in the region where the first overlapping portion CA1 of the first driving voltage line VL1 and the second overlapping portion CA2 of the second driving voltage line VL2 are arranged.

[0256] Signal line SL may include a clock line to which a clock signal is provided. Therefore, the level of the signal provided to signal line SL can be changed periodically. As the level of the signal provided to signal line SL changes, there may be power consumption due to the charging and discharging of a capacitive load. According to some exemplary embodiments of the present invention, designs can be applied to reduce the capacitive load formed in signal line SL.

[0257] exist Figure 10A In this configuration, the first opening OP1a can be defined within the first overlapping portion CA1a of the first driving voltage line VL1a, and / or the second opening OP2a can be defined within the second overlapping portion CA2a of the second driving voltage line VL2a. Therefore, the area where the first driving voltage line VL1, the second driving voltage line VL2, and the signal line SL overlap in the plane can be reduced. That is, in the second line region SPA2, the parasitic capacitance between the first driving voltage line VL1, the second driving voltage line VL2, and / or the signal line SL can be reduced. Additionally, the capacitive load of each or one or more of the signal lines SL can be reduced.

[0258] In some exemplary embodiments of the present invention, if the capacitive load formed in the signal line SL is reduced, the power consumption of the capacitive load during charging and discharging can be reduced, and as a result, the power consumption of the entire display panel DP can also be reduced. For example, when the display panel DP operates at 120Hz, the power consumption of the display panel according to the comparative example can be measured as 217.6mW, and the power consumption of the display panel DP according to the example can be measured as 199.9mW. Therefore, the power consumption can be reduced by 8.2%. In addition, at 60Hz, the power consumption can be reduced by 6.8% compared to the power consumption of the comparative example, and at 1Hz, the power consumption can be reduced by 3.4% compared to the power consumption of the comparative example.

[0259] Figure 11 The diagram shows Figure 9A and Figure 10A The power consumption is taken as an example, but some exemplary embodiments of the present invention are not limited thereto. For example, in Figures 10B to 10G In the example embodiment illustrated in the figure, the parasitic capacitance of the second line region SPA2 is reduced, such that, as in Figure 10A In this way, power consumption can be reduced.

[0260] Figure 12A This is a layout of multiple scan lines GWL, GIL, GCL and GBL and an emission control line EMLA according to some exemplary embodiments of the present invention.

[0261] refer to Figure 6 , Figure 7 and Figure 12A The first to fourth scan lines GWL, GIL, GCL, and GBL, as well as the emission control line EMLa, are electrically connected to the pixel PX, and when viewed on a flat surface, they can be seen as... Figure 12A The arrangement shown is merely an example, and the arrangement of the first to fourth scan lines GWL, GIL, GCL, and GBL, as well as the transmit control line EMLa, can be altered.

[0262] As referenced above Figure 7 Specifically, during the data writing period MD1, the levels of one or more of the signals provided to the first to fourth scan lines GWL, GIL, GCL, and GBL, as well as the transmit control line EMLa, can be changed. Additionally, during the period MD2, the signals provided to the first to third scan lines GWL, GIL, and GCL can maintain predetermined or alternately given levels, but the levels of the signals provided to the transmit control line EMLa and the fourth scan line GBL can be changed. If the levels of the signals provided to the predetermined or alternately given lines are changed, power consumption may increase due to the charging and discharging of capacitive loads generated in the predetermined or alternately given lines.

[0263] In some exemplary embodiments of the present invention, in order to reduce or minimize the power consumption of the capacitive load during charging and discharging, the capacitive load of each or more of the transmit control line EMLa and the fourth scan line GBL can be adjusted to be smaller than the capacitive load of each or more of the first to third scan lines GWL, GIL, and GCL. Therefore, since the capacitive load of each or more of the transmit control line EMLa and the fourth scan line GBL, where the signal level changes more frequently, is adjusted to be relatively small, the power consumption of the electronic device ED (see...) can be reduced. Figure 1A and Figure 1B Total power consumption.

[0264] In some exemplary embodiments of the present invention, to adjust the capacitive load, the width of one or more of the first to fourth scan lines GWL, GIL, GCL, and GBL, and the transmit control line EMLa, can be adjusted. For example, the first scan line GWL can have a first width W1. The transmit control line EMLa can have a second width W2. The first width W1 can be greater than the second width W2. Therefore, when the first width W1 is greater than the second width W2, the capacitive load of the first scan line GWL can be greater than the capacitive load of the transmit control line EMLa.

[0265] exist Figure 12AIn this example, the widths of each of the first scan line GWL and the transmit control line EMLa are compared. However, some exemplary embodiments of the present invention are not limited to this example, and the second width W2 of the transmit control line EMLa can be smaller than the width of each or one or more of the second scan line GIL and the third scan line GCL. Furthermore, the width of the fourth scan line GBL can also be smaller than the width of each or one or more of the first scan line GWL, the second scan line GIL, and the third scan line GCL. Therefore, the capacitive load of each or one or more of the first scan line GWL, the second scan line GIL, and the third scan line GCL can be greater than the capacitive load of each or one or more of the transmit control line EMLa and the fourth scan line GBL.

[0266] Figure 12B This is a layout of multiple scan lines GWL, GIL, GCL and GBL and transmit control line EML according to some exemplary embodiments of the present invention.

[0267] refer to Figure 6 , Figure 7 and Figure 12B In order to adjust the capacitive load of each or one of the first scan lines to the fourth scan lines GWL, GIL, GCL and GBL and the transmit control line EML, the distance between the first scan lines to the fourth scan lines GWL, GIL, GCL and GBL and the transmit control line EML can be adjusted.

[0268] For example, the distance between the first scan line GWL and other scan lines GIL and / or GBL adjacent to the first scan line GWL can be a first distance DT1. In this case, the distance between the first scan line GWL and the second scan line GIL, and the distance between the first scan line GWL and the fourth scan line GBL, can also be the first distance DT1. Figure 12B In this example, the distance between the first scan line GWL and the second scan line GIL, as well as the distance between the first scan line GWL and the fourth scan line GBL, are the same. However, some exemplary embodiments of the present invention are not limited to this example.

[0269] The distance between the transmit control line EML and other adjacent scan lines GBL and / or GCL can be a second distance DT2. In this case, the distance between the transmit control line EML and the fourth scan line GBL, and the distance between the transmit control line EML and the third scan line GCL, can be the second distance DT2. Figure 12B In this example, the distance between the transmit control line EML and the fourth scan line GBL and the distance between the transmit control line EML and the third scan line GCL are the same, but some exemplary embodiments of the present invention are not limited to this example.

[0270] The distance between lines can affect the capacitive load formed in each or one or more of the lines. For example, if the distance between the lines is small, the capacitive load can increase due to interference with adjacent lines, and correspondingly, the power consumption may increase depending on the level of the corresponding signal.

[0271] In some exemplary embodiments of the present invention, the first distance DT1 may be smaller than the second distance DT2. Therefore, since the capacitive loads of each or more of the transmit control line EML and the fourth scan line GBL, where the signal levels change more frequently, are adjusted to be relatively small, the electronic device ED (see [reference]) can be reduced. Figure 1A and Figure 1B Total power consumption.

[0272] exist Figure 12B In this example, the distances between the first scan line GWL and other scan lines GIL and / or GBL adjacent to the first scan line GWL, and the distances between the transmit control line EML and other scan lines GBL and / or GCL adjacent to the transmit control line EML are compared. However, some exemplary embodiments of the present invention are not limited to this example.

[0273] Figure 13 This is a table showing the values ​​of the capacitive loads of multiple scan lines GWL, GIL, GCL and GBL and the transmit control line EML in some exemplary embodiments of the present invention.

[0274] and Figure 12A and Figure 12B Different from China Figure 13 The comparative examples described illustrate the magnitude of the capacitive load when the width of each of the multiple scan lines and emitter control lines, or the distance between adjacent lines, is the same. Figure 13 The example described in the text shows Figure 12A or Figure 12B The size of the capacitive load is used as an example.

[0275] According to the comparative example, the capacitance of the capacitive load on the transmit control line can be maximum, at 70.54 pF. (See above reference.) Figure 7 Unlike the first scan signal GW, the second scan signal GI, and / or the third scan signal GC, the levels of the transmit signal EM and / or the fourth scan signal GB can be changed during the self-time period MD2 and the data write time period MD1. Therefore, according to the comparative example, whenever the signal level of the transmit control line is changed, the power consumption may increase due to the charging and discharging of the capacitive load formed in the transmit control line.

[0276] According to some exemplary embodiments of the present invention, the capacitance of the capacitive load of the transmit control lines EML and / or EMLa can be minimal, at 44.26 pF, and the capacitance of the capacitive load of the fourth scan line GBL can be the second smallest, at 57.28 pF. Therefore, since the capacitive loads of each or more of the transmit control lines EML and / or EMLa and the fourth scan line GBL, where the signal level changes more frequently, are adjusted to be relatively small, the electronic device ED (see...) can be reduced. Figure 1A and Figure 1B Total power consumption.

[0277] In some exemplary embodiments of the present invention, when the capacitive load of each or one or more of the first to fourth scan lines GWL, GIL, GCL and GBL and the transmit control lines EML and / or EMLA is adjusted, the load of the second circuit CC2 corresponding to the transmit signal EM and the load of the fifth circuit CC5 corresponding to the fourth scan signal GB can be adjusted to be less than the load of the first circuit CC1 corresponding to the first scan signal GW, the load of the third circuit CC3 corresponding to the second scan signal GI and the load of the fourth circuit CC4 corresponding to the third scan signal GC.

[0278] although Figure 12A and Figure 12B The illustrations show some example implementations where the width of the lines or the distance between the lines is adjusted, but various other methods can be applied to adjust the capacitive load of each line.

[0279] Unlike the comparative example, the capacitive load of the first scan line GWL in this example can be greater than the capacitive load of the transmit control lines EML and / or EMLA. Therefore, the load of the first circuit CC1, which includes the first scan line GWL, can be greater than the load of the second circuit CC2, which includes the transmit control lines EML and / or EMLA.

[0280] In some exemplary embodiments of the present invention, the capacitive load of the transmit control lines EML and / or EMLa may be less than each or one or more of the capacitive load of the second scan line GIL and the third scan line GCL. Therefore, the load of the second circuit CC2, which includes the transmit control lines EML and / or EMLa, may be less than each or one or more of the load of the third circuit CC3, which includes the second scan line GIL, and the load of the fourth circuit CC4, which includes the third scan line GCL.

[0281] In some exemplary embodiments of the present invention, the capacitive load of the fourth scan line GBL may be less than one or more of the capacitive loads of the first scan line GWL, the second scan line GIL, and the third scan line GCL. Therefore, the load of the fifth circuit CC5, including the fourth scan line GBL, may be less than one or more of the loads of the first circuit CC1, including the first scan line GWL, the third circuit CC3, including the second scan line GIL, and the fourth circuit CC4, including the third scan line GCL.

[0282] Figure 14 This illustrates some example embodiments of a display panel DP based on the concept of the present invention (see...). Figure 3 A table showing the power consumption of ( ).

[0283] exist Figure 14 In the middle, the display panel DP (see Figure 3 The power consumption for each frequency is shown in the table. Figure 14 The comparative examples described in the text describe the... Figure 13 The power consumption of the display panel in the comparative example described in the text, and Figure 14 The examples described in the text describe about Figure 13 The example display panel DP described in [the document] (see [the document]). Figure 3 The power consumption of ).

[0284] Let's refer to each other. Figure 3 and Figure 13 In a comparative example, the capacitance of the capacitive load on the transmit control line can be the largest, at 70.54 pF. However, in some exemplary embodiments of the invention, the capacitance of the capacitive load on the transmit control lines EML and / or EMLa can be the smallest, at 44.26 pF, and the capacitance of the capacitive load on the fourth scan line GBL can be the second smallest, at 57.28 pF. Therefore, since the capacitive loads of each or more of the transmit control lines EML and / or EMLa and the fourth scan line GBL, where the signal level changes more frequently, are adjusted to be relatively small, the capacitance of the electronic device ED (see...) can be reduced. Figure 1A and Figure 1B Total power consumption.

[0285] When the display panel DP is operated at 120Hz, the power consumption of the display panel according to the comparative example can be measured as 219.16mW, and the power consumption of the display panel DP according to the example can be measured as 215.36mW. Therefore, the power consumption can be reduced by 1.7%.

[0286] According to some example embodiments, power consumption improvements can be increased in low-frequency drive. For example, in low-frequency drive mode, self-time period MD2 (see [link to example]) is included in a frame. Figure 7 The number of MD2 (see MD2) can be increased. Figure 7 In this embodiment, the signals provided to the first scan lines GWL, GIL, and GCL from the time period MD2 are maintained at predetermined or alternately given levels, while the levels of the signals provided to the transmit control lines EML and / or EMLa and / or the fourth scan line GBL can be changed. Therefore, when the capacitive load of the transmit control lines EML and / or EMLa and / or the fourth scan line GBL is adjusted to a relatively small value, at 60Hz, power consumption can be reduced by 4.6% compared to the comparative example, and at 1Hz, power consumption can be reduced by 9.0% compared to the comparative example.

[0287] As described above, the capacitive load of the transmit control line, where the signal level changes relatively frequently, can be designed to be smaller than that of the scan line (e.g., the first scan line). Additionally, an opening can be provided for the drive voltage line overlapping the signal line to reduce the overlap area between the signal line and the drive voltage line. Therefore, the capacitive load formed in the signal line can be further reduced. In this case, the power consumption of the capacitive load due to changes in the signal level provided to predetermined or alternately given lines is reduced, and thus, the power consumption of the electronic device can be reduced.

[0288] One or more of the elements disclosed above may include or be implemented in: one or more processing circuits such as hardware including logic circuits; hardware / software combinations such as processors executing software; or combinations thereof. For example, more specifically, the processing circuits may include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0289] In the foregoing description, some exemplary embodiments of the present invention have been described with reference to the inventive concept. However, those skilled in the art will understand that various modifications and alterations can be made to the inventive concept, as long as such modifications and alterations do not depart from the spirit and technical scope of the inventive concept set forth in the claims. Therefore, the technical scope of the inventive concept is not limited to the contents stated in the detailed description of the specification, but should be determined by the claims.

Claims

1. An electronic device comprising: The base layer includes a first region and a second region adjacent to the first region; Pixels, in the first region; Multiple scan lines, in the first region, and including a first scan line electrically connected to the pixel; A transmission control line is located in the first region and is electrically connected to the pixel; A scan drive circuit is located in the second region and is electrically connected to the plurality of scan lines; A transmit drive circuit is located in the second region and is electrically connected to the transmit control line; Multiple driving voltage lines are located in the second region and are electrically connected to the pixel; as well as Multiple signal lines, in the second region, include a first signal line electrically connected to the scan driving circuit and a second signal line electrically connected to the transmit driving circuit. The load of the first circuit, which includes the first scan line and the first signal line, is greater than the load of the second circuit, which includes the transmit control line and the second signal line.

2. The electronic device according to claim 1, wherein: The plurality of scan lines further includes a second scan line, a third scan line, and a fourth scan line; and The plurality of signal lines further includes a third signal line, a fourth signal line, and a fifth signal line electrically connected to the scan drive circuit.

3. The electronic device according to claim 2, wherein, The scan drive circuit is configured to output a first scan signal to the first scan line. The transmit drive circuit is configured to output a transmit signal to the transmit control line, and During the self-time period, the scan driving circuit is configured to maintain the level of the first scan signal, and the transmit driving circuit is configured to change the level of the transmit signal.

4. The electronic device according to claim 3, wherein, The scan drive circuit is configured to output a second scan signal to the second scan line, a third scan signal to the third scan line, and a fourth scan signal to the fourth scan line. During the self-time period, the scan drive circuit is configured to maintain the level of the second scan signal and the level of the third scan signal, and change the level of the fourth scan signal.

5. The electronic device according to claim 2, wherein, The load of the second circuit is less than the load of the third circuit, which includes the second scan line and the third signal line, and the load of the fourth circuit, which includes the third scan line and the fourth signal line.

6. The electronic device according to claim 5, wherein, The load of the fifth circuit, which includes the fourth scan line and the fifth signal line, is less than the load of the first circuit, the load of the third circuit, and the load of the fourth circuit.

7. The electronic device according to claim 1, wherein, The first width of the first scan line is greater than the second width of the emission control line.

8. The electronic device according to claim 1, wherein, The first distance between the first scan line and the plurality of other scan lines adjacent to the first scan line is less than the second distance between the emission control line and the plurality of other scan lines adjacent to the emission control line.

9. The electronic device according to claim 1, wherein, The capacitive load of the first scan line is greater than the capacitive load of the emission control line.

10. The electronic device according to claim 9, wherein: The plurality of scan lines further includes a second scan line, a third scan line, and a fourth scan line; and The capacitive load of the transmit control line is less than the capacitive load of the second scan line and the capacitive load of the third scan line.

11. The electronic device according to claim 10, wherein, The capacitive load of the fourth scan line is less than each of the capacitive loads of the first scan line, the second scan line, and the third scan line.

12. The electronic device according to any one of claims 1-11, wherein, The plurality of driving voltage lines include a first driving voltage line that is provided with a first driving voltage and a second driving voltage line that is provided with a second driving voltage. in: The first driving voltage line includes a first overlapping portion that overlaps with the plurality of signal lines on a plane; and The second driving voltage line includes a second overlapping portion that overlaps with the plurality of signal lines on the plane.

13. The electronic device according to claim 12, wherein, The first overlapping portion includes a first opening.

14. The electronic device according to claim 13, wherein, The first opening is provided as multiple.

15. The electronic device according to claim 12, wherein, The first overlapping portion includes a first opening, and the second overlapping portion includes a second opening.

16. The electronic device according to claim 15, wherein, The first opening is provided in multiple ways, and the second opening is provided in multiple ways.

17. An electronic device comprising: A display panel includes a display area and a non-display area adjacent to the display area, wherein the display panel includes: A pixel, located in the display area, includes pixel circuitry and an emitting element; The first scan line is electrically connected to the pixel circuit; and The transmit control line is electrically connected to the pixel circuit. The capacitive load of the first scan line is greater than the capacitive load of the emission control line.

18. The electronic device of claim 17, further comprising: The processing circuit is configured as follows: The pixel circuit is operated based on the data writing period and the self-period; During the data writing period, the level of the first scan signal provided to the first scan line is changed; During the self-time period, the level of the first scan signal provided to the first scan line is maintained; and During the data writing period and the self-time period, the level of the transmission signal provided to the transmission control line is changed.

19. The electronic device according to claim 18, wherein, The display panel further includes a second scan line, a third scan line, and a fourth scan line. Wherein, the capacitive load of the transmit control line is less than the capacitive load of the second scan line and the capacitive load of the third scan line. Wherein, the capacitive load of the fourth scan line is less than each of the capacitive loads of the first scan line, the second scan line, and the third scan line, and The processing circuit is configured to maintain the level of each of the signals provided to the second scan line and the third scan line during the self-period, and to change the level of the signal provided to the fourth scan line during the self-period.

20. The electronic device according to any one of claims 17-19, wherein, The display panel further includes: Multiple signal lines are located in the non-display area; and A driving voltage line, in the non-display area, is configured to transmit a driving voltage to the pixel, the driving voltage line including at least one opening in a plane overlapping the plurality of signal lines.

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