Flyback converter synchronous rectification control method, flyback converter circuit and chip

Abstract

The present application relates to the field of switching power supply control, and particularly relates to a flyback converter synchronous rectification control method, a flyback converter circuit and a chip. The control method comprises obtaining a first drain-source voltage signal of a secondary side synchronous rectification tube, a voltage holding time threshold value; when the first drain-source voltage signal is a high level and the holding time is greater than the voltage holding time threshold value, obtaining a rectification tube enable signal allowing the rectification tube to conduct, and when the rectification tube conduction signal is obtained, the secondary side synchronous rectification tube conducts; when the holding time of the high level of the first drain-source voltage signal is not greater than the voltage holding time threshold value, the secondary side synchronous rectification tube does not conduct. Based on the first drain-source voltage signal of the secondary side synchronous rectification tube and the voltage holding time threshold value, the rectification tube enable signal and the rectification tube conduction signal allowing the rectification tube to conduct are obtained, the true rectification demand of the secondary side synchronous rectification tube is judged, and the conduction or non-conduction of the secondary side synchronous rectification tube is regulated.

Description

Technical Field

[0001] This invention relates to the field of switching power supply control, and more particularly to a synchronous rectification control method for a flyback converter, a flyback converter circuit, and a chip. Background Technology

[0002] Flyback converters, with their advantages of simple structure, low cost, ease of implementing multiple outputs, and electrical isolation, have been widely used in the field of low-power switching power supplies. As power systems increasingly demand higher efficiency and higher power density, synchronous rectification technology has become the mainstream choice for flyback converters.

[0003] In the synchronous rectification control of flyback converters, firstly, during the energy transfer from the primary side to the secondary side (i.e., after the primary side main switch is turned off), the secondary side synchronous rectifier should be turned on promptly and reliably to provide a low-impedance freewheeling path; secondly, before the primary side main switch is turned on again, the secondary side synchronous rectifier should be completely turned off. If the control is improper, during the brief overlap between the primary side main switch and the secondary side synchronous rectifier being turned on simultaneously, the primary and secondary sides will be connected together. This will not only cause a sharp drop in converter efficiency and a serious deterioration in electromagnetic interference (EMI), but will also damage the main switch and the secondary side synchronous rectifier due to overcurrent and overheating, seriously threatening the reliability of the power supply system. Therefore, the existing technology still lacks a simple and reliable synchronous rectification control method for flyback converters to eliminate the risk of connection and ensure the high efficiency and long-term stable operation of the power supply system. Summary of the Invention

[0004] In view of this, in order to solve the above-mentioned technical problems, embodiments of the present invention provide a synchronous rectification control method for a flyback converter, a flyback converter circuit, and a chip.

[0005] The following technical solution is adopted in this application:

[0006] This invention provides a synchronous rectification control method for a flyback converter, wherein the flyback converter includes a primary-side main switch, a primary-side winding, a secondary-side winding, and a secondary-side synchronous rectifier, characterized in that it includes:

[0007] Obtain the first drain-source voltage signal and voltage hold time threshold of the secondary-side synchronous rectifier diode;

[0008] When the first drain-source voltage signal is high and the holding time is greater than the voltage holding time threshold, a rectifier enable signal that allows the rectifier to conduct is obtained, and when the control terminal of the secondary synchronous rectifier obtains the rectifier conduction signal, the secondary synchronous rectifier is turned on.

[0009] When the high-level holding time of the first drain-source voltage signal is not greater than the voltage holding time threshold, the secondary-side synchronous rectifier is not turned on.

[0010] Optionally, the step of obtaining the holding time of the first drain-source voltage signal at a high level includes:

[0011] The first drain-source voltage signal is processed to obtain a second drain-source voltage signal with the same waveform but a time lag compared to the first drain-source voltage signal;

[0012] When the first drain-source voltage signal coincides with the second drain-source voltage signal, the coincidence time is obtained, and the coincidence time is used as the holding time of the high level of the drain-source voltage.

[0013] Optionally, the step of determining that the first drain-source voltage signal and the second drain-source voltage signal coincide includes:

[0014] Obtain the judgment threshold;

[0015] When the absolute value of the difference between the first drain-source voltage signal and the second drain-source voltage signal is not greater than the determination threshold, it is determined that the first drain-source voltage signal and the second drain-source voltage signal coincide.

[0016] Optionally, the step of obtaining the rectifier tube conduction signal at the control terminal of the secondary-side synchronous rectifier tube includes:

[0017] Obtain the turn-on threshold of the secondary-side synchronous rectifier diode;

[0018] When the first drain-source voltage signal drops below the turn-on threshold, the control terminal of the secondary-side synchronous rectifier obtains the rectifier turn-on signal.

[0019] When the rectifier tube conduction signal and the rectifier tube enable signal that allow the rectifier tube to conduct are obtained, the secondary side synchronous rectifier tube is turned on.

[0020] Optionally, the flyback converter circuit further includes a primary-side control module, a secondary-side control module, and a control circuit; specifically, the flyback converter circuit comprises: the primary-side main switch and the primary-side winding forming a first series structure, one end of the first series structure being a voltage input terminal, and the other end of the first series structure being grounded; the secondary-side synchronous rectifier and the secondary-side winding forming a second series structure, one end of the second series structure being a voltage output terminal, and the other end of the second series structure being grounded; the first output terminal of the primary-side control module is connected to the control terminal of the primary-side main switch, the first output terminal of the secondary-side control module is connected to the control terminal of the secondary-side synchronous rectifier, the second output terminal of the secondary-side control module is connected to the input terminal of the control circuit, and the output terminal of the control circuit is connected to the input terminal of the secondary-side control module.

[0021] The present invention also provides a flyback converter circuit, comprising:

[0022] The flyback converter main circuit and control circuit;

[0023] The flyback converter main circuit includes a primary-side main switch, a primary-side winding, a secondary-side winding, and a secondary-side synchronous rectifier.

[0024] The control circuit is used to acquire the first drain-source voltage signal and the voltage holding time threshold of the secondary-side synchronous rectifier; when the first drain-source voltage signal is high and the holding time is greater than the voltage holding time threshold, the control circuit acquires the rectifier enable signal that allows the rectifier to conduct; and when the control terminal of the secondary-side synchronous rectifier acquires the rectifier conduction signal, the secondary-side synchronous rectifier conducts; when the holding time of the high level of the first drain-source voltage signal is not greater than the voltage holding time threshold, the secondary-side synchronous rectifier does not conduct.

[0025] Optionally, the control circuit includes:

[0026] The circuit includes a sampling circuit, a switch threshold detection circuit, and a logic control circuit; the output terminal of the sampling circuit is connected to the input terminal of the switch threshold detection circuit and the first input terminal of the logic control circuit, and the output terminal of the switch threshold detection circuit is connected to the second input terminal of the logic control circuit.

[0027] The sampling circuit is used to acquire the first drain-source voltage signal of the secondary-side synchronous rectifier diode;

[0028] The switching threshold detection circuit is used to obtain the rectifier tube turn-on signal and rectifier tube turn-off signal at the control terminal of the secondary side synchronous rectifier tube;

[0029] The logic control circuit is used to obtain the voltage holding time threshold, and based on the first drain-source voltage signal, the voltage holding time threshold and the rectifier diode conduction signal, control the secondary-side synchronous rectifier diode to conduct or not conduct.

[0030] Optionally, the control circuit further includes:

[0031] A second drain-source voltage signal acquisition circuit and a signal processing circuit; the output terminal of the sampling circuit is connected to the input terminal of the second drain-source voltage signal acquisition circuit and the first input terminal of the signal processing circuit, the output terminal of the second drain-source voltage signal acquisition circuit is connected to the second input terminal of the signal processing circuit, and the output terminal of the signal processing circuit is connected to the first input terminal of the logic control circuit;

[0032] The second drain-source voltage signal acquisition circuit is used to process the first drain-source voltage signal to obtain a second drain-source voltage signal with the same waveform but a time lag compared to the first drain-source voltage signal.

[0033] The signal processing circuit is used to output a coincidence signal to the logic control circuit when the first drain-source voltage signal coincides with the second drain-source voltage signal.

[0034] The logic control circuit obtains the overlap time of the first drain-source voltage signal and the second drain-source voltage signal based on the overlap signal, and the overlap time is used as the holding time of the high level of the drain-source voltage.

[0035] Optionally, the flyback converter main circuit further includes a primary-side control module and a secondary-side control module; specifically, the flyback converter main circuit comprises: the primary-side main switch and the primary-side winding forming a first series structure, one end of the first series structure being a voltage input terminal, and the other end of the first series structure being grounded; the secondary-side synchronous rectifier and the secondary-side winding forming a second series structure, one end of the second series structure being a voltage output terminal, and the other end of the second series structure being grounded; the first output terminal of the primary-side control module is connected to the control terminal of the primary-side main switch, the first output terminal of the secondary-side control module is connected to the control terminal of the secondary-side synchronous rectifier, the second output terminal of the secondary-side control module is connected to the input terminal of the control circuit, and the input terminal of the secondary-side control module is connected to the output terminal of the control circuit.

[0036] The present invention provides a chip for implementing the above-described synchronous rectification control method for a flyback converter.

[0037] In summary, the advantages and beneficial effects of the present invention are as follows:

[0038] This invention provides a synchronous rectification control method for a flyback converter, a flyback converter circuit, and a chip. The synchronous rectification control method for the flyback converter includes: acquiring a first drain-source voltage signal and a voltage hold-time threshold of the secondary-side synchronous rectifier; when the first drain-source voltage signal is high and its hold-time is greater than the voltage hold-time threshold, acquiring a rectifier enable signal that allows the rectifier to conduct; and when the control terminal of the secondary-side synchronous rectifier acquires a rectifier conduction signal, the secondary-side synchronous rectifier conducts; when the high level of the first drain-source voltage signal is held for a time not greater than the voltage hold-time threshold, the secondary-side synchronous rectifier does not conduct.

[0039] Based on the first drain-source voltage signal of the secondary-side synchronous rectifier and the voltage holding time threshold, the actual rectification demand of the secondary-side synchronous rectifier is determined, and the conduction or non-conduction of the secondary-side synchronous rectifier is controlled. That is: when the first drain-source voltage signal of the secondary-side synchronous rectifier is high and held for a certain time, the corresponding primary-side main switch is turned on, and the secondary-side synchronous rectifier corresponds to the actual rectification demand. The rectifier enable signal and rectifier turn-on signal are obtained to jointly control the secondary-side synchronous rectifier to turn on for rectification. When the first drain-source voltage signal of the secondary-side synchronous rectifier is high, but the high-level holding time of the first drain-source voltage signal is less than a certain time, the secondary-side synchronous rectifier does not correspond to the actual rectification demand, and the secondary-side synchronous rectifier is controlled to turn off. This accurately controls the turn-on timing of the secondary-side synchronous rectifier and effectively avoids the risk of primary and secondary sides being connected due to accidental turn-on of the secondary-side synchronous rectifier. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, but they should fall within the protection scope of this application.

[0041] Figure 1 This is a schematic diagram of an asymmetric half-bridge flyback converter circuit.

[0042] Figure 2 This is a schematic diagram of the timing waveform of the rectifier control signal in an asymmetric half-bridge flyback converter.

[0043] Figure 3 A schematic diagram of a flyback converter circuit provided in an embodiment of the present invention;

[0044] Figure 4 A schematic diagram of an asymmetric half-bridge flyback converter circuit provided in an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the control circuit of a flyback converter circuit provided in an embodiment of the present invention;

[0046] Figure 6 A schematic diagram of the control circuit of a flyback converter circuit provided in an embodiment of the present invention;

[0047] Figure 7 A schematic diagram of the control circuit of a flyback converter circuit provided in an embodiment of the present invention;

[0048] Figure 8A schematic diagram of the control circuit of a flyback converter circuit provided in an embodiment of the present invention;

[0049] Figure 9 A flowchart illustrating a synchronous rectification control method for a flyback converter provided in an embodiment of the present invention;

[0050] Figure 10 This is a timing diagram illustrating the operation of a synchronous rectification control method for a flyback converter provided in an embodiment of the present invention. Detailed Implementation

[0051] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0052] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0053] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. Electrical connection primarily refers to the transmission of signals, including direct and indirect electrical connections.

[0054] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0055] The flyback converter described in this invention includes, but is not limited to, flyback converters, active clamp flyback converters (ACF), asymmetric half-bridge flyback converters (AHB), two-transistor flyback converters, or zero-voltage switching flyback converters (ZVSFlyback).

[0056] This invention is illustrated using an asymmetric half-bridge flyback converter (AHB) as an example.

[0057] like Figure 1As shown, in the novel flyback converter represented by the asymmetrical half-bridge flyback converter, a resonant circuit is constructed by adding an auxiliary switch QL and resonant devices (resonant capacitor Cr and resonant inductor Lr) on the primary side. The zero-voltage turn-on of the primary main switch is achieved by utilizing the resonance principle, thereby reducing the switching losses of the system and further improving the conversion efficiency of the converter. Here, QH is the main switch and QS is the secondary synchronous rectifier.

[0058] like Figure 2 As shown, in one duty cycle, the asymmetric half-bridge flyback converter AHB will have its primary-side auxiliary switch QL turn on twice. The first turn-on of QL is for freewheeling, pulling down the secondary winding voltage and causing the drain-source voltage VDS_QS of the secondary synchronous rectifier QS to decrease. Figure 2 During the dt1 stage shown, the secondary-side synchronous rectifier QS turns on for rectification. Before the primary-side main switch QH outputs and drives the next cycle, the secondary-side auxiliary switch QL turns on a second time to achieve the resonant pulse for the zero-voltage switching of the main switch QH, i.e., the ZVS Pulse. At this time, the drain-source voltage VDS_QS of the secondary-side synchronous rectifier QS drops again, as shown. Figure 2 During the dt2 stage shown, the secondary-side synchronous rectifier will turn on again (the secondary-side synchronous rectifier is mistakenly turned on during the ZVS resonance stage; the secondary-side synchronous rectifier cannot accurately distinguish between a normal rectification turn-on signal and an interference signal caused by ZVSSPulse). However, ZVS... After the pulse ends, the primary-side main switch QH will quickly turn on. If the secondary-side synchronous rectifier QS is not turned off in time, there is a risk that the primary-side main switch QH and the secondary-side synchronous rectifier QS will be connected simultaneously, causing excessive voltage stress on the power devices, seriously threatening the reliability of the flyback converter, and even damaging the power devices. Here, VGS_QH is the gate-source voltage of the primary-side main switch, VGS_QL is the gate-source voltage of the secondary-side auxiliary switch, VHB is the midpoint voltage of the bridge arm of the asymmetric half-bridge flyback circuit, VDS_QS is the drain-source voltage of the secondary-side synchronous rectifier, and VGS_QS is the gate-source voltage of the secondary-side synchronous rectifier. Therefore, this invention provides a synchronous rectification control method, a flyback converter circuit, and a chip for flyback converters, which precisely controls the conduction or non-conduction of the secondary-side synchronous rectifier QS, effectively avoiding the risk of primary and secondary-side simultaneous conduction caused by the false turn-on of the secondary-side synchronous rectifier due to the ZVS pulse.

[0059] Figure 3 , Figure 4 These are just two specific circuits in a flyback converter circuit provided by the present invention. The present invention actually includes, but is not limited to, these two specific circuits.

[0060] Specifically, this invention provides a flyback converter circuit, such as... Figure 3 As shown, it includes:

[0061] The flyback converter main circuit 100 and control circuit 200;

[0062] The flyback converter main circuit 100 includes a primary-side main switch QH, a primary-side winding Np, a secondary-side winding Ns, and a secondary-side synchronous rectifier QS.

[0063] The control circuit 200 is used to acquire the first drain-source voltage signal and the voltage holding time threshold of the secondary-side synchronous rectifier QS; when the first drain-source voltage signal is high and the holding time is greater than the voltage holding time threshold, the control circuit acquires the rectifier enable signal that allows the rectifier to conduct; and when the control terminal of the secondary-side synchronous rectifier QS acquires the rectifier conduction signal, the secondary-side synchronous rectifier QS conducts; when the holding time of the high level of the first drain-source voltage signal is not greater than the voltage holding time threshold, the secondary-side synchronous rectifier QS does not conduct.

[0064] In this embodiment of the invention, the flyback converter main circuit further includes a primary-side control module 101 and a secondary-side control module 102. Specifically, the flyback converter main circuit comprises: a first series structure consisting of a primary-side main switch QH and a primary-side winding Np, one end of which is a voltage input terminal and the other end of which is grounded; a second series structure consisting of a secondary-side synchronous rectifier QS and a secondary-side winding Ns, one end of which is a voltage output terminal and the other end of which is grounded; a first output terminal of the primary-side control module 101 is connected to the control terminal of the primary-side main switch, and a first output terminal of the secondary-side control module 102 is connected to the control terminal of the secondary-side synchronous rectifier.

[0065] In this embodiment of the invention, including but not limited to connecting the secondary-side synchronous rectifier tube between ground and the secondary-side winding or between the output terminal of the flyback converter and the secondary-side winding, the second output terminal of the secondary-side control module 102 is connected to the input terminal of the control circuit 200, and the input terminal of the secondary-side control module 102 is connected to the output terminal of the control circuit 200.

[0066] In this embodiment of the invention, the primary-side main switch QH is an NMOS field-effect transistor or other suitable power device; the primary-side auxiliary switch QL is an NMOS field-effect transistor or other suitable power device; and the secondary-side synchronous rectifier QS is an NMOS field-effect transistor or other suitable power device.

[0067] This invention provides another flyback converter circuit, namely the asymmetric half-bridge flyback converter AHB, such as... Figure 4 As shown, at this time, the main circuit 100 of the asymmetric half-bridge flyback converter adds an auxiliary switch and a resonant device (resonant capacitor Cr and resonant inductor Lr) to achieve zero-voltage turn-on of the primary-side main switch QH, effectively reducing the switching loss of the system and further improving the conversion efficiency of the converter.

[0068] In embodiments of the present invention, such as Figure 4 As shown, the flyback converter main circuit also includes a primary-side auxiliary switch QL, a resonant capacitor Cr, a resonant inductor Lr, a primary-side winding Np, a secondary-side winding Ns, a primary-side control module 101, and a secondary-side control module 102; the flyback converter main circuit 100 is configured such that: the drain of the primary-side main switch QH is the voltage input terminal; the source of the primary-side main switch QH is connected to one end of the resonant inductor Lr and the drain of the primary-side auxiliary switch QL; the other end of the resonant inductor Lr is connected to one end of the primary-side winding Np; the other end of the primary-side winding Np is connected to one end of the resonant capacitor Cr; and the other end of the resonant capacitor Cr is connected to the source of the primary-side auxiliary switch QL and a reference ground. The first output terminal of the primary-side control module 101 is connected to the gate of the primary-side main switch QH, and the second output terminal of the primary-side control module 101 is connected to the gate of the primary-side auxiliary switch QL. The source of the secondary-side synchronous rectifier QS serves as the output terminal of the flyback converter, the drain of the secondary-side synchronous rectifier QS is connected to one end of the secondary-side winding Ns, and the other end of the secondary-side winding is connected to ground. The first output terminal of the secondary-side control module 102 is connected to the gate of the secondary-side synchronous rectifier QS, the second output terminal of the secondary-side control module 102 is connected to the input terminal of the control circuit 200, and the input terminal of the secondary-side control module 102 is connected to the output terminal of the control circuit 200.

[0069] In other embodiments, the asymmetric half-bridge flyback converter AHB includes, but is not limited to, connecting the resonant device between ground and the primary winding or connecting the resonant device between the source of the primary main switch and the primary winding.

[0070] This includes, but is not limited to, connecting the secondary-side synchronous rectifier tube between ground and the secondary-side winding, or connecting the secondary-side synchronous rectifier tube between the output terminal of the flyback converter and the secondary-side winding.

[0071] In this embodiment of the invention, the flyback converter, through the control circuit 200, determines the actual rectification demand for the secondary-side synchronous rectifier diode and controls the conduction or non-conduction of the secondary-side synchronous rectifier diode, thereby accurately determining the conduction timing of the secondary-side synchronous rectifier diode QS and effectively avoiding the risk of primary and secondary sides being connected due to the secondary-side synchronous rectifier diode QS being mistakenly turned on.

[0072] In this embodiment of the invention, the input terminal of the control circuit 200 is connected to the second output terminal of the secondary control module 102, and is used to acquire the first drain-source voltage signal of the secondary synchronous rectifier QS. The output terminal of the control circuit 200 is connected to the input terminal of the secondary control module 102, and is used to output a rectifier control signal to the secondary synchronous rectifier QS to regulate whether the secondary synchronous rectifier QS is turned on or off.

[0073] In this embodiment of the invention, the primary side control module 101 is an AHB controller, and the secondary side control module 102 is an SR controller.

[0074] by Figure 4 Taking the asymmetric half-bridge flyback converter AHB as an example, in this embodiment of the invention, as shown... Figure 5 As shown, the control circuit 200 specifically includes:

[0075] The circuit includes a sampling circuit 201, a switch threshold detection circuit 202, and a logic control circuit 203; the output terminal of the sampling circuit 201 is connected to the input terminal of the switch threshold detection circuit 202 and the first input terminal of the logic control circuit 203, and the output terminal of the switch threshold detection circuit 202 is connected to the second input terminal of the logic control circuit 203.

[0076] The sampling circuit 201 is used to acquire the first drain-source voltage signal VDS_QS of the secondary-side synchronous rectifier.

[0077] The switching threshold detection circuit 202 is used to acquire the rectifier tube turn-on signal VGS_on and the rectifier tube turn-off signal VGS_off at the control terminal of the secondary side synchronous rectifier tube;

[0078] The logic control circuit 203 is used to obtain the voltage holding time threshold Tset, and based on the first drain-source voltage signal VDS_QS1, the voltage holding time threshold Tset, and the rectifier diode turn-on signal VGS_on, control the secondary-side synchronous rectifier diode QS to be turned on or off.

[0079] In this embodiment of the invention, the sampling circuit 201 is used to acquire the first drain-source voltage signal VDS_QS1 of the secondary-side synchronous rectifier QS.

[0080] In this embodiment of the invention, the sampling circuit processes the voltage across the drain and source terminals of the secondary-side synchronous rectifier QS to obtain a low-voltage signal that can be calculated as the first drain-source voltage signal VDS_QS1.

[0081] In this embodiment of the invention, the switch threshold detection circuit 202 is used to acquire the rectifier turn-on signal VGS_on of the secondary-side synchronous rectifier control terminal and the rectifier turn-off signal VGS_off controlled by the secondary-side synchronous rectifier.

[0082] In this embodiment of the invention, the logic control circuit 203 is used to output a rectifier control signal VGS_en based on the first drain-source voltage signal VDS_QS1, the voltage holding time threshold Tset, and the rectifier turn-on signal VGS_on, to control the secondary-side synchronous rectifier QS to be turned on or off.

[0083] In this embodiment of the invention, when the logic control circuit 203 acquires the rectifier diode turn-on signal VGS_on, and when the logic control circuit 203 acquires the rectifier diode enable signal Tdet_en that allows the rectifier diode to turn on, the logic control circuit 203 outputs the rectifier diode control signal VGS_en to control the secondary side synchronous rectifier diode QS to turn on.

[0084] In embodiments of the present invention, such as Figure 5 As shown, the logic control circuit 203 includes a first unit 2031 and a second unit 2032. The input terminal of the first unit 2031 serves as the first input terminal of the logic control circuit. The input terminal of the first unit 2031 is connected to the output terminal of the sampling circuit 201. The output terminal of the first unit 2031 is connected to the first input terminal of the second unit 2032. The second input terminal of the second unit 2032 serves as the second input terminal of the logic control circuit 203. The second input terminal of the second unit 2032 is connected to the output terminal of the switch threshold detection circuit 202. The output terminal of the second unit 2032 serves as the output terminal of the logic control circuit 203. The output terminal of the second unit 2032 is connected to the input terminal of the secondary control module 102.

[0085] The first unit 2031 acquires a voltage hold-up time threshold Tset. Based on the first drain-source voltage signal VDS_QS1 and the voltage hold-up time threshold Tset, it acquires a rectifier enable signal that allows the rectifier to conduct. Specifically, when the first drain-source voltage signal VDS_QS1 is high and its hold-up time is greater than the voltage hold-up time threshold Tset, the rectifier enable signal is set to high. When the rectifier enable signal is high, the rectifier is allowed to conduct, and the rectifier enable signal Tdet_en that allows the rectifier to conduct is acquired. When the hold-up time Tdet of the first drain-source voltage signal VDS_QS1 is not greater than the voltage hold-up time threshold Tset, the rectifier enable signal is kept low. When the rectifier enable signal is low, the rectifier is not allowed to conduct, and the low-level rectifier enable signal Tdet_en is acquired.

[0086] The second unit 2032 outputs a rectifier control signal VGS_en based on the rectifier turn-on signal VGS_on and the rectifier enable signal Tdet_en output by the first unit, which enables the rectifier to turn on, thereby controlling the secondary-side synchronous rectifier QS to turn on. Specifically, when both the rectifier turn-on signal VGS_on and the rectifier enable signal Tdet_en are present, a high-level rectifier control signal is output to control the secondary-side synchronous rectifier to turn on; when the rectifier enable signal Tdet_en is low, a low-level rectifier control signal is output, and the secondary-side synchronous rectifier is not turned on.

[0087] In this embodiment of the invention, the first unit 2031 further includes acquiring a reference voltage threshold Vset. When the first drain-source voltage signal VDS_QS1 rises to the reference voltage threshold Vset, the rectifier enable signal Tdet_en is reset to zero, that is, the rectifier enable signal Tdet_en is set to a low level.

[0088] In embodiments of the present invention, such as Figure 6 As shown, the control circuit further includes:

[0089] Second drain-source voltage signal acquisition circuit 204, signal processing circuit 205;

[0090] The input terminal of the second drain-source voltage signal acquisition circuit 204, the first input terminal of the signal processing circuit 205, and the output terminal of the sampling circuit 201 are connected. The output terminal of the second drain-source voltage signal acquisition circuit 204 is connected to the second input terminal of the signal processing circuit 205, and the output terminal of the signal processing circuit 205 is connected to the first input terminal of the logic control circuit 203.

[0091] The second drain-source voltage signal acquisition circuit 204 is used to process the first drain-source voltage signal VDS_QS1 to obtain a second drain-source voltage signal VDS_QS2 with the same waveform but a time lag behind the first drain-source voltage signal VDS_QS1.

[0092] The signal processing circuit 205 is used to output a coincidence signal Tdet to the logic control circuit when the first drain-source voltage signal VDS_QS1 coincides with the second drain-source voltage signal VDS_QS2.

[0093] The logic control circuit 203 obtains the overlap time of the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 based on the overlap signal Tdet, and the overlap time is used as the holding time of the high level of the drain-source voltage.

[0094] In this embodiment of the invention, when the control circuit 200 includes the second drain-source voltage signal acquisition circuit 204 and the signal processing circuit 205, the first unit 2031 in the logic control circuit 203 times the overlap time of the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 based on the overlap signal Tdet, and obtains the overlap time. The overlap time is used as the holding time of the high level of the drain-source voltage. When the holding time is greater than the voltage holding time threshold Tset, the rectifier enable signal of the secondary side synchronous rectifier is set to a high level, and the rectifier enable signal Tdet_en that allows the rectifier to conduct is obtained and output to the second unit 2032. When the holding time is not greater than the voltage holding time threshold Tset, the rectifier enable signal is kept at a low level and output to the second unit 2032.

[0095] The second unit 2032, based on the rectifier diode on signal VGS_on and the rectifier diode enable signal Tdet_en output by the first unit 2031, outputs a rectifier diode control signal VGS_en to control whether the secondary-side synchronous rectifier diode QS is turned on or off. Specifically, when the rectifier diode on signal VGS_on and the rectifier diode enable signal Tdet_en, which allows the rectifier diode to turn on, are both present, a high-level rectifier diode control signal is output to control the secondary-side synchronous rectifier diode to turn on; when the rectifier diode enable signal Tdet_en is low, a low-level rectifier diode control signal VGS_en is output to control the secondary-side synchronous rectifier diode to turn off.

[0096] Specifically, in the embodiments of the present invention, such as Figure 7As shown, the sampling circuit 201 specifically includes: a first resistor R1 and a second resistor R2. One end of the first resistor R1 serves as the input terminal of the sampling circuit, and the input terminal of the sampling circuit acquires the voltage across the drain and source terminals of the secondary-side synchronous rectifier. The other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded. The other end of the first resistor R1 serves as the output terminal of the sampling circuit, and the other end of the first resistor R1 is connected to the input terminal of the second drain-source voltage signal acquisition circuit 204 and the first input terminal of the signal processing circuit 205.

[0097] In embodiments of the present invention, such as Figure 7 As shown, the second drain-source voltage signal acquisition circuit 204 specifically includes: a third resistor R3 and a first capacitor C1;

[0098] One end of the third resistor R3 serves as the input terminal of the second drain-source voltage signal acquisition circuit 204. One end of the third resistor R3 is connected to the output terminal of the sampling circuit 201. The other end of the third resistor R3 is connected to one end of the first capacitor C1. The other end of the third resistor R3 serves as the output terminal of the second drain-source voltage signal acquisition circuit 204. The other end of the first capacitor C1 is grounded.

[0099] In embodiments of the present invention, such as Figure 7 As shown, the switch threshold detection circuit specifically includes: a first comparator U2021 and a second comparator U2022.

[0100] The negative input terminal of the first comparator U2021 in the detection circuit serves as the input terminal of the switch threshold detection circuit. The negative input terminal of the first comparator U2021 in the detection circuit is connected to the output terminal of the sampling circuit. The positive input terminal of the first comparator U2021 in the detection circuit is used to obtain the turn-on threshold VON_TH of the secondary synchronous rectifier. The output terminal of the first comparator U2021 in the detection circuit serves as the first output terminal of the switch threshold detection circuit 202. The output terminal of the first comparator U2021 in the detection circuit is connected to the second input terminal of the logic control circuit 203.

[0101] The negative input terminal of the second comparator U2022 in the detection circuit is used to obtain the turn-off threshold VOFF_TH of the secondary synchronous rectifier. The positive input terminal of the second comparator U2022 in the detection circuit is connected to the negative input terminal of the first comparator U2021 in the detection circuit. The output terminal of the second comparator U2022 in the detection circuit serves as the second output terminal of the switch threshold detection circuit 202. The output terminal of the second comparator U2022 in the detection circuit is connected to the third input terminal of the logic control circuit 203.

[0102] In embodiments of the present invention, such as Figure 7 As shown, the signal processing circuit 205 specifically includes: a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first operational amplifier U1, a first comparator U2 of the signal processing circuit, a second comparator U3 of the signal processing circuit, and a first AND gate U4.

[0103] One end of the fourth resistor R4 serves as the first input terminal of the signal processing circuit 205, and one end of the fourth resistor R4 is connected to the output terminal of the sampling circuit 201. The other end of the fourth resistor R4 is connected to the positive input terminal of the first operational amplifier U1 and one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the output terminal of the first operational amplifier U1. One end of the fifth resistor R5 serves as the second input terminal of the signal processing circuit 205, and one end of the fifth resistor R5 is connected to the output terminal of the second drain-source voltage signal acquisition circuit 204. The other end of the fifth resistor R5 is connected to the negative input terminal of the first operational amplifier U1 and one end of the seventh resistor R7. The other end of the seventh resistor R7 is grounded. The output terminal of the first operational amplifier U1 is connected to the negative input terminal of the first comparator U2 of the signal processing circuit and the second comparator U2... The positive input terminal of the first comparator U2 in the signal processing circuit is connected to the first input terminal of the first AND gate U4, and the output terminal of the second comparator U3 in the signal processing circuit is connected to the second input terminal of the first AND gate U4. The output terminal of the first AND gate U4 serves as the output terminal of the signal processing circuit 205. The resistance values ​​of the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, and the seventh resistor R7 are equal. VDS_err is the drain-source voltage difference, which is the difference between the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2.

[0104] In this embodiment of the invention, the determination thresholds include a first threshold Vref_err1 for difference determination and a second threshold Vref_err2 for difference determination, wherein the first threshold Vref_err1 for difference determination and the second threshold Vref_err2 for difference determination are opposites of each other.

[0105] In this embodiment of the invention, the first operational amplifier U1 further includes a first power supply terminal VCC and a second power supply terminal -VCC, through which the first operational amplifier U1 is powered.

[0106] In embodiments of the present invention, such as Figure 7When the signal processing circuit 205 shown is working:

[0107] Obtain the drain-source voltage difference VDS_err: The first operational amplifier U1 calculates the difference between the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 to obtain the drain-source voltage difference VDS_err;

[0108] The drain-source voltage difference VDS_err is used to determine the difference: the drain-source voltage difference VDS_err is compared with the first threshold Vref_err1 and the second threshold Vref_err2 of the difference determination by the first comparator U2 and the second comparator U3 of the signal processing circuit, respectively.

[0109] When the drain-source voltage difference VDS_err is less than the first threshold Vref_err1 for difference determination, the first comparator U2 of the signal processing circuit outputs a high level; when the drain-source voltage difference VDS_err is greater than the second threshold Vref_err2 for difference determination, the second comparator U3 of the signal processing circuit outputs a high level.

[0110] When the first comparator U2 and the second comparator U3 of the signal processing circuit simultaneously output high levels, it is determined that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide. The AND gate U4 outputs a high-level coincidence signal Tdet. At this time, it is determined that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide.

[0111] In another embodiment of the invention, such as Figure 8 As shown, the signal processing circuit 205 specifically includes: an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15, a third comparator U5, a fourth comparator U6, and a second AND gate U7.

[0112] One end of the twelfth resistor R12 serves as the first input terminal of the signal processing circuit 205. One end of the twelfth resistor R12 is connected to the output terminal of the sampling circuit 201 and one end of the eighth resistor R8. The other end of the twelfth resistor R12 is connected to the positive input terminal of the third comparator U5 of the signal processing circuit and one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is used to obtain the third threshold value Vref_err3 for difference determination. One end of the fourteenth resistor R14 serves as the second input terminal of the signal processing circuit 205. One end of the fourteenth resistor R14 is connected to the output terminal of the second drain-source voltage signal acquisition circuit 204 and one end of the tenth resistor R10. The other end of the fourteenth resistor R14 is connected to the negative input terminal of the third comparator U5 of the signal processing circuit and one end of the fifteenth resistor R15. The other end of the fifteenth resistor R15 is grounded. The other end of the eighth resistor R8 is connected to the signal processing circuit 205. The negative input terminal of the fourth comparator U6 of the signal processing circuit is connected to one end of the ninth resistor, the other end of the ninth resistor R9 is grounded, the other end of the tenth resistor R10 is connected to the positive input terminal of the fourth comparator U6 of the signal processing circuit and the other end of the eleventh resistor R11, the other end of the eleventh resistor R11 is used to obtain the third threshold Vref_err3 for difference determination, the output terminal of the third comparator U5 of the signal processing circuit is connected to the first input terminal of the second AND gate U7, the output terminal of the fourth comparator U6 of the signal processing circuit is connected to the second input terminal of the second AND gate U7, the output terminal of the second AND gate U7 is used as the output terminal of the signal processing circuit 205, wherein the resistance values ​​of the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14 and the fifteenth resistor R15 are equal, and the resistance values ​​of the eighth resistor R8, the ninth resistor R9, the tenth resistor R10 and the eleventh resistor R11 are equal.

[0113] In some other embodiments of the present invention, the third threshold for difference determination, Vref_err3, is used as the determination threshold.

[0114] In other embodiments of the present invention, such as Figure 8 When the signal processing circuit 205 shown is in operation:

[0115] According to the superposition law and the voltage division relationship of resistors, we can obtain:

[0116] The in-phase input signal VT1 of the third comparator U5 in the signal processing circuit is:

[0117] VT1=0.5 (VDS_QS1+Vref_err3);

[0118] The inverted input signal VT2 of the third comparator U5 in the signal processing circuit is:

[0119] VT2=0.5 VDS_QS2;

[0120] When the non-inverting input signal VT1 of the third comparator U5 of the signal processing circuit is higher than the inverting input signal VT2 of the third comparator U5 of the signal processing circuit, the third comparator U5 of the signal processing circuit outputs a high-level signal.

[0121] The inverted input signal VT3 of the fourth comparator U6 in the signal processing circuit is:

[0122] VT3=0.5 VDS_QS1;

[0123] The in-phase input signal VT4 of the fourth comparator U6 in the signal processing circuit is:

[0124] VT4=0.5 (VDS_QS2+Vref_err3);

[0125] When the inverted input signal VT4 of the fourth comparator U6 of the signal processing circuit is higher than the non-inverted input signal VT3 of the fourth comparator U6, the comparator U6 of the signal processing circuit outputs a high-level signal.

[0126] The output terminals of the third comparator U5 and the fourth comparator U6 of the signal processing circuit are connected to the input terminal of the second AND gate U7. When the outputs of the third comparator U5 and the fourth comparator U6 of the signal processing circuit are both high, the second AND gate U7 outputs the high-level coincident signal Tdet. At this time, the first drain-source voltage signal VDS_QS1 coincides with the second drain-source voltage signal VDS_QS2.

[0127] In some other embodiments of the present invention, the third threshold Vref_err3 for difference determination is a set voltage slightly greater than 0V, for example, 0.1V.

[0128] This invention provides a synchronous rectification control method for a flyback converter, such as... Figure 9 As shown, it includes:

[0129] Step S10: Obtain the first drain-source voltage signal and voltage hold time threshold of the secondary-side synchronous rectifier.

[0130] Step S20: When the first drain-source voltage signal is high and the holding time is greater than the voltage holding time threshold, a rectifier enable signal that allows the rectifier to conduct is obtained, and when the control terminal of the secondary synchronous rectifier obtains the rectifier conduction signal, the secondary synchronous rectifier is turned on.

[0131] Step S30: When the holding time of the high level of the first drain-source voltage signal is not greater than the voltage holding time threshold, the secondary-side synchronous rectifier is not turned on.

[0132] Based on the first drain-source voltage signal of the secondary-side synchronous rectifier and the voltage holding time threshold, the actual rectification demand of the secondary-side synchronous rectifier is determined, and the conduction or non-conduction of the secondary-side synchronous rectifier is controlled, thereby accurately controlling the turn-on timing of the secondary-side synchronous rectifier and effectively avoiding the risk of primary and secondary sides being connected due to accidental turn-on of the secondary-side synchronous rectifier.

[0133] by Figure 4 Taking the asymmetric half-bridge flyback converter AHB as an example, specifically,

[0134] Execute step S10 to obtain the first drain-source voltage signal VDS_QS1 of the secondary side synchronous rectifier and the voltage holding time threshold Tset.

[0135] In this embodiment of the invention, the voltages across the drain and source terminals of the secondary-side synchronous rectifier are processed to obtain a low-voltage signal that can be calculated, which is then used as the first drain-source voltage signal VDS_QS1.

[0136] In this embodiment of the invention, the voltage holding time threshold Tset is a set value.

[0137] In this embodiment of the invention, the voltage holding time threshold Tset is in the range of 100ns to 1us, and the voltage holding time threshold can be adjusted according to the actual system application.

[0138] Execute step S20: when the first drain-source voltage signal VDS_QS1 is high and the holding time is greater than the voltage holding time threshold Tset, obtain the rectifier enable signal Tdet_en that allows the rectifier to conduct; and when the control terminal of the secondary-side synchronous rectifier QS obtains the rectifier conduction signal VGS_on, the secondary-side synchronous rectifier QS conducts.

[0139] In step S30, when the holding time of the high level of the first drain-source voltage signal is not greater than the voltage holding time threshold Tset, the secondary-side synchronous rectifier is not turned on.

[0140] The execution order of steps S20 and S30 is not important.

[0141] In this embodiment of the invention, during the operating cycle of the flyback converter, when the first drain-source voltage signal of the secondary-side synchronous rectifier is high and remains high for a certain period of time, the corresponding primary-side main switch is turned on. The secondary-side synchronous rectifier corresponds to the actual rectification demand, and obtains the rectifier enable signal and the rectifier turn-on signal to jointly regulate the turn-on rectification of the secondary-side synchronous rectifier. When the first drain-source voltage signal of the secondary-side synchronous rectifier is high, but the high-level holding time of the first drain-source voltage signal is less than a certain period of time, the secondary-side synchronous rectifier does not correspond to the actual rectification demand. Instead, the primary-side auxiliary switch QL is used to realize the resonant pulse of the main switch ZVS, which causes the first drain-source voltage signal of the secondary-side synchronous rectifier to rise. At this time, the rectifier enable signal is kept low, and the secondary-side synchronous rectifier is controlled not to conduct, thereby accurately regulating the turn-on timing of the secondary-side synchronous rectifier and effectively avoiding the risk of primary and secondary sides being connected due to accidental turn-on of the secondary-side synchronous rectifier.

[0142] In this embodiment of the invention, the step of obtaining the high-level holding time of the first drain-source voltage signal VDS_QS1 includes:

[0143] Please refer to step S201. Figure 10 The solid line in the diagram represents the first drain-source voltage signal VDS_QS1, and the dashed line represents the second drain-source voltage signal VDS_QS2. The first drain-source voltage signal VDS_QS1 is processed to obtain the second drain-source voltage signal VDS_QS2, which has the same waveform but lags behind the first drain-source voltage signal VDS_QS1 in time.

[0144] In this embodiment of the invention, the first drain-source voltage signal VDS_QS1 is filtered to obtain the second drain-source voltage signal VDS_QS2. The waveform of the second drain-source voltage signal VDS_QS2 is the same as that of the first drain-source voltage signal VDS_QS1, but the time lags slightly behind the first drain-source voltage signal VDS_QS1, so that the second drain-source voltage signal VDS_QS2 follows the first drain-source voltage signal VDS_QS1.

[0145] In this embodiment of the invention, the second drain-source voltage signal VDS_QS2 lags behind the first drain-source voltage signal VDS_QS1 by a time range of 100ns to 300ns, in order to distinguish the first drain-source voltage signal VDS_QS1 from the second drain-source voltage signal VDS_QS2.

[0146] For step S202, please refer to... Figure 10During the time periods t1~t3 and t6~t8, when the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide, the coincidence time is obtained, and the coincidence time is used as the holding time of the high level of the drain-source voltage.

[0147] In this embodiment of the invention, when the first drain-source voltage signal VDS_QS1 is high and maintained for a certain period of time, the second drain-source voltage signal VDS_QS2 follows the high level of the first drain-source voltage signal VDS_QS1, causing the second drain-source voltage signal VDS_QS2 and the first drain-source voltage signal VDS_QS1 to overlap for a period of time. The overlap time between the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 is obtained as the holding time of the high level of the drain-source voltage.

[0148] In this embodiment of the invention, an overlap signal Tdet is obtained based on the first drain-source voltage signal and the second drain-source voltage signal. When the first drain-source voltage signal and the second drain-source voltage signal overlap, the overlap signal Tdet is at a high level, and the high level holding time of the overlap signal Tdet is taken as the holding time of the high level of the drain-source voltage.

[0149] In this embodiment of the invention, when the holding time of the high level of the drain-source voltage is greater than the voltage holding time threshold Tset, the rectifier enable signal of the secondary-side synchronous rectifier is set to a high level. The high-level rectifier enable signal allows the rectifier to conduct, and the rectifier enable signal Tdet_en that allows the rectifier to conduct is obtained.

[0150] In this embodiment of the invention, when the holding time of the high level of the drain-source voltage is not greater than the voltage holding time threshold Tset, the rectifier enable signal of the secondary-side synchronous rectifier is kept at a low level, and the low-level rectifier enable signal does not allow the rectifier to conduct.

[0151] In this embodiment of the invention, the step of determining that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide includes:

[0152] Step S2021: Obtain the judgment threshold;

[0153] In this embodiment of the invention, the determination threshold is slightly greater than 0V, for example, 0.1V.

[0154] Step S2022: When the absolute value of the difference between the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 is not greater than the determination threshold, it is determined that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide, and the coincident signal is obtained.

[0155] In this embodiment of the invention, if the absolute value of the difference between the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 is not greater than the determination threshold, then it is determined that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 are within the allowable fluctuation range, and it is considered that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide.

[0156] Furthermore, in embodiments of the present invention, the following are employed: Figure 7 The circuit shown includes the following steps for determining whether the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide:

[0157] Obtain the first threshold Vref_err1 and the second threshold Vref_err2 for difference determination, wherein the first threshold Vref_err1 is slightly greater than 0V and the second threshold Vref_err2 is slightly less than 0V;

[0158] The difference VDS_err between the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 is obtained. The difference VDS_err is compared with the first threshold Vref_err1 and the second threshold Vref_err2 for difference determination. When the difference VDS_err is between the first threshold Vref_err1 and the second threshold Vref_err2 for difference determination, it is determined that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide.

[0159] In this embodiment of the invention, the first threshold Vref_err1 for difference determination and the second threshold Vref_err2 for difference determination are opposites of each other.

[0160] In other embodiments, the first threshold for difference determination is slightly less than 0V, for example, 0.1V, and the second threshold for difference determination is slightly greater than 0V, for example, 0.1V.

[0161] In other embodiments, the first threshold for difference determination and the second threshold for difference determination may not be equal.

[0162] In this embodiment of the invention, the difference VDS_err between the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 may be positive or negative.

[0163] Furthermore, in some other embodiments of the present invention, the following are employed: Figure 8 The circuit shown includes the following steps for determining whether the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide:

[0164] Obtain the third threshold value Vref_err3 for difference determination, which is slightly greater than 0V;

[0165] When the first drain-source voltage signal VDS_QS1, after being superimposed with the third threshold Vref_err3 for difference determination, is greater than the second drain-source voltage signal VDS_QS2, and the second drain-source voltage signal VDS_QS2, after being superimposed with the third threshold Vref_err3 for difference determination, is greater than the first drain-source voltage signal VDS_QS1, it is determined that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide.

[0166] In other embodiments, the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 are digitally sampled and processed by software to determine that the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 coincide.

[0167] In this embodiment of the invention, when the first drain-source voltage signal VDS_QS1 coincides with the second drain-source voltage signal VDS_QS2, the coincidence time is timed to obtain the coincidence time, and the coincidence time is used as the holding time of the high level of the drain-source voltage.

[0168] In the embodiments of the present invention, please refer to Figure 10 During the time period t4~t6, the steps for the control terminal of the secondary-side synchronous rectifier to obtain the rectifier conduction signal include:

[0169] Obtain the turn-on threshold VON_TH of the secondary-side synchronous rectifier diode;

[0170] When the first drain-source voltage signal VDS_QS1 drops below the turn-on threshold VON_TH, the control terminal of the secondary-side synchronous rectifier obtains the rectifier turn-on signal VGS_on.

[0171] When the rectifier diode conduction signal VGS_on and the rectifier diode enable signal Tdet_en are obtained, the secondary-side synchronous rectifier diode is turned on.

[0172] In this embodiment of the invention, when both the rectifier turn-on signal VGS_on and the rectifier enable signal Tdet_en are present, the secondary-side synchronous rectifier QS is turned on; when only the rectifier turn-on signal VGS_on or the rectifier enable signal is present, the secondary-side synchronous rectifier QS is not turned on.

[0173] In this embodiment of the invention, the control terminal of the secondary-side synchronous rectifier QS also acquires the rectifier turn-off signal VGS_off. Please refer to [link / reference needed]. Figure 10 During the time period t5~t6, the specific steps for obtaining the rectifier diode turn-off signal VGS_off include:

[0174] Get the turn-off threshold VOFF_TH of the secondary-side synchronous rectifier;

[0175] When the first drain-source voltage signal VDS_QS1 rises to the turn-off threshold VOFF_TH, the control terminal of the secondary synchronous rectifier QS acquires the rectifier turn-off signal VGS_off.

[0176] When the rectifier tube turn-off signal VGS_off is received, the secondary-side synchronous rectifier tube QS is turned off.

[0177] In this embodiment of the invention, when the rectifier enable signal that allows the rectifier to conduct does not exist, the secondary-side synchronous rectifier QS will not conduct regardless of whether the rectifier conduction signal VGS_on exists.

[0178] In this embodiment of the invention, the method further includes obtaining a reference voltage threshold Vset. When the first drain-source voltage signal VDS_QS1 rises to the reference voltage threshold Vset, the rectifier enable signal Tdet_en is reset to zero, that is, the rectifier enable signal Tdet_en is set low.

[0179] In embodiments of the present invention, as follows Figure 10 The following is a timing diagram of the synchronous rectification control method for a flyback converter:

[0180] The first drain-source voltage signal VDS_QS1 is acquired, and the first drain-source voltage signal VDS_QS1 is processed to obtain a second drain-source voltage signal VDS_QS2 with the same waveform but a time lag compared to the first drain-source voltage signal VDS_QS1.

[0181] At time t0, the secondary-side synchronous rectifier diode QS is in the off state;

[0182] At time t0~t1, the first drain-source voltage signal VDS_QS1 rapidly rises to a high level, and then the second drain-source voltage signal VDS_QS2 also begins to rise to a high level.

[0183] When the first drain-source voltage signal VDS_QS1 coincides with the second drain-source voltage signal VDS_QS2, the coincidence time is obtained. This coincidence time is used as the holding time of the high level of the drain-source voltage, i.e., from time t1 to t2.

[0184] At time t1, the second drain-source voltage signal VDS_QS2 follows the first drain-source voltage signal VDS_QS1 and tends to stabilize. The two voltage signals begin to enter the overlap phase. The overlap phase is timed to obtain the overlap time. The overlap time is used as the time during which the first drain-source voltage signal is high and held.

[0185] Specifically, obtaining the overlap time involves: obtaining an overlap signal Tdet between the first drain-source voltage signal and the second drain-source voltage signal based on the first drain-source voltage signal and the second drain-source voltage signal; when the first drain-source voltage signal and the second drain-source voltage signal overlap, the overlap signal Tdet is set to a high level, and the high level of the overlap signal Tdet is maintained for the overlap time.

[0186] The overlap signal Tdet is compared with the voltage hold time threshold Tset in real time. When the overlap signal Tdet is greater than the voltage hold time threshold Tset, the rectifier enable signal of the secondary synchronous rectifier is set to high level.

[0187] At time t2, when the overlap time of the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 (the high-level holding time of the overlap signal Tdet), that is, when the high-level holding time of the first drain-source voltage signal reaches the voltage holding time threshold Tset, the rectifier enable signal of the secondary side synchronous rectifier is set to high level, and the rectifier enable signal Tdet_en that allows the rectifier to conduct is obtained;

[0188] At time t3, the first drain-source voltage signal VDS_QS1 drops rapidly and no longer remains at a high level. The second drain-source voltage signal VDS_QS2 lags behind the first drain-source voltage signal VDS_QS1 and does not drop immediately. The deviation between the two increases, and the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 no longer coincide. At this time, the coincidence signal Tdet of the first drain-source voltage signal and the second drain-source voltage signal is set to a low level.

[0189] During times t3 to t4, the first drain-source voltage signal VDS_QS1 continuously drops below zero;

[0190] At time t4, when the first drain-source voltage signal VDS_QS1 drops below the turn-on threshold VON_TH, the control terminal of the secondary synchronous rectifier acquires the rectifier turn-on signal VGS_on. At this time, the rectifier enable signal Tdet_en and the rectifier turn-on signal VGS_on exist simultaneously, and the output rectifier control signal VGS_en of the secondary synchronous rectifier QS controls the secondary synchronous rectifier to turn on.

[0191] At times t4~t5, the secondary-side synchronous rectifier QS is continuously turned on. At this time, the secondary-side excitation current gradually decreases, and the first drain-source voltage signal VDS_QS1 gradually increases.

[0192] At time t5, the first drain-source voltage signal VDS_QS1 rises to the turn-off threshold VOFF_TH, the control terminal of the secondary synchronous rectifier QS obtains the rectifier turn-off signal VGS_off, and the secondary synchronous rectifier QS is turned off.

[0193] At time t6, the first drain-source voltage signal VDS_QS1 rises to the reference voltage threshold Vset, and the rectifier enable signal Tdet_en is reset to zero, that is, the rectifier enable signal Tdet_en is set low;

[0194] At times t6~t7, after the secondary-side synchronous rectifier QS is turned off, the voltage across the drain and source terminals of the secondary-side synchronous rectifier QS begins to oscillate under the influence of parasitic parameters.

[0195] At time t7, the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 overlap again. Timing begins for the overlap phase, and the obtained overlap time is taken as the holding time Tdet of the high level of the first drain-source voltage signal. However, due to oscillation, the first drain-source voltage signal VDS_QS1 does not have a stable holding phase, so the overlap time of the first drain-source voltage signal VDS_QS1 and the second drain-source voltage signal VDS_QS2 is only a brief intersection point. That is, the holding time Tdet of the high level does not reach (is not greater than) the voltage holding time threshold Tset, and the rectifier enable signal Tdet_en is still low.

[0196] At time t8, the ZVS Pulse drive output of the primary-side auxiliary switch QL is activated, and the first drain-source voltage signal VDS_QS1 decreases rapidly.

[0197] At time t9, when the first drain-source voltage signal VDS_QS1 drops below the turn-on threshold VON_TH again, the control terminal of the secondary synchronous rectifier obtains the rectifier turn-on signal VGS_on again. At this time, only the rectifier turn-on signal VGS_on exists, which does not meet the turn-on condition of the secondary synchronous rectifier QS, so the secondary synchronous rectifier QS is not turned on.

[0198] In this embodiment of the invention, during the time period t6~t9, although the first drain-source voltage signal of the secondary-side synchronous rectifier is at a high level, the high level is short-lived. The secondary-side synchronous rectifier does not correspond to the actual rectification requirement, but rather the increase in the first drain-source voltage signal of the secondary-side synchronous rectifier is caused by the resonance pulse of the primary-side auxiliary switch QL to realize the main switch ZVS. Therefore, based on the high level and high level duration of the first drain-source voltage signal VDS_QS1, it is determined whether the secondary-side synchronous rectifier needs to be turned on. Furthermore, under the combined action of the rectifier turn-on signal at the control terminal of the secondary-side synchronous rectifier, a precise turn-on timing is determined for the secondary-side synchronous rectifier, effectively avoiding the risk of primary and secondary sides being connected due to accidental turn-on of the secondary-side synchronous rectifier.

[0199] The present invention also provides a chip for implementing the above-described synchronous rectification control method for a flyback converter.

[0200] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0201] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A synchronous rectification control method for a flyback converter, the flyback converter comprising a primary-side main switch, a primary-side winding, a secondary-side winding, and a secondary-side synchronous rectifier, characterized in that, include: Obtain the first drain-source voltage signal and voltage hold time threshold of the secondary-side synchronous rectifier; When the first drain-source voltage signal is high and its holding time is greater than the voltage holding time threshold, a rectifier enable signal that allows the rectifier to conduct is obtained, and when the control terminal of the secondary synchronous rectifier obtains a rectifier conduction signal, the secondary synchronous rectifier is turned on. The step of obtaining the holding time of the high level of the first drain-source voltage signal includes: processing the first drain-source voltage signal to obtain a second drain-source voltage signal with the same waveform but a time lag behind the first drain-source voltage signal; when the first drain-source voltage signal and the second drain-source voltage signal coincide, the coincidence time is obtained, and the coincidence time is used as the holding time of the high level of the drain-source voltage. When the high-level holding time of the first drain-source voltage signal is not greater than the voltage holding time threshold, the secondary-side synchronous rectifier is not turned on.

2. The synchronous rectification control method for a flyback converter as described in claim 1, characterized in that, The steps for determining whether the first drain-source voltage signal and the second drain-source voltage signal coincide include: Obtain the judgment threshold; When the absolute value of the difference between the first drain-source voltage signal and the second drain-source voltage signal is not greater than the determination threshold, it is determined that the first drain-source voltage signal and the second drain-source voltage signal coincide.

3. The synchronous rectification control method for a flyback converter as described in claim 1, characterized in that, The steps for the control terminal of the secondary-side synchronous rectifier to obtain the rectifier conduction signal include: Obtain the turn-on threshold of the secondary-side synchronous rectifier diode; When the first drain-source voltage signal drops below the turn-on threshold, the control terminal of the secondary-side synchronous rectifier obtains the rectifier turn-on signal. When the rectifier tube conduction signal and the rectifier tube enable signal that allow the rectifier tube to conduct are obtained, the secondary side synchronous rectifier tube is turned on.

4. The synchronous rectification control method for a flyback converter as described in claim 1, characterized in that, The flyback converter circuit further includes a primary-side control module, a secondary-side control module, and a control circuit. Specifically, the flyback converter circuit comprises: a primary-side main switch and a primary-side winding forming a first series structure, one end of which is a voltage input terminal, and the other end of which is grounded; a secondary-side synchronous rectifier and a secondary-side winding forming a second series structure, one end of which is a voltage output terminal, and the other end of which is grounded; a first output terminal of the primary-side control module is connected to the control terminal of the primary-side main switch, a first output terminal of the secondary-side control module is connected to the control terminal of the secondary-side synchronous rectifier, a second output terminal of the secondary-side control module is connected to the input terminal of the control circuit, and an output terminal of the control circuit is connected to the input terminal of the secondary-side control module.

5. A flyback converter circuit, characterized in that, include: The flyback converter main circuit and control circuit; The flyback converter main circuit includes a primary-side main switch, a primary-side winding, a secondary-side winding, and a secondary-side synchronous rectifier. The control circuit is used to acquire the first drain-source voltage signal and the voltage holding time threshold of the secondary-side synchronous rectifier. When the first drain-source voltage signal is high and the holding time is greater than the voltage holding time threshold, a rectifier enable signal that allows the rectifier to conduct is acquired. When the control terminal of the secondary-side synchronous rectifier acquires a rectifier conduction signal, the secondary-side synchronous rectifier is turned on. The step of acquiring the holding time of the high level of the first drain-source voltage signal includes: processing the first drain-source voltage signal to obtain a second drain-source voltage signal with the same waveform but a time lag behind the first drain-source voltage signal; when the first drain-source voltage signal and the second drain-source voltage signal coincide, the coincidence time is acquired, and the coincidence time is used as the holding time of the high level of the drain-source voltage; when the holding time of the high level of the first drain-source voltage signal is not greater than the voltage holding time threshold, the secondary-side synchronous rectifier is not turned on.

6. A flyback converter circuit as described in claim 5, characterized in that, The control circuit includes: The circuit includes a sampling circuit, a switch threshold detection circuit, and a logic control circuit; the output terminal of the sampling circuit is connected to the input terminal of the switch threshold detection circuit and the first input terminal of the logic control circuit, and the output terminal of the switch threshold detection circuit is connected to the second input terminal of the logic control circuit. The sampling circuit is used to acquire the first drain-source voltage signal of the secondary-side synchronous rectifier diode; The switching threshold detection circuit is used to obtain the rectifier tube turn-on signal and rectifier tube turn-off signal at the control terminal of the secondary side synchronous rectifier tube; The logic control circuit is used to obtain the voltage holding time threshold, and based on the first drain-source voltage signal, the voltage holding time threshold and the rectifier diode conduction signal, control the secondary-side synchronous rectifier diode to conduct or not conduct.

7. A flyback converter circuit as described in claim 6, characterized in that, The control circuit also includes: A second drain-source voltage signal acquisition circuit and a signal processing circuit; the output terminal of the sampling circuit is connected to the input terminal of the second drain-source voltage signal acquisition circuit and the first input terminal of the signal processing circuit, the output terminal of the second drain-source voltage signal acquisition circuit is connected to the second input terminal of the signal processing circuit, and the output terminal of the signal processing circuit is connected to the first input terminal of the logic control circuit; The second drain-source voltage signal acquisition circuit is used to process the first drain-source voltage signal to obtain a second drain-source voltage signal with the same waveform but a time lag compared to the first drain-source voltage signal. The signal processing circuit is used to output a coincidence signal to the logic control circuit when the first drain-source voltage signal coincides with the second drain-source voltage signal. The logic control circuit obtains the overlap time of the first drain-source voltage signal and the second drain-source voltage signal based on the overlap signal, and the overlap time is used as the holding time of the high level of the drain-source voltage.

8. A flyback converter circuit as described in claim 7, characterized in that, The flyback converter main circuit also includes a primary-side control module and a secondary-side control module. Specifically, the primary-side main switch and the primary-side winding form a first series structure, one end of which is the voltage input terminal, and the other end of which is grounded. The secondary-side synchronous rectifier and the secondary-side winding form a second series structure, one end of which is the voltage output terminal, and the other end of which is grounded. The first output terminal of the primary-side control module is connected to the control terminal of the primary-side main switch, the first output terminal of the secondary-side control module is connected to the control terminal of the secondary-side synchronous rectifier, the second output terminal of the secondary-side control module is connected to the input terminal of the control circuit, and the input terminal of the secondary-side control module is connected to the output terminal of the control circuit.

9. A chip for implementing a synchronous rectification control method for a flyback converter as described in claim 1.

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