F-type high-power rectifying circuit based on admittance matching

Abstract

The invention discloses an F-type high-power rectifying circuit based on admittance matching, and belongs to the field of microwave wireless energy transmission. The circuit comprises a dielectric substrate, an upper surface circuit structure and a grounding metal floor, wherein the upper surface circuit structure comprises a three-stage F-class harmonic network, an admittance matching structure, a direct current filtering structure, a 50-ohm bonding pad, a metal floor, a Schottky diode, a blocking capacitor, a load resistor and a grounding via hole. A novel three-level F-type harmonic network is adopted, the network can not only perform impedance control on second and third harmonics, but also perform impedance control on fourth harmonics, and the more multi-level harmonic control network can reduce the diode loss and further improve the rectification efficiency; in addition, a new technology based on admittance matching is adopted, impedance is converted into admittance, so that admittance of the parallel circuit can be directly added, the matching complexity of the parallel circuit can be reduced by matching the admittance, and the matching intuition is improved.

Description

Technical Field

[0001] This invention belongs to the field of microwave wireless power transmission technology, specifically relating to a Class F high-power rectifier circuit based on admittance matching. Background Technology

[0002] In recent years, with the continuous development of new energy technologies, people's demand for wireless charging and high-power charging has been increasing. Microwave Power Transfer (MPT) systems can meet these demands. As one of the key circuits in a microwave power transfer system, the rectifier circuit's input power and rectification efficiency determine the amount of energy transmitted by the entire system. Therefore, research on the high power and high efficiency of microwave rectifier circuits is crucial. A microwave rectifier circuit converts the radio frequency (RF) signal received by the MPT system into a DC signal, which then powers the battery to complete the wireless power transfer. In the process of converting RF energy into DC energy, the most important technical indicators are the input power and rectification efficiency. The input power that the rectifier circuit can withstand determines the maximum RF energy threshold that the MPT system can receive; the higher this threshold, the greater the energy the MPT system can transmit. Secondly, the rectification efficiency determines the ratio of RF energy converted to DC energy in the MPT system; the higher this ratio, the greater the energy transmitted by the MPT system, and the lower the overall system energy loss. In summary, as long as the rectifier circuit achieves the highest possible input power while maintaining the highest possible rectification efficiency, the entire MPT system can realize high-power and high-efficiency wireless power transmission.

[0003] However, there are still many difficulties in achieving high power and high efficiency in rectifier circuits. Schottky diodes, as the core components of rectifier circuits, contain a series parasitic resistance Rs in their equivalent circuit. The greater the input power of the rectifier circuit, the higher the energy loss loaded on the series parasitic resistance Rs, and the lower the rectification efficiency. Therefore, it is quite difficult for rectifier circuits to achieve both high power and high efficiency at the same time. Summary of the Invention

[0004] To overcome the problems of difficult matching and low efficiency in traditional microwave rectifier circuits mentioned above, this invention proposes a Class F high-power rectifier circuit based on admittance matching, combining principles such as Class F harmonic control and admittance matching. The three-stage Class F harmonic network reduces diode losses by controlling the impedance state of the third-stage harmonics, thereby increasing rectification efficiency. The admittance matching structure matches the admittance of the rectifier circuit, not only reducing the complexity of matching and increasing its intuitiveness, but also optimizing the return loss S11 of the rectifier circuit, ultimately achieving a balance between high power and high efficiency.

[0005] The technical solution adopted in this invention is as follows: A Class F high-power rectifier circuit based on admittance matching includes a dielectric substrate, a circuit structure disposed on the upper surface of the dielectric substrate, and a grounded metal ground plane disposed on the lower surface of the dielectric substrate. The rectifier circuit consists of three material layers.

[0006] The circuit structure includes a three-level Class F harmonic network, an admittance matching structure, a DC filter structure, a 50-ohm pad, a Schottky diode, a load resistor, and a grounding via. The three-level Class F harmonic network includes a first microstrip line, a second microstrip line, and a third microstrip line; the first microstrip line and the third microstrip line with open terminals are connected to the output terminal of a Schottky diode, and the second microstrip line with short-circuited terminals is connected to the input terminal of a Schottky diode. One end of the admittance matching structure is connected to the input terminal of the Schottky diode, the other end of the admittance matching structure is connected to one end of the DC filter structure, the other end of the DC filter structure is connected to the load resistor, and the other end of the load resistor is grounded. One end of the 50-ohm pad is connected to the RF input terminal, and the other end is connected to one end of the DC filter structure.

[0007] In one implementation, the first microstrip line, the second microstrip line, and the third microstrip line are respectively λ / 8 microstrip line, λ / 12 microstrip line, and λ / 16 microstrip line, where λ is the wavelength.

[0008] In one implementation, the admittance matching structure and the DC filter structure include a first admittance matching microstrip line Filter&Match, a second admittance matching microstrip line Match_Turn, and a λ / 4 sector microstrip line. The admittance matching structure and the DC filter structure share the first admittance matching microstrip line Filter&Match. The first admittance matching microstrip line Filter&Match and the second admittance matching microstrip line Match_Turn are connected in series, and the other end of the second admittance matching microstrip line Match_Turn is connected to the input terminal of a Schottky diode. The other end of the first admittance matching microstrip line Filter&Match is connected to one end of the λ / 4 sector microstrip line, and the other end of the λ / 4 sector microstrip line is connected to a load resistor.

[0009] In one implementation, the 50-ohm pad comprises two 50-ohm microstrip lines connected in series, with a DC blocking capacitor connected in series between the two 50-ohm microstrip lines. The width of each 50-ohm microstrip line is 1.89 mm, and the lengths are 5.0 mm and 4.4 mm, respectively.

[0010] In one implementation, the length and width dimensions of the λ / 8 microstrip line, λ / 12 microstrip line, and λ / 16 microstrip line are 9.74 mm long / 1.89 mm wide, 5.92 mm long / 1.89 mm wide, and 5.57 mm long / 1.89 mm wide, respectively.

[0011] In one implementation, the first admittance matching microstrip line Filter & Match has a length of 9.94 mm and a width of 1.89 mm, the second admittance matching microstrip line Match_Turn has a length of 9.94 mm and a width of 1.89 mm, and the λ / 4 sector microstrip line has a radius of 11.8 mm and an angle of 70°.

[0012] In one embodiment, the circuit operates at a center frequency of 2.55 GHz, the dielectric substrate has a thickness of 0.76 mm, and a relative permittivity of 2.94.

[0013] Compared with the prior art, the main advantages of the present invention are: 1. A novel three-stage Class F harmonic control network is employed to reduce diode losses and improve rectifier circuit efficiency. Traditional Class F harmonic control networks only perform impedance control on the second and third harmonics to reduce diode losses and improve rectification efficiency. This invention proposes a novel three-stage Class F harmonic control network that not only performs impedance control on the second and third harmonics but also on the fourth harmonic. The more stages of the harmonic control network, the more effectively diode losses can be reduced, and the higher the rectification efficiency can be further improved.

[0014] 2. A new admittance-based matching technique is adopted to reduce the complexity of parallel circuit matching and increase its intuitiveness. Traditional impedance matching techniques have the advantages of being simple and intuitive for cascaded circuits because multiple cascaded impedances can be directly added. However, multiple parallel impedances cannot be directly added, making impedance matching more complex for parallel circuits. This invention proposes a new admittance-based matching technique that converts impedance into admittance, allowing the admittances of parallel circuits to be directly added. By matching the admittances, the complexity of parallel circuit matching can be reduced and the intuitiveness of matching can be increased. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the rectifier circuit of the present invention.

[0016] Figure 2 This is a diagram illustrating the admittance matching process of the rectifier circuit in this invention.

[0017] Figure 3 The figures show the simulation and measured performance curves of the rectifier circuit of this invention. Detailed Implementation

[0018] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0019] A Class F high-power rectifier circuit based on admittance matching, operating at a center frequency of 2.55 GHz, comprises a dielectric substrate, a circuit structure disposed on the upper surface of the dielectric substrate, and a grounding metal ground plane disposed on the lower surface of the dielectric substrate. The rectifier circuit consists of three material layers. The dielectric substrate is Teflon 300CA-C, with a thickness of 0.76 mm, a relative permittivity of 2.94, a loss tangent of 0.0016, and the overall circuit dimensions are 3.99 cm × 3.1 cm.

[0020] The metal floor consists of a single copper sheet on the back of the PCB board, serving as a common ground for radio frequency and DC signals, and a reservoir for signal energy.

[0021] The circuit structure on the upper surface, such as Figure 1 As shown, it includes a three-level Class-F Harmonic Control Network, an Admittance Match structure, an Admittance Match & DC Filter structure, a 50-ohm Solder Pad, a metal ground plane, a Schottky diode, a DC blocking capacitor (Cin), a load resistor (RL), and a grounding via.

[0022] Grounding vias are metallized vias with windows, used to connect the rectifier circuit structure on the front of the PCB board to the metal ground on the back. These grounding vias are mainly distributed at the solder joints of small coaxial cable connectors (SMA), the grounding points of λ / 12 microstrip lines, and the grounding points of load resistors.

[0023] The Schottky diode used in this embodiment is the HSMS-270B Schottky diode manufactured by AVAGO, which is a core component for rectifying current. This Schottky diode has a high reverse breakdown voltage of 25 V, a low series resistance of 0.65 Ω, and a zero-bias junction capacitance of 6.7 pF, making it very suitable for high-power rectifier circuit designs.

[0024] The three-stage Class F harmonic network includes a λ / 8 microstrip line (ML-λ / 8), a λ / 16 microstrip line (ML-λ / 16), and a λ / 12 microstrip line (ML-λ / 12), where λ represents the wavelength on the dielectric substrate at 2.55 GHz, and ML represents the length of the microstrip line corresponding to that wavelength at 2.55 GHz. An open-circuit λ / 8 microstrip line (9.74 mm / 1.89 mm) is connected in parallel to the output of a Schottky diode. An open-circuit λ / 16 microstrip line (5.57 mm / 1.89 mm) is also connected in parallel to the output of a Schottky diode. A ground-short-circuit λ / 12 microstrip line (5.92 mm / 1.89 mm) is connected in series to the input of a Schottky diode. The ground connection is via a metal via to the back metal plate. This structure enables Class F harmonic impedance control of the third harmonic, reducing diode losses and thus improving rectification efficiency. This invention employs a novel three-stage Class-F harmonic control network. A λ / 8 open-circuit microstrip line is connected in parallel at the diode's output to achieve low impedance for the second harmonic. A λ / 12 short-circuit microstrip line is connected in series at the diode's input to achieve high impedance for the third harmonic. A λ / 16 open-circuit microstrip line is connected in parallel at the diode's output to achieve low impedance for the fourth harmonic. By controlling the impedance of these three harmonics (second, third, and fourth) and satisfying the conditions of low impedance for even harmonics and high impedance for odd harmonics, the design of the Class-F harmonic control network is achieved. This makes the voltage and current waveforms across the diode die approximate square waves and half-sine waves, respectively, reducing the time-domain overlap of the voltage and current waveforms, lowering diode losses, and thus improving rectification efficiency. Unlike traditional Class-F harmonic control networks that only control the second and third harmonics to reduce diode losses and improve rectification efficiency, this invention proposes a novel three-stage Class-F harmonic control network that controls the impedance of not only the second and third harmonics but also the fourth harmonic. The more stages of harmonic control the network, the lower the diode losses and the higher the rectification efficiency.

[0025] The admittance matching structure consists of two admittance matching microstrip lines: an impedance matching stub (Match_Turn) and a DC filter + impedance matching (Filter&Match). This admittance matching structure reduces the complexity of rectifier circuit matching and increases the intuitiveness of matching. The first admittance matching microstrip line, Filter&Match (9.94mm long / 1.89mm wide), is connected in parallel after the λ / 4 sector microstrip line, participating not only in DC filtering but also in admittance matching together with the impedance matching stub at the other end. The second admittance matching microstrip line, Match_Turn (9.94mm long / 1.89mm wide), is connected in series after the third-level Class F harmonic network. Finally, the other ends of the two admittance matching microstrip lines are connected in parallel.

[0026] The DC filter structure consists of a λ / 4 sector microstrip line (FML_λ / 4) and a first admittance matching microstrip line (Filter & Match). This DC filter structure filters out radio frequency (RF) signals. The λ / 4 sector microstrip line has a radius of 11.8 mm and an angle of 70°. The first admittance matching microstrip line (Filter & Match, 9.74 mm long and 1.89 mm wide) is connected in parallel after the λ / 4 sector microstrip line. The other end of the sector microstrip line is connected to the load resistor RL at the output of the rectifier circuit. This load resistor is placed at the DC output of the rectifier circuit, i.e., after the DC filter structure, to carry the energy of the DC signal. The first admittance matching microstrip line is connected in parallel after the open-circuit λ / 4 sector microstrip line, which not only achieves the function of passing DC and filtering RF signals but also provides admittance matching. In other words, this structure differs from traditional filters that only have a single filtering function; the DC filter structure of this invention also has an admittance matching function, deeply participating in the matching of the entire circuit.

[0027] The 50-ohm solder pad consists of two 50-ohm microstrip lines (Line_50 Ω, each 1.89 mm wide and 5.0 mm and 4.4 mm long respectively) connected in series with a DC blocking capacitor (Cin) at the RF input terminal. The RF input terminal is where the RF signal is input. The DC signal is blocked by the DC blocking capacitor through the 50-ohm solder pad microstrip lines, preventing it from flowing back into the RF input terminal and avoiding DC signal loss and reduced rectification efficiency. The DC blocking capacitor is located between the two solder pads, with the other end of the pad connected to two admittance matching microstrip lines. The output terminals of the Schottky diodes are connected in parallel to λ / 8 microstrip lines (ML_λ / 8) and λ / 16 microstrip lines (ML_λ / 16), while the input terminals are connected in series to λ / 12 microstrip lines (ML_λ / 12).

[0028] Figure 2 This diagram illustrates the admittance matching process of the rectifier circuit in this invention. The admittance matching process mainly consists of three steps. The admittance matching structure comprises two admittance matching microstrip lines (Match_Turn and Filter&Match). This structure reduces the complexity of rectifier circuit matching and increases the intuitiveness of the matching process. The second admittance matching microstrip line, Match_Turn, is connected in series after the three-stage Class F harmonic network, while the first admittance matching microstrip line, Filter&Match, is connected in parallel after the DC filter fan-shaped microstrip line. These two admittance matching microstrip lines are connected in parallel.

[0029] Figure 2 In the diagram, (a) indicates that the input impedance after connecting the second admittance matching microstrip line Match_Turn is Z. in2=30.8 - j27.1 Ω, where j represents the imaginary unit. At this moment, the input impedance can be equivalent to a 30.8 Ω resistor connected in series with a -27.1 Ω capacitor. Simultaneously, the input impedance of the first admittance matching microstrip line Filter & Match is Z. in3 = 0 + j56.8Ω, the input impedance at this moment can be equivalent to a j56.8 Ω inductor. Since two input impedances connected in parallel cannot be directly added, Z... in2 The series circuit of 30.8 - j27.1 Ω is transformed into an equivalent parallel circuit of 54.6 - j62.1 Ω. This results in an equivalent circuit with a 54.6 Ω resistor, a - j62.1 Ω capacitor, and a j56.8 Ω inductor connected in parallel. This process is called... Figure 2 (b) Since it is an input impedance, the structures cannot be directly added. Therefore, the equivalent circuit of the three impedances in parallel above is transformed into an equivalent circuit of the three admittances in parallel. In this way, the admittances can be directly added. The transformed equivalent circuit of admittances is a series connection of 1 / 54.6 S conductance, -1 / j62.1 S s susceptance, and 1 / j56.8 S susceptance, where Y in2 = 1 / 54.6 - 1 / j62.1 S, the admittance value after addition is Y. in = 1 / 54.6 – j665.5 S, approximately equal to Y in = 1 / 55S admittance, which, when converted to impedance, is approximately equal to Z. in With an input impedance of 55 Ω, which is very close to the ideal matching condition of 50 Ω, admittance matching is finally achieved. This process is called... Figure 2 (c) Traditional impedance matching techniques offer the advantages of simplicity and intuitiveness in matching cascaded circuits because multiple cascaded impedances can be directly added together. However, multiple parallel impedances cannot be directly added together, making impedance matching for parallel circuits more complex. This invention proposes a new admittance matching technique that converts impedances into admittances, allowing the admittances of parallel circuits to be directly added together. By matching the admittances, the complexity of matching parallel circuits can be reduced, and the intuitiveness of the matching process can be increased.

[0030] It should be noted here that because the two admittance matching microstrip lines are connected in parallel, if impedance matching is used, the input impedance Z after connecting the second admittance matching microstrip line Match_Turn will be higher. in2 = 30.8 - j27.1 Ω and the first admittance. The input impedance of the microstrip line Filter & Match, 0 + j56.8 Ω, does not have an intuitive impedance matching relationship. It is necessary to compare the two input impedances Z. in2The series equivalent circuit is first transformed into a parallel equivalent circuit, and then into admittances of 1 / 54.6S, -1 / j62.1S, and 1 / j56.8S before they can be directly added to complete admittance matching. Another point to note during the design is that by adjusting the lengths of the two admittance matching microstrip lines, the imaginary parts of the input impedance of the parallel equivalent circuit can cancel each other out to zero. This leaves only the real parts. For example, the imaginary parts of the impedance adjusted in this invention are -j62.1Ω and j56.8Ω, which cancel out to approximately zero.

[0031] Figure 3 The figure shows the simulation and measured performance curves of the rectifier circuit of this invention. The rectifier circuit operates at 2.55 GHz, with a load resistance of RL=90 Ω and a default input power of 32 dBm. Figure 3 (a) shows the performance curve of the rectifier circuit efficiency as a function of input power. The input power range of the rectifier circuit is 15 dBm ~ 32 dBm. When the input power reaches the maximum of 32 dBm, the simulated and measured rectification efficiencies reach their maximum values ​​of 79.6% and 76.6%, respectively, with a difference of only 3%. Figure 3 (b) shows the performance curve of the rectifier circuit efficiency as a function of operating frequency. It can be seen that the highest rectification efficiency is at 2.55 GHz, which is the center frequency of the rectifier circuit. The corresponding simulated efficiency and measured efficiency are 79.6% and 76.6%, respectively. Figure 3 (c) shows the performance curve of the rectifier circuit efficiency as a function of load resistance. The load range of this rectifier circuit is 50 Ω to 130 Ω. The simulated and measured efficiencies at 90 Ω are 79.6% and 76.6%, respectively, reaching the highest efficiency value. Overall, the rectifier circuit designed in this invention achieves good high power and high efficiency performance at 2.55 GHz, and the simulated and measured data of the three performance curves are not significantly different.

[0032] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A Class F high-power rectifier circuit based on admittance matching, characterized in that, It includes a dielectric substrate, a circuit structure disposed on the upper surface of the dielectric substrate, and a grounding metal ground plate disposed on the lower surface of the dielectric substrate; The circuit structure includes a three-level Class F harmonic network, an admittance matching structure, a DC filter structure, a 50-ohm pad, a Schottky diode, a load resistor, and a grounding via. The three-level Class F harmonic network includes a first microstrip line, a second microstrip line, and a third microstrip line; the first microstrip line and the third microstrip line with open terminals are connected to the output terminal of a Schottky diode, and the second microstrip line with short-circuited terminals is connected to the input terminal of a Schottky diode. One end of the admittance matching structure is connected to the input terminal of the Schottky diode, the other end of the admittance matching structure is connected to one end of the DC filter structure, the other end of the DC filter structure is connected to the load resistor, and the other end of the load resistor is grounded. One end of the 50-ohm pad is connected to the RF input terminal, and the other end is connected to one end of the DC filter structure.

2. The Class F high-power rectifier circuit based on admittance matching according to claim 1, characterized in that, The first microstrip line, the second microstrip line, and the third microstrip line are λ / 8 microstrip line, λ / 12 microstrip line, and λ / 16 microstrip line, respectively, where λ is the wavelength.

3. The Class F high-power rectifier circuit based on admittance matching according to claim 2, characterized in that, The admittance matching structure and DC filter structure include a first admittance matching microstrip line Filter&Match, a second admittance matching microstrip line Match_Turn, and a λ / 4 sector microstrip line. The admittance matching structure and the DC filter structure share the first admittance matching microstrip line Filter&Match. The first admittance matching microstrip line Filter&Match and the second admittance matching microstrip line Match_Turn are connected in series, and the other end of the second admittance matching microstrip line Match_Turn is connected to the input terminal of a Schottky diode. The other end of the first admittance matching microstrip line Filter&Match is connected to one end of the λ / 4 sector microstrip line, and the other end of the λ / 4 sector microstrip line is connected to a load resistor.

4. The Class F high-power rectifier circuit based on admittance matching according to claim 3, characterized in that, The 50-ohm pad comprises two 50-ohm microstrip lines connected in series, with a DC blocking capacitor connected in series between the two 50-ohm microstrip lines.

5. A Class F high-power rectifier circuit based on admittance matching according to claim 4, characterized in that, The length and width dimensions of the λ / 8 microstrip line, λ / 12 microstrip line, and λ / 16 microstrip line are 9.74 mm long / 1.89 mm wide, 5.92 mm long / 1.89 mm wide, and 5.57 mm long / 1.89 mm wide, respectively.

6. A Class F high-power rectifier circuit based on admittance matching according to claim 5, characterized in that, The first admittance matching microstrip line Filter & Match has a length of 9.94 mm and a width of 1.89 mm, the second admittance matching microstrip line Match_Turn has a length of 9.94 mm and a width of 1.89 mm, and the λ / 4 sector microstrip line has a radius of 11.8 mm and an angle of 70°.

7. A Class F high-power rectifier circuit based on admittance matching according to claim 6, characterized in that, The circuit operates at a center frequency of 2.55 GHz, the dielectric substrate has a thickness of 0.76 mm, and a relative permittivity of 2.

94.

8. A Class F high-power rectifier circuit based on admittance matching according to claim 7, characterized in that, The width of each 50-ohm microstrip line is 1.89 mm, and the lengths are 5.0 mm and 4.4 mm, respectively.

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