Series-parallel high-transformation-ratio DC-DC converter and control method

Abstract

The invention discloses a series-parallel high-transformation-ratio DC-DC converter and a control method, and relates to the technical field of power electronics. The converter is composed of N identical modules, and each module comprises a voltage dividing capacitor, a switched capacitor unit (comprising an upper bridge arm switch, a lower bridge arm switch and a blocking capacitor) and a shunt inductor unit (comprising a follow current switch and an inductor) which are connected in sequence. All the voltage-dividing capacitors are connected in series to two ends of the direct-current power supply to form a multi-level potential node; the switched capacitor unit of each module is connected with a shunt inductor through a blocking capacitor, and finally all shunt inductors are connected in parallel and output to a load, thereby achieving the functions of voltage division and current convergence. According to the invention, the voltage and current stress of the switching device of the high transformation ratio converter is reduced, the hardware complexity of the auxiliary driving power supply of the switching device is also reduced, and the bidirectional power transmission capability is realized.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a series-parallel high-ratio DC-DC converter and its control method. Background Technology

[0002] With the explosive growth of cloud computing, big data, and generative artificial intelligence technologies, the computing density of modern data centers is constantly increasing, with single-rack power ranging from several kilowatts to tens or even hundreds of kilowatts. In traditional 12V data center power distribution architectures, as load power increases, the current in the distribution bus increases dramatically, leading to a significant increase in transmission losses on the bus and severely impacting the power efficiency of the data center. To address this issue, data center power supply architectures are rapidly evolving from traditional 12V centralized distribution to 48V bus architectures. Compared to the 12V architecture, the 48V architecture can reduce bus current, thereby reducing line transmission losses and significantly improving the overall system efficiency.

[0003] Despite the clear advantages of the 48V architecture, board-level power conversion technology faces significant challenges during implementation. Existing 48V architectures primarily include traditional two-stage and single-stage direct buck architectures, both of which have significant limitations. Two-stage architectures typically use an intermediate bus converter to step down the 48V to 12V, and then a multi-phase Buck converter to step down the 12V to the chip power supply voltage, such as 0.5V to 1V. While technically mature, the two-stage conversion leads to secondary energy losses, making it difficult to meet the stringent requirements of data centers for extreme conversion efficiency and high power density. Traditional single-stage Buck converters, when facing high buck ratio applications, achieve voltage reduction through an extremely narrow duty cycle. This results in excessive voltage stress on the power switches, significantly increased conduction and switching losses, limiting the increase in switching frequency, and also causing large current ripple and poor transient response performance. The emerging hybrid switched capacitor single-stage architecture directly reduces the 48V voltage to the chip supply voltage of 0.5V~1V. Although the voltage stress of the device is reduced by capacitor voltage division, the existing series capacitor voltage reduction scheme often faces the problem of capacitor pre-charging during startup, as well as the problem of complex power supply circuit for switching device drive.

[0004] In addition to the unidirectional step-down power supply to the chip, the chip power supply also needs to simulate loads for aging and reliability testing. To reduce the power consumption costs of aging and reliability testing, electronic loads are often required, which necessitates that the converter have bidirectional power transmission capabilities, such as stepping down and boosting 0.5V~1V to a 12V or 48V DC bus.

[0005] The high-voltage side drive circuit design of existing single-stage buck DC-DC converters is extremely complex. Because the source potential of the high-side switching transistors is floating, expensive isolated drive power supply modules or complex bootstrap circuits are typically required. Especially in multi-level or multi-phase interleaved topologies, a large number of independent floating-ground isolated drive power supplies not only increase PCB layout complexity but also significantly drive up system costs. Bootstrap drive circuits in complex converter topologies are often limited by startup and duty cycle ranges, and also increase system size and cost, hindering improvements in converter power density. Summary of the Invention

[0006] The purpose of this invention is to provide a series-parallel high-ratio DC-DC converter and control method, aiming to solve or improve at least one of the above-mentioned technical problems.

[0007] To achieve the above objectives, the present invention provides the following solution: A series-parallel high-ratio DC-DC converter includes: N circuit modules; each circuit module includes a voltage divider capacitor unit, a switched capacitor unit, and a shunt inductor unit connected in sequence; wherein, N≥2, and the N voltage divider capacitor units are connected in series between the positive and negative terminals of the DC input power supply to form N+1 medium DC potential nodes; the output terminals of the N shunt inductor units are connected in parallel and connected to the load terminal; In each of the circuit modules: The voltage divider capacitor unit includes one voltage divider capacitor; The switched capacitor unit includes an upper bridge arm switch, a lower bridge arm switch, and a DC blocking capacitor. The first terminal of the upper bridge arm switch is connected to the positive potential terminal of the voltage dividing capacitor; the second terminal of the upper bridge arm switch is connected to the first terminal of the lower bridge arm switch; and the second terminal of the lower bridge arm switch is connected to the negative potential terminal of the voltage dividing capacitor. The series connection point between the upper and lower bridge arm switches forms the midpoint of the bridge arm. The first terminal of the DC blocking capacitor is connected to the midpoint of the bridge arm. The shunt inductor unit includes a freewheeling switch and an inductor; wherein, the first end of the freewheeling switch is connected to the first end of the inductor to form a freewheeling node, and the freewheeling node is also connected to the second end of the DC blocking capacitor; the second end of the freewheeling switch is used to connect to the output negative terminal, and the second end of the inductor is used to connect to the output positive terminal.

[0008] Optionally, the converter composed of N circuit modules has a bidirectional power conversion function; the bidirectional power conversion function includes switching between two modes: Buck and Boost.

[0009] Optionally, each voltage divider capacitor unit precharges all voltage divider capacitors before startup, and all voltage divider capacitors have the same charging current during precharging, and all voltage divider capacitors have the same capacitance.

[0010] The present invention also provides a control method for a series-parallel high-ratio DC-DC converter, comprising: Step 1: In each control cycle, acquire the output voltage and output current; Step 2: Calculate the output voltage deviation between the current sampling time and the previous sampling time. Select the control mode based on the output current, output voltage deviation and system status. Engage the inner current loop under heavy load or rapid dynamic conditions, and allow the inner current loop to be switched out under light load conditions. Set hysteresis and minimum dwell time for the current loop switching to avoid frequent jitter. The control modes include Buck buck mode and Boost boost mode. Step 3: Compare the output voltage with the given reference voltage and generate a current reference signal through the voltage error compensator; compare the actual acquired output current with the corresponding current reference signal and generate a duty cycle signal through the current error compensator. Step 4: Set N phases to be staggered, with a phase difference of 360° / N between adjacent units, so that at the same time, only one of the N inductors is in the charging state, while the other N-1 inductors are in the discharging freewheeling state. Step 5: Input the duty cycle signal and phase difference into the PWM modulator, compare it with the carrier wave, and output a PWM wave. Use the output PWM wave as the trigger signal for the switch to drive each switch. Set a dead time for the complementary switch and add a rate of change limit to suppress peak current and improve transient response.

[0011] Optionally, the sampling frequencies of the output voltage and the output current are synchronized with the PWM carrier to reduce the impact of switching noise on sampling.

[0012] Optionally, in step 5, the method of setting a dead time for the complementary switch includes: In the converter, the upper and lower bridge arm switches of the switched capacitor unit are complementary in conduction, and dead time is set between the upper bridge arm switch being turned off and the lower bridge arm switch being turned on, and between the upper bridge arm switch being turned on and the lower bridge arm switch being turned off.

[0013] Optionally, in step 5, the method of setting a dead time for the complementary switch further includes: In the converter, the upper arm switch and the freewheeling switch of the switched capacitor unit are complementary in conduction, and a dead time is set between the upper arm switch being turned off and the freewheeling switch being turned on, and between the upper arm switch being turned on and the freewheeling switch being turned off.

[0014] Optionally, before starting step 1, the converter is powered on; in the initial stage of powering on the converter, all switching transistors are forced to be in the off state until each voltage divider capacitor is pre-charged. At this time, the duty cycle signal increases linearly from zero on a ramp until the output voltage reaches the set value to limit the start-up inrush current.

[0015] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects: This invention discloses a series-parallel high-ratio DC-DC converter and its control method. The converter includes N circuit modules. Each circuit module includes a voltage divider capacitor unit, a switched capacitor unit, and a shunt inductor unit connected in sequence. N ≥ 2, and the N voltage divider capacitor units are connected in series between the positive and negative terminals of the DC input power supply to form N+1 medium DC potential nodes. The output terminals of the N shunt inductor units are connected in parallel and connected to the load terminal.

[0016] In each of the circuit modules: the voltage divider capacitor unit includes one voltage divider capacitor; the switched capacitor unit includes one upper bridge arm switch, one lower bridge arm switch, and one DC blocking capacitor; wherein, the first end of the upper bridge arm switch is connected to the positive potential end of the voltage divider capacitor, the second end of the upper bridge arm switch is connected to the first end of the lower bridge arm switch, and the second end of the lower bridge arm switch is connected to the negative potential end of the voltage divider capacitor; the series connection point between the upper bridge arm switch and the lower bridge arm switch constitutes the midpoint of the bridge arm; the first end of the DC blocking capacitor is connected to the midpoint of the bridge arm; the shunt inductor unit includes one freewheeling switch and one inductor; wherein, the first end of the freewheeling switch is connected to the first end of the inductor to form a freewheeling node, and the freewheeling node is also connected to the second end of the DC blocking capacitor; the second end of the freewheeling switch is used to connect to the output negative terminal, and the second end of the inductor is used to connect to the output positive terminal.

[0017] Furthermore, based on the aforementioned converter structure, a corresponding control method is also provided. This invention effectively solves the problem of voltage stress on switching devices faced by high buck ratio topologies; it also enables high current output, improving efficiency; and the converter can achieve self-powered drive, reducing the number of components in the drive circuit and lowering the converter cost, especially eliminating the need for an isolated DC-DC converter that requires power for the drive, as well as a bootstrap circuit for the drive power supply; the converter also avoids the problems caused by capacitor charging during startup; and it features easy driving, easy expansion, and reliable startup. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is the N-phase schematic diagram of the series-parallel high-ratio DC-DC converter in this embodiment; Figure 2 This embodiment reduces the number of series capacitors and switching devices in the series-parallel high-ratio DC-DC converter N-phase circuit diagram; Figure 3 This is the N-phase circuit diagram of a high-ratio DC-DC converter using an LC series network in this embodiment; Figure 4 This is a three-phase schematic diagram of the series-parallel high-ratio DC-DC converter in this embodiment; Figure 5 This is a waveform diagram of the switching duty cycle and inductor current of the three phases of the series-parallel high-ratio DC-DC converter in Buck mode in this embodiment. Figure 6 This is a waveform diagram of the switching duty cycle and inductor current of the three phases of the series-parallel high-ratio DC-DC converter in Boost mode in this embodiment. Figure 7 This is the control block diagram of the series-parallel high-ratio DC-DC converter in this embodiment. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The purpose of this invention is to provide a series-parallel high-ratio DC-DC converter and control method, aiming to solve or improve at least one of the above-mentioned technical problems.

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] This invention provides a series-parallel high-ratio DC-DC converter, comprising: N circuit modules; each circuit module includes a voltage divider capacitor unit, a switched capacitor unit, and a shunt inductor unit connected in sequence; wherein, N≥2, and the N voltage divider capacitor units are connected in series between the positive and negative terminals of the DC input power supply to form N+1 medium DC potential nodes; the output terminals of the N shunt inductor units are connected in parallel and connected to the load terminal.

[0024] In each of the circuit modules: The voltage divider capacitor unit includes one voltage divider capacitor; the switched capacitor unit includes one upper bridge arm switch, one lower bridge arm switch, and one DC blocking capacitor; wherein, the first end of the upper bridge arm switch is connected to the positive potential end of the voltage divider capacitor, the second end of the upper bridge arm switch is connected to the first end of the lower bridge arm switch, and the second end of the lower bridge arm switch is connected to the negative potential end of the voltage divider capacitor; the series connection point between the upper bridge arm switch and the lower bridge arm switch constitutes the midpoint of the bridge arm; the first end of the DC blocking capacitor is connected to the midpoint of the bridge arm; the shunt inductor unit includes one freewheeling switch and one inductor; wherein, the first end of the freewheeling switch is connected to the first end of the inductor to form a freewheeling node, and the freewheeling node is also connected to the second end of the DC blocking capacitor; the second end of the freewheeling switch is used to connect to the output negative terminal, and the second end of the inductor is used to connect to the output positive terminal.

[0025] In one specific implementation, the converter features bidirectional power conversion capability, which includes switching between Buck and Boost modes. Each voltage divider capacitor unit pre-charges all voltage divider capacitors before startup, with all capacitors receiving the same charging current during pre-charging, and all capacitors having the same capacitance.

[0026] As a specific implementation, this converter can operate in Buck mode for high buck ratio chip power supplies, and in Boost mode for power electronic loads. This invention innovatively solves the problem of power supply difficulty for high-side switching transistors by utilizing the stable voltage characteristics of the voltage divider capacitors in the topology. In the circuit design, the power supply terminal of the main switching transistor driver chip of each switching unit is directly connected in parallel to its corresponding voltage divider capacitor. Regardless of the converter's operating mode, as long as there is voltage on the high-voltage side, the voltage divider on the series capacitors can provide a stable operating voltage for the driver chip. This self-powered driver design completely eliminates the need for multiple independent isolated power supplies or complex bootstrap circuits required in traditional multi-level topologies, not only reducing system cost but also significantly reducing PCB routing complexity and system size.

[0027] Therefore, based on the above converter structure, this invention also solves the startup voltage equalization problem faced by traditional switched-capacitor converters. In traditional pure capacitor switching circuits, the capacitor voltages are unbalanced at startup, requiring pre-charging measures. However, this invention uses series capacitors on the high-voltage side, ensuring that all series capacitors receive equal charging current during overall circuit startup, thus providing automatic voltage equalization.

[0028] Furthermore, the present invention also provides a control method applicable to the above-mentioned converter. The control method is executed by a controller, which is connected to at least an output voltage sampling circuit and an output current sampling circuit, and provides PWM drive signals to each power switch. The control method includes the following steps: Step 1: Acquire the output voltage and output current in each control cycle. Preferably, the sampling is synchronized with the PWM carrier to reduce the impact of switching noise on the sampling.

[0029] Step 2: Select the control mode according to the output current magnitude, output voltage deviation and system status. Engage the inner current loop under heavy load or rapid dynamic conditions, and allow the inner current loop to be switched out under light load conditions. Set hysteresis and minimum dwell time for the current loop switching to avoid frequent jitter.

[0030] Step 3: Compare the acquired output voltage with the given reference voltage and generate a current reference signal through the voltage error compensator; compare the actual acquired output current with the corresponding current reference value and generate a duty cycle signal through the current error compensator.

[0031] Step 4: Set N phases to be staggered, with a phase difference of 360° / N between adjacent units, so that at the same time, only one of the N inductors is in the charging state, while the other N-1 inductors are in the discharging freewheeling state.

[0032] Step 5: Input the duty cycle signal and phase difference into the PWM modulator, compare it with the carrier wave, and output a PWM wave. Use the output PWM wave as the trigger signal for the switch to drive each switch. Set a dead time for the complementary switch and add a rate of change limit to suppress peak current and improve transient response.

[0033] During startup, the controller first enters a pre-charging process to charge the voltage divider capacitor to the preset voltage value. After pre-charging, it enters a soft-start process, smoothly ramping up the reference voltage from zero, gradually increasing the duty cycle signal from small to large until the output voltage reaches the set value. During soft start, current sharing and voltage division balancing are continuously performed, and current is limited to suppress surges. During operation, overvoltage, undervoltage, overcurrent, short circuit, voltage divider capacitor overvoltage, overtemperature, and other conditions are continuously monitored. When protection is triggered, power limiting and drive shutdown strategies are implemented to avoid circuit failures.

[0034] It is evident that the beneficial effects of adopting this technical solution are as follows: 1. The converter is configured to perform bidirectional power conversion, enabling it to switch between Buck and Boost modes, and can be applied to both high buck ratio chip power supplies and power electronic loads.

[0035] 2. By using a series of voltage divider capacitors on the high-voltage side to distribute the high voltage to each stage of the unit, each power switching device can operate in a lower voltage stress range, which is beneficial for selecting devices with lower withstand voltage and lower on-resistance, thereby reducing conduction loss and switching loss.

[0036] 3. The N-phase interleaved parallel structure naturally possesses the characteristics of multi-phase parallel current sharing and ripple cancellation, which can reduce output current ripple and input side pulsation and improve transient response.

[0037] 4. Large current input or output can be achieved by connecting shunt inductors in parallel, and the current of each phase inductor is controlled, which facilitates the equal distribution of current.

[0038] 5. The introduction of pre-charging and soft-start strategies effectively suppresses charging surges and startup overcurrents in the voltage divider capacitor, improving engineering reliability.

[0039] 6. This converter can achieve self-powered drive, reducing the number of components in the drive circuit and lowering the cost of the converter. In particular, it eliminates the need for an isolated DC-DC converter that requires power to the drive and also eliminates the need for a drive power supply bootstrap circuit.

[0040] 7. The topology has modular expansion capabilities: By changing the N value, the balance between device stress, ripple and power level can be achieved, which facilitates platform reuse for different power levels.

[0041] Based on the above technical solution, the following embodiments are provided.

[0042] Figure 1 This is an N-phase schematic diagram of a series-parallel high-ratio DC-DC converter in this embodiment. This embodiment includes N voltage-dividing capacitor units, N switched capacitor units, and N shunt inductor units, where N ≥ 2. Each voltage-dividing capacitor unit includes one voltage-dividing capacitor. Each switched capacitor unit includes one upper bridge arm switch, one lower bridge arm switch, and one DC-blocking capacitor. The upper and lower bridge arm switches are connected in series, and their connection point forms the midpoint of the bridge arm. The first end of the DC-blocking capacitor is connected to the midpoint of the bridge arm. Each shunt inductor unit includes one freewheeling switch and one inductor. The first end of the freewheeling switch is connected to the first end of the inductor to form a freewheeling node. The second end of the freewheeling switch is used to connect to the negative output terminal, and the second end of the inductor is used to connect to the positive output terminal. N voltage divider capacitor units are connected in series between the positive and negative terminals of the DC input power supply; the k-th switched capacitor unit is connected in parallel across the k-th voltage divider capacitor unit (k=1, 2, ..., N); specifically, the first terminal of the upper bridge arm switch in the k-th switched capacitor unit is connected to the positive potential terminal of the k-th voltage divider capacitor, and the second terminal of the lower bridge arm switch is connected to the negative potential terminal of the k-th voltage divider capacitor; the second terminal of the DC blocking capacitor in the k-th switched capacitor unit is connected to the freewheeling node of the k-th shunt inductor unit; the output terminals of the N shunt inductor units are connected in parallel and connected to the load terminal.

[0043] Figure 2 This invention presents an N-phase circuit diagram of a series-parallel high-ratio DC-DC converter with reduced series capacitor and switching device. Through voltage and current analysis of the passive devices and voltage stress analysis of the active devices in this embodiment, it was found that when the input voltage fluctuation is small or the output ripple requirement is not stringent, the DC blocking capacitor in the Nth switched capacitor unit and the freewheeling switch in the Nth shunt inductor unit can be removed. Specifically, since the negative terminal of the Nth voltage divider capacitor is directly connected to the negative terminal of the DC input power supply, the potential at the midpoint of the bridge arm of the Nth phase switched capacitor unit no longer exhibits a high common-mode floating ground characteristic relative to the output negative terminal, but instead oscillates near a low potential reference. Based on this potential relationship, the midpoint of the bridge arm of the Nth phase can be directly connected to the Nth phase inductor as the switching node of that phase, thus eliminating the need for level shifting through the DC blocking capacitor, and therefore the DC blocking capacitor can be omitted. Simultaneously, after omitting the DC blocking capacitor, the freewheeling and charging path of the Nth phase inductor current can be provided by the switch of the lower bridge arm of the Nth phase, thus eliminating the need for a separate freewheeling switch. This achieves the effect of reducing one series capacitor and one switching device, and further reduces system cost and drive control complexity.

[0044] Figure 3 This is an N-phase circuit diagram of a high-ratio DC-DC converter using an LC series network according to the present invention. In this embodiment, to suppress the peak current caused by the charging and discharging of the DC blocking capacitor, reduce switching stress, and improve high-frequency efficiency, a resonant inductor can be added after the DC blocking capacitor in each switched capacitor unit to form an LC series network. Specifically, in the k-th switched capacitor unit, the DC blocking capacitor and a resonant inductor are connected in series between the midpoint of the bridge arm and the freewheeling node. This resonant inductor can be an independent inductor device, or it can be implemented by inductor leakage inductance, trace parasitic inductance, or a specially designed equivalent inductance.

[0045] By employing the aforementioned LC series network, the rate of change of the charging and discharging current of the DC blocking capacitor is limited, thereby effectively reducing the current conversion rate and peak current during phase switching and commutation. Simultaneously, the resonant inductor and the DC blocking capacitor can form a controlled energy exchange process during switching transients, resulting in a smoother transition between the bridge arm midpoint voltage and the freewheeling node voltage, which helps reduce switching losses. Preferably, the value of the resonant inductor is much smaller than the main inductor in the shunt inductor unit, ensuring that the main energy storage and current ripple are still determined by the main inductor. The resonant inductor is primarily used to buffer or resonantly commutate the charging and discharging process of the DC blocking capacitor, thus achieving higher efficiency without significantly increasing the volume.

[0046] Figure 4 This is a three-phase schematic diagram of a series-parallel high-ratio DC-DC converter according to this embodiment. Using this schematic diagram as an example, the working principle of the series-parallel high-ratio DC-DC converter in this embodiment is introduced: When N=3, three voltage-dividing capacitors are connected in series between the positive and negative terminals of the DC input power supply to form four mid-DC potential nodes. The three voltage-dividing capacitors have the same capacitance, and in steady state, the voltage of each voltage-dividing capacitor approximately evenly shares the input voltage, thereby reducing the withstand voltage requirement of each power switching device. The three switching capacitor units are connected in parallel across the corresponding voltage-dividing capacitors, and their bridge arm midpoints are connected to the freewheeling node of the corresponding shunt inductor unit via the corresponding DC blocking capacitor; the inductor output terminals of the three shunt inductor units are connected in parallel to the load terminal. The DC blocking capacitor is used to block the DC component and realize AC coupling of energy, so that the freewheeling node obtains a pulsating voltage relative to the load terminal to drive the inductor charging and discharging.

[0047] Figure 5This diagram illustrates the switching duty cycle and inductor current waveforms of a series-parallel high-ratio DC-DC converter in Buck mode according to this embodiment. When the circuit operates in Buck mode, energy flows from the high-voltage side to the low-voltage side. Within one switching cycle Ts, the upper arm switch in the three-phase switched capacitor unit is the main control switch, using interleaved drive, with a phase difference of 120° between adjacent phases. At any given time, only one phase is allowed to be in the charging state, while the other two phases are in the discharging freewheeling state; therefore, the conduction pulse width of each phase's upper arm switch does not exceed 120°, and a dead time is set between each complementary switch. Taking the charging range of the first phase from 0° to 120° as an example: In this range, the upper bridge arm switch of the first phase is turned on, and the lower bridge arm switch and freewheeling switch of the first phase are turned off. The freewheeling node potential of the first phase is coupled to the higher medium DC potential node by the DC blocking capacitor, so that the inductor of the first phase obtains a positive voltage difference, the inductor current rises and transfers energy to the load; at the same time, the upper bridge arm switches of the second and third phases are turned off, and their freewheeling switches are turned on. The inductors of the second and third phases are in the discharge freewheeling state, the inductor current decreases and together with the first phase maintains the continuous output current. After the first phase charging interval ends, the first phase upper bridge arm switch turns off and enters a dead zone. Subsequently, the first phase freewheeling switch turns on, clamping the first phase freewheeling node to the output negative terminal to achieve inductor freewheeling. In the 120°~240° interval, the second phase upper bridge arm switch turns on, the second phase inductor enters charging, and the other two phases freewheel and discharge. In the 240°~360° interval, the third phase upper bridge arm switch turns on, the third phase inductor enters charging, and the other two phases freewheel and discharge. The above three intervals cycle repeatedly, thus realizing the three phases taking energy from the high-voltage side and transmitting it to the low-voltage side in turn within one cycle.

[0048] Figure 6This diagram illustrates the switching duty cycle and inductor current waveforms of a series-parallel high-ratio DC-DC converter in Boost mode according to this embodiment. When the circuit operates in Boost mode, energy flows from the low-voltage side to the high-voltage side. Within one switching cycle Ts, the freewheeling switch in the three-phase shunt inductor unit is the main control switch, using interleaved drive, with a phase difference of 120° between adjacent phases. At any given time, only one phase is allowed to be in the charging state, while the other two phases are in the discharging freewheeling state. Taking the charging range of the first phase from 0° to 120° as an example: within this range, the first phase freewheeling switch is turned on, the upper and lower bridge arm switches of the first phase are turned off, the freewheeling node potential of the first phase is grounded, and the low-voltage input causes the inductor current to rise; simultaneously, the freewheeling switches of the second and third phases are turned off, their upper bridge arm switches are turned on, the inductors of the second and third phases are in the discharging freewheeling state, the inductor current decreases, and together with the first phase, they maintain the continuous output current. After the first phase charging interval ends, the first phase freewheeling switch turns off and enters a dead zone. Subsequently, the first phase upper bridge arm switch turns on, and the inductor discharges and freewheels. In the 120°~240° interval, the second phase freewheeling switch turns on, and the second phase inductor enters charging, while the other two phases freewheel and discharge. In the 240°~360° interval, the third phase freewheeling switch turns on, and the third phase inductor enters charging, while the other two phases freewheel and discharge. These three intervals cycle repeatedly, thus enabling the three phases to take energy from the low-voltage side and transmit it to the high-voltage side in turn within one cycle.

[0049] Figure 7 This is a control block diagram of a series-parallel high-ratio DC-DC converter according to this embodiment. The converter control method adopts a dual closed-loop control strategy, including an outer voltage loop and an inner current loop. The inner current loop is configured to be either active or disconnected depending on the load conditions. When the converter operates in Buck mode, it acquires the low-voltage side output voltage and output current, as well as the voltage of each voltage divider capacitor on the high-voltage side, in real time. The acquired output voltage is compared with a given reference voltage, and a current reference signal is generated through a voltage error compensator. The actual acquired output current is compared with the corresponding current reference value, and a duty cycle signal is generated through a current error compensator. This duty cycle signal is input to a PWM modulator, compared with a carrier wave, and outputs a PWM wave. The output PWM wave is used as a trigger signal to drive each switch. When the converter operates in Boost mode, it acquires the high-voltage side output voltage and output current in real time. The acquired output voltage is compared with a given reference voltage, and a current reference signal is generated through a voltage error compensator. The actual acquired output current is compared with the corresponding current reference value, and a duty cycle signal is generated through a current error compensator. This duty cycle signal is input to a PWM modulator, compared with a carrier wave, and outputs a PWM wave. The output PWM wave is used as a trigger signal to drive each switch.

[0050] The controller monitors port voltage and load demand in real time, smoothly switching between Buck and Boost modes. A reasonable dead time is set at the moment of switching action to prevent shoot-through on the same bridge arm. Since the upper transistor in this topology is powered by its corresponding voltage divider capacitor, the drive circuit can operate normally in either mode as long as there is voltage on the high-voltage side or a voltage is established through pre-charging via the body diode, ensuring reliable bidirectional switching.

[0051] Meanwhile, during the initial power-on phase of the converter, the controller can force all power switches to remain off, and use the pre-charging of the voltage divider capacitor unit to slowly charge the voltage divider capacitor to the preset voltage. After the pre-charging is completed, the soft-start process is entered, and the reference voltage or duty cycle is increased by ramping up to gradually build up the inductor current, so as to limit the starting inrush current and ensure the voltage balance of the voltage divider capacitor.

[0052] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0053] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A series-parallel high-ratio DC-DC converter, characterized in that, include: N circuit modules; Each circuit module includes a voltage divider capacitor unit, a switched capacitor unit, and a shunt inductor unit connected in sequence; wherein, N≥2, and N voltage divider capacitor units are connected in series between the positive and negative terminals of the DC input power supply to form N+1 medium DC potential nodes; the output terminals of the N shunt inductor units are connected in parallel and connected to the load terminal; In each of the circuit modules: The voltage divider capacitor unit includes one voltage divider capacitor; The switched capacitor unit includes an upper bridge arm switch, a lower bridge arm switch, and a DC blocking capacitor. The first terminal of the upper bridge arm switch is connected to the positive potential terminal of the voltage dividing capacitor; the second terminal of the upper bridge arm switch is connected to the first terminal of the lower bridge arm switch; and the second terminal of the lower bridge arm switch is connected to the negative potential terminal of the voltage dividing capacitor. The series connection point between the upper and lower bridge arm switches forms the midpoint of the bridge arm. The first terminal of the DC blocking capacitor is connected to the midpoint of the bridge arm. The shunt inductor unit includes a freewheeling switch and an inductor; wherein, the first end of the freewheeling switch is connected to the first end of the inductor to form a freewheeling node, and the freewheeling node is also connected to the second end of the DC blocking capacitor; the second end of the freewheeling switch is used to connect to the output negative terminal, and the second end of the inductor is used to connect to the output positive terminal.

2. The series-parallel high-ratio DC-DC converter according to claim 1, characterized in that, The converter, composed of N circuit modules, has a bidirectional power conversion function; the bidirectional power conversion function includes switching between two modes: Buck and Boost.

3. The series-parallel high-ratio DC-DC converter according to claim 1, characterized in that, Before startup, each voltage divider capacitor unit precharges all voltage divider capacitors. The charging current of all voltage divider capacitors during precharging is equal, and the capacitance of each voltage divider capacitor is the same.

4. A control method for a series-parallel high-ratio DC-DC converter, characterized in that, include: Step 1: In each control cycle, acquire the output voltage and output current; Step 2: Calculate the output voltage deviation between the current sampling time and the previous sampling time. Select the control mode based on the output current, output voltage deviation and system status. Engage the inner current loop under heavy load or rapid dynamic conditions, and allow the inner current loop to be switched out under light load conditions. Set hysteresis and minimum dwell time for the current loop switching to avoid frequent jitter. The control modes include Buck buck mode and Boost boost mode. Step 3: Compare the output voltage with the given reference voltage and generate a current reference signal through the voltage error compensator; compare the actual acquired output current with the corresponding current reference signal and generate a duty cycle signal through the current error compensator. Step 4: Set N phases to be staggered, with a phase difference of 360° / N between adjacent units, so that at the same time, only one of the N inductors is in the charging state, while the other N-1 inductors are in the discharging freewheeling state. Step 5: Input the duty cycle signal and phase difference into the PWM modulator, compare it with the carrier wave, and output a PWM wave. Use the output PWM wave as the trigger signal for the switch to drive each switch. Set a dead time for the complementary switch and add a rate of change limit to suppress peak current and improve transient response.

5. The control method for a series-parallel high-ratio DC-DC converter according to claim 4, characterized in that, The sampling frequency of the output voltage and the output current is synchronized with the PWM carrier to reduce the impact of switching noise on sampling.

6. The control method for a series-parallel high-ratio DC-DC converter according to claim 4, characterized in that, In step 5, the methods for setting the dead zone for the complementary switch include: In the converter, the upper and lower bridge arm switches of the switched capacitor unit are complementary in conduction, and dead time is set between the upper bridge arm switch being turned off and the lower bridge arm switch being turned on, and between the upper bridge arm switch being turned on and the lower bridge arm switch being turned off.

7. The control method for a series-parallel high-ratio DC-DC converter according to claim 4, characterized in that, In step 5, the method of setting a dead zone for the complementary switch also includes: In the converter, the upper arm switch and the freewheeling switch of the switched capacitor unit are complementary in conduction, and a dead time is set between the upper arm switch being turned off and the freewheeling switch being turned on, and between the upper arm switch being turned on and the freewheeling switch being turned off.

8. The control method for a series-parallel high-ratio DC-DC converter according to claim 4, characterized in that, Before starting step 1, the converter is powered on. In the initial stage of powering on the converter, all switching transistors are forced to be in the off state until each voltage divider capacitor is pre-charged. At this time, the duty cycle signal increases linearly from zero on a ramp until the output voltage reaches the set value to limit the start-up inrush current.

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