Oscillator circuit without comparator and reference voltage

Abstract

The invention discloses an oscillator circuit without a comparator and reference voltage, which belongs to the field of integrated circuits and comprises a current-limiting resistor R, integrating capacitors C1 and C2, P-type charging and discharging switch tubes PM1 to PM3, N-type charging and discharging switch tubes NM1 to NM3, digital logic circuits INV1 to INV3, a NOR gate NOR1, a NAND gate NAND1 and a buffer BUF1. According to the invention, the structure is simple, and stable oscillation can be realized only by a small number of basic components; dependence on a comparator or a high-precision reference voltage source in a traditional scheme is abandoned, system power consumption is effectively reduced, and meanwhile the chip area is remarkably reduced. By adjusting resistance and capacitance parameters, the frequency and the duty ratio of the output square wave can be flexibly adjusted, and the wide application prospect is achieved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an oscillator circuit without a comparator or reference voltage. Background Technology

[0002] Oscillators have wide applications in integrated circuits. Oscillators built based on comparators typically rely on a precise reference voltage and a high-gain comparator to achieve periodic switching. However, generating the reference voltage requires a bandgap reference source, which occupies a large chip area and consumes a lot of power; high-gain comparators also introduce significant power consumption. Summary of the Invention

[0003] The purpose of this invention is to provide an oscillator circuit without a comparator and without a reference voltage, so as to solve the problems in the prior art.

[0004] To solve the above-mentioned technical problems, the present invention provides an oscillator circuit without comparator and reference voltage, including inverters INV1 to INV3, NAND gate NAND1, NOR gate NOR1, Schmitt trigger SMIT1, buffer BUF1, PMOS transistors PM1 to PM3, NMOS transistors NM1 to NM3, resistor R, and capacitors C1 and C2.

[0005] The input of inverter INV1 is connected to the output of NOR1; the output of inverter INV1 is connected to the first input of NAND1; the second input of NAND1 is simultaneously connected to the first input of NOR1, the output of Schmitt trigger SMIT1, the gate of NMOS transistor NM2, and the gate of PMOS transistor PM3; the output of NAND1 is connected to the gate of PMOS transistor PM1 and the input of inverter INV2; the output of inverter INV2 is connected to the second input of NOR1.

[0006] The source of PMOS transistor PM1 is simultaneously connected to the power supply V. dd The source of PMOS transistor PM2 is connected to the upper plate of capacitor C1; the drain of PMOS transistor PM1 is connected to both the first terminal of resistor R and the drain of NMOS transistor NM1; the source of NMOS transistor NM1 is connected to the source of NMOS transistor NM3 and the lower plate of capacitor C2 and grounded; the second terminal of resistor R is connected to the input of Schmitt trigger SMIT1, the drain of PMOS transistor PM3, and the drain of NMOS transistor NM2.

[0007] The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM3 and the upper plate of capacitor C2; the source of PMOS transistor PM3 is connected to the lower plate of capacitor C1 and the drain of PMOS transistor PM2; the gates of NMOS transistor NM2 and NMOS transistor PM3 are connected to the output of Schmitt trigger SMIT1; the gates of NMOS transistor NM3 and PM2 are connected to the output of inverter INV3; the output of Schmitt trigger SMIT1 is connected to the output of inverter INV3; the output of inverter INV3 is connected to the input of buffer BUF1; the output of buffer BUF1 serves as the output of the oscillator.

[0008] In one embodiment, when the OUT terminal is at a low level, the gates of PMOS transistors PM1, PM2, and NMOS transistor NM3 are at a high level, while the gates of PMOS transistors PM3, NMOS transistor NM1, and NMOS transistor NM2 are at a low level. At this time, PMOS transistors PM1 and PM2 are off, and PMOS transistor PM3 is on; NMOS transistors NM1 and NMOS transistor NM2 are off, and NMOS transistor NM3 is on. The lower plate of capacitor C1 discharges through the path formed by PMOS transistor PM3, resistor R, and NMOS transistor NM1. At the same time, the lower plate of capacitor C2 is connected to ground potential through NMOS transistor NM3, thus quickly completing the discharge.

[0009] In one embodiment, when the OUT terminal is high, the gates of PMOS transistors PM1, PM2, and NMOS transistor NM3 are low, while the gates of PMOS transistors PM3, NMOS transistors NM1, and NMOS transistor NM2 are high. At this time, PMOS transistors PM1 and PM2 are turned on, and PMOS transistor PM3 is turned off; NMOS transistors NM1 and NMOS transistor NM2 are turned on, and NMOS transistor NM3 is turned off; the upper plate of capacitor C1 is directly connected to the power supply through PMOS transistor PM2, and is quickly charged to the power supply voltage through PMOS transistor PM2; the upper plate of capacitor C2 is charged through the path formed by NMOS transistor NM2, resistor R, and PMOS transistor PM3.

[0010] This invention provides an oscillator circuit without a comparator or reference voltage, which eliminates the reliance on comparators or high-precision reference voltage sources in traditional solutions, effectively reducing system power consumption and significantly reducing chip area. By adjusting the resistor and capacitor parameters, the frequency and duty cycle of the output square wave can be flexibly adjusted, and it has broad application prospects. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of an oscillator circuit structure without a comparator and without a reference voltage provided by the present invention.

[0012] Figure 2This is a waveform diagram of a key node in this invention. Detailed Implementation

[0013] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a more detailed explanation of the comparator-free and reference voltage-free oscillator circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0014] This invention provides an oscillator circuit without a comparator and without a reference voltage, such as... Figure 1 The diagram shows inverters INV1-INV3, NAND gate NAND1, NOR gate NOR1, Schmitt trigger SMIT1, buffer BUF1, PMOS transistors PM1-PM3, NMOS transistors NM1-NM3, resistor R, and capacitors C1 and C2. The input of inverter INV1 is connected to the output of NOR gate NOR1; the output of inverter INV1 is connected to the first input of NAND gate NAND1; the second input of NAND gate NAND1 is simultaneously connected to the first input of NOR gate NOR1, the output of Schmitt trigger SMIT1, the gate of NMOS transistor NM2, and the gate of PMOS transistor PM3; the output of NAND gate NAND1 is connected to the gate of PMOS transistor PM1 and the input of inverter INV2; the output of inverter INV2 is connected to the second input of NOR gate NOR1. The source of PMOS transistor PM1 is simultaneously connected to power supply V. dd The source of PMOS transistor PM2 is connected to the upper plate of capacitor C1. The drain of PMOS transistor PM1 is connected to both the first terminal of resistor R and the drain of NMOS transistor NM1. The source of NMOS transistor NM1 is connected to the source of NMOS transistor NM3, the lower plate of capacitor C2, and grounded. The second terminal of resistor R is connected to the input of Schmitt trigger SMIT1, the drain of PMOS transistor PM3, and the drain of NMOS transistor NM2. The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM3 and the upper plate of capacitor C2. The source of PMOS transistor PM3 is connected to the lower plate of capacitor C1 and the drain of PMOS transistor PM2. The gates of NMOS transistor NM2 and NMOS transistor PM3 are connected to the output of Schmitt trigger SMIT1. The gates of NMOS transistor NM3 and PM2 are connected to the output of inverter INV3. The output of Schmitt trigger SMIT1 is connected to the output of inverter INV3. The output of inverter INV3 is connected to the input of buffer BUF1. The output of buffer BUF1 serves as the output of the oscillator.

[0015] The circuit operates based on the synergistic effect of capacitor charging / discharging and logic gate feedback. Periodic switching signals are generated through the alternating charging and discharging of capacitors C1 and C2. When the OUT terminal is low, the gates of PMOS transistors PM1, PM2, and NMOS transistor NM3 are high, while the gates of PMOS transistors PM3, NMOS transistors NM1, and NMOS transistor NM2 are low. At this time, PMOS transistors PM1 and PM2 are off, and PMOS transistor PM3 is on; NMOS transistors NM1 and NM2 are off, and NMOS transistor NM3 is on. The lower plate of capacitor C1 discharges through the path formed by PMOS transistor PM3, resistor R, and NMOS transistor NM1. Simultaneously, the lower plate of capacitor C2 is connected to ground potential through NMOS transistor NM3, quickly completing its discharge. The discharge current of the lower plate of capacitor C1 is limited by resistor R, and the discharge current is:

[0016]

[0017] Where V C1 This is the voltage across the lower plate of capacitor C1.

[0018] When capacitor C1 discharges to the point where the voltage of the lower plate equals the toggling threshold of Schmitt trigger SMIT1, the potential at the OUT terminal becomes high.

[0019] When the OUT terminal is high, the gates of PMOS transistors PM1, PM2, and NMOS transistor NM3 are low, while the gates of PMOS transistors PM3, NMOS transistors NM1, and NM2 are high. At this time, PMOS transistors PM1 and PM2 are turned on, and PMOS transistor PM3 is turned off; NMOS transistors NM1 and NM2 are turned on, and NMOS transistor NM3 is turned off. The upper plate of capacitor C1 is directly connected to the power supply through PMOS transistor PM2, and is quickly charged to the power supply voltage through PM2. The upper plate of capacitor C2 is charged through a path formed by NMOS transistor NM2, resistor R, and PMOS transistor PM3. The charging current of the upper plate of capacitor C2 is limited by resistor R, and the charging current is:

[0020]

[0021] Where V dd V is the power supply voltage. C2 This is the voltage across the upper plate of capacitor C2. When the voltage across the upper plate of capacitor C2 rises to the toggling threshold of Schmitt trigger SMIT1, the OUT terminal returns to a low level, and the circuit enters the next operating cycle. Through repeated cycles of the above charging and discharging process, the OUT terminal continuously outputs a periodic square wave signal.

[0022] like Figure 2The diagram shows the voltage waveforms at the lower plate of capacitor C1, the upper plate of capacitor C2, the input terminal of Schmitt trigger SMIT1, and the OUT terminal. Figure 2 It can be seen that the period T of the square wave output at the OUT terminal can be divided into the discharge time t of capacitor C1. c1 With the charging time t of capacitor C2 c2 .Right now:

[0023] T = t c1 +t c2

[0024] Wherein, the discharge time t of capacitor C1 c1 The voltage from its lower plate is V dd The voltage drops to the high threshold level V of the Schmitt trigger SMIT1. thH The required time determines whether the following conditions are met:

[0025]

[0026] Similarly, the charging time t of capacitor C2 c2 The voltage on its upper plate rises from 0 to the low threshold level V of the Schmitt trigger SMIT1. thL The required time determines whether the following conditions are met:

[0027]

[0028] The period T of the square wave output at the OUT terminal can be expressed as:

[0029]

[0030] The period T of the output at the OUT terminal is related to the resistor R and capacitors C1 and C2, while the duty cycle is related to the charging and discharging time of capacitors C1 and C2. Therefore, the period of the OUT terminal can be adjusted by adjusting the resistor R and capacitors C1 and C2, and the duty cycle of the output square wave can be adjusted by adjusting the ratio of capacitors C1 and C2.

[0031] The flip-flop, composed of inverters INV1 and INV2, NAND gate NAND1 and NOR gate NOR1, can ensure that PMOS transistor PM1 and NMOS transistor NM1 will not be turned on at the same time, avoiding the generation of shoot-through current and further reducing the static power consumption of the circuit.

[0032] In summary, this invention realizes an oscillator circuit that is independent of comparators and reference voltages. The circuit has a simple structure and low power consumption. By properly configuring the parameters of resistor R and capacitors C1 and C2, the frequency and duty cycle of the output square wave can be adjusted.

[0033] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An oscillator circuit without a comparator and without a reference voltage, characterized in that, Including inverters INV1 to INV3, NAND gate NAND1, NOR gate NOR1, Schmitt trigger SMIT1, buffer BUF1, PMOS transistors PM1 to PM3, NMOS transistors NM1 to NM3, resistor R, and capacitors C1 and C2; The input of inverter INV1 is connected to the output of NOR1; the output of inverter INV1 is connected to the first input of NAND1; the second input of NAND1 is simultaneously connected to the first input of NOR1, the output of Schmitt trigger SMIT1, the gate of NMOS transistor NM2, and the gate of PMOS transistor PM3; the output of NAND1 is connected to the gate of PMOS transistor PM1 and the input of inverter INV2; the output of inverter INV2 is connected to the second input of NOR1. The source of PMOS transistor PM1 is simultaneously connected to the power supply V. dd The source of PMOS transistor PM2 is connected to the upper plate of capacitor C1; the drain of PMOS transistor PM1 is connected to both the first terminal of resistor R and the drain of NMOS transistor NM1; the source of NMOS transistor NM1 is connected to the source of NMOS transistor NM3 and the lower plate of capacitor C2 and grounded; the second terminal of resistor R is connected to the input of Schmitt trigger SMIT1, the drain of PMOS transistor PM3, and the drain of NMOS transistor NM2. The source of NMOS transistor NM2 is connected to the drain of NMOS transistor NM3 and the upper plate of capacitor C2; the source of PMOS transistor PM3 is connected to the lower plate of capacitor C1 and the drain of PMOS transistor PM2; the gates of NMOS transistor NM2 and NMOS transistor PM3 are connected to the output of Schmitt trigger SMIT1; the gates of NMOS transistor NM3 and PM2 are connected to the output of inverter INV3; the output of Schmitt trigger SMIT1 is connected to the output of inverter INV3; the output of inverter INV3 is connected to the input of buffer BUF1; the output of buffer BUF1 serves as the output of the oscillator.

2. The oscillator circuit without comparator and reference voltage as described in claim 1, characterized in that, When the OUT terminal is at a low level, the gates of PMOS transistors PM1, PM2, and NMOS transistor NM3 are at a high level, while the gates of PMOS transistors PM3, NMOS transistor NM1, and NMOS transistor NM2 are at a low level. At this time, PMOS transistors PM1 and PM2 are cut off, and PMOS transistor PM3 is turned on; NMOS transistors NM1 and NMOS transistor NM2 are cut off, and NMOS transistor NM3 is turned on. The lower plate of capacitor C1 discharges through the path formed by PMOS transistor PM3, resistor R, and NMOS transistor NM1. At the same time, the lower plate of capacitor C2 is connected to ground potential through NMOS transistor NM3, and discharges quickly.

3. The oscillator circuit without comparator and reference voltage as described in claim 1, characterized in that, When the OUT terminal is high, the gates of PMOS transistors PM1, PM2, and NMOS transistor NM3 are low, while the gates of PMOS transistors PM3, NMOS transistors NM1, and NMOS transistor NM2 are high. At this time, PMOS transistors PM1 and PM2 are turned on, and PMOS transistor PM3 is turned off; NMOS transistors NM1 and NMOS transistor NM2 are turned on, and NMOS transistor NM3 is turned off. The upper plate of capacitor C1 is directly connected to the power supply through PMOS transistor PM2, and is quickly charged to the power supply voltage through PMOS transistor PM2. The upper plate of capacitor C2 is charged through the path formed by NMOS transistor NM2, resistor R, and PMOS transistor PM3.

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