Pulse width modulation method for simulating D-type audio power amplifier with zero input working mode
By employing a pulse width modulation method with real-time detection and frequency adjustment, the high-frequency interference and harmonic distortion problems of analog audio power amplifiers under zero-input conditions are solved, achieving stable waveforms and low power consumption. This method is applicable to various input/output architectures, reducing filter costs and space requirements.
Patent Information
- Application Number
- CN202511782131.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-29
- Publication Date
- 2026-04-21
AI Technical Summary
Analog audio input amplifiers are susceptible to environmental interference in the zero-input state, generating high-frequency signals that cause the output filter to malfunction or consume extra power. Furthermore, they suffer from severe harmonic distortion during small-amplitude audio output, which affects audio quality.
The audio signal is detected in real time by the zero-input detection module, the sawtooth wave generator is controlled to reduce the operating frequency, the comparator output signal and selector selection are adjusted, and the duty cycle is optimized by the adjustment module to generate stable OUTP and OUTN pulse waveforms, thereby reducing harmonic distortion and power consumption.
It achieves waveform stabilization under zero input conditions, reduces high-frequency interference and harmonic distortion, improves audio fidelity and optimizes power consumption, is suitable for various input/output architectures, and reduces filter cost and space occupation.
Smart Images
Figure CN121907209A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog audio processing technology, specifically relating to a pulse width modulation method for an analog Class D audio power amplifier with zero-input operating mode. Background Technology
[0002] In the field of Class D audio amplifier technology, stable PWM pulse waveforms with zero input are relatively easy to achieve with good results for digital audio input amplifiers. However, for analog audio input amplifiers, two key issues exist in practical applications: 1. High-frequency interference problem under zero input state: When the analog audio input is zero, due to environmental factors (such as electromagnetic interference, temperature fluctuation) and circuit non-ideality (such as device noise, circuit offset), the power output terminal OUTP may occasionally generate a high-frequency signal with a frequency exceeding the audio frequency range (20~20kHz), and the frequency characteristics of the high-frequency signal have random variations, which can easily lead to abnormal operation of the output filter or generate additional power consumption. 2. Harmonic distortion problem during small-amplitude audio output: When outputting small-amplitude audio signals, existing pulse width modulation methods will produce slightly larger harmonic distortion, which will affect the audio output quality and cannot meet the needs of high-fidelity audio application scenarios. Summary of the Invention
[0003] The main objective of this invention is to provide a pulse width modulation method for analog Class D audio power amplifiers with zero-input operating mode, enabling the system to output stable OUTP and OUTN pulse waveforms at a working frequency under zero-input conditions for a continuous period of time or when the audio output signal changes through 0V, and reducing harmonic distortion under small-amplitude audio output conditions.
[0004] To achieve the above objectives, this invention provides a pulse width modulation method for simulating a Class D audio power amplifier with a zero-input operating mode, comprising the following steps: Step S1: The zero-input detection module U1 detects the audio input signal status in real time. The zero-input detection module U1 is set with a zero-input amplitude detection threshold, which is used to control the harmonic distortion value under small-amplitude audio output conditions. When the zero-input detection module U1 detects that the audio input signal is in a zero-input state, it outputs a real-time zero-input flag signal ZDET. Step S2: The zero-input flag signal ZDET controls the sawtooth wave generator U3 to reduce the sawtooth wave output operating frequency from a high frequency to a specific value RAMP of a low frequency and transmit it to comparators U6 and U7 respectively, so that the PWM_P signal output by comparator U6 and the PWM_N signal output by comparator U7 are at the low frequency value of the sawtooth wave. Meanwhile, the zero-input flag signal ZDET controls selector U9 and selector U10 respectively, stopping the selection of the PWMO_P signal and PWMO_N signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selecting the PWM_P signal and PWM_N signal as input and transmitting them to the power output terminal to generate OUTP and OUTN pulse waveforms respectively, thereby realizing the low-frequency operation of OUTP and OUTN under zero-input conditions; Step S3: The zero-input flag signal ZDET is also input to the configuration adjustment module U2 to appropriately adjust the corresponding loop bandwidth parameter value and adjust the final OUTP and OUTN pulse width duty cycle values under zero input.
[0005] As a further preferred technical solution to the above technical solution, step S2 is specifically implemented as follows: The output of comparator U6 outputs a PWM_P signal to the first input of selector U9, and the output of comparator U6 also outputs a PWMO_P signal to the second input of selector U9 through the inductor-saving PWM conversion circuit U8. The zero-input flag signal ZDET controls selector U9 to stop selecting the PWMO_P signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selects the PWM_P signal directly output by comparator U6 as input, and outputs an OUT_P signal to the driver and power transistor U11, thereby outputting the OUTP pulse waveform. The output of comparator U7 outputs a PWM_N signal to the first input of selector U10. The output of comparator U7 also outputs a PWM_O_N signal to the second input of selector U10 through the inductor-saving PWM conversion circuit U8. The zero-input flag signal ZDET controls selector U10 to stop selecting the PWM_O_N signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selects the PWM_N signal directly output by comparator U7 as input, and outputs an OUT_N signal to the driver and power transistor U12, thereby outputting the OUTN pulse waveform.
[0006] As a further preferred technical solution to the above technical solution, step S3 is specifically implemented as follows: The adjustment module U2 includes an integrator, a bandwidth configuration circuit, and an output common-mode level adjustment circuit. The zero-input flag signal ZDET is input to the integrator and the bandwidth configuration circuit to adjust the corresponding loop bandwidth parameter value appropriately. The common-mode level of the integrator is adjusted by the common-mode level adjustment circuit, which adjusts the final OUTP and OUTN pulse width duty cycle values under zero input. When the common-mode level of the integrator output is equal to the common-mode level of the RAMP sawtooth wave, the duty cycle of the PWM_P and PWM_N signals under zero input is equal to 50%. Otherwise, when they are not equal, the duty cycle is allocated according to the system architecture.
[0007] As a further preferred technical solution to the above technical solution, the OUTP pulse waveform is input to the configuration adjustment module U2 through the feedback network U4, and the OUTN pulse waveform is input to the configuration adjustment module U2 through the feedback network U5.
[0008] As a further preferred technical solution to the above technical solution, the adjustment module U2 is connected to the input terminal of comparator U6 and the input terminal of comparator U7 respectively.
[0009] The beneficial effects of this invention are as follows: 1. Zero-input waveform stabilization: By fixing the low-frequency operating frequency, the problem of OUTP occasionally generating random high-frequency signals when there is zero input is completely solved, ensuring the stable operation of the output filter; 2. Harmonic distortion reduction: By optimizing the zero-input detection threshold and duty cycle parameters, harmonic distortion during small-amplitude audio output is effectively suppressed, improving audio fidelity; 3. Power consumption optimization: The power loss of the output filter at zero input can be reduced by adjusting the duty cycle, thereby improving system energy efficiency; 4. Strong compatibility: It is compatible with a variety of input / output architectures, has a wide range of applications, and can meet the design requirements of different analog Class D audio amplifiers.
[0010] 5. Eliminating the LC filter or ferrite bead filter at the OUTP end results in significant cost savings for inductors / ferrite beads in two-channel and multi-channel systems, especially suitable for medium to high power applications; furthermore, reducing the board space occupied by a filter facilitates the miniaturization of audio equipment and improves product integration. Attached Figure Description
[0011] Figure 1 This is a schematic diagram of the PWM modulation waveform under zero input conditions of the present invention (the figure shows the PWM modulation waveform diagrams when the audio input is not equal to zero and when it is equal to zero). Figure 2 This is a schematic diagram of the PWM modulation structure of the analog Class D audio power amplifier with zero-input detection of the present invention. Detailed Implementation
[0012] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.
[0013] In a preferred embodiment of the present invention, those skilled in the art should note that the audio input signals and the like involved in the present invention can be considered as prior art.
[0014] Preferred embodiment.
[0015] like Figure 1-2 As shown, this invention discloses a pulse width modulation method for simulating a Class D audio power amplifier with zero-input operating mode, comprising the following steps: Step S1: The zero-input detection module U1 detects the audio input signal (INN / INP) status in real time. The zero-input detection module U1 is set with a zero-input amplitude detection threshold, which is used to control the harmonic distortion value under small-amplitude audio output conditions. When the zero-input detection module U1 detects that the audio input signal is in a (brief or long) zero-input state or the change of the audio output signal passes through 0V, it outputs a real-time zero-input flag signal ZDET. Step S2: The zero-input flag signal ZDET controls the sawtooth wave generator U3 to reduce the sawtooth wave output operating frequency from a high frequency (e.g., 500k~3MHz) to a specific value RAMP at a low frequency (20~200kHz) and transmits it to comparators U6 and U7 respectively, so that the PWM_P signal output by comparator U6 and the PWM_N signal output by comparator U7 are at the low frequency value of the sawtooth wave. Meanwhile, the zero-input flag signal ZDET controls selector U9 and selector U10 respectively, stopping the selection of the PWMO_P signal and PWMO_N signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selecting the PWM_P signal and PWM_N signal as input and transmitting them to the power output terminal to generate OUTP and OUTN pulse waveforms respectively, thereby realizing the low-frequency operation of OUTP and OUTN under zero-input conditions; Step S3: The zero-input flag signal ZDET is also input to the configuration adjustment module U2 to appropriately adjust the corresponding loop bandwidth parameter value and adjust the final OUTP and OUTN pulse width duty cycle values under zero input.
[0016] Specifically, step S2 is implemented as follows: The output of comparator U6 outputs a PWM_P signal to the first input of selector U9, and the output of comparator U6 also outputs a PWMO_P signal to the second input of selector U9 through the inductor-saving PWM conversion circuit U8. The zero-input flag signal ZDET controls selector U9 to stop selecting the PWMO_P signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selects the PWM_P signal directly output by comparator U6 as input, and outputs an OUT_P signal to the driver and power transistor U11, thereby outputting the OUTP pulse waveform. The output of comparator U7 outputs a PWM_N signal to the first input of selector U10. The output of comparator U7 also outputs a PWM_O_N signal to the second input of selector U10 through the inductor-saving PWM conversion circuit U8. The zero-input flag signal ZDET controls selector U10 to stop selecting the PWM_O_N signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selects the PWM_N signal directly output by comparator U7 as input, and outputs an OUT_N signal to the driver and power transistor U12, thereby outputting the OUTN pulse waveform.
[0017] More specifically, step S3 is implemented as follows: The adjustment module U2 includes an integrator, a bandwidth configuration circuit, and an output common-mode level adjustment circuit. The zero-input flag signal ZDET is input to the integrator and the bandwidth configuration circuit to appropriately adjust the corresponding loop bandwidth parameter value (so that the subsequent comparator can operate within a suitable range, thereby matching the system loop parameters at low frequencies). The common-mode level of the integrator output is adjusted by the common-mode level adjustment circuit, which adjusts the final OUTP and OUTN pulse width duty cycle values under zero input. When the common-mode level of the integrator output is equal to the RAMP sawtooth wave common-mode level, the duty cycle of the PWM_P and PWM_N signals under zero input is 50%. Conversely, when they are not equal, the duty cycle is allocated according to the system architecture (it can be greater than 50% or less than 50%). Adjusting and decreasing this duty cycle can reduce the power loss on the output filter under zero input, but if the duty cycle value is too small, it may increase harmonic distortion under small-amplitude output conditions. Therefore, a trade-off can be made between these two parameters by adjusting the duty cycle value.
[0018] Furthermore, the OUTP pulse waveform is input to the configuration adjustment module U2 through the feedback network U4, and the OUTN pulse waveform is input to the configuration adjustment module U2 through the feedback network U5.
[0019] Furthermore, the adjustment module U2 is connected to the input terminals of comparator U6 and comparator U7, respectively.
[0020] For the present invention: Based on the OUTP and OUTN characteristics under zero-input conditions, the output LC filter and C filter can function normally.
[0021] Zero-input detection circuit Figure 2 In addition to using differential audio input signals for detection in the implementation case, single-ended audio input can also be used as the detection signal, or digital circuit detection methods can be used to detect PWM_P and PWM_N differential pulse signals to obtain the ZDET detection signal.
[0022] The specific implementation of this invention includes, but is not limited to, the methods described above. In addition to differential audio input, it is also applicable to single-ended audio input and differential output structures; the signal names OUTP and OUTN are interchangeable; the output architecture can be a BTL bridge load or a PBTL parallel bridge load.
[0023] It is worth mentioning that the technical features such as audio input signals involved in this patent application should be regarded as prior art. The specific structure, working principle, and possible control methods and spatial arrangement of these technical features can be adopted using conventional choices in the field, and should not be regarded as the inventive point of this patent. This patent will not be further elaborated in detail.
[0024] For those skilled in the art, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.
Claims
1. A pulse width modulation method for simulating a Class D audio power amplifier with zero-input operating mode, characterized in that, Includes the following steps: Step S1: The audio input signal status is detected in real time by the zero-input detection module U1. The zero-input detection module U1 is set with a zero-input amplitude detection threshold, and this threshold is used to control the harmonic distortion value under small-amplitude audio output conditions. When the zero-input detection module U1 detects that the audio input signal is in a zero-input state, it outputs a real-time zero-input flag signal ZDET; Step S2: The zero-input flag signal ZDET controls the sawtooth wave generator U3 to reduce the sawtooth wave output operating frequency from a high frequency to a specific value RAMP of a low frequency and transmit it to comparators U6 and U7 respectively, so that the PWM_P signal output by comparator U6 and the PWM_N signal output by comparator U7 are at the low frequency value of the sawtooth wave. Meanwhile, the zero-input flag signal ZDET controls selector U9 and selector U10 respectively, stopping the selection of the PWMO_P signal and PWMO_N signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selecting the PWM_P signal and PWM_N signal as input and transmitting them to the power output terminal to generate OUTP and OUTN pulse waveforms respectively, thereby realizing the low-frequency operation of OUTP and OUTN under zero-input conditions; Step S3: The zero-input flag signal ZDET is also input to the configuration adjustment module U2 to appropriately adjust the corresponding loop bandwidth parameter value and adjust the final OUTP and OUTN pulse width duty cycle values under zero input.
2. The pulse width modulation method for simulating a Class D audio power amplifier with zero-input operating mode according to claim 1, characterized in that, For step S2, the specific implementation is as follows: The output of comparator U6 outputs a PWM_P signal to the first input of selector U9, and the output of comparator U6 also outputs a PWMO_P signal to the second input of selector U9 through the inductor-saving PWM conversion circuit U8. The zero-input flag signal ZDET controls selector U9 to stop selecting the PWMO_P signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selects the PWM_P signal directly output by comparator U6 as input, and outputs an OUT_P signal to the driver and power transistor U11, thereby outputting the OUTP pulse waveform. The output of comparator U7 outputs a PWM_N signal to the first input of selector U10. The output of comparator U7 also outputs a PWM_O_N signal to the second input of selector U10 through the inductor-saving PWM conversion circuit U8. The zero-input flag signal ZDET controls selector U10 to stop selecting the PWM_O_N signal output by the inductor-saving PWM conversion circuit U8 as input, and instead selects the PWM_N signal directly output by comparator U7 as input, and outputs an OUT_N signal to the driver and power transistor U12, thereby outputting the OUTN pulse waveform.
3. The pulse width modulation method for simulating a Class D audio power amplifier with zero-input operating mode according to claim 2, characterized in that, For step S3, the specific implementation is as follows: The adjustment module U2 includes an integrator, a bandwidth configuration circuit, and an output common-mode level adjustment circuit. The zero-input flag signal ZDET is input to the integrator and the bandwidth configuration circuit to adjust the corresponding loop bandwidth parameter value appropriately. The common-mode level of the integrator is adjusted by the common-mode level adjustment circuit, which adjusts the final OUTP and OUTN pulse width duty cycle values under zero input. When the common-mode level of the integrator output is equal to the common-mode level of the RAMP sawtooth wave, the duty cycle of the PWM_P and PWM_N signals under zero input is equal to 50%. Otherwise, when they are not equal, the duty cycle is allocated according to the system architecture.
4. The pulse width modulation method for simulating a Class D audio power amplifier with zero-input operating mode according to claim 3, characterized in that, The OUTP pulse waveform is input to the configuration adjustment module U2 through the feedback network U4, and the OUTN pulse waveform is input to the configuration adjustment module U2 through the feedback network U5.
5. The pulse width modulation method for simulating a Class D audio power amplifier with zero-input operating mode according to claim 4, characterized in that, The adjustment module U2 is connected to the input terminals of comparator U6 and comparator U7, respectively.