Circuit, cell region and method of manufacturing the same

Abstract

An embodiment of the present invention provides a circuit comprising: a first inverter and a second inverter configured to receive a first pin signal and a second pin signal, respectively, and to generate inverts of the first pin signal and the second pin signal, the first pin signal and the second pin signal are respectively a first input signal and a second input signal of the circuit; and a tri-state inversion sub-circuit including a first data transistor, a second data transistor, and a sleep transistor, where each control terminal of the first data transistor and the second data transistor is coupled to a first node having the second pin signal inversion, a control terminal of the sleep transistor is coupled to a second node having a first pin signal inversion, and the first data transistor, the second data transistor, and the sleep transistor are coupled in series between a third node having a first reference voltage and a fourth node having a non-reference voltage (NRV) signal. The embodiment of the invention also provides a cell region and a manufacturing method thereof.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of electronic circuits, and more specifically, to circuits, unit regions and methods of manufacturing thereof. Background Technology

[0002] The semiconductor integrated circuit (IC) industry produces a wide variety of analog and digital devices to solve problems in many different fields. Advances in semiconductor process technology nodes have gradually reduced component size and reduced spacing, leading to a gradual increase in transistor density. ICs are becoming smaller. Summary of the Invention

[0003] An embodiment of the present invention provides a circuit comprising: a first inverter and a second inverter, respectively configured to receive a first pin signal and a second pin signal and generate inverted versions of the first pin signal and the second pin signal, wherein the first pin signal and the second pin signal are respectively a first input signal and a second input signal of the circuit; and a tri-state inverting sub-circuit, comprising a first data transistor, a second data transistor and a sleep transistor, wherein each control terminal of the first data transistor and the second data transistor is coupled to a first node having the inverted second pin signal, the control terminal of the sleep transistor is coupled to a second node having the inverted first pin signal, and the first data transistor, the second data transistor and the sleep transistor are series coupled between a third node having a first reference voltage and a fourth node having a non-reference voltage (NRV) signal.

[0004] Another embodiment of the present invention provides a cell region of a semiconductor device, the cell region comprising: an active region (AR) extending in a first direction and including a first active region and a second active region of a first type, and a third active region of a different second type; a gate segment extending in a second direction perpendicular to the first direction and including: a first gate segment above the second active region and the third active region, configured to receive a first pin signal, and a second gate segment above the first active region, configured to receive an inverted second pin signal, and collinear with the first gate segment; and a first source / drain. A source / drain (S / D) region, located in the second active region and the third active region and adjacent to the second side of the first gate segment, wherein the first source / drain (S / D) region is coupled together and configured to provide an inverted signal for the first pin; a second source / drain region, located in the second active region and the third active region and adjacent to the first side of the first gate segment, wherein the second source / drain region is configured to receive different first reference voltages and second reference voltages; and a first source / drain region in the first active region, adjacent to the second gate segment and configured to receive a non-reference voltage (NRV) signal.

[0005] Another embodiment of the present invention provides a method for manufacturing a cell region, the method comprising: forming an active region extending in a first direction, the active region comprising: a first active region of a first type and a second active region, and a third active region of a different second type; doping sub-regions of the active region to form source / drain (S / D) regions, and comprising: aligning first source / drain regions of the source / drain regions with each other relative to the first direction, aligning second source / drain regions of the source / drain regions with each other, and corresponding portions of the active regions representing channel regions between adjacent first source / drain regions and second source / drain regions; forming a gate segment extending in a second direction perpendicular to the first direction, the gate segment comprising: a first gate segment above corresponding portions of the channel regions of each of the second and third active regions, and a second gate segment above corresponding portions of the channel regions of the first active region. The first source / drain region is partially above and collinear with the first gate segment; and selectively couples one or more of the source / drain regions or one or more of the gate segments, including: the first gate segment receiving a first pin signal, the second gate segment receiving an inverted second pin signal, the first source / drain region being in the second active region and the third active region and adjacent to a second side of the first gate segment, the first source / drain region providing an inverted first pin signal, the first source / drain region in the third active region and adjacent to a second side of the second gate segment receiving an inverted first pin signal; the second source / drain region in the second active region and the third active region and adjacent to a first side of the first gate segment correspondingly receiving different first reference voltages and second reference voltages; and the first source / drain region in the first active region and adjacent to a second side of the second gate segment receiving a non-reference voltage (NRV) signal. Attached Figure Description

[0006] In the accompanying drawings, one or more embodiments are shown by way of example and not limitation, wherein elements designated by the same reference numerals denote the same elements throughout the drawings. Unless otherwise stated, the drawings are not drawn to scale.

[0007] Figure 1 These are block diagrams based on some embodiments.

[0008] Figure 2A and Figure 2C These are corresponding circuit diagrams based on some embodiments.

[0009] Figure 2B and Figure 2D These are layout diagrams based on some embodiments.

[0010] Figures 3A to 3BThese are cross-sectional views based on some embodiments.

[0011] Figures 4A to 4B These are corresponding circuit diagrams based on some embodiments.

[0012] Figures 4C to 4E These are block diagrams based on some embodiments.

[0013] Figure 5A , Figure 5C , Figure 5E and Figure 5G These are corresponding circuit diagrams based on some embodiments.

[0014] Figure 5B , Figure 5D , Figure 5F and Figure 5H These are layout diagrams based on some embodiments.

[0015] Figure 6 and Figure 7 This is a flowchart of a corresponding method according to some embodiments.

[0016] Figure 8 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system and its related IC manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure discloses numerous different embodiments or examples for implementing various components of the subject matter. Examples of components, materials, values, steps, operations, arrangements, etc., are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are considered. For example, in the following description, the formation of a first component on or above a second component includes embodiments in which the first and second components form direct contact, and further includes embodiments in which an additional component is formed between the first and second components, such that the first and second components are in indirect contact. Furthermore, reference numerals and / or letters are repeated in various examples in this disclosure. This repetition is for the purpose of brevity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, spatially relative terms, such as “below,” “under,” “lower,” “above,” “upper,” etc., are used herein to facilitate the description of the relationship between one element or component and another, as illustrated in the accompanying drawings. Spatially relative terms are intended to cover different orientations of devices in use or operation, in addition to those depicted in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein are interpreted accordingly. According to some embodiments, the term standard cell structure refers to a standardized building block contained in a library of various standard cell structures. According to some embodiments, various standard cell structures are selected from their library and used as components in layout diagrams representing circuits.

[0020] According to some embodiments, the cell region (of the device) includes: a first inverter and a second inverter configured to receive a first pin signal and a second pin signal respectively and generate inverted versions of the first pin signal and the second pin signal, which are respectively the first input signal and the second input signal of the circuit; and a tri-state inverting sub-circuit including three transistors, namely a first data transistor, a second data transistor, and a sleep transistor. Each control terminal of the first data transistor and the second data transistor is coupled to a first node having an inverted second pin signal. The control terminal of the sleep transistor is coupled to a second node having an inverted first pin signal. The first data transistor, the second data transistor, and the sleep transistor are coupled in series between a third node having a first reference voltage and a fourth node having a non-reference voltage (NRV) signal. According to some embodiments, the NRV signal is the inverted version of the first pin signal.

[0021] Consider another method for generating a three-state inverter, which is the counterpart of a three-transistor (3T) three-state (3S) inverting sub-circuit (3T3S-inverter). This corresponding three-state inverter has four transistors instead of three, and is referred to herein as the first corresponding 4T3S-inverter. The first corresponding portion of the 4T3S-inverter includes three transistors, which are the counterparts of the first data transistor, the second data transistor, and the sleep transistor, and additionally includes a fourth transistor. In other methods, the fourth transistor (i) is coupled between the corresponding first transistor and the first reference voltage, or (ii) is coupled between the corresponding third transistor and the second reference voltage. The control terminals, i.e., the gate terminals, of the corresponding first data transistor and the corresponding second data transistor are configured to receive the corresponding inverted signal of the corresponding second pin. The control terminal, i.e., the gate terminal, of the corresponding sleep transistor is configured to receive the corresponding inverted signal of the corresponding first pin. In other methods, the control terminal, i.e., the gate terminal, of the fourth transistor is configured to receive the counterpart of pin signal A1. Due to the gate capacitance effect caused by the pin signal relative to the internal signal, the fourth transistor in other methods experiences a relatively larger gate capacitance than the corresponding first to third transistors. Therefore, the switching speed of the fourth transistor in other methods is relatively slower than that of the corresponding first to third transistors, which slows down the operating speed of the first 4T3S inverter in other methods. In contrast, the gates of the transistors in a 3T3S inverter are not coupled to the pin signal. Therefore, by avoiding transistors with gates coupled to the pin signal, for example by excluding the fourth transistor in other methods, the transistors in the 3T3S inverter experience relatively lower gate capacitance, which increases the operating speed of the 3T3S inverter compared to the operating speed of the first 4T3S inverter in other methods.

[0022] Figure 1 This is a block diagram of a cell region 102 of a device 100 according to some embodiments.

[0023] Device 100 is an example of an integrated circuit (IC). According to some embodiments, device 100 is referred to as a semiconductor device. Device 100 includes a macro region 101. Macro region 101 includes a functional unit region 102. Functional unit region 102 includes a tri-state inverting circuit (see, for example, Figures 2A to 2D This is coupled between a reference voltage and a non-reference voltage signal. According to some embodiments, functional unit region 102 includes one or more active devices, passive devices, etc. Examples of active devices or active elements include, but are not limited to, transistors, diodes, etc. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, etc.

[0024] According to some embodiments, macro region 101 comprises one or more instances of functional unit region 102 and / or one or more other functional unit regions. In such embodiments, macro region 101 is configured to provide / perform a given computational function, which comprises simpler functions correspondingly provided by the instances of functional unit region 102 and / or the one or more other functional unit regions. According to some embodiments, one or more instances of functional unit region 102 and / or one or more other functional unit regions represent interconnected building blocks that constitute macro region 101.

[0025] According to some embodiments, macro region 101 is understood in a context analogous to an architectural hierarchy of modular programming, where subroutines / procedures are called by a main program (or other subroutines) to perform a given computational function. In this context, device 100 uses macro region 101 to perform one or more given functions. Therefore, in this context and architectural hierarchy, device 100 is analogous to a main program, while macro region 101 is analogous to a subroutine / procedure. According to some embodiments, macro region 101 is a soft macro. According to some embodiments, macro region 101 is a hard macro. According to some embodiments, macro region 101 is a soft macro described digitally in register-transfer-level (RTL) code. According to some embodiments, macro region 101 has not yet been synthesized, placed, and routed, allowing the soft macro to be synthesized, placed, and routed for various process technology nodes. According to some embodiments, macro region 101 is a hard macro, described digitally in a binary file format (e.g., Graphical Database System II (GDSII) stream format), wherein the binary file format represents the planar geometry, text labels, other information, etc., of one or more layouts of macro region 101 in a hierarchical manner. According to some embodiments, the binary file format is referred to as a non-text file format. According to some embodiments, synthesis, placement, and routing have been performed on macro region 101, making the hard macro specific to a particular process technology node.

[0026] According to some embodiments, examples of functions provided by a macro region (e.g., macro region 101) include memory, power grid, clock tree, adder, phase-locked loop (PLL), delay-locked loop (DLL), flip-flop, shift register, analog-to-digital converter (ADC), digital-to-analog converter (DAC), interface, high-level Boolean logic, etc. Examples of memory include static random access memory (SRAM), dynamic RAM (DRAM), resistive RAM, magnetoresistive RAM (MRAM), read-only memory (ROM), etc. Examples of flip-flops are scan-insertion type D flip-flops (SDFQ), etc. According to some embodiments, examples of functions provided by a functional unit region (e.g., functional unit region 102) include inverter, buffer, latch, multiplexer (MUX), driver, latch, delay, half adder, full adder, compressor, low-level Boolean logic, etc. Examples of low-level Boolean logic include AND, OR, NAND, NOR, XOR, inverted, AND-OR-inverted (AOI) (see, e.g., Figure 5A ), or opposite phase (OAI), etc.

[0027] Functional unit region 102 includes corresponding segments in one or more metallization layers (see, for example, Figures 3A to 3B The accompanying drawings of this disclosure assume a Cartesian coordinate system (unless otherwise stated), wherein the first, second, and third directions are, for example, parallel to the X, Y, and Z axes respectively. According to some embodiments, the first to third directions correspond to directions other than the X, Y, and Z axes. According to some embodiments, in even-numbered metallization layers, the major and minor axes of the segments extend respectively along the first and second directions; in such embodiments, in odd-numbered metallization layers, the major and minor axes of the segments extend respectively along the second and first directions. In such embodiments, the boundaries of the functional unit region 102 are described according to the first and second directions.

[0028] According to some embodiments, functional unit region 102 corresponds to a transistor component layer (see, for example, ...). Figures 3A to 3B This layer has circuit components, such as transistors, formed during front-end process (FEOL) fabrication. In functional cell region 102, in the active region (AR) layer (see, for example, Figures 3A to 3B Above and / or below, various metal layers (see, for example, Figures 3A to 3B ) and the corresponding interconnect layer (see, for example, Figures 3A to 3B They are staggered on and / or under an insulating layer during back-end process (BEOL) fabrication. This BEOL fabrication provides power networks and / or wiring for the circuitry of device 100, including macro regions 101 and functional unit regions 102.

[0029] Figure 2A This is a circuit diagram of an XOR logic (XOR) circuit 218A according to some embodiments.

[0030] XOR circuit 218A is a two-input XOR circuit. XOR circuit 218A consists of field-effect transistors (FETs) and is an example of a complementary metal-oxide-semiconductor (CMOS) architecture. The FETs include N-type metal-oxide-semiconductor (NMOS) FETs (NFETs) and P-type metal-oxide-semiconductor (PMOS) FETs (PFETs). XOR circuit 218A includes PFETs P11 to P16 and NFETs N11 to N14 and N16. Figure 2A In the middle, boxes I2B, I1B, FP1, FP2, FP3, and Zout overlap with the corresponding portions of P11 to P16, N11 to N14, and N16; such boxes help to indicate Figure 2A FET in Figure 2B The correspondence between FETs in the circuit. The XOR circuit 218A includes: a latch 224(1) coupled between inverter 222(1) and inverter 222(3); and inverter 222(2).

[0031] Inverter 222(1) includes P11 and N11, which are coupled in series between node 226(1) having a first reference voltage (e.g., VDD) and node 226(2) having a second reference voltage (e.g., VSS). Inverter 222(1) is configured to receive pin signal A2 and generate signal a2b at node nd11, where signal a2b is the inverse of pin signal A2 and is an internal signal relative to XOR circuit 218A. According to some embodiments, typically, pin signals are generated outside the circuit and represent the circuit's input; therefore, pin signals are also coupled to something outside the circuit. In such embodiments, pin signals contrast with internal signals, which are generated inside the circuit and are not coupled to anything outside the circuit. In such embodiments, pin signals also contrast with the circuit's output signal, i.e., a signal generated inside the circuit but coupled to something outside the circuit. Therefore, pin signal A2 is the input to XOR circuit 218A.

[0032] Inverter 222(2) includes P12 and N12, which are coupled in series between VDD and VSS. Inverter 222(2) is configured to receive pin signal A1 and generate signal a1b at node nd12, wherein signal a1b is the inverse of pin signal A1 and signal a1b is an internal signal relative to XOR circuit 218A.

[0033] exist Figure 2AIn the inverter 222(3), there are P16 and N16, which are coupled in series between VDD and VSS. The inverter 222(3) is configured to receive the internal signal IS1 at node nd13 and generate signal Z, where signal Z is the inverse of signal IS1 and represents the output of XOR circuit 218A.

[0034] Latch 224(1) is coupled between nodes nd11 and nd13. Latch 224(1) includes a tri-state inverter 204A and a transmission gate 230(1), which are coupled in parallel between nodes nd11 and nd13.

[0035] Transmission gate 230(1) is coupled between nodes nd11 and nd13; therefore, nodes nd11 and nd13 respectively represent the input and output of transmission gate 230(1). Transmission gate 230(1) includes P13 and N13, which are coupled in parallel between nodes nd11 and nd13. The control terminal, i.e., the gate terminal, of P13 is configured to receive pin signal A1. The control terminal, i.e., the gate terminal, of N13 is configured to receive signal a1b.

[0036] exist Figure 2A In the example, a three-state (3S) inverting (3S-INV) circuit 204A is coupled between nodes nd11 and nd13; therefore, nodes nd11 and nd13 respectively represent the input and output of the 3S-INV 204A. The 3S-INV circuit 204A comprises three field-effect transistors and is therefore referred to herein as a 3T3S-INV circuit 204A. The 3T3S-INV circuit 204A includes P14, P15, and N14 series coupled between VDD and the non-reference voltage (NRV) signal, where in the example... Figure 2A In this configuration, the NRV signal is the internal signal a1b. P14 is coupled between VDD and node nd14. P15 is coupled between node nd14 and node nd13. N14 is coupled between node nd13 and the NRV signal, i.e., coupled between node nd13 and signal a1b. The drain of N14 is coupled to node nd13. The source of N14 is coupled to the NRV signal, i.e., signal a1b. Each control terminal, i.e., the gate terminal, of P14 and N14 is configured to receive signal a2b. The control terminal, i.e., the gate terminal, of P15 is configured to receive signal a1b.

[0037] Generally, for field-effect transistors (FETs), a larger gate capacitance results in a longer charging time, causing the FET to turn on more slowly, while a smaller gate capacitance results in a shorter charging time, causing the FET to turn on more quickly. A longer turn-on time leads to slower switching, i.e., a slower switching speed. A shorter turn-on time leads to faster switching, i.e., a faster switching speed. Typically, for FETs included in functional circuitry, the gate capacitance varies depending on the type of signal coupled to the gate. Generally, when the gate of an FET is coupled to a pin signal, the gate capacitance experienced by the FET is greater than when the gate is coupled to an internal signal, i.e., a signal coupled to the circuitry within which the FET belongs.

[0038] Consider another method for generating a tri-state inverter, which is a counterpart to the 3T3S-INV 204A. This counterpart tri-state inverter has four field-effect transistors instead of three, and is referred to herein as the second counterpart 4T3S-inverter. The second counterpart 4T3S-inverter includes a first PFET, which is a counterpart to P14; a second PFET, which is a counterpart to P15; a first NFET, which is a counterpart to N14; and a second NFET coupled between the corresponding first NFET and VSS. The control terminal, i.e., the gate terminal, of each of the corresponding first PFET and the corresponding second NFET is configured to receive a counterpart to the internal signal a2b. The control terminal, i.e., the gate terminal, of the corresponding second PFET is configured to receive a counterpart to the internal signal a1b. The control terminal, i.e., the gate terminal, of the corresponding second PFET is configured to receive a counterpart to the pin signal A1.

[0039] Due to the influence of pin signals on gate capacitance relative to internal signals, the gate capacitance experienced by the second NFET in other methods is relatively greater than that experienced by the corresponding first PFET, the corresponding second PFET, and the corresponding first NFET. Therefore, the switching speed of the second NFET in other methods is relatively slower, at least compared to the switching speed of the corresponding first NFET, which slows down the operating speed of the first 4T3S-inverter in other methods. In contrast, each gate terminal of P14 to P15 and N14 of the 3T3S-INV circuit 204A is coupled to the internal signal, so that the gate terminals of the field-effect transistors in the 3T3S-INV circuit 204A are not coupled to the pin signals. Therefore, by avoiding field-effect transistors with gate terminals coupled to pin signals, for example by excluding the second NFET of other methods, the field-effect transistors of the 3T3S-INV circuit 204A experience relatively low gate capacitance, which increases the operating speed of the 3T3S-INV circuit 204A compared to the operating speed of the first 4T3S-inverter in other methods.

[0040] Consider another method for manufacturing an XOR circuit, a counterpart to XOR circuit 218A, and including a first 4T3S-inverter of another method. The relatively slow operating speed of the first 4T3S-inverter of the other method results in a relatively slow operating speed for the corresponding XOR circuit. In contrast, the relatively fast operating speed of the 3T3S-INV circuit 204A results in a relatively fast operating speed for XOR circuit 218A compared to the operating speed of the corresponding XOR circuit.

[0041] Figure 2B This is a layout diagram of functional unit region (CR) 202B according to some embodiments.

[0042] Cell area 202B is Figure 1 Example of functional unit region 102. Unit region 202B is arranged relative to the following: an α track (or α line) extending parallel to the X-axis (not shown), and a β track (β line) extending parallel to the Y-axis (not shown).

[0043] exist Figure 2B In the present disclosure, and in other layout diagrams, the first and second directions are assumed to be parallel to the X-axis and Y-axis respectively. According to some embodiments, the first and second directions are assumed to have directions other than being parallel to the X-axis and Y-axis respectively. Figure 2B In the middle, and in other layout diagrams of this disclosure, the rows extend parallel to the X-axis and overlap with the corresponding α-tracks.

[0044] Figure 2B The layout diagrams, as well as other layout diagrams disclosed herein, represent transistor-based devices. The structures within the device are represented by patterns (also called shapes) in the layout diagrams. For the sake of simplicity, Figure 2B The elements in the layout diagrams (and other layout diagrams disclosed herein) will be referred to as structures rather than patterns. For example, Figure 2B The shape of the M0 segment instance is referred to as the M0 segment itself, not the M0 shape.

[0045] A layout diagram is a top view. Shapes in a layout diagram are two-dimensional relative to, for example, the X and Y axes, while the represented devices are three-dimensional. Therefore, shapes in such layout diagrams are described as having a width / length relative to the X-axis and a height relative to the Y-axis. Relative to the Z-axis, for example, the bottom / back of a first component represented in the layout diagram is stacked on top / front of a second component device represented in the layout diagram, or the top / front of the first component is stacked below, for example, the bottom / back of the second component.

[0046] Typically, devices are organized as layer stacks relative to the Z-axis, with corresponding structures positioned within each layer. Each shape in the layout diagram more specifically represents a component within the corresponding layer of the corresponding device. Furthermore, the layout diagram typically represents the relative depth of a shape and its corresponding layer, i.e., its position along the Z-axis, by superimposing a second shape on top of a first shape such that the second shape at least partially overlaps the first shape. For simplification, some structures in the device with a first stacking order along the Z-axis are represented in the layout diagram using a second stacking order along the Z-axis, i.e., a different / twisted stacking order.

[0047] Layout diagrams vary in the amount of detail they represent. In some cases, such as for simplification, selected layers of a layout diagram are combined / abstracted into a single layer. Or, and / or additionally, in some cases, such as for simplification, not all layers of the corresponding device are represented, i.e., selected layers of the layout diagram are omitted. Or, and / or additionally, in some cases, such as for simplification, not all elements of a given depicting layer of the corresponding device are represented, i.e., selected elements of a given depicting layer of the layout diagram are omitted. The layout diagrams disclosed herein are examples in which selected layers and / or selected elements depicting a given layer have been omitted.

[0048] According to some embodiments, an isolated dummy gate (IDG) structure is a dielectric structure that includes one or more dielectric materials and serves as an electrical isolation structure. Therefore, the IDG structure is not a conductive structure and thus does not act as an active gate, for example, a transistor. The IDG structure includes one or more dielectric materials and serves as an electrical isolation structure. According to some embodiments, the IDG structure is based on a gate segment as a precursor. According to some embodiments, the IDG structure is based on a dummy gate structure. According to some embodiments, the dummy gate structure includes a gate segment that is decoupled to not act as a gate, gate insulating layer, (optionally) one or more spacers, etc. According to some embodiments, the IDG structure is formed by first forming a gate segment (e.g., which is included in the dummy gate structure), sacrificing / removing (e.g., etching) the gate segment to form a trench, (optionally) removing a portion of the substrate previously below, above, or around the gate segment to deepen the trench, and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrically isolated structure (i.e., the IDG) are similar to the dimensions of the sacrificed gate segment. According to some embodiments, the IDG is a dielectric component comprising one or more dielectric materials (e.g., oxides, nitrides, oxynitrides, or other suitable materials) and serves as an isolation component. According to some embodiments, the IDG is a continuous polysilicon structure on an oxide diffusion (OD) edge structure and is referred to as a CPODE structure.

[0049] According to the numbering convention of the corresponding process technology node of the device to be manufactured, on the front side of the device (see, for example, Figures 3A to 3BIn this embodiment, the first metallization layer is either metallization layer 0 (MET0) or metallization layer 1 (MET1), and correspondingly, the first interconnect layer on the first metallization layer is interconnect layer 0 (VIA0) or interconnect layer 1 (VIA1). In this embodiment, again according to the numbering convention of the corresponding process technology node, on the back side of the device (not shown), the first buried metallization layer is buried metallization layer 0 (BMET0) or buried metallization layer 1 (BMET1), and correspondingly, the first buried interconnect layer under the first metallization layer is interconnect layer 0 (VIA0) or interconnect layer 1 (VIA1).

[0050] Generally, regarding the figures disclosed herein (unless otherwise stated), the following nomenclature is used for the front side of the device: the first metallization layer is assumed to be MET0; the first interconnect layer is assumed to be VIA0; the second metallization layer is assumed to be MET1; the second interconnect layer is assumed to be VIA1; and the third metallization layer is assumed to be MET2. The metallization segment in the MET0 layer is called the M0 segment. The via structure in the VIA0 layer is called the V0 structure. The metallization segment in the MET1 layer is called the M1 segment. The via structure in the VIA1 layer is called the V1 structure. The metallization segment in the MET2 layer is called the M2 segment.

[0051] Generally, regarding the figures disclosed herein (unless otherwise stated), the following nomenclature is used for the back side of the device: the first buried metallization layer is assumed to be BMET0; the first buried interconnect layer is assumed to be BVIA0; the second buried metallization layer is assumed to be BMET1; the second buried interconnect layer is assumed to be BVIA1; and the third buried metallization layer is assumed to be BMET2. The metallization segment in the BMET0 layer is called the buried M0 (BM0) segment. The via structure in the BVIA0 layer is called the BV0 structure. The metallization segment in the BMET1 layer is called the buried M1 (BM1) segment. The via structure in the BVIA1 layer is called the BV1 structure. The metallization segment in the BMET2 layer is called the buried M2 (BM2) segment.

[0052] The components included in cell region 202B include: positive (p-type) active regions (AR) 208P(1) to 208P(2) that extend substantially parallel to the X-axis and are used for corresponding PFETs; negative (n-type) active regions (AR) 208N(1) to 208N(2) that extend substantially parallel to the X-axis and are used for corresponding NFETs; gate segments 210(1) to 210(9) that extend substantially parallel to the Y-axis; IDG 212(1) that extends substantially parallel to the X-axis; M0 segments 214(1) to 214(4) that extend substantially parallel to the X-axis; and M1 segments 216(1) to 216(5) that extend substantially parallel to the Y-axis.

[0053] exist Figure 2BIn the middle, boxes I2B, I1B, FP1, FP2, FP3, and Zout overlap with the corresponding boxes P11 to P16, N11 to N14, and N16; such boxes help to indicate Figure 2B FET in Figure 2C The correspondence between the FETs in the diagram. Gate segments 210(8) and 210(9) are basically aligned with the left and right boundaries of cell region 202B, respectively. Relative to the Y-axis: the upper ends of gate segments 210(1), 210(4), 210(6) and 210(8) to 210(9) are basically aligned with the top boundary of cell region 202B; the lower ends of gate segments 210(3), 210(5) and 210(7) to 210(9) are basically aligned with the bottom boundary of cell region 202B.

[0054] The function of cell region 202B is the same as that of an XOR circuit. Therefore, cell region 202B is... Figure 2A An example of the XOR circuit 218A. Therefore, cell region 202B is also referred to herein as XOR circuit 218B. Figure 2B In the middle, the section line 3A-3A' corresponds to Figure 3A The cross-section. In Figure 2B In the middle, section line 3B-3B' corresponds to Figure 3B The cross section.

[0055] Relative to the Y-axis: Active regions 208N(1) and 208N(2) lie between active regions 208P(1) and 208P(2); Active region 208N(1) lies between active regions 208P(1) and 208N(2); Active region 208N(2) lies between active regions 208N(1) and 208P(2). Active regions 208P(1) and 208N(1) are in row 1. Active regions 208N(2) and 208P(2) are in row 2.

[0056] exist Figure 2B In this context, adjacent segments of gate segments 210(1) to 210(9) are separated by a uniform distance / pitch p_gate relative to the X-axis. The value of the pitch p_gate depends on the corresponding semiconductor process technology node. According to some embodiments, the pitch p_gate represents a contact poly pitch (CPP) for the corresponding semiconductor process technology node. Here, the term "poly" in the term CPP does not necessarily mean based on Figure 2B The gate structure in the corresponding manufactured semiconductor device will not be formed of polysilicon, but rather represents historical practice, as the gate structure in ICs manufactured according to previous semiconductor process technology nodes is typically formed of polysilicon. Figure 2BIn the example, the width w_202B of cell region 202B relative to the X-axis is equal to 4 × p_gate, i.e., w_202B = (4 × p_gate). According to some embodiments, the width w_CR of the cell region is different from w_202B.

[0057] exist Figure 2B And in other figures disclosed herein: the M0 segment is aligned with the corresponding α orbital (not shown); the gate segment, metal-to-source / drain contact (MD) structure (see, for example, see...) Figures 3A to 3B ) and IDG are aligned with the corresponding β orbitals (not shown).

[0058] Typically, when the MD structure overlaps with an active region, the overlapping portion of the active region can be configured as a source or drain region; that is, the overlapping portion of the active region can be used as a source or drain region of a transistor through doping. According to some embodiments, in the context of NMOS transistor technology with N-type active regions, the source and drain regions are doped with one or more N-type dopants more heavily than other regions of the active region, and the doping methods of the source and drain regions are substantially the same. According to some embodiments, in the context of NMOS, the source and drain regions are doped with one or more substantially different combinations of N-type dopants, but each source and drain region is still more heavily doped than other regions of the active region. According to some embodiments, in the context of NMOS, although the source and drain regions employ different combinations of doping process parameters, they are doped using the same combination of one or more N-type dopants, and each source and drain region is still more heavily doped than other regions of the active region. According to some embodiments, in the context of PMOS transistor technology with P-type active regions, the source and drain regions are doped with one or more P-type dopants more heavily than other regions of the active region, and the doping methods of the source and drain regions are substantially the same. According to some embodiments, in the PMOS context, the source and drain regions are doped with one or more substantially different combinations of P-type dopants, but each source and drain region is still more heavily doped than other regions of the active region. According to some embodiments, in the PMOS context, although the source and drain regions employ different combinations of doping process parameters, they are doped using the same one or more combinations of P-type dopants, and each source and drain region is still more heavily doped than other regions of the active region.

[0059] Furthermore, when the gate segment overlaps with the portion of the active region located between two adjacent source / drain (S / D) regions, the overlapping portion of the gate segment, the two adjacent S / D regions, and the active region typically represents a field-effect transistor (FET). The portion of the active region between the two adjacent S / D regions represents the channel region of the FET.

[0060] exist Figure 2B In the active region 208P(1), P14 to P16 are formed in the active region 208N(1). N14, N16 and dummy FET D11 are formed in the active region 208N(1). D11 contains IDG 212(1) replacing the corresponding gate segment, therefore D11 is a dummy FET and not an NFET. N11 to N13 are formed in the active region 208N(2). P11 to P13 are formed in the active region 208P(2).

[0061] Gate segment 210(7) is located above active regions 208N(2) and 208P(2) and is configured to receive pin signal A1. Gate segment 210(6) is located above active regions 208N(1) and 208P(1) and is configured to receive signal a2b, and is substantially collinear with gate segment 210(7).

[0062] Regarding the first S / D regions adjacent to the right side of gate segment 210(7) in active regions 208N(2) and 208P(2): these first S / D regions are coupled to each other and configured to provide signal a1b. Regarding the first S / D region adjacent to the right side of gate segment 210(6) in active region 208N(1): this first S / D region is configured to receive signal a1b. Regarding the second S / D regions adjacent to the left side of the first gate segment 210(7) in active regions 208N(2) and 208P(2): these second S / D regions are configured to receive VSS and VDD, respectively.

[0063] Regarding the first S / D region to the right of the gate segment 210(6) in the active region 208N(1): this first S / D region is configured to receive a non-reference voltage (NRV) signal, in Figure 2B In this example, the NRV signal is the internal signal a1b. Further regarding the first S / D region in the active region 208N(1): it serves as the source region of N14, in... Figure 2B The standard number is 207. P14 to P15 together with N14 constitute... Figure 2B The 3T3S-inverter 204B in the text corresponds to... Figure 2A The 3T3S-inverter 204A is mentioned.

[0064] Gate segment 210(5) is located above active regions 208N(2) and 208P(2) and is configured to receive pin signal A2. A second S / D region in active regions 208N(2) and 208P(2) is also adjacent to the right side of gate segment 210(5). A third S / D region in active regions 208N(2) and 208P(2) is adjacent to the left side of gate segment 210(5), coupled to each other, and configured to provide signal a2b.

[0065] Gate segment 210(2) is located above active region 208N(2) and configured to receive signal a1b. Gate segment 210(3) is located above active region 208P(2) and configured to receive pin signal A1. Active region 208N(2) ( Figure 2D The third S / D region in active region 208N(2) and active region 208P(2) is also adjacent to the right side of gate segment 210(2) and gate segment 210(3), respectively. The fourth S / D region in active region 208N(2) and active region 208P(2) is adjacent to the left side of gate segment 210(2) and gate segment 210(3), respectively, coupled to each other and configured to provide internal signal IS1.

[0066] M0 segment 214(1) is located above active region 208P(2) and gate segments 210(7), 210(5) and 210(3), and is coupled to gate segments 210(7) and 210(3). M0 segment 214(1) is not coupled to gate segment 210(5).

[0067] IDG 212(1) is located above active region 208N(1) and is substantially collinear with gate segments 210(3) and 210(5). The right side of IDG 212(1) is adjacent to the left side of gate segment 210(6). The second S / D region in active region 208N(1) is adjacent to the right side of IDG 212(1). The third S / D region in active region 208N(1) is adjacent to the left side of IDG 212(1) and is configured to receive signal a2b.

[0068] Figure 2C This is a circuit diagram of an XOR NOT logic (XNR) circuit 220C according to some embodiments.

[0069] XNR circuit 220C is a two-input XNR circuit. Composed of field-effect transistors, XNR circuit 220C is an example of a complementary metal-oxide-semiconductor (CMOS) architecture. XNR circuit 220C includes PFETs P21-P24, P26 and NFETs N21 to N26. Figure 2C In the middle, boxes I2B, I1B, FP1, FP2, FP3, and Zout overlap with the corresponding portions in P21 to P24, P26, and N21 to N26; such boxes help to indicate Figure 2C FET in Figure 2D The correspondence between FETs in the XNR circuit 220C includes: a latch 224(2) coupled between inverter 222(5) and inverter 222(6); and inverter 222(4).

[0070] Inverter 222(4) includes P21 and N21, which are series-coupled between VDD (i.e., node 226(1)) and VSS (i.e., node 226(2)). Inverter 222(5) is configured to receive pin signal A1 and generate signal a1b at node nd22, wherein signal a1b is the inverse of pin signal A1 and is an internal signal relative to XNR circuit 220C.

[0071] Inverter 222(5) includes P22 and N22 series coupled between VDD and VSS. Inverter 222(5) is configured to receive pin signal A2 and generate signal a2b at node nd21, where signal a2b is the inverted version of pin signal A2 and is an internal signal relative to XNR circuit 220C. Therefore, pin signal A2 is the input of XNR circuit 220C.

[0072] exist Figure 2C In the inverter 222(6), P26 and N26 are series coupled between VDD and VSS. The inverter 222(6) is configured to receive the internal signal IS2 at node nd23 and generate a signal Zb, where the signal Zb is the inverse of the signal IS2 and represents the output of the XNR circuit 220C.

[0073] Latch 224(2) is coupled between nodes nd21 and nd23. Latch 224(2) includes a tri-state inverting (3S-INV) circuit 206C and a transmission gate 230(2) coupled in parallel between nodes nd21 and nd23.

[0074] Transmission gate 230(2) is coupled between nodes nd21 and nd23; therefore, nodes nd21 and nd23 respectively represent the input and output of transmission gate 230(2). Transmission gate 230(2) includes P23 and N23 coupled in parallel between nodes nd21 and nd23. The control terminal, i.e., the gate terminal, of P23 is configured to receive signal a1b. The control terminal, i.e., the gate terminal, of N23 is configured to receive pin signal A1.

[0075] exist Figure 2C In this circuit, the tri-state inverting (3S-INV) circuit 206C is coupled between nodes nd21 and nd23; therefore, nodes nd21 and nd23 respectively represent the input and output of the 3S-INV 206C. The 3S-INV circuit 206C comprises three field-effect transistors and is therefore referred to herein as the 3T3S-INV circuit 206C. The 3T3S-INV circuit 206C includes P24 and N24 through N25, which are coupled in series between the VDD and the non-reference voltage (NRV) signal, where... Figure 2CIn this example, the NRV signal is signal a1b. P24 is coupled between VDD and node nd23. N24 is coupled between nodes nd23 and nd24. N25 is coupled between node nd24 and the NRV signal, i.e., between node nd24 and signal a1b. The drain of N25 is coupled to node nd24. The source of N25 is coupled to the NRV signal, i.e., to signal a1b. Each control terminal, i.e., the gate terminal, of P24 and N24 is configured to receive signal a2b. The control terminal, i.e., the gate terminal, of N25 is configured to receive signal a1b.

[0076] Consider another method for generating a tri-state inverter, a counterpart to the 3T3S-INV 206C. This counterpart tri-state inverter has four field-effect transistors instead of three, and is referred to herein as the third counterpart 4T3S-inverter. The third counterpart 4T3S-inverter includes: a first PFET (a counterpart to P24) coupled between VDD and a second PFET; a first NFET (a counterpart to N24); and a second NFET (a counterpart to N25). The control terminals, i.e., gate terminals, of each of the first PFET and the second NFET are configured to receive a counterpart to the internal signal a2b. The control terminal, i.e., gate terminal, of the second PFET is configured to receive an internal signal a1b. The control terminal, i.e., gate terminal, of the first NFET is configured to receive a counterpart to the pin signal A1.

[0077] Due to the influence of pin signals on gate capacitance compared to internal signals, the first NFET in this alternative method experiences a relatively large gate capacitance, greater than that experienced by the corresponding first PFET, second PFET, and second NFET. Therefore, the switching speed of the first NFET in this alternative method is relatively slower than that of at least the corresponding second NFET, which slows down the operating speed of the second 4T3S-inverter in this alternative method. In contrast, the gate terminals of each of P24 and N24 to N25 in the 3T3S-INV circuit 206C are coupled to internal signals, such that the gate terminals of the FETs in the 3T3S-INV circuit 206C are not coupled to pin signals. Therefore, by avoiding FETs with gate terminals coupled to pin signals, for example by excluding the first NFET of this alternative method, the FETs in the 3T3S-INV circuit 206C experience relatively low gate capacitance, which increases the operating speed of the 3T3S-INV circuit 206C compared to the operating speed of the second 4T3S-inverter in this alternative method.

[0078] Consider another method for generating an XNR circuit, corresponding to XNR circuit 220C, and including a second 4T3S-inverter of this other method. The relatively slow operating speed of the second 4T3S-inverter of this other method results in a relatively slow operating speed of the corresponding XNR circuit. In contrast, the relatively fast operating speed of the 3T3S-INV circuit 206C results in a relatively fast operating speed of XNR circuit 220C compared to the operating speed of the corresponding XNR circuit.

[0079] Figure 2D This is a layout diagram of the functional unit region 202D according to some embodiments.

[0080] Cell region 202D is Figure 1 Example of functional unit region 102. Unit region 202D is similar. Figure 2B Cell region 202B. For the sake of brevity, the discussion will focus on the differences between cell region 202D and cell region 202B, rather than their similarities.

[0081] The components included in cell region 202D include: p-type active region (AR) 208P(3) and value 208P(4) for corresponding PFET; n-type active regions 208N(3) to 208N(4) for corresponding NFET; gate segments 210(1) to 210(9); IDG 212(1); M0 segments 214(1) to 214(3); and M1 segments 216(1) to 216(3) and 216(5) to 216(7). Figure 2B Compared to cell region 202B, Figure 2D The element region 202D does not include segment M0 214(4). Furthermore, segment M1 216(6) of element region 202D replaces... Figure 2B The M1 segment 216(4) of the unit region 202B.

[0082] exist Figure 2D In the middle, boxes I2B, I1B, FP1, FP2, FP3, and Zout overlap with the corresponding portions in P21 to P24, P26, and N21 to N26; these boxes help to indicate Figure 2D FET in Figure 2C The correspondence between FETs in the diagram.

[0083] The function of cell region 202D is the same as that of the XNR circuit. Therefore, cell region 202D is... Figure 2C An example of the XNR circuit 220C. Therefore, cell region 202D is also referred to herein as XNR circuit 218B.

[0084] Relative to the Y-axis: Active regions 208P(3) and 208P(4) are located between active regions 208N(3) and 208N(4); active region 208P(3) is located between active regions 208N(3) and 208P(4); and active region 208P(4) is located between active regions 208P(3) and 208N(4). Active regions 208N(3) and 208P(3) are located in row 1. Active regions 208P(4) and 208N(4) are located in row 2.

[0085] exist Figure 2D In the diagram, relative to the X-axis, adjacent segments in gate segments 210(1) to 210(9) are separated from each other by a distance / spacing p_gate. Figure 2D In the example, the width w_202D of the cell region 202D relative to the X-axis is equal to 4 × p_gate, such that w_202D = (4 × p_gate). According to some embodiments, the width w_CR of the cell region is different from w_202D.

[0086] exist Figure 2D In the active region 208N(3), N24 to N26 are formed in the active region 208P(3). P24, P26 and dummy FET D21 are formed in the active region 208P(3). D21 includes IDG 212(1) instead of the corresponding gate segment, so D21 is a dummy FET instead of a PFET. P21 to P23 are formed in the active region 208P(4). N21 to N23 are formed in the active region 208N(4).

[0087] Gate segment 210(7) is located above each of active regions 208P(4) and active regions 208N(4) and is configured to receive pin signal A1. Gate segment 210(6) is located above active regions 208P(3) and active regions 208N(3) and is configured to receive signal a2b, and is substantially collinear with gate segment 210(7).

[0088] Regarding the first S / D regions adjacent to the right side of the gate segment 210 (7) in the active regions 208P (4) and 208N (4), these first S / D regions are coupled together and configured to provide signal a1b.

[0089] Regarding the first S / D region in active region 208P(3) adjacent to the right side of gate segment 210(6), the first S / D region is configured to receive signal a1b. Regarding the second S / D regions in active regions 208P(4) and active regions 208N(4) respectively adjacent to the left side of the first gate segment 210(7), they are respectively configured to receive VDD and VSS.

[0090] Regarding the first S / D region adjacent to the right side of gate segment 210(6) in active region 208P(3), the first S / D region is configured to receive a non-reference voltage (NRV) signal, wherein in example Figure 2D In this context, the NRV signal is the internal signal a1b. Further, regarding the first S / D region in the active region 208P(3), the first S / D region serves as the source region of P24, and in... Figure 2D Reference number 207 was assigned to it. Figure 2D In this process, P24 and N24 to N25 together constitute 3T3S-INV 204D, where... Figure 2D 3T3S-INV 204D corresponds to Figure 2C 3T3S-INV 204C.

[0091] Gate segment 210(5) is located above each of active regions 208P(4) and active regions 208N(4) and is configured to receive pin signal A2. A second S / D region in active regions 208P(4) and 208N(4) is also adjacent to the right side of gate segment 210(5). A third S / D region in active regions 208P(4) and 208N(4) is adjacent to the left side of gate segment 210(5), coupled together, and is configured to provide signal a2b.

[0092] Gate segment 210(2) is located above active region 208P(4) and is configured to receive signal a1b. Gate segment 210(3) is located above active region 208N(4) and is configured to receive pin signal A1. Figure 2D The third S / D region in active regions 208P(4) and 208N(4) is also adjacent to the right side of gate segments 210(2) and 210(3). The fourth S / D region in active regions 208P(4) and 208N(4) is adjacent to the left side of gate segments 210(2) and 210(3), coupled together, and configured to provide the internal signal IS2.

[0093] M0 segment 214(1) covers the active region 208N(4) and each of the gate segments 210(7), 210(5) and 210(3), and is coupled to each of the gate segments 210(7) and 210(3). M0 segment 214(1) is not coupled to the gate segment 210(5).

[0094] IDG 212(1) is located above active region 208P(3) and is substantially collinear with gate segments 210(3) and 210(5). The right side of IDG 212(1) is adjacent to the left side of gate segment 210(6). The second S / D region in active region 208P(3) is adjacent to the right side of IDG 212(1). The third S / D region in active region 208P(3) is adjacent to the left side of IDG 212(1) and is configured to receive signal a2b.

[0095] Figures 3A to 3B These are the corresponding sections 328A to 328B of the XOR circuit according to some embodiments.

[0096] According to some embodiments, the XOR circuit corresponding to sections 328A to 328B is Figure 2B Example of XOR circuit 202B. Figure 3A The cross section 328A corresponds to Figure 2B The cross-sectional line is 3A-3A'. Figure 3B Section 328B corresponds to Figure 2B The cross-sectional line is 3B-3B'.

[0097] Figure 3A and / or Figure 3B The structure includes: a substrate; active regions 308P(2) and 308N(1) to 308N(2); gate segments 310(3), 310(5) and 310(7); metal-to-source / drain contact (MD) structure; via-to-gate (VG) contact; via-to-MD (VD) contact; VD rail (VDR) contact; M0 segments 314(1) and 314(5) to 314(6); V0 structure; and M1 segment 316(1).

[0098] VD contacts are typically square, making all boundary edges approximately equal in length. An example of a VD contact where the left and right boundary edges are significantly longer than the top and bottom boundary edges, or vice versa, i.e., an example of a VD contact that is essentially rectangular, is called a VD rail (VDR) contact.

[0099] Figure 4A This is a circuit diagram of an XOR circuit 432 according to some embodiments.

[0100] XOR circuit 432 is a four-input XOR circuit. XOR circuit 432 includes two XOR circuits 418(1) and 418(2). According to some embodiments, each XOR circuit 418(1) and 418(2) is... Figure 2A An example of the XOR circuit 218A. Therefore, each XOR circuit 418(1) and 418(2) is a two-input XOR. As... Figure 4AAs shown, XOR circuits 418(1) and 418(2) are coupled together, making XOR circuit 342 a four-input XOR circuit.

[0101] The signals in the XOR circuit 432 include: pin signals A1, A2, A3 and A4 and their corresponding inverted signals a1b, a2b, a3b and a4b, wherein signals a1b to a4b are internal signals; internal signals xor12, xor34, xnr12 and xnr34; and output signal Z.

[0102] Figure 4B This is a circuit diagram of the XNR circuit 4434 according to some embodiments.

[0103] XNR circuit 434 is a four-input XNR circuit. XNR circuit 434 includes two XNR circuits 420(1) and 420(2). According to some embodiments, each XNR circuit 420(1) and 420(2) is... Figure 2C An example of the XNR circuit 220C. Therefore, each XNR circuit 420(1) and 420(2) is a two-input XNR. Figure 4B As shown, XNR circuits 420(1) and 420(2) are coupled together, making XNR circuit 434 a four-input XNR circuit.

[0104] The signals in the XNR circuit 434 include: pin signals A1, A2, A3 and A4 and their corresponding inverted signals a1b, a2b, a3b and a4b, wherein signals a1b to a4b are internal signals; internal signals xor12, xor34, xnr12 and xnr34; and output signal Z.

[0105] Figures 4C to 4E These are block diagrams of corresponding multi-member-circuit (MMC) combinations 436C to 436E according to some embodiments.

[0106] exist Figure 4C In the MMC combo 436C, member circuit 438(1) and member circuit 438(2) are included. Member circuits 438(1) to 438(2) are coupled in parallel to input signals in1 and in2.

[0107] Member circuit 438(1) based on Figure 2A 3T3S-INV 204A or Figure 2C The 3T3S-INV 206C is configured to perform a first function that generates the output signal out1. Member circuit 438(2) is based on Figure 2A 3T3S-INV 204A or Figure 2CThe 3T3S-INV 206C is configured to perform a second function that generates an output signal out2, which is different from the first function.

[0108] exist Figure 4D In the MMC combination 436D, there are member circuits 438(3) and 440. Member circuits 438(3) and 440 are coupled in parallel to the input signals in3 and in4.

[0109] Member circuit 438(3) based on Figure 2A 3T3S-INV 204A or Figure 2C The 3T3S-INV 206C is configured to perform a third function that generates an output signal out3. Member circuit 440(2) is based on a first 4T3S-inverter or a second 4T3S-inverter of the other method and is configured to perform a fourth function that generates an output signal out4, which is different from the third function.

[0110] exist Figure 4E In this configuration, the MMC combination 436E includes member circuits 438(4), 438(5), ..., and 438(N), where N is a positive integer and 3 ≤ N. The MMC combination 436E is coupled to input signals in4, in5, in6, ..., and in(M), where M is a positive integer and 4 ≤ N. According to some embodiments, N = M + 1.

[0111] Each member circuit 438(4) to 438(N) is based accordingly on Figure 2A 3T3S-INV 204A or Figure 2C The 3T3S-INV 206C. Member circuits 438(4) to 438(N) are configured to perform functions that generate corresponding output signals out4 to outN. According to some embodiments, each member circuit 438(4) to 438(N) is configured to perform the same function. According to some embodiments, at least one of the member circuits 438(4) to 438(N) is configured to perform a function different from the function performed by at least one of the other member circuits 438(4) to 438(N).

[0112] Figure 5A This is a circuit diagram of a half-adder 544A according to some embodiments.

[0113] The half-adder 544A includes an XOR circuit 518(1) and a logic AND circuit 548(1). According to some embodiments, the XOR circuit 518(1) is... Figure 2AAn example of the XOR circuit 218A. The XOR circuit 518(1) includes a 3T3S-INV 504. According to some embodiments, the 3T3S-INV 504 is Figure 2A An example of the 3T3S-INV 204A. The signals in the half-adder 544A include: pin signals A and B and their corresponding inverted signals ab and bb, where signals ab and bb are internal signals; and output signals S and CO.

[0114] Figure 5B This is a layout diagram of functional unit region 502B according to some embodiments.

[0115] Cell area 502B is Figure 1 Example of functional unit region 102. Unit region 502B is a part of larger region 544B, that is, it includes larger region 544B, wherein the function of larger region 544B is a half-adder. Therefore, larger region 544B is Figure 5A An example of half-adder 544A. Therefore, the larger region 544B is referred to herein as half-adder 544B.

[0116] Unit region 502B includes region 518(2) and region 548(2). Region 518(2) functions as an XOR circuit. Therefore, region 518(2) is referred to herein as XOR circuit 518(2). Region 548(2) functions as a logic AND circuit. Therefore, region 548(2) is referred to herein as AND circuit 548(2). According to some embodiments, XOR circuit 518(2) is... Figure 5A An example of the XOR circuit 518(1). According to some embodiments, the AND circuit 548(2) is... Figure 5A An example of an AND circuit 548(1).

[0117] The XOR circuit 518(2) includes region 504B. The function of region 504B is the same as that of 3T3S-INV. Therefore, region 504B is referred to as 3T3S-INV 504B. According to some embodiments, 3T3S-INV 504B is... Figure 5A An example of 3T3S-INV 504A.

[0118] The signals in the half-adder 544A include: pin signals A and B and their corresponding inverted signals ab and bb, where signals ab and bb are internal signals; internal signal COb, which is the inverted phase of output signal CO (not shown); and output signals S and CO.

[0119] Figure 5C This is a circuit diagram of a full adder 550C according to some embodiments.

[0120] The full adder 550C includes an XNR circuit 520(1) and a logic AND circuit 548(3). According to some embodiments, the XNR circuit 520(1) is... Figure 2C An example of the XNR circuit 220C. The XNR circuit 520(1) includes a 3T3S-INV 506C. According to some embodiments, the 3T3S-INV 506C is... Figure 2A An example of the 3T3S-INV 204A. The signals in the full adder 550C include: pin signals A, B, CI and their corresponding inverted signals ab, bb, and CIb, where signals ab, bb, and CIb are internal signals; and output signals S and CO.

[0121] Figure 5D This is a layout diagram of the functional unit region 502D according to some embodiments.

[0122] Cell region 502D is Figure 1 An example of functional unit region 102. Unit region 502D is a part of larger region 550D, that is, it includes larger region 550D, wherein the function of larger region 550D is the function of a full adder. Therefore, larger region 544D is Figure 5C An example of an adder 550C. Therefore, the larger region 550D is referred to herein as the full adder 550D.

[0123] Cell region 502D includes region 520(2) and region 548(4). Region 520(2) functions as an XNR circuit. Therefore, region 520(2) is referred to herein as XNR circuit 520(2). Region 548(4) functions as a logic AND circuit. Therefore, region 548(4) is referred to herein as AND circuit 548(4). According to some embodiments, XOR circuit 520(2) is... Figure 5C An example of the XNR circuit 520(1). According to some embodiments, the AND circuit 548(4) is... Figure 5C An example of the AND circuit 548(3).

[0124] XNR circuit 520(2) includes region 506D. The function of region 506D is the same as that of 3T3S-INV. Therefore, region 506D is referred to as 3T3S-INV 506D. According to some embodiments, 3T3S-INV 506D is... Figure 5C An example of 3T3S-INV 506C.

[0125] The signals in the half-adder 544A include: pin signals A and B and their corresponding inverted signals ab and bb, where signals ab and bb are internal signals; pin signal CI; internal signals xor12 and IS2; internal signal COb, which is the inverted phase of the output signal CO (not shown); and output signals S and CO.

[0126] Figure 5E This is a circuit diagram of compressor 552E according to some embodiments.

[0127] Compressor 552E includes full adder 550E(1) and full adder 550E(2). Full adder 550E(1) includes XNR circuit 520(3). According to some embodiments, XNR circuit 520(3) is Figure 2C An example of the XNR circuit 220C. The XNR circuit 520(3) includes 3T3S-INV 506E(1). According to some embodiments, 3T3S-INV 506E(1) is Figure 2C An example of the 3T3S-INV 206C. The full adder 550E(2) includes an XNR circuit 520(4). According to some embodiments, the XNR circuit 520(4) is... Figure 2C An example of the XNR circuit 220C. The XNR circuit 520(4) includes 3T3S-INV 506E(2). According to some embodiments, 3T3S-INV 506E(2) is Figure 2C An example of 3T3S-INV 206C.

[0128] The signals in compressor 552E include: pin signals A, B, C, and D and their corresponding inverted signals ab, bb, CIB, and db, where signals ab, bb, CIB, and db are internal signals; pin signal CIX and its inverted signal CIXB, where signal CIXB is an internal signal; internal signals xor12, sum, sumb, and xor23; internal signal Sb (not shown), which is the inverted form of output signal S; and output signals S and CO.

[0129] Figure 5F This is a layout diagram of the functional unit region 502F according to some embodiments.

[0130] Cell area 502F is Figure 1 An example of functional unit region 102. Unit region 502F is a part of larger region 552F, that is, it includes larger region 552F, wherein the function of larger region 552F is the function of the compressor. Therefore, larger region 552F is Figure 5E An example of compressor 552E. Therefore, the larger region 552F is referred to herein as compressor 552F.

[0131] Unit region 502F includes region 520(5) and region 520(6). Region 520(5) functions as an XNR circuit. Therefore, region 520(5) is referred to herein as XNR circuit 520(2). Region 520(6) also functions as an XNR circuit. Therefore, region 520(6) is referred to herein as XNR circuit 520(6). According to some embodiments, XOR circuit 520(5) is... Figure 5E An example of the XNR circuit 520(3). According to some embodiments, the XOR circuit 520(6) is... Figure 5C An example of the XNR circuit 520(4).

[0132] The signals in compressor 552F include: pin signals A and D and their corresponding inverted signals ab and db, where signals ab and db are internal signals; internal signal bb, which is the inverted version of pin signal B (not shown); and internal signal sumb.

[0133] Figure 5G This is a circuit diagram of compressor 552G according to some embodiments.

[0134] Compressor 552G includes full adder 550G and full adder 554. Full adder 550G includes XNR circuit 520(7). According to some embodiments, XNR circuit 520(7) is Figure 2C An example of the XNR circuit 220C. The XNR circuit 520(7) includes a 3T3S-INV 506(4). According to some embodiments, the 3T3S-INV 506(4) is Figure 2C An example of the 3T3S-INV 206C. The full adder 554 is based on either a first 4T3S-inverter or a second 4T3S-inverter of the same method.

[0135] The signals in compressor 552G include: pin signals A, B, C and D and their corresponding inverted signals ab, bb, CIB and db, wherein signals ab, bb, CIB and db are internal signals; pin signals; internal signals xor12 and sum; internal signal Sb (not shown), which is the inverted output signal S; and output signals S and CO.

[0136] Figure 5H This is a layout diagram of the functional unit region 502H according to some embodiments.

[0137] Cell region 502H is Figure 1 An example of functional unit region 102. Unit region 502H is a part of larger region 552H, that is, it includes larger region 552H, wherein the function of larger region 552H is the function of the compressor. Therefore, larger region 552H is Figure 5E An example of compressor 552F. Therefore, the larger region 552H is referred to herein as compressor 552H.

[0138] Unit region 502H includes region 520(8). The function of region 520(8) is the function of the XNR circuit. Therefore, region 520(7) is referred to herein as XNR circuit 520(8).

[0139] According to some embodiments, XOR circuit 520(8) is Figure 5G An example of the XNR circuit 520(7).

[0140] The signals in compressor 552H include: pin signals A and D and their corresponding inverted signals ab and db, where signals ab and db are internal signals; and an internal signal bb, which is the inverted version of pin signal B (not shown).

[0141] Figure 6 This is a flowchart (flow diagram) of a method 600 for manufacturing a device according to some embodiments.

[0142] According to some embodiments, method 600 is achievable, for example, using the EDA system 800 discussed below. Figure 8 ) and IC Manufacturing System 900 (discussed below) Figure 9 Examples of cell regions and / or macro regions that can be manufactured according to method 600 include the cell regions and / or macro regions disclosed herein.

[0143] exist Figure 6 In this method 600, blocks 602 through 604 are included. In block 602, a layout diagram is generated, which, among other things, includes one or more layout diagrams corresponding to one or more circuit schematics disclosed herein, one or more layout diagrams corresponding to one or more cell regions disclosed herein, one or more macro regions disclosed herein, etc. According to some embodiments, block 602 is implementable, for example, using the EDA system 800 discussed below (…). Figure 8 From box 602, the process proceeds to box 604.

[0144] In box 604, based on this layout, at least one of the following is performed: (A) one or more photolithographic exposures are performed, or (B) one or more photolithographic masks are fabricated, or (C) one or more components are fabricated in the device layer, for example, the device is fabricated. See below. Figure 9 Discussion of IC manufacturing system 900.

[0145] Figure 7 This is a flowchart of a method 700 for manufacturing a device according to some embodiments.

[0146] Method 700 is an example of box 604 (see discussion above). Figure 6 According to some embodiments, method 700 is achievable, for example, using IC manufacturing system 900 (see discussion below). Figure 9 Examples of devices that can be manufactured according to method 700 include devices comprising one or more circuit diagrams corresponding to those disclosed herein, one or more cell regions disclosed herein, or one or more macro regions disclosed herein. Method 700 includes blocks 710 to 738.

[0147] In box 710, first, second, and third active regions are formed (e.g., Figure 2B 208N(1) to 208N(2) and 208P(1); Figure 2D The 208P(3), 208P(4), and 208N(4); etc., extend in a first direction (e.g., parallel to the X-axis). The first and second active regions have a first conductivity type (e.g., Figure 2B The N-type; Figure 2D The third active region has a second conductivity type (e.g., P-type in the P-type region). Figure 2B P-type in; Figure 2D (N-type in the example; or similar), the second conductivity type is different from the first conductivity type. From box 710, the process proceeds to box 712.

[0148] In block 712, a sub-region of the active region is doped to form at least one of the following: (i) one or more first S / D regions, (ii) one or more second S / D regions, (iii) one or more third S / D regions, or (iv) one or more fourth S / D regions. Typically, the S / D regions are adjacent to the left or right side of the corresponding gate segment (e.g., 210(1) to 210(9)). Examples of the first to fourth S / D regions are shown in... Figure 2B , Figure 2D The discussion will proceed in the context of [etc.]. From box 712, the process moves to box 714.

[0149] In block 714, a gate segment is formed extending in a second direction (e.g., parallel to the Y-axis), which is perpendicular to the first direction. Block 712 includes blocks 716 through 724. Within block 714, the process proceeds to block 716.

[0150] In box 716, in the second active region (e.g., Figure 2B 208N(2); Figure 2D 208P(4); or similar) and the third active region (e.g., Figure 2B 208P(2); Figure 2DA first gate segment (e.g., 210(7)) is formed on top of 208P(3), 208N(4); or similar. From block 716, the process proceeds to block 718.

[0151] In box 718, in the first active region (e.g., Figure 2B 208N(1); Figure 2D A second gate segment (e.g., 210(6)) is formed on top of the first gate segment (e.g., 210(7)), and the second gate segment is substantially collinear with the first gate segment (e.g., 210(7)). From block 718, the process proceeds to block 720.

[0152] In box 720, in the second active region (e.g., Figure 2B 208N(2); Figure 2D 208P(4); or similar) and the third active region (e.g., Figure 2B 208P(2); Figure 2D A third gate segment (e.g., 210(5)) is formed on top of 208P(3), 208N(4); etc. From block 720, the process proceeds to block 722.

[0153] In box 722, in the second active region (e.g., Figure 2B 208N(2); Figure 2D A fourth gate segment (e.g., 210(2)) is formed on top of 208P(4); or similar). From block 722, the process proceeds to block 724.

[0154] In box 724, in the third active region (e.g., Figure 2B 208P(2); Figure 2D A fifth gate segment (e.g., 210(3)) is formed on top of 208P(3), 208N(4); or similar). From block 724, the process exits block 714. From block 714, the process proceeds to block 726.

[0155] In box 726, the IDG structure is formed (e.g., 212(1)). From box 726, the process proceeds to box 728.

[0156] In box 728, an MD structure is formed (see, for example, see...). Figures 3A to 3B From box 728, the process proceeds to box 730.

[0157] In box 730, a VG contact is formed (see, for example, see...). Figures 3A to 3B ) and VD contacts (e.g., see Figures 3A to 3B From box 7230, the process proceeds to box 732.

[0158] In block 732, one or more S / D regions and / or one or more gate segments are coupled together. Examples of one or more gate segments being coupled together include: Figure 2B or Figure 2D Gate segments 210(3), 210(5), and 210(7) are coupled together. Figure 2B or Figure 2D Gate segments 210(1) and 210(6) are coupled together, etc. Examples of one or more S / D regions being coupled together include: Figure 2B The first S / D region in the active regions 208N(1), 208N(2) and 208P(2); Figure 2D The first S / D region in the active regions 208P(3), 208P(4) and 208N(4); Figure 2B The first S / D region in the active region 208P(1), the second S / D region in the active region 208N(1), and the fourth S / D region in the active regions 208N(2) and 208P(2); Figure 2B The first S / D region in the active region 208N(3), the second S / D region in the active region 208P(3), and the fourth S / D region in the active regions 208P(4) and 208N(4); etc. Within box 732, the process proceeds to box 734.

[0159] In box 734, segment M0 is formed (e.g., segments M0 214(1) to 214(3)). Within box 734, the process proceeds to box 736.

[0160] In box 736, a first M0 segment is formed (e.g., 214(1)), which covers the third active region (e.g., Figure 2B 208P(2); Figure 2D 208P(3), 208N(4); etc.) and

[0161] Each of the first gate segment (e.g., 210(7)), the third gate segment (e.g., 210(5)), and the fifth gate segment (e.g., 210(3)). From block 736, the process exits block 734. From block 734, the process proceeds to block 738.

[0162] In box 738, a V0 structure is formed (see, for example, see...). Figures 3A to 3B From box 738, the process proceeds to box 740.

[0163] In box 740, segment M1 is formed (e.g., 216(1) to 216(3)).

[0164] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0165] According to some embodiments, EDA system 800 includes an Automatic Placement and Routing (APR) system. According to some embodiments, EDA system 800 is a general-purpose computing device including processor 802 (e.g., a hardware processor) and non-transitory computer-readable storage medium 804. Storage medium 804 is encoded, among other things, with, stored, computer program code 806, i.e., a set of executable instructions. According to one or more embodiments (hereinafter referred to as the process and / or method), processor 802 executes instructions 806 representing (at least partially) an EDA tool that implements, for example, one or more methods for generating a layout diagram corresponding to those disclosed herein.

[0166] Storage medium 804 is a storage layout diagram 811, such as the layout diagram disclosed herein.

[0167] Processor 802 is electrically coupled to storage medium 804 via bus 808. Processor 802 is also electrically coupled to I / O interface 810 via bus 808. Network interface 812 is further electrically connected to processor 802 via bus 808. Network interface 812 is connected to network 814, enabling processor 802 and storage medium 804 to be connected to external components via network 814. Processor 802 is configured to execute computer program code 806 stored in storage medium 804 to make EDA system 800 available for performing some or all of the processes and / or methods. In one or more embodiments, processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0168] In one or more embodiments, storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disk, storage medium 804 includes compact read-only optical disk (CD-ROM), compact read-write optical disk (CD-R / W), and / or digital video optical disk (DVD).

[0169] In one or more embodiments, storage medium 804 stores instructions, namely computer program code 806, configured to enable EDA system 800 (where the execution representation (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 further stores information facilitating the execution of some or all of the said processes and / or methods. In one or more embodiments, storage medium 804 stores a standard cell library 807, which includes standard cells corresponding to the layout diagram components disclosed herein. Storage medium 804 stores one or more layout diagrams 816, such as one or more layout diagrams corresponding to the layout diagrams disclosed herein, one or more compiler macros 817 based on the layout diagrams (including one or more layout diagrams disclosed herein), etc.

[0170] EDA system 800 includes an I / O interface 810. The I / O interface 810 is coupled to external circuitry. In one or more embodiments, the I / O interface 810 includes a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 802.

[0171] EDA system 800 further includes a network interface 812 coupled to processor 802. Network interface 812 allows EDA system 800 to communicate with network 814, to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the described processes and / or methods are implemented in two or more EDA systems 800.

[0172] EDA system 800 is configured to receive information via I / O interface 810. The information received via I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters, for processing by processor 802. This information is transmitted to processor 802 via bus 808. EDA system 800 is also configured to receive information related to the user interface (UI) via I / O interface 810. This information is stored as UI 842 on computer-readable medium 804.

[0173] According to some embodiments, some or all of the processes and / or methods are implemented as a standalone software application executed by a processor. According to some embodiments, some or all of the processes and / or methods are implemented as part of an additional software application. According to some embodiments, some or all of the processes and / or methods are implemented as a plug-in to a software application. According to some embodiments, at least one of the processes and / or methods is implemented as part of an EDA tool. According to some embodiments, some or all of the processes and / or methods are implemented as a software application used by an EDA system 800. According to some embodiments, tools (such as those from CADENCE DESIGN SYSTEMS, Inc.) are used. (or other suitable layout generation tools) generate a layout that includes standard cells.

[0174] According to some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as one or more optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM, memory cards), etc.

[0175] According to some embodiments, Figure 9 This is a block diagram of an integrated circuit (IC) manufacturing system 900, and the associated IC manufacturing process.

[0176] According to some embodiments, based on Figure 6 The layout diagram generated by frame 602 is implemented in IC manufacturing system 900. Figure 6 Box 604, wherein a manufacturing system 900 is used to manufacture (A) one or more semiconductor masks or (B) at least one component in an unfinished semiconductor integrated circuit layer. According to some embodiments, the IC manufacturing system 900 implements... Figure 6 Flowcharts, etc.

[0177] exist Figure 9In this IC manufacturing system 900, entities such as design company 920, mask factory 930, and IC manufacturer / foundry ("fab") 950 collaborate with each other in the design, development, and manufacturing cycle and / or related services of IC device 960. The entities in system 900 are connected via a communication network. According to some embodiments, this communication network is a single network; in other embodiments, the communication network includes multiple different networks (such as intranets and the Internet) and includes wired and / or wireless communication channels. Each entity interacts with one or more other entities, providing or receiving services from them. According to some embodiments, two or more of the design company 920, mask factory 930, and IC foundry 950 belong to the same large company; in other embodiments, two or more coexist in the same facility and share resources.

[0178] Design company (or design team) 920 generates IC design layout 922. This layout contains various geometric patterns designed for IC device 960, corresponding to the metal layers, oxide layers, or semiconductor layers that constitute the components of IC device 960. The layers combine to form various IC components: for example, a portion of layout 922 includes active regions, gate terminals, source / drain terminals, metal lines or vias for interlayer interconnects, and pad openings to be formed on a semiconductor substrate (such as a silicon wafer) and its material layers. Source / drain (S / D) regions may refer to the source or drain individually or collectively, depending on the context. Design company 920 generates IC design layout 922 through design flows such as logic design, physical design, or place-and-route. This layout is presented as a data file containing geometric pattern information (such as GDSII or DFII file format).

[0179] Mask fabrication plant 930 includes data preparation 932 and mask fabrication 934. Based on IC design layout 922, mask fabrication plant 930 uses IC design layout 922 to fabricate one or more masks 935 for fabricating various layers of IC device 960 according to IC design layout 922. Mask fabrication plant 930 performs mask data preparation 932, where IC design layout 922 is translated into a representative data file (“RDF”). Mask data preparation 932 provides this RDF to mask fabrication 934. Mask fabrication 934 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (photomask) or semiconductor wafer. The design layout is manipulated by mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of IC fabrication plant 950. Figure 9 In this illustration, mask data preparation 932, mask manufacturing 934, and mask 935 are shown as separate elements. According to some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0180] According to some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. According to some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution adjustment components, phase-shift masks, other suitable techniques, or combinations thereof. According to some embodiments, inverse lithography (ILT) is further used, which treats OPC as an inverse imaging problem.

[0181] According to some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that examines the IC design layout that has been processed in the OPC using a set of mask creation rules. These rules include certain geometric and / or connectivity constraints to ensure sufficient margins, taking into account variability in semiconductor manufacturing processes, etc. According to some embodiments, the MRC modifies the IC design layout to compensate for limitations during mask fabrication 934, which may undo some modifications performed by the OPC to satisfy the mask creation rules.

[0182] According to some embodiments, mask data preparation 932 includes a lithography process check (LPC), which simulates a process to be implemented by an IC manufacturing plant 950 to manufacture an IC device 960. The LPC simulates this process based on an IC design layout 922 to manufacture a simulated manufactured device, such as IC device 960. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. According to some embodiments, after the LPC manufactures the simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 922.

[0183] The above description of mask data preparation 932 has been simplified for clarity. According to some embodiments, mask data preparation 932 includes additional components, such as logic operations (LOPs), to modify the IC design layout according to manufacturing rules. Furthermore, the processes applied to IC design layout 922 during data preparation 932 can be performed in various different sequences.

[0184] After mask data preparation 932 and during mask fabrication 934, a mask 935 or a set of masks 935 is fabricated based on the modified IC design layout. According to some embodiments, a pattern is formed on the mask (photomask) based on the modified IC design layout using an electron beam (e-beam) or multi-electron beam mechanism. The mask is formed using various techniques. According to some embodiments, the mask is formed using a binary technique. According to some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, is used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer; this radiation beam is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the mask. In another example, the mask is formed using a phase-shifting technique. In a phase-shifting mask (PSM), various components in the pattern formed on the mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shifting mask is either a decaying PSM or an alternating PSM. The mask generated by mask fabrication 934 is used in a variety of processes. For example, the mask is used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions, and / or in other suitable processes.

[0185] IC manufacturing plant 950 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing various IC products. According to some embodiments, IC manufacturing plant 950 is a semiconductor foundry. For example, there may be manufacturing facilities for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end process (BEOL) manufacturing) for IC product interconnection and packaging, and a third manufacturing facility may provide other services for the foundry business.

[0186] IC manufacturing plant 950 uses a mask 935 manufactured by mask factory 930 to manufacture IC device 960 via manufacturing tool 952. Therefore, IC manufacturing plant 950 at least indirectly uses IC design layout 922 to manufacture IC device 960. According to some embodiments, semiconductor wafer 953 is manufactured by IC manufacturing plant 950 using mask 935 to form IC device 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate on which a material layer is formed. The semiconductor wafer further includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0187] According to some embodiments, a circuit includes: first and second inverters configured to receive first and second pin signals and generate inverted versions of the first and second pin signals, which are respectively first and second input signals of the circuit; and a tri-state inverting sub-circuit including first and second data transistors and a sleep transistor, each control terminal of the first and second data transistors being coupled to a first node having an inverted second pin signal, the control terminal of the sleep transistor being coupled to a second node having an inverted first pin signal, and the first and second data transistors and the sleep transistor being coupled in series between a third node having a first reference voltage and a fourth node having a non-reference voltage (NRV) signal.

[0188] According to some embodiments, the fourth node and the second node are the same node.

[0189] According to some embodiments, the circuit further includes: a transmission gate coupled between the first node and the fifth node; and wherein the fifth node has a first internal signal; the transmission gate is coupled in parallel with the tri-state inverting sub-circuit; a first control terminal of the transmission gate is configured to receive the first pin signal, and a second control terminal of the transmission gate is coupled to the second node to receive the inversion of the first pin signal.

[0190] According to some embodiments, regarding the three-state inverting sub-circuit, the first data transistor and the sleep transistor are positive channel metal-oxide-semiconductor (PMOS) field-effect transistors (FETs) (PFETs), and the second data transistor is a negative channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) (NFETs); and the first reference voltage is VDD.

[0191] According to some embodiments, the circuit further includes: a third inverter coupled to the fifth node to receive the first internal signal and configured to generate an inverted first internal signal representing the output signal of the circuit; and wherein the circuit is an XOR logic circuit.

[0192] According to some embodiments, the circuit further includes: an AND gate configured to receive the first and second pin signals and generate a logic AND signal; and wherein the circuit is a half-adder circuit; the inverted first internal signal represents the sum signal of the half-adder circuit; and the logic AND signal represents the output carry signal of the half-adder circuit.

[0193] According to some embodiments, regarding the three-state inverting sub-circuit, the first data transistor is a positive-channel metal-oxide-semiconductor (PMOS) field-effect transistor (PFET); the second data transistor and the sleep transistor are negative-channel metal-oxide-semiconductor (NMOS) field-effect transistors (NFET); and the first reference voltage is VSS.

[0194] According to some embodiments, the circuit further includes: a third inverter coupled to the fifth node to receive the first internal signal and configured to generate an inverted first internal signal representing the output signal of the circuit; and wherein the circuit is an XOR NOT (XNR) logic circuit.

[0195] According to some embodiments, the circuit further includes an AND gate configured to receive the first and second pin signals and generate a logic AND signal, wherein: the circuit is a half-adder circuit; the inverted first internal signal represents the sum signal of the half-adder circuit; and the logic AND signal represents the output carry signal of the half-adder circuit.

[0196] According to some embodiments, a cell region (of a semiconductor device) includes: an active region (AR) extending in a first direction, including first and second ARs of a first type, and a third AR of a second type; a gate segment extending in a second direction perpendicular to the first direction, including: a first gate segment on the second and third ARs configured to receive a first pin signal, and a second gate segment on the first AR configured to receive an inverted second pin signal and substantially collinear with the first gate segment; a first source / drain (S / D) region in the second and third ARs and adjacent to a second side of the first gate segment coupled together and configured to provide an inverted first pin signal; second S / D regions in the second and third ARs and adjacent to a first side of the first gate segment respectively configured to receive different first and second reference voltages; and a first S / D region in the first AR and adjacent to a second side of the second gate segment configured to receive a non-reference voltage (NRV) signal.

[0197] According to some embodiments, the NRV signal is a first internal signal within the cell region.

[0198] According to some embodiments, the gate segment further includes a third gate segment on the second and third ARs, configured to receive a second pin signal; the third gate segment has a first side and a second side relative to a first direction, the second side of the third gate segment being adjacent to the first side of the first gate segment; a second S / D region in the second and third ARs being adjacent to the second side of the third gate segment; and a third S / D region in the second and third ARs and adjacent to the first side of the third gate segment being coupled together and configured to provide an inversion of the second pin signal.

[0199] According to some embodiments, the gate segment further includes a fourth gate segment on the second AR configured to receive the inverted first pin signal, and a fifth gate segment on the third AR configured to receive the first pin signal; the fourth and fifth gate segments are substantially collinear, and each second side of the fourth and fifth gate segments is adjacent to a first side of the third gate segment; third S / D regions in the second and third ARs are respectively adjacent to the second sides of the fourth and fifth gate segments; and fourth S / D regions in the second and third ARs respectively adjacent to the first sides of the fourth and fifth gate segments are coupled together and configured to provide a first internal signal within the cell region.

[0200] According to some embodiments, the cell region further includes: a metallized M_1st segment extending in a first direction in a first metallization layer (M_1st layer), and including a first M_1st segment covering the third AR, the first, third and fifth gate segments, and coupled to each of the first and fifth gate segments.

[0201] According to some embodiments, the cell region further includes: a first isolation dummy gate (IDG) extending in a second direction and on a first AR, the first IDG being substantially collinear with a third gate segment; the first IDG having a first side and a second side relative to the first direction, the second side of the first IDG being adjacent to the first side of the second gate segment; a second S / D region in the first AR adjacent to the second side of the first IDG; and a third S / D region in the first AR adjacent to the first side of the first IDG and configured to receive an inverted second pin signal.

[0202] According to some embodiments, the method (of forming cell regions) includes: forming an active region (AR) extending in a first direction, including first and second ARs of a first type, and a third AR of a different second type; doping sub-regions of the AR to form source / drain (S / D) regions, resulting in the first S / D regions being aligned with each other relative to the first direction, the second S / D regions being aligned with each other, and corresponding portions of the ARs representing channel regions between adjacent first and second S / D regions; forming a gate segment extending in a second direction perpendicular to the first direction, resulting in a first gate segment on each channel region of the second and third ARs, and a second gate segment on the channel region of the first AR. Furthermore, it is substantially collinear with the first gate segment and selectively coupled to one or more S / D regions or one or more gate segments, including the following: the first gate segment receives a first pin signal; the second gate segment receives an inverted version of the second pin signal; a first S / D region in the second and third ARs and adjacent to the second side of the first gate segment provides an inverted version of the first pin signal; a first S / D region in the third AR and adjacent to the second side of the second gate segment receives the inverted version of the first pin signal; the second S / D regions in the second and third ARs and adjacent to the first side of the first gate segment respectively receive different first and second reference voltages; and the first S / D region in the first AR and adjacent to the second side of the second gate segment receives a non-reference voltage (NRV) signal.

[0203] According to some embodiments, the doped subregion further includes third S / D regions aligned with each other relative to a first direction, and corresponding portions of the ARs represent channel regions between adjacent second and S / D regions; the forming gate segment further includes a third gate segment on the second and third ARs; the third gate segment has a first side and a second side relative to the first direction, the second side of the third gate segment being adjacent to the first side of the first gate segment; the forming active regions (ARs) further include a second S / D region in the second and third ARs adjacent to the second side of the third gate segment; and a third S / D region in the second and third ARs adjacent to the first side of the third gate segment; the selective coupling further results in the third gate segment receiving a second pin signal, and the third S / D regions in the second and third ARs together providing an inversion of the first pin signal.

[0204] According to some embodiments, the doped subregion further includes fourth S / D regions aligned with each other relative to a first direction, and corresponding portions of the ARs represent channel regions between adjacent third and fourth S / D regions; the forming gate segment further includes a fourth gate segment on a second AR and a fifth gate segment on a third AR; the fourth and fifth gate segments are substantially collinear, and each second side of the fourth and fifth gate segments is adjacent to a first side of the third gate segment; the forming active region (AR) further includes third S / D regions in the second and third ARs respectively adjacent to the second sides of the fourth and fifth gate segments; fourth S / D regions in the second and third ARs respectively adjacent to the first sides of the fourth and fifth gate segments are coupled together and configured to provide a first internal signal within the cell region; and the selective coupling further includes the fourth gate segment receiving an inverted first pin signal and the fifth gate segment receiving the first pin signal.

[0205] According to some embodiments, the method further includes: in the first metallization layer (M_1st layer), an M_1st segment extending in a first direction, including a first M_1st segment covering the third AR, first, third and fifth gate segments; and wherein the selective coupling further includes the first M_1st segment coupled to each of the first and fifth gate segments.

[0206] According to some embodiments, the method further includes: forming a first isolation dummy gate (IDG) extending in a second direction and on a first AR, the first IDG being substantially collinear with a third gate segment; and wherein the first IDG has a first side and a second side relative to a first direction, the second side of the first IDG being adjacent to the first side of the second gate segment; a second S / D region in the first AR being adjacent to the second side of the first IDG; a third S / D region in the first AR being adjacent to the first side of the first IDG; and the selective coupling further includes coupling the third S / D region in the first AR to receive an inverted second pin signal.

[0207] Those skilled in the art will readily recognize that the disclosed one or more embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to make various modifications, substitutions of equivalents, and various other embodiments as broadly disclosed herein. Therefore, the protection granted herein is intended to be limited only to the definitions contained in the appended claims and their equivalents.

Claims

1. A circuit comprising: The first inverter and the second inverter are respectively configured to receive the first pin signal and the second pin signal and generate the inverted versions of the first pin signal and the second pin signal, wherein the first pin signal and the second pin signal are the first input signal and the second input signal of the circuit, respectively. as well as The three-state inverting sub-circuit includes a first data transistor, a second data transistor, and a sleep transistor. Each control terminal of the first data transistor and the second data transistor is coupled to a first node having the inverted second pin signal. The control terminal of the sleep transistor is coupled to a second node having the inverted signal of the first pin, and The first data transistor, the second data transistor, and the sleep transistor are coupled in series between a third node having a first reference voltage and a fourth node having a non-reference voltage (NRV) signal.

2. The circuit according to claim 1, wherein: The fourth node and the second node are the same node.

3. The circuit according to claim 2 further includes: A transmission gate is coupled between the first node and the fifth node; as well as in: The fifth node has a first internal signal; The transmission gate is coupled in parallel with the three-state inverting sub-circuit; The first control terminal of the transmission gate is configured to receive the first pin signal, and The second control terminal of the transmission gate is coupled to the second node to receive the inverted signal of the first pin.

4. The circuit according to claim 3, wherein: Regarding the aforementioned three-state inverting sub-circuit The first data transistor and the sleep transistor are P-type metal-oxide-semiconductor (PMOS) field-effect transistors (PFETs), and The second data transistor is an N-type metal-oxide-semiconductor (NMOS) field-effect transistor (NFET); and The first reference voltage is VDD.

5. The circuit according to claim 4, further comprising: A third inverter, coupled to the fifth node, is configured to receive the first internal signal and generate an inverted first internal signal, the inverted first internal signal representing the output signal of the circuit; and The circuit in question is an XOR logic circuit.

6. A cell region of a semiconductor device, the cell region comprising: Active region (AR), extending in the first direction and including the following: The first active region and the second active region of the first type, and Different types of third active regions; The gate segment extends in a second direction perpendicular to the first direction and includes the following: A first gate segment is located above the second active region and the third active region, and is configured to receive a first pin signal. The second gate segment is located above the first active region and is configured to receive the inverted second pin signal, and is collinear with the first gate segment; A first source / drain (S / D) region is located in the second active region and the third active region and on the second side adjacent to the first gate segment. The first source / drain (S / D) region is coupled together and configured to provide an inverted signal of the first pin. The second source / drain region is located in the second active region and the third active region and on the first side adjacent to the first gate segment. The second source / drain region is configured to receive different first reference voltages and second reference voltages, respectively. as well as In the first source / drain region of the first active region, adjacent to the second side of the second gate segment and configured to receive a non-reference voltage (NRV) signal.

7. The unit region according to claim 6, wherein: The non-reference voltage signal is the first internal signal within the cell region.

8. The unit region according to claim 6, wherein: The gate segment also includes the following: A third gate segment is located above the second active region and the third active region, and is configured to receive the second pin signal; The third gate segment has a first side and a second side relative to the first direction. The second side of the third gate segment is adjacent to the first side of the first gate segment; The second source / drain region in the second active region and the third active region is adjacent to the second side of the third gate segment; and The third source / drain region is in the second and third active regions and is adjacent to the first side of the third gate segment. The third source / drain region is coupled together and configured to provide the inversion of the second pin signal.

9. A method for manufacturing a cell region, the method comprising: An active region extending in a first direction is formed, the active region comprising: The first active region and the second active region of the first type, and Different types of third active regions; Doping a subregion of the active region to form a source / drain (S / D) region, and including: Relative to the first direction, the first source / drain regions of the source / drain regions are aligned with each other, and the second source / drain regions of the source / drain regions are aligned with each other. A corresponding portion of the active region represents a channel region between adjacent first source / drain regions and second source / drain regions; A gate segment is formed extending in a second direction perpendicular to the first direction, the gate segment comprising: The first gate segment is located above the corresponding portion of the channel region of each of the second and third active regions, and The second gate segment is located above a corresponding portion of the channel region of the first active region and is collinear with the first gate segment; and Selectively coupling one or more of the source / drain regions or one or more of the gate segments includes: The first gate segment receives the first pin signal. The second gate segment receives the inverted signal from the second pin. The first source / drain region is located in the second active region and the third active region and is adjacent to the second side of the first gate segment. The first source / drain region provides inversion of the first pin signal. The first source / drain region in the third active region and on the second side adjacent to the second gate segment receives the inverted version of the first pin signal; In the second active region and the third active region, and adjacent to the first side of the first gate segment, the second source / drain region receives different first reference voltages and second reference voltages respectively; and The first source / drain region, located in the first active region and on the second side adjacent to the second gate segment, receives a non-reference voltage (NRV) signal.

10. The method according to claim 9, wherein: The doped sub-region further includes: Relative to the first direction, the third source / drain regions of the source / drain regions are aligned with each other, and The corresponding portion of the active region represents a channel region between the adjacent second and source / drain regions; Forming the gate segment further includes: The third gate segment is located above the second active region and the third active region; The third gate segment has a first side and a second side relative to the first direction. The second side of the third gate segment is adjacent to the first side of the first gate segment; Forming the active region (AR) also includes the following: In the second active region and the third active region, the second source / drain region is adjacent to the second side of the third gate segment; and The third source / drain region in the second active region and the third active region is adjacent to the first side of the third gate segment; The selective coupling also includes: The third gate segment receives the second pin signal, and The second active region and the third source / drain region in the third active region together provide the inversion of the first pin signal.

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